target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/delay.h>
  19 #include <linux/skbuff.h>
  20 #include <linux/rtl8366.h>
  21
  22 #include "rtl8366_smi.h"
  23
  24 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  25 #define RTL8366S_DRIVER_VER     "0.2.2"
  26
  27 #define RTL8366S_PHY_NO_MAX     4
  28 #define RTL8366S_PHY_PAGE_MAX   7
  29 #define RTL8366S_PHY_ADDR_MAX   31
  30
  31 /* Switch Global Configuration register */
  32 #define RTL8366S_SGCR                           0x0000
  33 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  34 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  35 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  38 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  39 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  40 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  41
  42 /* Port Enable Control register */
  43 #define RTL8366S_PECR                           0x0001
  44
  45 /* Green Ethernet Feature (based on GPL_BELKIN_F5D8235-4_v1000 v1.01.24) */
  46 #define RTL8366S_GREEN_ETHERNET_CTRL_REG        0x000a
  47 #define RTL8366S_GREEN_ETHERNET_CTRL_MASK       0x0018
  48 #define RTL8366S_GREEN_ETHERNET_TX_BIT          (1 << 3)
  49 #define RTL8366S_GREEN_ETHERNET_RX_BIT          (1 << 4)
  50
  51 /* Switch Security Control registers */
  52 #define RTL8366S_SSCR0                          0x0002
  53 #define RTL8366S_SSCR1                          0x0003
  54 #define RTL8366S_SSCR2                          0x0004
  55 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  56
  57 #define RTL8366S_RESET_CTRL_REG                 0x0100
  58 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  59 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  60
  61 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  62 #define RTL8366S_CHIP_VERSION_MASK              0xf
  63 #define RTL8366S_CHIP_ID_REG                    0x0105
  64 #define RTL8366S_CHIP_ID_8366                   0x8366
  65
  66 /* PHY registers control */
  67 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  68 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  69
  70 #define RTL8366S_PHY_CTRL_READ                  1
  71 #define RTL8366S_PHY_CTRL_WRITE                 0
  72
  73 #define RTL8366S_PHY_REG_MASK                   0x1f
  74 #define RTL8366S_PHY_PAGE_OFFSET                5
  75 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  76 #define RTL8366S_PHY_NO_OFFSET                  9
  77 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  78
  79 /* Green Ethernet Feature for PHY ports */
  80 #define RTL8366S_PHY_POWER_SAVING_CTRL_REG      12
  81 #define RTL8366S_PHY_POWER_SAVING_MASK          0x1000
  82
  83 /* LED control registers */
  84 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  85 #define RTL8366S_LED_BLINKRATE_BIT              0
  86 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  87
  88 #define RTL8366S_LED_CTRL_REG                   0x0421
  89 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  90 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  91
  92 #define RTL8366S_MIB_COUNT                      33
  93 #define RTL8366S_GLOBAL_MIB_COUNT               1
  94 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  95 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  96 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  97 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  98 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  99 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
 100 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
 101 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
 102
 103 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
 104 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
 105 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
 106
 107
 108 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
 109 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 110                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 111 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 112 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 113
 114
 115 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 116 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 117
 118 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 119
 120 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 121 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 122 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 123
 124 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 125
 126 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 127
 128 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 129 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 130 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 131 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 132 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 133 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 134 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 135
 136
 137 #define RTL8366S_PORT_NUM_CPU           5
 138 #define RTL8366S_NUM_PORTS              6
 139 #define RTL8366S_NUM_VLANS              16
 140 #define RTL8366S_NUM_LEDGROUPS          4
 141 #define RTL8366S_NUM_VIDS               4096
 142 #define RTL8366S_PRIORITYMAX            7
 143 #define RTL8366S_FIDMAX                 7
 144
 145
 146 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 147 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 148 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 149 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 150
 151 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 152 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 153
 154 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 155                                          RTL8366S_PORT_2 |      \
 156                                          RTL8366S_PORT_3 |      \
 157                                          RTL8366S_PORT_4 |      \
 158                                          RTL8366S_PORT_UNKNOWN | \
 159                                          RTL8366S_PORT_CPU)
 160
 161 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 162                                          RTL8366S_PORT_2 |      \
 163                                          RTL8366S_PORT_3 |      \
 164                                          RTL8366S_PORT_4 |      \
 165                                          RTL8366S_PORT_UNKNOWN)
 166
 167 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 168                                          RTL8366S_PORT_2 |      \
 169                                          RTL8366S_PORT_3 |      \
 170                                          RTL8366S_PORT_4)
 171
 172 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 173                                          RTL8366S_PORT_CPU)
 174
 175 #define RTL8366S_VLAN_VID_MASK          0xfff
 176 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 177 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 178 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 179 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 180 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 181 #define RTL8366S_VLAN_FID_SHIFT         12
 182 #define RTL8366S_VLAN_FID_MASK          0x7
 183
 184 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 185         { 0,  0, 4, "IfInOctets"                                },
 186         { 0,  4, 4, "EtherStatsOctets"                          },
 187         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 188         { 0, 10, 2, "EtherFragments"                            },
 189         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 190         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 191         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 192         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 193         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 194         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 195         { 0, 24, 2, "EtherOversizeStats"                        },
 196         { 0, 26, 2, "EtherStatsJabbers"                         },
 197         { 0, 28, 2, "IfInUcastPkts"                             },
 198         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 199         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 200         { 0, 34, 2, "EtherStatsDropEvents"                      },
 201         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 202         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 203         { 0, 40, 2, "Dot3InPauseFrames"                         },
 204         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 205         { 0, 44, 4, "IfOutOctets"                               },
 206         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 207         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 208         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 209         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 210         { 0, 56, 2, "EtherStatsCollisions"                      },
 211         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 212         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 213         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 214
 215         /*
 216          * The following counters are accessible at a different
 217          * base address.
 218          */
 219         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 220         { 1,  2, 2, "IfOutUcastPkts"                            },
 221         { 1,  4, 2, "IfOutMulticastPkts"                        },
 222         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 223 };
 224
 225 #define REG_WR(_smi, _reg, _val)                                        \
 226         do {                                                            \
 227                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 228                 if (err)                                                \
 229                         return err;                                     \
 230         } while (0)
 231
 232 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 233         do {                                                            \
 234                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 235                 if (err)                                                \
 236                         return err;                                     \
 237         } while (0)
 238
 239 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 240 {
 241         int timeout = 10;
 242         u32 data;
 243
 244         rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
 245                                     RTL8366S_CHIP_CTRL_RESET_HW);
 246         do {
 247                 msleep(1);
 248                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 249                         return -EIO;
 250
 251                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 252                         break;
 253         } while (--timeout);
 254
 255         if (!timeout) {
 256                 printk("Timeout waiting for the switch to reset\n");
 257                 return -EIO;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 264                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 265 {
 266         u32 reg;
 267         int ret;
 268
 269         if (phy_no > RTL8366S_PHY_NO_MAX)
 270                 return -EINVAL;
 271
 272         if (page > RTL8366S_PHY_PAGE_MAX)
 273                 return -EINVAL;
 274
 275         if (addr > RTL8366S_PHY_ADDR_MAX)
 276                 return -EINVAL;
 277
 278         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 279                                     RTL8366S_PHY_CTRL_READ);
 280         if (ret)
 281                 return ret;
 282
 283         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 284               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 285               (addr & RTL8366S_PHY_REG_MASK);
 286
 287         ret = rtl8366_smi_write_reg(smi, reg, 0);
 288         if (ret)
 289                 return ret;
 290
 291         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 292         if (ret)
 293                 return ret;
 294
 295         return 0;
 296 }
 297
 298 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 299                                   u32 phy_no, u32 page, u32 addr, u32 data)
 300 {
 301         u32 reg;
 302         int ret;
 303
 304         if (phy_no > RTL8366S_PHY_NO_MAX)
 305                 return -EINVAL;
 306
 307         if (page > RTL8366S_PHY_PAGE_MAX)
 308                 return -EINVAL;
 309
 310         if (addr > RTL8366S_PHY_ADDR_MAX)
 311                 return -EINVAL;
 312
 313         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 314                                     RTL8366S_PHY_CTRL_WRITE);
 315         if (ret)
 316                 return ret;
 317
 318         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 319               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 320               (addr & RTL8366S_PHY_REG_MASK);
 321
 322         ret = rtl8366_smi_write_reg(smi, reg, data);
 323         if (ret)
 324                 return ret;
 325
 326         return 0;
 327 }
 328
 329 static int rtl8366s_set_green_port(struct rtl8366_smi *smi, int port, int enable)
 330 {
 331         int err;
 332         u32 phyData;
 333
 334         if (port >= RTL8366S_NUM_PORTS)
 335                 return -EINVAL;
 336
 337         err = rtl8366s_read_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData);
 338         if (err)
 339                 return err;
 340
 341         if (enable)
 342                 phyData |= RTL8366S_PHY_POWER_SAVING_MASK;
 343         else
 344                 phyData &= ~RTL8366S_PHY_POWER_SAVING_MASK;
 345
 346         err = rtl8366s_write_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, phyData);
 347         if (err)
 348                 return err;
 349
 350         return 0;
 351 }
 352
 353 static int rtl8366s_set_green(struct rtl8366_smi *smi, int enable)
 354 {
 355         int err;
 356         unsigned i;
 357         u32 data = 0;
 358
 359         if (!enable) {
 360                 for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) {
 361                         rtl8366s_set_green_port(smi, i, 0);
 362                 }
 363         }
 364
 365         if (enable)
 366                 data = (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT);
 367
 368         REG_RMW(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, RTL8366S_GREEN_ETHERNET_CTRL_MASK, data);
 369
 370         return 0;
 371 }
 372
 373 static int rtl8366s_setup(struct rtl8366_smi *smi)
 374 {
 375         struct rtl8366_platform_data *pdata;
 376         int err;
 377         unsigned i;
 378 #ifdef CONFIG_OF
 379         struct device_node *np;
 380         unsigned num_initvals;
 381         const __be32 *paddr;
 382 #endif
 383
 384         pdata = smi->parent->platform_data;
 385         if (pdata && pdata->num_initvals && pdata->initvals) {
 386                 dev_info(smi->parent, "applying initvals\n");
 387                 for (i = 0; i < pdata->num_initvals; i++)
 388                         REG_WR(smi, pdata->initvals[i].reg,
 389                                pdata->initvals[i].val);
 390         }
 391
 392 #ifdef CONFIG_OF
 393         np = smi->parent->of_node;
 394
 395         paddr = of_get_property(np, "realtek,initvals", &num_initvals);
 396         if (paddr) {
 397                 dev_info(smi->parent, "applying initvals from DTS\n");
 398
 399                 if (num_initvals < (2 * sizeof(*paddr)))
 400                         return -EINVAL;
 401
 402                 num_initvals /= sizeof(*paddr);
 403
 404                 for (i = 0; i < num_initvals - 1; i += 2) {
 405                         u32 reg = be32_to_cpup(paddr + i);
 406                         u32 val = be32_to_cpup(paddr + i + 1);
 407
 408                         REG_WR(smi, reg, val);
 409                 }
 410         }
 411
 412         if (of_property_read_bool(np, "realtek,green-ethernet-features")) {
 413                 dev_info(smi->parent, "activating Green Ethernet features\n");
 414
 415                 err = rtl8366s_set_green(smi, 1);
 416                 if (err)
 417                         return err;
 418
 419                 for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) {
 420                         err = rtl8366s_set_green_port(smi, i, 1);
 421                         if (err)
 422                                 return err;
 423                 }
 424         }
 425 #endif
 426
 427         /* set maximum packet length to 1536 bytes */
 428         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 429                 RTL8366S_SGCR_MAX_LENGTH_1536);
 430
 431         /* enable learning for all ports */
 432         REG_WR(smi, RTL8366S_SSCR0, 0);
 433
 434         /* enable auto ageing for all ports */
 435         REG_WR(smi, RTL8366S_SSCR1, 0);
 436
 437         /*
 438          * discard VLAN tagged packets if the port is not a member of
 439          * the VLAN with which the packets is associated.
 440          */
 441         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 442
 443         /* don't drop packets whose DA has not been learned */
 444         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 445
 446         return 0;
 447 }
 448
 449 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 450                                    int port, unsigned long long *val)
 451 {
 452         int i;
 453         int err;
 454         u32 addr, data;
 455         u64 mibvalue;
 456
 457         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 458                 return -EINVAL;
 459
 460         switch (rtl8366s_mib_counters[counter].base) {
 461         case 0:
 462                 addr = RTL8366S_MIB_COUNTER_BASE +
 463                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 464                 break;
 465
 466         case 1:
 467                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 468                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 469                 break;
 470
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         addr += rtl8366s_mib_counters[counter].offset;
 476
 477         /*
 478          * Writing access counter address first
 479          * then ASIC will prepare 64bits counter wait for being retrived
 480          */
 481         data = 0; /* writing data will be discard by ASIC */
 482         err = rtl8366_smi_write_reg(smi, addr, data);
 483         if (err)
 484                 return err;
 485
 486         /* read MIB control register */
 487         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 488         if (err)
 489                 return err;
 490
 491         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 492                 return -EBUSY;
 493
 494         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 495                 return -EIO;
 496
 497         mibvalue = 0;
 498         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 499                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 500                 if (err)
 501                         return err;
 502
 503                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 504         }
 505
 506         *val = mibvalue;
 507         return 0;
 508 }
 509
 510 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 511                                 struct rtl8366_vlan_4k *vlan4k)
 512 {
 513         u32 data[2];
 514         int err;
 515         int i;
 516
 517         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 518
 519         if (vid >= RTL8366S_NUM_VIDS)
 520                 return -EINVAL;
 521
 522         /* write VID */
 523         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 524                                     vid & RTL8366S_VLAN_VID_MASK);
 525         if (err)
 526                 return err;
 527
 528         /* write table access control word */
 529         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 530                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 531         if (err)
 532                 return err;
 533
 534         for (i = 0; i < 2; i++) {
 535                 err = rtl8366_smi_read_reg(smi,
 536                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 537                                            &data[i]);
 538                 if (err)
 539                         return err;
 540         }
 541
 542         vlan4k->vid = vid;
 543         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 544                         RTL8366S_VLAN_UNTAG_MASK;
 545         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 546         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 547                         RTL8366S_VLAN_FID_MASK;
 548
 549         return 0;
 550 }
 551
 552 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 553                                 const struct rtl8366_vlan_4k *vlan4k)
 554 {
 555         u32 data[2];
 556         int err;
 557         int i;
 558
 559         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 560             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 561             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 562             vlan4k->fid > RTL8366S_FIDMAX)
 563                 return -EINVAL;
 564
 565         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 566         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 567                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 568                         RTL8366S_VLAN_UNTAG_SHIFT) |
 569                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 570                         RTL8366S_VLAN_FID_SHIFT);
 571
 572         for (i = 0; i < 2; i++) {
 573                 err = rtl8366_smi_write_reg(smi,
 574                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 575                                             data[i]);
 576                 if (err)
 577                         return err;
 578         }
 579
 580         /* write table access control word */
 581         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 582                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 583
 584         return err;
 585 }
 586
 587 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 588                                 struct rtl8366_vlan_mc *vlanmc)
 589 {
 590         u32 data[2];
 591         int err;
 592         int i;
 593
 594         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 595
 596         if (index >= RTL8366S_NUM_VLANS)
 597                 return -EINVAL;
 598
 599         for (i = 0; i < 2; i++) {
 600                 err = rtl8366_smi_read_reg(smi,
 601                                            RTL8366S_VLAN_MC_BASE(index) + i,
 602                                            &data[i]);
 603                 if (err)
 604                         return err;
 605         }
 606
 607         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 608         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 609                            RTL8366S_VLAN_PRIORITY_MASK;
 610         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 611                         RTL8366S_VLAN_UNTAG_MASK;
 612         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 613         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 614                       RTL8366S_VLAN_FID_MASK;
 615
 616         return 0;
 617 }
 618
 619 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 620                                 const struct rtl8366_vlan_mc *vlanmc)
 621 {
 622         u32 data[2];
 623         int err;
 624         int i;
 625
 626         if (index >= RTL8366S_NUM_VLANS ||
 627             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 628             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 629             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 630             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 631             vlanmc->fid > RTL8366S_FIDMAX)
 632                 return -EINVAL;
 633
 634         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 635                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 636                         RTL8366S_VLAN_PRIORITY_SHIFT);
 637         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 638                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 639                         RTL8366S_VLAN_UNTAG_SHIFT) |
 640                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 641                         RTL8366S_VLAN_FID_SHIFT);
 642
 643         for (i = 0; i < 2; i++) {
 644                 err = rtl8366_smi_write_reg(smi,
 645                                             RTL8366S_VLAN_MC_BASE(index) + i,
 646                                             data[i]);
 647                 if (err)
 648                         return err;
 649         }
 650
 651         return 0;
 652 }
 653
 654 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 655 {
 656         u32 data;
 657         int err;
 658
 659         if (port >= RTL8366S_NUM_PORTS)
 660                 return -EINVAL;
 661
 662         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 663                                    &data);
 664         if (err)
 665                 return err;
 666
 667         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 668                RTL8366S_PORT_VLAN_CTRL_MASK;
 669
 670         return 0;
 671 }
 672
 673 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 674 {
 675         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 676                 return -EINVAL;
 677
 678         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 679                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 680                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 681                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 682                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 683 }
 684
 685 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 686 {
 687         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 688                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 689 }
 690
 691 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 692 {
 693         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 694                                 1, (enable) ? 1 : 0);
 695 }
 696
 697 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 698 {
 699         unsigned max = RTL8366S_NUM_VLANS;
 700
 701         if (smi->vlan4k_enabled)
 702                 max = RTL8366S_NUM_VIDS - 1;
 703
 704         if (vlan == 0 || vlan >= max)
 705                 return 0;
 706
 707         return 1;
 708 }
 709
 710 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 711 {
 712         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 713                                 (enable) ? 0 : (1 << port));
 714 }
 715
 716 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 717                                   const struct switch_attr *attr,
 718                                   struct switch_val *val)
 719 {
 720         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 721
 722         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 723 }
 724
 725 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 726                                      const struct switch_attr *attr,
 727                                      struct switch_val *val)
 728 {
 729         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 730         u32 data;
 731
 732         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 733
 734         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 735
 736         return 0;
 737 }
 738
 739 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 740                                     const struct switch_attr *attr,
 741                                     struct switch_val *val)
 742 {
 743         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 744
 745         if (val->value.i >= 6)
 746                 return -EINVAL;
 747
 748         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 749                                 RTL8366S_LED_BLINKRATE_MASK,
 750                                 val->value.i);
 751 }
 752
 753 static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
 754                                         const struct switch_attr *attr,
 755                                         struct switch_val *val)
 756 {
 757         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 758         u32 data;
 759
 760         rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
 761
 762         val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
 763
 764         return 0;
 765 }
 766
 767 static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
 768                                         const struct switch_attr *attr,
 769                                         struct switch_val *val)
 770 {
 771         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 772         char length_code;
 773
 774         switch (val->value.i) {
 775                 case 0:
 776                         length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
 777                         break;
 778                 case 1:
 779                         length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
 780                         break;
 781                 case 2:
 782                         length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
 783                         break;
 784                 case 3:
 785                         length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
 786                         break;
 787                 default:
 788                         return -EINVAL;
 789         }
 790
 791         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
 792                         RTL8366S_SGCR_MAX_LENGTH_MASK,
 793                         length_code);
 794 }
 795
 796 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 797                                            const struct switch_attr *attr,
 798                                            struct switch_val *val)
 799 {
 800         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 801         u32 data;
 802
 803         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 804         val->value.i = !data;
 805
 806         return 0;
 807 }
 808
 809
 810 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 811                                            const struct switch_attr *attr,
 812                                            struct switch_val *val)
 813 {
 814         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 815         u32 portmask = 0;
 816         int err = 0;
 817
 818         if (!val->value.i)
 819                 portmask = RTL8366S_PORT_ALL;
 820
 821         /* set learning for all ports */
 822         REG_WR(smi, RTL8366S_SSCR0, portmask);
 823
 824         /* set auto ageing for all ports */
 825         REG_WR(smi, RTL8366S_SSCR1, portmask);
 826
 827         return 0;
 828 }
 829
 830 static int rtl8366s_sw_get_green(struct switch_dev *dev,
 831                               const struct switch_attr *attr,
 832                               struct switch_val *val)
 833 {
 834         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 835         u32 data;
 836         int err;
 837
 838         err = rtl8366_smi_read_reg(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, &data);
 839         if (err)
 840                 return err;
 841
 842         val->value.i = ((data & (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT)) != 0) ? 1 : 0;
 843
 844         return 0;
 845 }
 846
 847 static int rtl8366s_sw_set_green(struct switch_dev *dev,
 848                                  const struct switch_attr *attr,
 849                                  struct switch_val *val)
 850 {
 851         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 852
 853         return rtl8366s_set_green(smi, val->value.i);
 854 }
 855
 856 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 857                                      int port,
 858                                      struct switch_port_link *link)
 859 {
 860         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 861         u32 data = 0;
 862         u32 speed;
 863
 864         if (port >= RTL8366S_NUM_PORTS)
 865                 return -EINVAL;
 866
 867         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
 868                              &data);
 869
 870         if (port % 2)
 871                 data = data >> 8;
 872
 873         link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
 874         if (!link->link)
 875                 return 0;
 876
 877         link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
 878         link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
 879         link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
 880         link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
 881
 882         speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
 883         switch (speed) {
 884         case 0:
 885                 link->speed = SWITCH_PORT_SPEED_10;
 886                 break;
 887         case 1:
 888                 link->speed = SWITCH_PORT_SPEED_100;
 889                 break;
 890         case 2:
 891                 link->speed = SWITCH_PORT_SPEED_1000;
 892                 break;
 893         default:
 894                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 895                 break;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 902                                     const struct switch_attr *attr,
 903                                     struct switch_val *val)
 904 {
 905         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 906         u32 data;
 907         u32 mask;
 908         u32 reg;
 909
 910         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 911             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 912                 return -EINVAL;
 913
 914         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 915                 reg = RTL8366S_LED_BLINKRATE_REG;
 916                 mask = 0xF << 4;
 917                 data = val->value.i << 4;
 918         } else {
 919                 reg = RTL8366S_LED_CTRL_REG;
 920                 mask = 0xF << (val->port_vlan * 4),
 921                 data = val->value.i << (val->port_vlan * 4);
 922         }
 923
 924         return rtl8366_smi_rmwr(smi, reg, mask, data);
 925 }
 926
 927 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 928                                     const struct switch_attr *attr,
 929                                     struct switch_val *val)
 930 {
 931         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 932         u32 data = 0;
 933
 934         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 935                 return -EINVAL;
 936
 937         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 938         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 939
 940         return 0;
 941 }
 942
 943 static int rtl8366s_sw_get_green_port(struct switch_dev *dev,
 944                                       const struct switch_attr *attr,
 945                                       struct switch_val *val)
 946 {
 947         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 948         int err;
 949         u32 phyData;
 950
 951         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 952                 return -EINVAL;
 953
 954         err = rtl8366s_read_phy_reg(smi, val->port_vlan, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData);
 955         if (err)
 956                 return err;
 957
 958         val->value.i = ((phyData & RTL8366S_PHY_POWER_SAVING_MASK) != 0) ? 1 : 0;
 959
 960         return 0;
 961 }
 962
 963 static int rtl8366s_sw_set_green_port(struct switch_dev *dev,
 964                                       const struct switch_attr *attr,
 965                                       struct switch_val *val)
 966 {
 967         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 968         return rtl8366s_set_green_port(smi, val->port_vlan, val->value.i);
 969 }
 970
 971 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 972                                        const struct switch_attr *attr,
 973                                        struct switch_val *val)
 974 {
 975         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 976
 977         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 978                 return -EINVAL;
 979
 980
 981         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 982                                 0, (1 << (val->port_vlan + 3)));
 983 }
 984
 985 static struct switch_attr rtl8366s_globals[] = {
 986         {
 987                 .type = SWITCH_TYPE_INT,
 988                 .name = "enable_learning",
 989                 .description = "Enable learning, enable aging",
 990                 .set = rtl8366s_sw_set_learning_enable,
 991                 .get = rtl8366s_sw_get_learning_enable,
 992                 .max = 1,
 993         }, {
 994                 .type = SWITCH_TYPE_INT,
 995                 .name = "enable_vlan",
 996                 .description = "Enable VLAN mode",
 997                 .set = rtl8366_sw_set_vlan_enable,
 998                 .get = rtl8366_sw_get_vlan_enable,
 999                 .max = 1,
1000                 .ofs = 1
1001         }, {
1002                 .type = SWITCH_TYPE_INT,
1003                 .name = "enable_vlan4k",
1004                 .description = "Enable VLAN 4K mode",
1005                 .set = rtl8366_sw_set_vlan_enable,
1006                 .get = rtl8366_sw_get_vlan_enable,
1007                 .max = 1,
1008                 .ofs = 2
1009         }, {
1010                 .type = SWITCH_TYPE_NOVAL,
1011                 .name = "reset_mibs",
1012                 .description = "Reset all MIB counters",
1013                 .set = rtl8366s_sw_reset_mibs,
1014         }, {
1015                 .type = SWITCH_TYPE_INT,
1016                 .name = "blinkrate",
1017                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1018                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1019                 .set = rtl8366s_sw_set_blinkrate,
1020                 .get = rtl8366s_sw_get_blinkrate,
1021                 .max = 5
1022         }, {
1023                 .type = SWITCH_TYPE_INT,
1024                 .name = "max_length",
1025                 .description = "Get/Set the maximum length of valid packets"
1026                 " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
1027                 .set = rtl8366s_sw_set_max_length,
1028                 .get = rtl8366s_sw_get_max_length,
1029                 .max = 3,
1030         }, {
1031                 .type = SWITCH_TYPE_INT,
1032                 .name = "green_mode",
1033                 .description = "Get/Set the router green feature",
1034                 .set = rtl8366s_sw_set_green,
1035                 .get = rtl8366s_sw_get_green,
1036                 .max = 1,
1037         },
1038 };
1039
1040 static struct switch_attr rtl8366s_port[] = {
1041         {
1042                 .type = SWITCH_TYPE_NOVAL,
1043                 .name = "reset_mib",
1044                 .description = "Reset single port MIB counters",
1045                 .set = rtl8366s_sw_reset_port_mibs,
1046         }, {
1047                 .type = SWITCH_TYPE_STRING,
1048                 .name = "mib",
1049                 .description = "Get MIB counters for port",
1050                 .max = 33,
1051                 .set = NULL,
1052                 .get = rtl8366_sw_get_port_mib,
1053         }, {
1054                 .type = SWITCH_TYPE_INT,
1055                 .name = "led",
1056                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1057                 .max = 15,
1058                 .set = rtl8366s_sw_set_port_led,
1059                 .get = rtl8366s_sw_get_port_led,
1060         }, {
1061                 .type = SWITCH_TYPE_INT,
1062                 .name = "green_port",
1063                 .description = "Get/Set port green feature (0 - 1)",
1064                 .max = 1,
1065                 .set = rtl8366s_sw_set_green_port,
1066                 .get = rtl8366s_sw_get_green_port,
1067         },
1068 };
1069
1070 static struct switch_attr rtl8366s_vlan[] = {
1071         {
1072                 .type = SWITCH_TYPE_STRING,
1073                 .name = "info",
1074                 .description = "Get vlan information",
1075                 .max = 1,
1076                 .set = NULL,
1077                 .get = rtl8366_sw_get_vlan_info,
1078         }, {
1079                 .type = SWITCH_TYPE_INT,
1080                 .name = "fid",
1081                 .description = "Get/Set vlan FID",
1082                 .max = RTL8366S_FIDMAX,
1083                 .set = rtl8366_sw_set_vlan_fid,
1084                 .get = rtl8366_sw_get_vlan_fid,
1085         },
1086 };
1087
1088 static const struct switch_dev_ops rtl8366_ops = {
1089         .attr_global = {
1090                 .attr = rtl8366s_globals,
1091                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1092         },
1093         .attr_port = {
1094                 .attr = rtl8366s_port,
1095                 .n_attr = ARRAY_SIZE(rtl8366s_port),
1096         },
1097         .attr_vlan = {
1098                 .attr = rtl8366s_vlan,
1099                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1100         },
1101
1102         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1103         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1104         .get_port_pvid = rtl8366_sw_get_port_pvid,
1105         .set_port_pvid = rtl8366_sw_set_port_pvid,
1106         .reset_switch = rtl8366_sw_reset_switch,
1107         .get_port_link = rtl8366s_sw_get_port_link,
1108 };
1109
1110 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
1111 {
1112         struct switch_dev *dev = &smi->sw_dev;
1113         int err;
1114
1115         dev->name = "RTL8366S";
1116         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
1117         dev->ports = RTL8366S_NUM_PORTS;
1118         dev->vlans = RTL8366S_NUM_VIDS;
1119         dev->ops = &rtl8366_ops;
1120         dev->alias = dev_name(smi->parent);
1121
1122         err = register_switch(dev, NULL);
1123         if (err)
1124                 dev_err(smi->parent, "switch registration failed\n");
1125
1126         return err;
1127 }
1128
1129 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
1130 {
1131         unregister_switch(&smi->sw_dev);
1132 }
1133
1134 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1135 {
1136         struct rtl8366_smi *smi = bus->priv;
1137         u32 val = 0;
1138         int err;
1139
1140         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1141         if (err)
1142                 return 0xffff;
1143
1144         return val;
1145 }
1146
1147 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1148 {
1149         struct rtl8366_smi *smi = bus->priv;
1150         u32 t;
1151         int err;
1152
1153         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1154         /* flush write */
1155         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1156
1157         return err;
1158 }
1159
1160 static int rtl8366s_detect(struct rtl8366_smi *smi)
1161 {
1162         u32 chip_id = 0;
1163         u32 chip_ver = 0;
1164         int ret;
1165
1166         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1167         if (ret) {
1168                 dev_err(smi->parent, "unable to read chip id\n");
1169                 return ret;
1170         }
1171
1172         switch (chip_id) {
1173         case RTL8366S_CHIP_ID_8366:
1174                 break;
1175         default:
1176                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1177                 return -ENODEV;
1178         }
1179
1180         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1181                                    &chip_ver);
1182         if (ret) {
1183                 dev_err(smi->parent, "unable to read chip version\n");
1184                 return ret;
1185         }
1186
1187         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1188                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1189
1190         return 0;
1191 }
1192
1193 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1194         .detect         = rtl8366s_detect,
1195         .reset_chip     = rtl8366s_reset_chip,
1196         .setup          = rtl8366s_setup,
1197
1198         .mii_read       = rtl8366s_mii_read,
1199         .mii_write      = rtl8366s_mii_write,
1200
1201         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1202         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1203         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1204         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1205         .get_mc_index   = rtl8366s_get_mc_index,
1206         .set_mc_index   = rtl8366s_set_mc_index,
1207         .get_mib_counter = rtl8366_get_mib_counter,
1208         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1209         .enable_vlan    = rtl8366s_enable_vlan,
1210         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1211         .enable_port    = rtl8366s_enable_port,
1212 };
1213
1214 static int rtl8366s_probe(struct platform_device *pdev)
1215 {
1216         static int rtl8366_smi_version_printed;
1217         struct rtl8366_smi *smi;
1218         int err;
1219
1220         if (!rtl8366_smi_version_printed++)
1221                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1222                        " version " RTL8366S_DRIVER_VER"\n");
1223
1224         smi = rtl8366_smi_probe(pdev);
1225         if (!smi)
1226                 return -ENODEV;
1227
1228         smi->clk_delay = 10;
1229         smi->cmd_read = 0xa9;
1230         smi->cmd_write = 0xa8;
1231         smi->ops = &rtl8366s_smi_ops;
1232         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1233         smi->num_ports = RTL8366S_NUM_PORTS;
1234         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1235         smi->mib_counters = rtl8366s_mib_counters;
1236         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1237
1238         err = rtl8366_smi_init(smi);
1239         if (err)
1240                 goto err_free_smi;
1241
1242         platform_set_drvdata(pdev, smi);
1243
1244         err = rtl8366s_switch_init(smi);
1245         if (err)
1246                 goto err_clear_drvdata;
1247
1248         return 0;
1249
1250  err_clear_drvdata:
1251         platform_set_drvdata(pdev, NULL);
1252         rtl8366_smi_cleanup(smi);
1253  err_free_smi:
1254         kfree(smi);
1255         return err;
1256 }
1257
1258 static int rtl8366s_remove(struct platform_device *pdev)
1259 {
1260         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1261
1262         if (smi) {
1263                 rtl8366s_switch_cleanup(smi);
1264                 platform_set_drvdata(pdev, NULL);
1265                 rtl8366_smi_cleanup(smi);
1266                 kfree(smi);
1267         }
1268
1269         return 0;
1270 }
1271
1272 #ifdef CONFIG_OF
1273 static const struct of_device_id rtl8366s_match[] = {
1274         { .compatible = "realtek,rtl8366s" },
1275         {},
1276 };
1277 MODULE_DEVICE_TABLE(of, rtl8366s_match);
1278 #endif
1279
1280 static struct platform_driver rtl8366s_driver = {
1281         .driver = {
1282                 .name           = RTL8366S_DRIVER_NAME,
1283                 .owner          = THIS_MODULE,
1284 #ifdef CONFIG_OF
1285                 .of_match_table = of_match_ptr(rtl8366s_match),
1286 #endif
1287         },
1288         .probe          = rtl8366s_probe,
1289         .remove         = rtl8366s_remove,
1290 };
1291
1292 static int __init rtl8366s_module_init(void)
1293 {
1294         return platform_driver_register(&rtl8366s_driver);
1295 }
1296 module_init(rtl8366s_module_init);
1297
1298 static void __exit rtl8366s_module_exit(void)
1299 {
1300         platform_driver_unregister(&rtl8366s_driver);
1301 }
1302 module_exit(rtl8366s_module_exit);
1303
1304 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1305 MODULE_VERSION(RTL8366S_DRIVER_VER);
1306 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1307 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1308 MODULE_LICENSE("GPL v2");
1309 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);