target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366RB ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
   7  * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/of.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/delay.h>
  21 #include <linux/skbuff.h>
  22 #include <linux/rtl8366.h>
  23
  24 #include "rtl8366_smi.h"
  25
  26 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  27 #define RTL8366RB_DRIVER_VER    "0.2.4"
  28
  29 #define RTL8366RB_PHY_NO_MAX    4
  30 #define RTL8366RB_PHY_PAGE_MAX  7
  31 #define RTL8366RB_PHY_ADDR_MAX  31
  32
  33 /* Switch Global Configuration register */
  34 #define RTL8366RB_SGCR                          0x0000
  35 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  36 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  39 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  40 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  41 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  42 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  43 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  44
  45 /* Port Enable Control register */
  46 #define RTL8366RB_PECR                          0x0001
  47
  48 /* Port Mirror Control Register */
  49 #define RTL8366RB_PMCR                          0x0007
  50 #define RTL8366RB_PMCR_SOURCE_PORT(_x)          (_x)
  51 #define RTL8366RB_PMCR_SOURCE_PORT_MASK         0x000f
  52 #define RTL8366RB_PMCR_MONITOR_PORT(_x)         ((_x) << 4)
  53 #define RTL8366RB_PMCR_MONITOR_PORT_MASK        0x00f0
  54 #define RTL8366RB_PMCR_MIRROR_RX                BIT(8)
  55 #define RTL8366RB_PMCR_MIRROR_TX                BIT(9)
  56 #define RTL8366RB_PMCR_MIRROR_SPC               BIT(10)
  57 #define RTL8366RB_PMCR_MIRROR_ISO               BIT(11)
  58
  59 /* Switch Security Control registers */
  60 #define RTL8366RB_SSCR0                         0x0002
  61 #define RTL8366RB_SSCR1                         0x0003
  62 #define RTL8366RB_SSCR2                         0x0004
  63 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  64
  65 #define RTL8366RB_RESET_CTRL_REG                0x0100
  66 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  67 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  68
  69 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  70 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  71 #define RTL8366RB_CHIP_ID_REG                   0x0509
  72 #define RTL8366RB_CHIP_ID_8366                  0x5937
  73
  74 /* PHY registers control */
  75 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  76 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  77
  78 #define RTL8366RB_PHY_CTRL_READ                 1
  79 #define RTL8366RB_PHY_CTRL_WRITE                0
  80
  81 #define RTL8366RB_PHY_REG_MASK                  0x1f
  82 #define RTL8366RB_PHY_PAGE_OFFSET               5
  83 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  84 #define RTL8366RB_PHY_NO_OFFSET                 9
  85 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  86
  87 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  88
  89 /* LED control registers */
  90 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  91 #define RTL8366RB_LED_BLINKRATE_BIT             0
  92 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  93
  94 #define RTL8366RB_LED_CTRL_REG                  0x0431
  95 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  96 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  97
  98 #define RTL8366RB_MIB_COUNT                     33
  99 #define RTL8366RB_GLOBAL_MIB_COUNT              1
 100 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
 101 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
 102 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
 103 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
 104 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
 105 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
 106 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
 107 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
 108
 109 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
 110 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
 111                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 112 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 113 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 114
 115
 116 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 117 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 118
 119
 120 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 121 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 122 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 123
 124 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 125
 126
 127 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 128 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 129 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 130 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 131 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 132 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 133 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 134
 135
 136 #define RTL8366RB_PORT_NUM_CPU          5
 137 #define RTL8366RB_NUM_PORTS             6
 138 #define RTL8366RB_NUM_VLANS             16
 139 #define RTL8366RB_NUM_LEDGROUPS         4
 140 #define RTL8366RB_NUM_VIDS              4096
 141 #define RTL8366RB_PRIORITYMAX           7
 142 #define RTL8366RB_FIDMAX                7
 143
 144
 145 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 146 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 147 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 148 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 149 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 150
 151 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 152
 153 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 154                                          RTL8366RB_PORT_2 |     \
 155                                          RTL8366RB_PORT_3 |     \
 156                                          RTL8366RB_PORT_4 |     \
 157                                          RTL8366RB_PORT_5 |     \
 158                                          RTL8366RB_PORT_CPU)
 159
 160 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 161                                          RTL8366RB_PORT_2 |     \
 162                                          RTL8366RB_PORT_3 |     \
 163                                          RTL8366RB_PORT_4 |     \
 164                                          RTL8366RB_PORT_5)
 165
 166 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 167                                          RTL8366RB_PORT_2 |     \
 168                                          RTL8366RB_PORT_3 |     \
 169                                          RTL8366RB_PORT_4)
 170
 171 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 172
 173 #define RTL8366RB_VLAN_VID_MASK         0xfff
 174 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 175 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 176 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 177 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 178 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 179 #define RTL8366RB_VLAN_FID_MASK         0x7
 180
 181
 182 /* Port ingress bandwidth control */
 183 #define RTL8366RB_IB_BASE               0x0200
 184 #define RTL8366RB_IB_REG(pnum)          (RTL8366RB_IB_BASE + pnum)
 185 #define RTL8366RB_IB_BDTH_MASK          0x3fff
 186 #define RTL8366RB_IB_PREIFG_OFFSET      14
 187 #define RTL8366RB_IB_PREIFG_MASK        (1 << RTL8366RB_IB_PREIFG_OFFSET)
 188
 189 /* Port egress bandwidth control */
 190 #define RTL8366RB_EB_BASE               0x02d1
 191 #define RTL8366RB_EB_REG(pnum)          (RTL8366RB_EB_BASE + pnum)
 192 #define RTL8366RB_EB_BDTH_MASK          0x3fff
 193 #define RTL8366RB_EB_PREIFG_REG 0x02f8
 194 #define RTL8366RB_EB_PREIFG_OFFSET      9
 195 #define RTL8366RB_EB_PREIFG_MASK        (1 << RTL8366RB_EB_PREIFG_OFFSET)
 196
 197 #define RTL8366RB_BDTH_SW_MAX           1048512
 198 #define RTL8366RB_BDTH_UNIT             64
 199 #define RTL8366RB_BDTH_REG_DEFAULT      16383
 200
 201 /* QOS */
 202 #define RTL8366RB_QOS_BIT               15
 203 #define RTL8366RB_QOS_MASK              (1 << RTL8366RB_QOS_BIT)
 204 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
 205 #define RTL8366RB_QOS_DEFAULT_PREIFG    1
 206
 207
 208 #define RTL8366RB_MIB_RXB_ID            0       /* IfInOctets */
 209 #define RTL8366RB_MIB_TXB_ID            20      /* IfOutOctets */
 210
 211 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 212         { 0,  0, 4, "IfInOctets"                                },
 213         { 0,  4, 4, "EtherStatsOctets"                          },
 214         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 215         { 0, 10, 2, "EtherFragments"                            },
 216         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 217         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 218         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 219         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 220         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 221         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 222         { 0, 24, 2, "EtherOversizeStats"                        },
 223         { 0, 26, 2, "EtherStatsJabbers"                         },
 224         { 0, 28, 2, "IfInUcastPkts"                             },
 225         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 226         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 227         { 0, 34, 2, "EtherStatsDropEvents"                      },
 228         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 229         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 230         { 0, 40, 2, "Dot3InPauseFrames"                         },
 231         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 232         { 0, 44, 4, "IfOutOctets"                               },
 233         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 234         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 235         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 236         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 237         { 0, 56, 2, "EtherStatsCollisions"                      },
 238         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 239         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 240         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 241         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 242         { 0, 66, 2, "IfOutUcastPkts"                            },
 243         { 0, 68, 2, "IfOutMulticastPkts"                        },
 244         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 245 };
 246
 247 #define REG_WR(_smi, _reg, _val)                                        \
 248         do {                                                            \
 249                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 250                 if (err)                                                \
 251                         return err;                                     \
 252         } while (0)
 253
 254 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 255         do {                                                            \
 256                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 257                 if (err)                                                \
 258                         return err;                                     \
 259         } while (0)
 260
 261 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 262 {
 263         int timeout = 10;
 264         u32 data;
 265
 266         rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
 267                                     RTL8366RB_CHIP_CTRL_RESET_HW);
 268         do {
 269                 msleep(1);
 270                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 271                         return -EIO;
 272
 273                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 274                         break;
 275         } while (--timeout);
 276
 277         if (!timeout) {
 278                 printk("Timeout waiting for the switch to reset\n");
 279                 return -EIO;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int rtl8366rb_setup(struct rtl8366_smi *smi)
 286 {
 287         int err;
 288 #ifdef CONFIG_OF
 289         unsigned i;
 290         struct device_node *np;
 291         unsigned num_initvals;
 292         const __be32 *paddr;
 293
 294         np = smi->parent->of_node;
 295
 296         paddr = of_get_property(np, "realtek,initvals", &num_initvals);
 297         if (paddr) {
 298                 dev_info(smi->parent, "applying initvals from DTS\n");
 299
 300                 if (num_initvals < (2 * sizeof(*paddr)))
 301                         return -EINVAL;
 302
 303                 num_initvals /= sizeof(*paddr);
 304
 305                 for (i = 0; i < num_initvals - 1; i += 2) {
 306                         u32 reg = be32_to_cpup(paddr + i);
 307                         u32 val = be32_to_cpup(paddr + i + 1);
 308
 309                         REG_WR(smi, reg, val);
 310                 }
 311         }
 312 #endif
 313
 314         /* set maximum packet length to 1536 bytes */
 315         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 316                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 317
 318         /* enable learning for all ports */
 319         REG_WR(smi, RTL8366RB_SSCR0, 0);
 320
 321         /* enable auto ageing for all ports */
 322         REG_WR(smi, RTL8366RB_SSCR1, 0);
 323
 324         /*
 325          * discard VLAN tagged packets if the port is not a member of
 326          * the VLAN with which the packets is associated.
 327          */
 328         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 329
 330         /* don't drop packets whose DA has not been learned */
 331         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 332
 333         return 0;
 334 }
 335
 336 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 337                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 338 {
 339         u32 reg;
 340         int ret;
 341
 342         if (phy_no > RTL8366RB_PHY_NO_MAX)
 343                 return -EINVAL;
 344
 345         if (page > RTL8366RB_PHY_PAGE_MAX)
 346                 return -EINVAL;
 347
 348         if (addr > RTL8366RB_PHY_ADDR_MAX)
 349                 return -EINVAL;
 350
 351         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 352                                     RTL8366RB_PHY_CTRL_READ);
 353         if (ret)
 354                 return ret;
 355
 356         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 357               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 358               (addr & RTL8366RB_PHY_REG_MASK);
 359
 360         ret = rtl8366_smi_write_reg(smi, reg, 0);
 361         if (ret)
 362                 return ret;
 363
 364         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 365         if (ret)
 366                 return ret;
 367
 368         return 0;
 369 }
 370
 371 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 372                                   u32 phy_no, u32 page, u32 addr, u32 data)
 373 {
 374         u32 reg;
 375         int ret;
 376
 377         if (phy_no > RTL8366RB_PHY_NO_MAX)
 378                 return -EINVAL;
 379
 380         if (page > RTL8366RB_PHY_PAGE_MAX)
 381                 return -EINVAL;
 382
 383         if (addr > RTL8366RB_PHY_ADDR_MAX)
 384                 return -EINVAL;
 385
 386         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 387                                     RTL8366RB_PHY_CTRL_WRITE);
 388         if (ret)
 389                 return ret;
 390
 391         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 392               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 393               (addr & RTL8366RB_PHY_REG_MASK);
 394
 395         ret = rtl8366_smi_write_reg(smi, reg, data);
 396         if (ret)
 397                 return ret;
 398
 399         return 0;
 400 }
 401
 402 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 403                                      int port, unsigned long long *val)
 404 {
 405         int i;
 406         int err;
 407         u32 addr, data;
 408         u64 mibvalue;
 409
 410         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 411                 return -EINVAL;
 412
 413         addr = RTL8366RB_MIB_COUNTER_BASE +
 414                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 415                rtl8366rb_mib_counters[counter].offset;
 416
 417         /*
 418          * Writing access counter address first
 419          * then ASIC will prepare 64bits counter wait for being retrived
 420          */
 421         data = 0; /* writing data will be discard by ASIC */
 422         err = rtl8366_smi_write_reg(smi, addr, data);
 423         if (err)
 424                 return err;
 425
 426         /* read MIB control register */
 427         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 428         if (err)
 429                 return err;
 430
 431         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 432                 return -EBUSY;
 433
 434         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 435                 return -EIO;
 436
 437         mibvalue = 0;
 438         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 439                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 440                 if (err)
 441                         return err;
 442
 443                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 444         }
 445
 446         *val = mibvalue;
 447         return 0;
 448 }
 449
 450 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 451                                  struct rtl8366_vlan_4k *vlan4k)
 452 {
 453         u32 data[3];
 454         int err;
 455         int i;
 456
 457         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 458
 459         if (vid >= RTL8366RB_NUM_VIDS)
 460                 return -EINVAL;
 461
 462         /* write VID */
 463         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 464                                     vid & RTL8366RB_VLAN_VID_MASK);
 465         if (err)
 466                 return err;
 467
 468         /* write table access control word */
 469         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 470                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 471         if (err)
 472                 return err;
 473
 474         for (i = 0; i < 3; i++) {
 475                 err = rtl8366_smi_read_reg(smi,
 476                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 477                                            &data[i]);
 478                 if (err)
 479                         return err;
 480         }
 481
 482         vlan4k->vid = vid;
 483         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 484                         RTL8366RB_VLAN_UNTAG_MASK;
 485         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 486         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 487
 488         return 0;
 489 }
 490
 491 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 492                                  const struct rtl8366_vlan_4k *vlan4k)
 493 {
 494         u32 data[3];
 495         int err;
 496         int i;
 497
 498         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 499             vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
 500             vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 501             vlan4k->fid > RTL8366RB_FIDMAX)
 502                 return -EINVAL;
 503
 504         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 505         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 506                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 507                         RTL8366RB_VLAN_UNTAG_SHIFT);
 508         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 509
 510         for (i = 0; i < 3; i++) {
 511                 err = rtl8366_smi_write_reg(smi,
 512                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 513                                             data[i]);
 514                 if (err)
 515                         return err;
 516         }
 517
 518         /* write table access control word */
 519         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 520                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 521
 522         return err;
 523 }
 524
 525 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 526                                  struct rtl8366_vlan_mc *vlanmc)
 527 {
 528         u32 data[3];
 529         int err;
 530         int i;
 531
 532         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 533
 534         if (index >= RTL8366RB_NUM_VLANS)
 535                 return -EINVAL;
 536
 537         for (i = 0; i < 3; i++) {
 538                 err = rtl8366_smi_read_reg(smi,
 539                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 540                                            &data[i]);
 541                 if (err)
 542                         return err;
 543         }
 544
 545         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 546         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 547                            RTL8366RB_VLAN_PRIORITY_MASK;
 548         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 549                         RTL8366RB_VLAN_UNTAG_MASK;
 550         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 551         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 552
 553         return 0;
 554 }
 555
 556 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 557                                  const struct rtl8366_vlan_mc *vlanmc)
 558 {
 559         u32 data[3];
 560         int err;
 561         int i;
 562
 563         if (index >= RTL8366RB_NUM_VLANS ||
 564             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 565             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 566             vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
 567             vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 568             vlanmc->fid > RTL8366RB_FIDMAX)
 569                 return -EINVAL;
 570
 571         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 572                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 573                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 574         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 575                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 576                         RTL8366RB_VLAN_UNTAG_SHIFT);
 577         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 578
 579         for (i = 0; i < 3; i++) {
 580                 err = rtl8366_smi_write_reg(smi,
 581                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 582                                             data[i]);
 583                 if (err)
 584                         return err;
 585         }
 586
 587         return 0;
 588 }
 589
 590 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 591 {
 592         u32 data;
 593         int err;
 594
 595         if (port >= RTL8366RB_NUM_PORTS)
 596                 return -EINVAL;
 597
 598         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 599                                    &data);
 600         if (err)
 601                 return err;
 602
 603         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 604                RTL8366RB_PORT_VLAN_CTRL_MASK;
 605
 606         return 0;
 607
 608 }
 609
 610 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 611 {
 612         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 613                 return -EINVAL;
 614
 615         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 616                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 617                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 618                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 619                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 620 }
 621
 622 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 623 {
 624         unsigned max = RTL8366RB_NUM_VLANS;
 625
 626         if (smi->vlan4k_enabled)
 627                 max = RTL8366RB_NUM_VIDS - 1;
 628
 629         if (vlan == 0 || vlan >= max)
 630                 return 0;
 631
 632         return 1;
 633 }
 634
 635 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
 636 {
 637         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 638                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 639 }
 640
 641 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 642 {
 643         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 644                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 645                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 646 }
 647
 648 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
 649 {
 650         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
 651                                 (enable) ? 0 : (1 << port));
 652 }
 653
 654 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 655                                   const struct switch_attr *attr,
 656                                   struct switch_val *val)
 657 {
 658         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 659
 660         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 661                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 662 }
 663
 664 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 665                                      const struct switch_attr *attr,
 666                                      struct switch_val *val)
 667 {
 668         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 669         u32 data;
 670
 671         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 672
 673         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 674
 675         return 0;
 676 }
 677
 678 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 679                                     const struct switch_attr *attr,
 680                                     struct switch_val *val)
 681 {
 682         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 683
 684         if (val->value.i >= 6)
 685                 return -EINVAL;
 686
 687         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 688                                 RTL8366RB_LED_BLINKRATE_MASK,
 689                                 val->value.i);
 690 }
 691
 692 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
 693                                        const struct switch_attr *attr,
 694                                        struct switch_val *val)
 695 {
 696         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 697         u32 data;
 698
 699         rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
 700         val->value.i = !data;
 701
 702         return 0;
 703 }
 704
 705
 706 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
 707                                        const struct switch_attr *attr,
 708                                        struct switch_val *val)
 709 {
 710         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 711         u32 portmask = 0;
 712         int err = 0;
 713
 714         if (!val->value.i)
 715                 portmask = RTL8366RB_PORT_ALL;
 716
 717         /* set learning for all ports */
 718         REG_WR(smi, RTL8366RB_SSCR0, portmask);
 719
 720         /* set auto ageing for all ports */
 721         REG_WR(smi, RTL8366RB_SSCR1, portmask);
 722
 723         return 0;
 724 }
 725
 726 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 727                                      int port,
 728                                      struct switch_port_link *link)
 729 {
 730         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 731         u32 data = 0;
 732         u32 speed;
 733
 734         if (port >= RTL8366RB_NUM_PORTS)
 735                 return -EINVAL;
 736
 737         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
 738                              &data);
 739
 740         if (port % 2)
 741                 data = data >> 8;
 742
 743         link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
 744         if (!link->link)
 745                 return 0;
 746
 747         link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
 748         link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
 749         link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
 750         link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
 751
 752         speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
 753         switch (speed) {
 754         case 0:
 755                 link->speed = SWITCH_PORT_SPEED_10;
 756                 break;
 757         case 1:
 758                 link->speed = SWITCH_PORT_SPEED_100;
 759                 break;
 760         case 2:
 761                 link->speed = SWITCH_PORT_SPEED_1000;
 762                 break;
 763         default:
 764                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 765                 break;
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 772                                     const struct switch_attr *attr,
 773                                     struct switch_val *val)
 774 {
 775         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 776         u32 data;
 777         u32 mask;
 778         u32 reg;
 779
 780         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 781                 return -EINVAL;
 782
 783         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 784                 reg = RTL8366RB_LED_BLINKRATE_REG;
 785                 mask = 0xF << 4;
 786                 data = val->value.i << 4;
 787         } else {
 788                 reg = RTL8366RB_LED_CTRL_REG;
 789                 mask = 0xF << (val->port_vlan * 4),
 790                 data = val->value.i << (val->port_vlan * 4);
 791         }
 792
 793         return rtl8366_smi_rmwr(smi, reg, mask, data);
 794 }
 795
 796 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 797                                     const struct switch_attr *attr,
 798                                     struct switch_val *val)
 799 {
 800         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 801         u32 data = 0;
 802
 803         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 804                 return -EINVAL;
 805
 806         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 807         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 808
 809         return 0;
 810 }
 811
 812 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
 813                                     const struct switch_attr *attr,
 814                                     struct switch_val *val)
 815 {
 816         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 817         u32 mask, data;
 818
 819         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 820                 return -EINVAL;
 821
 822         mask = 1 << val->port_vlan ;
 823         if (val->value.i)
 824                 data = mask;
 825         else
 826                 data = 0;
 827
 828         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
 829 }
 830
 831 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
 832                                     const struct switch_attr *attr,
 833                                     struct switch_val *val)
 834 {
 835         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 836         u32 data;
 837
 838         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 839                 return -EINVAL;
 840
 841         rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
 842         if (data & (1 << val->port_vlan))
 843                 val->value.i = 1;
 844         else
 845                 val->value.i = 0;
 846
 847         return 0;
 848 }
 849
 850 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
 851                                     const struct switch_attr *attr,
 852                                     struct switch_val *val)
 853 {
 854         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 855
 856         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 857                 return -EINVAL;
 858
 859         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 860                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 861         else
 862                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 863
 864         return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
 865                 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
 866                 val->value.i |
 867                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
 868
 869 }
 870
 871 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
 872                                     const struct switch_attr *attr,
 873                                     struct switch_val *val)
 874 {
 875         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 876         u32 data;
 877
 878         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 879                 return -EINVAL;
 880
 881         rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
 882         data &= RTL8366RB_IB_BDTH_MASK;
 883         if (data < RTL8366RB_IB_BDTH_MASK)
 884                 data += 1;
 885
 886         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 887
 888         return 0;
 889 }
 890
 891 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
 892                                     const struct switch_attr *attr,
 893                                     struct switch_val *val)
 894 {
 895         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 896
 897         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 898                 return -EINVAL;
 899
 900         rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
 901                 RTL8366RB_EB_PREIFG_MASK,
 902                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
 903
 904         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 905                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 906         else
 907                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 908
 909         return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
 910                         RTL8366RB_EB_BDTH_MASK, val->value.i );
 911
 912 }
 913
 914 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
 915                                     const struct switch_attr *attr,
 916                                     struct switch_val *val)
 917 {
 918         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 919         u32 data;
 920
 921         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 922                 return -EINVAL;
 923
 924         rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
 925         data &= RTL8366RB_EB_BDTH_MASK;
 926         if (data < RTL8366RB_EB_BDTH_MASK)
 927                 data += 1;
 928
 929         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 930
 931         return 0;
 932 }
 933
 934 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
 935                                     const struct switch_attr *attr,
 936                                     struct switch_val *val)
 937 {
 938         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 939         u32 data;
 940
 941         if (val->value.i)
 942                 data = RTL8366RB_QOS_MASK;
 943         else
 944                 data = 0;
 945
 946         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
 947 }
 948
 949 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
 950                                     const struct switch_attr *attr,
 951                                     struct switch_val *val)
 952 {
 953         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 954         u32 data;
 955
 956         rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 957         if (data & RTL8366RB_QOS_MASK)
 958                 val->value.i = 1;
 959         else
 960                 val->value.i = 0;
 961
 962         return 0;
 963 }
 964
 965 static int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev,
 966                                     const struct switch_attr *attr,
 967                                     struct switch_val *val)
 968 {
 969         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 970         u32 data;
 971
 972         if (val->value.i)
 973                 data = RTL8366RB_PMCR_MIRROR_RX;
 974         else
 975                 data = 0;
 976
 977         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data);
 978 }
 979
 980 static int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev,
 981                                     const struct switch_attr *attr,
 982                                     struct switch_val *val)
 983 {
 984         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 985         u32 data;
 986
 987         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
 988         if (data & RTL8366RB_PMCR_MIRROR_RX)
 989                 val->value.i = 1;
 990         else
 991                 val->value.i = 0;
 992
 993         return 0;
 994 }
 995
 996 static int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev,
 997                                     const struct switch_attr *attr,
 998                                     struct switch_val *val)
 999 {
1000         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1001         u32 data;
1002
1003         if (val->value.i)
1004                 data = RTL8366RB_PMCR_MIRROR_TX;
1005         else
1006                 data = 0;
1007
1008         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data);
1009 }
1010
1011 static int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev,
1012                                     const struct switch_attr *attr,
1013                                     struct switch_val *val)
1014 {
1015         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1016         u32 data;
1017
1018         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1019         if (data & RTL8366RB_PMCR_MIRROR_TX)
1020                 val->value.i = 1;
1021         else
1022                 val->value.i = 0;
1023
1024         return 0;
1025 }
1026
1027 static int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev,
1028                                     const struct switch_attr *attr,
1029                                     struct switch_val *val)
1030 {
1031         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1032         u32 data;
1033
1034         if (val->value.i)
1035                 data = RTL8366RB_PMCR_MIRROR_ISO;
1036         else
1037                 data = 0;
1038
1039         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data);
1040 }
1041
1042 static int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev,
1043                                     const struct switch_attr *attr,
1044                                     struct switch_val *val)
1045 {
1046         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1047         u32 data;
1048
1049         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1050         if (data & RTL8366RB_PMCR_MIRROR_ISO)
1051                 val->value.i = 1;
1052         else
1053                 val->value.i = 0;
1054
1055         return 0;
1056 }
1057
1058 static int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev,
1059                                     const struct switch_attr *attr,
1060                                     struct switch_val *val)
1061 {
1062         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1063         u32 data;
1064
1065         if (val->value.i)
1066                 data = RTL8366RB_PMCR_MIRROR_SPC;
1067         else
1068                 data = 0;
1069
1070         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data);
1071 }
1072
1073 static int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev,
1074                                     const struct switch_attr *attr,
1075                                     struct switch_val *val)
1076 {
1077         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1078         u32 data;
1079
1080         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1081         if (data & RTL8366RB_PMCR_MIRROR_SPC)
1082                 val->value.i = 1;
1083         else
1084                 val->value.i = 0;
1085
1086         return 0;
1087 }
1088
1089 static int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev,
1090                                     const struct switch_attr *attr,
1091                                     struct switch_val *val)
1092 {
1093         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1094         u32 data;
1095
1096         data = RTL8366RB_PMCR_MONITOR_PORT(val->value.i);
1097
1098         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data);
1099 }
1100
1101 static int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev,
1102                                     const struct switch_attr *attr,
1103                                     struct switch_val *val)
1104 {
1105         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1106         u32 data;
1107
1108         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1109         val->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4;
1110
1111         return 0;
1112 }
1113
1114 static int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev,
1115                                     const struct switch_attr *attr,
1116                                     struct switch_val *val)
1117 {
1118         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1119         u32 data;
1120
1121         data = RTL8366RB_PMCR_SOURCE_PORT(val->value.i);
1122
1123         return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data);
1124 }
1125
1126 static int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev,
1127                                     const struct switch_attr *attr,
1128                                     struct switch_val *val)
1129 {
1130         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1131         u32 data;
1132
1133         rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1134         val->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK;
1135
1136         return 0;
1137 }
1138
1139 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1140                                        const struct switch_attr *attr,
1141                                        struct switch_val *val)
1142 {
1143         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1144
1145         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1146                 return -EINVAL;
1147
1148         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1149                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1150 }
1151
1152 static int rtl8366rb_sw_get_port_stats(struct switch_dev *dev, int port,
1153                                         struct switch_port_stats *stats)
1154 {
1155         return (rtl8366_sw_get_port_stats(dev, port, stats,
1156                                 RTL8366RB_MIB_TXB_ID, RTL8366RB_MIB_RXB_ID));
1157 }
1158
1159 static struct switch_attr rtl8366rb_globals[] = {
1160         {
1161                 .type = SWITCH_TYPE_INT,
1162                 .name = "enable_learning",
1163                 .description = "Enable learning, enable aging",
1164                 .set = rtl8366rb_sw_set_learning_enable,
1165                 .get = rtl8366rb_sw_get_learning_enable,
1166                 .max = 1
1167         }, {
1168                 .type = SWITCH_TYPE_INT,
1169                 .name = "enable_vlan",
1170                 .description = "Enable VLAN mode",
1171                 .set = rtl8366_sw_set_vlan_enable,
1172                 .get = rtl8366_sw_get_vlan_enable,
1173                 .max = 1,
1174                 .ofs = 1
1175         }, {
1176                 .type = SWITCH_TYPE_INT,
1177                 .name = "enable_vlan4k",
1178                 .description = "Enable VLAN 4K mode",
1179                 .set = rtl8366_sw_set_vlan_enable,
1180                 .get = rtl8366_sw_get_vlan_enable,
1181                 .max = 1,
1182                 .ofs = 2
1183         }, {
1184                 .type = SWITCH_TYPE_NOVAL,
1185                 .name = "reset_mibs",
1186                 .description = "Reset all MIB counters",
1187                 .set = rtl8366rb_sw_reset_mibs,
1188         }, {
1189                 .type = SWITCH_TYPE_INT,
1190                 .name = "blinkrate",
1191                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1192                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1193                 .set = rtl8366rb_sw_set_blinkrate,
1194                 .get = rtl8366rb_sw_get_blinkrate,
1195                 .max = 5
1196         }, {
1197                 .type = SWITCH_TYPE_INT,
1198                 .name = "enable_qos",
1199                 .description = "Enable QOS",
1200                 .set = rtl8366rb_sw_set_qos_enable,
1201                 .get = rtl8366rb_sw_get_qos_enable,
1202                 .max = 1
1203         }, {
1204                 .type = SWITCH_TYPE_INT,
1205                 .name = "enable_mirror_rx",
1206                 .description = "Enable mirroring of RX packets",
1207                 .set = rtl8366rb_sw_set_mirror_rx_enable,
1208                 .get = rtl8366rb_sw_get_mirror_rx_enable,
1209                 .max = 1
1210         }, {
1211                 .type = SWITCH_TYPE_INT,
1212                 .name = "enable_mirror_tx",
1213                 .description = "Enable mirroring of TX packets",
1214                 .set = rtl8366rb_sw_set_mirror_tx_enable,
1215                 .get = rtl8366rb_sw_get_mirror_tx_enable,
1216                 .max = 1
1217         }, {
1218                 .type = SWITCH_TYPE_INT,
1219                 .name = "enable_monitor_isolation",
1220                 .description = "Enable isolation of monitor port (TX packets will be dropped)",
1221                 .set = rtl8366rb_sw_set_monitor_isolation_enable,
1222                 .get = rtl8366rb_sw_get_monitor_isolation_enable,
1223                 .max = 1
1224         }, {
1225                 .type = SWITCH_TYPE_INT,
1226                 .name = "enable_mirror_pause_frames",
1227                 .description = "Enable mirroring of RX pause frames",
1228                 .set = rtl8366rb_sw_set_mirror_pause_frames_enable,
1229                 .get = rtl8366rb_sw_get_mirror_pause_frames_enable,
1230                 .max = 1
1231         }, {
1232                 .type = SWITCH_TYPE_INT,
1233                 .name = "mirror_monitor_port",
1234                 .description = "Mirror monitor port",
1235                 .set = rtl8366rb_sw_set_mirror_monitor_port,
1236                 .get = rtl8366rb_sw_get_mirror_monitor_port,
1237                 .max = 5
1238         }, {
1239                 .type = SWITCH_TYPE_INT,
1240                 .name = "mirror_source_port",
1241                 .description = "Mirror source port",
1242                 .set = rtl8366rb_sw_set_mirror_source_port,
1243                 .get = rtl8366rb_sw_get_mirror_source_port,
1244                 .max = 5
1245         },
1246 };
1247
1248 static struct switch_attr rtl8366rb_port[] = {
1249         {
1250                 .type = SWITCH_TYPE_NOVAL,
1251                 .name = "reset_mib",
1252                 .description = "Reset single port MIB counters",
1253                 .set = rtl8366rb_sw_reset_port_mibs,
1254         }, {
1255                 .type = SWITCH_TYPE_STRING,
1256                 .name = "mib",
1257                 .description = "Get MIB counters for port",
1258                 .max = 33,
1259                 .set = NULL,
1260                 .get = rtl8366_sw_get_port_mib,
1261         }, {
1262                 .type = SWITCH_TYPE_INT,
1263                 .name = "led",
1264                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1265                 .max = 15,
1266                 .set = rtl8366rb_sw_set_port_led,
1267                 .get = rtl8366rb_sw_get_port_led,
1268         }, {
1269                 .type = SWITCH_TYPE_INT,
1270                 .name = "disable",
1271                 .description = "Get/Set port state (enabled or disabled)",
1272                 .max = 1,
1273                 .set = rtl8366rb_sw_set_port_disable,
1274                 .get = rtl8366rb_sw_get_port_disable,
1275         }, {
1276                 .type = SWITCH_TYPE_INT,
1277                 .name = "rate_in",
1278                 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1279                 .max = RTL8366RB_BDTH_SW_MAX,
1280                 .set = rtl8366rb_sw_set_port_rate_in,
1281                 .get = rtl8366rb_sw_get_port_rate_in,
1282         }, {
1283                 .type = SWITCH_TYPE_INT,
1284                 .name = "rate_out",
1285                 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1286                 .max = RTL8366RB_BDTH_SW_MAX,
1287                 .set = rtl8366rb_sw_set_port_rate_out,
1288                 .get = rtl8366rb_sw_get_port_rate_out,
1289         },
1290 };
1291
1292 static struct switch_attr rtl8366rb_vlan[] = {
1293         {
1294                 .type = SWITCH_TYPE_STRING,
1295                 .name = "info",
1296                 .description = "Get vlan information",
1297                 .max = 1,
1298                 .set = NULL,
1299                 .get = rtl8366_sw_get_vlan_info,
1300         }, {
1301                 .type = SWITCH_TYPE_INT,
1302                 .name = "fid",
1303                 .description = "Get/Set vlan FID",
1304                 .max = RTL8366RB_FIDMAX,
1305                 .set = rtl8366_sw_set_vlan_fid,
1306                 .get = rtl8366_sw_get_vlan_fid,
1307         },
1308 };
1309
1310 static const struct switch_dev_ops rtl8366_ops = {
1311         .attr_global = {
1312                 .attr = rtl8366rb_globals,
1313                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1314         },
1315         .attr_port = {
1316                 .attr = rtl8366rb_port,
1317                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1318         },
1319         .attr_vlan = {
1320                 .attr = rtl8366rb_vlan,
1321                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1322         },
1323
1324         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1325         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1326         .get_port_pvid = rtl8366_sw_get_port_pvid,
1327         .set_port_pvid = rtl8366_sw_set_port_pvid,
1328         .reset_switch = rtl8366_sw_reset_switch,
1329         .get_port_link = rtl8366rb_sw_get_port_link,
1330         .get_port_stats = rtl8366rb_sw_get_port_stats,
1331 };
1332
1333 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1334 {
1335         struct switch_dev *dev = &smi->sw_dev;
1336         int err;
1337
1338         dev->name = "RTL8366RB";
1339         dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1340         dev->ports = RTL8366RB_NUM_PORTS;
1341         dev->vlans = RTL8366RB_NUM_VIDS;
1342         dev->ops = &rtl8366_ops;
1343         dev->alias = dev_name(smi->parent);
1344
1345         err = register_switch(dev, NULL);
1346         if (err)
1347                 dev_err(smi->parent, "switch registration failed\n");
1348
1349         return err;
1350 }
1351
1352 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1353 {
1354         unregister_switch(&smi->sw_dev);
1355 }
1356
1357 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1358 {
1359         struct rtl8366_smi *smi = bus->priv;
1360         u32 val = 0;
1361         int err;
1362
1363         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1364         if (err)
1365                 return 0xffff;
1366
1367         return val;
1368 }
1369
1370 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1371 {
1372         struct rtl8366_smi *smi = bus->priv;
1373         u32 t;
1374         int err;
1375
1376         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1377         /* flush write */
1378         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1379
1380         return err;
1381 }
1382
1383 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1384 {
1385         u32 chip_id = 0;
1386         u32 chip_ver = 0;
1387         int ret;
1388
1389         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1390         if (ret) {
1391                 dev_err(smi->parent, "unable to read chip id\n");
1392                 return ret;
1393         }
1394
1395         switch (chip_id) {
1396         case RTL8366RB_CHIP_ID_8366:
1397                 break;
1398         default:
1399                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1400                 return -ENODEV;
1401         }
1402
1403         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1404                                    &chip_ver);
1405         if (ret) {
1406                 dev_err(smi->parent, "unable to read chip version\n");
1407                 return ret;
1408         }
1409
1410         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1411                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1412
1413         return 0;
1414 }
1415
1416 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1417         .detect         = rtl8366rb_detect,
1418         .reset_chip     = rtl8366rb_reset_chip,
1419         .setup          = rtl8366rb_setup,
1420
1421         .mii_read       = rtl8366rb_mii_read,
1422         .mii_write      = rtl8366rb_mii_write,
1423
1424         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1425         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1426         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1427         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1428         .get_mc_index   = rtl8366rb_get_mc_index,
1429         .set_mc_index   = rtl8366rb_set_mc_index,
1430         .get_mib_counter = rtl8366rb_get_mib_counter,
1431         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
1432         .enable_vlan    = rtl8366rb_enable_vlan,
1433         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
1434         .enable_port    = rtl8366rb_enable_port,
1435 };
1436
1437 static int rtl8366rb_probe(struct platform_device *pdev)
1438 {
1439         static int rtl8366_smi_version_printed;
1440         struct rtl8366_smi *smi;
1441         int err;
1442
1443         if (!rtl8366_smi_version_printed++)
1444                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1445                        " version " RTL8366RB_DRIVER_VER"\n");
1446
1447         smi = rtl8366_smi_probe(pdev);
1448         if (!smi)
1449                 return -ENODEV;
1450
1451         smi->clk_delay = 10;
1452         smi->cmd_read = 0xa9;
1453         smi->cmd_write = 0xa8;
1454         smi->ops = &rtl8366rb_smi_ops;
1455         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1456         smi->num_ports = RTL8366RB_NUM_PORTS;
1457         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1458         smi->mib_counters = rtl8366rb_mib_counters;
1459         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1460
1461         err = rtl8366_smi_init(smi);
1462         if (err)
1463                 goto err_free_smi;
1464
1465         platform_set_drvdata(pdev, smi);
1466
1467         err = rtl8366rb_switch_init(smi);
1468         if (err)
1469                 goto err_clear_drvdata;
1470
1471         return 0;
1472
1473  err_clear_drvdata:
1474         platform_set_drvdata(pdev, NULL);
1475         rtl8366_smi_cleanup(smi);
1476  err_free_smi:
1477         kfree(smi);
1478         return err;
1479 }
1480
1481 static int rtl8366rb_remove(struct platform_device *pdev)
1482 {
1483         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1484
1485         if (smi) {
1486                 rtl8366rb_switch_cleanup(smi);
1487                 platform_set_drvdata(pdev, NULL);
1488                 rtl8366_smi_cleanup(smi);
1489                 kfree(smi);
1490         }
1491
1492         return 0;
1493 }
1494
1495 #ifdef CONFIG_OF
1496 static const struct of_device_id rtl8366rb_match[] = {
1497         { .compatible = "realtek,rtl8366rb" },
1498         {},
1499 };
1500 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1501 #endif
1502
1503 static struct platform_driver rtl8366rb_driver = {
1504         .driver = {
1505                 .name           = RTL8366RB_DRIVER_NAME,
1506                 .owner          = THIS_MODULE,
1507                 .of_match_table = of_match_ptr(rtl8366rb_match),
1508         },
1509         .probe          = rtl8366rb_probe,
1510         .remove         = rtl8366rb_remove,
1511 };
1512
1513 static int __init rtl8366rb_module_init(void)
1514 {
1515         return platform_driver_register(&rtl8366rb_driver);
1516 }
1517 module_init(rtl8366rb_module_init);
1518
1519 static void __exit rtl8366rb_module_exit(void)
1520 {
1521         platform_driver_unregister(&rtl8366rb_driver);
1522 }
1523 module_exit(rtl8366rb_module_exit);
1524
1525 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1526 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1527 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1528 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1529 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1530 MODULE_AUTHOR("Colin Leitner <colin.leitner@googlemail.com>");
1531 MODULE_LICENSE("GPL v2");
1532 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);