2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
172 for (i = 0; i < 10; i++) {
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
179 usleep_range(100, 200);
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
192 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
194 if (dev->core_rev >= 3)
195 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
197 entry |= VA_VALID_25;
200 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
201 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
202 VTA_RW_STATE_WR | VTA_RW_OP_EN);
203 } else if (is5365(dev)) {
207 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
208 members | VA_VALID_65;
210 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
211 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
212 VTA_RW_STATE_WR | VTA_RW_OP_EN);
214 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
215 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
216 (untag << VTE_UNTAG_S) | members);
218 b53_do_vlan_op(dev, VTA_CMD_WRITE);
222 void b53_set_forwarding(struct b53_device *dev, int enable)
226 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
229 mgmt |= SM_SW_FWD_EN;
231 mgmt &= ~SM_SW_FWD_EN;
233 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
236 static void b53_enable_vlan(struct b53_device *dev, int enable)
238 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
240 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
244 if (is5325(dev) || is5365(dev)) {
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
247 } else if (is63xx(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
255 mgmt &= ~SM_SW_FWD_MODE;
258 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
259 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
260 vc4 &= ~VC4_ING_VID_CHECK_MASK;
261 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
262 vc5 |= VC5_DROP_VTABLE_MISS;
265 vc0 &= ~VC0_RESERVED_1;
267 if (is5325(dev) || is5365(dev))
268 vc1 |= VC1_RX_MCST_TAG_EN;
270 if (!is5325(dev) && !is5365(dev)) {
271 if (dev->allow_vid_4095)
272 vc5 |= VC5_VID_FFF_EN;
274 vc5 &= ~VC5_VID_FFF_EN;
277 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
278 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
279 vc4 &= ~VC4_ING_VID_CHECK_MASK;
280 vc5 &= ~VC5_DROP_VTABLE_MISS;
282 if (is5325(dev) || is5365(dev))
283 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
285 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
287 if (is5325(dev) || is5365(dev))
288 vc1 &= ~VC1_RX_MCST_TAG_EN;
290 if (!is5325(dev) && !is5365(dev))
291 vc5 &= ~VC5_VID_FFF_EN;
294 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
295 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
297 if (is5325(dev) || is5365(dev)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev) && enable)
300 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
307 } else if (is63xx(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
317 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
320 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
323 u16 max_size = JMS_MIN_SIZE;
325 if (is5325(dev) || is5365(dev))
329 port_mask = dev->enabled_ports;
330 max_size = JMS_MAX_SIZE;
332 port_mask |= JPM_10_100_JUMBO_EN;
335 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
336 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
339 static int b53_flush_arl(struct b53_device *dev)
343 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
344 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
346 for (i = 0; i < 10; i++) {
349 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
352 if (!(fast_age_ctrl & FAST_AGE_DONE))
358 pr_warn("time out while flushing ARL\n");
363 static void b53_enable_ports(struct b53_device *dev)
367 b53_for_each_port(dev, i) {
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
375 if (dev->enable_vlan || is_cpu_port(dev, i))
377 else if (is531x5(dev) || is5301x(dev))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask = BIT(dev->sw_dev.cpu_port);
381 pvlan_mask = BIT(B53_CPU_PORT);
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
387 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
390 else if (i == B53_CPU_PORT)
391 port_ctrl = PORT_CTRL_RX_BCST_EN |
392 PORT_CTRL_RX_MCST_EN |
393 PORT_CTRL_RX_UCST_EN;
397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
402 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
407 static void b53_enable_mib(struct b53_device *dev)
411 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
413 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
415 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
418 static int b53_apply(struct b53_device *dev)
422 /* clear all vlan entries */
423 if (is5325(dev) || is5365(dev)) {
424 for (i = 1; i < dev->sw_dev.vlans; i++)
425 b53_set_vlan_entry(dev, i, 0, 0);
427 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
430 b53_enable_vlan(dev, dev->enable_vlan);
432 /* fill VLAN table */
433 if (dev->enable_vlan) {
434 for (i = 0; i < dev->sw_dev.vlans; i++) {
435 struct b53_vlan *vlan = &dev->vlans[i];
440 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
443 b53_for_each_port(dev, i)
444 b53_write16(dev, B53_VLAN_PAGE,
445 B53_VLAN_PORT_DEF_TAG(i),
448 b53_for_each_port(dev, i)
449 b53_write16(dev, B53_VLAN_PAGE,
450 B53_VLAN_PORT_DEF_TAG(i), 1);
454 b53_enable_ports(dev);
456 if (!is5325(dev) && !is5365(dev))
457 b53_set_jumbo(dev, dev->enable_jumbo, 1);
462 static void b53_switch_reset_gpio(struct b53_device *dev)
464 int gpio = dev->reset_gpio;
470 * Reset sequence: RESET low(50ms)->high(20ms)
472 gpio_set_value(gpio, 0);
475 gpio_set_value(gpio, 1);
478 dev->current_page = 0xff;
481 static int b53_switch_reset(struct b53_device *dev)
485 b53_switch_reset_gpio(dev);
488 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
489 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
492 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
494 if (!(mgmt & SM_SW_FWD_EN)) {
495 mgmt &= ~SM_SW_FWD_MODE;
496 mgmt |= SM_SW_FWD_EN;
498 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
499 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
501 if (!(mgmt & SM_SW_FWD_EN)) {
502 pr_err("Failed to enable switch!\n");
507 /* enable all ports */
508 b53_enable_ports(dev);
510 /* configure MII port if necessary */
512 u8 mii_port_override;
514 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
516 /* reverse mii needs to be enabled */
517 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
518 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
519 mii_port_override | PORT_OVERRIDE_RV_MII_25);
520 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
523 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
524 pr_err("Failed to enable reverse MII mode\n");
528 } else if ((is531x5(dev) || is5301x(dev)) &&
529 dev->sw_dev.cpu_port == B53_CPU_PORT) {
530 u8 mii_port_override;
532 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
534 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
535 mii_port_override | PORT_OVERRIDE_EN |
541 return b53_flush_arl(dev);
545 * Swconfig glue functions
548 static int b53_global_get_vlan_enable(struct switch_dev *dev,
549 const struct switch_attr *attr,
550 struct switch_val *val)
552 struct b53_device *priv = sw_to_b53(dev);
554 val->value.i = priv->enable_vlan;
559 static int b53_global_set_vlan_enable(struct switch_dev *dev,
560 const struct switch_attr *attr,
561 struct switch_val *val)
563 struct b53_device *priv = sw_to_b53(dev);
565 priv->enable_vlan = val->value.i;
570 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
571 const struct switch_attr *attr,
572 struct switch_val *val)
574 struct b53_device *priv = sw_to_b53(dev);
576 val->value.i = priv->enable_jumbo;
581 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
582 const struct switch_attr *attr,
583 struct switch_val *val)
585 struct b53_device *priv = sw_to_b53(dev);
587 priv->enable_jumbo = val->value.i;
592 static int b53_global_get_4095_enable(struct switch_dev *dev,
593 const struct switch_attr *attr,
594 struct switch_val *val)
596 struct b53_device *priv = sw_to_b53(dev);
598 val->value.i = priv->allow_vid_4095;
603 static int b53_global_set_4095_enable(struct switch_dev *dev,
604 const struct switch_attr *attr,
605 struct switch_val *val)
607 struct b53_device *priv = sw_to_b53(dev);
609 priv->allow_vid_4095 = val->value.i;
614 static int b53_global_get_ports(struct switch_dev *dev,
615 const struct switch_attr *attr,
616 struct switch_val *val)
618 struct b53_device *priv = sw_to_b53(dev);
620 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
621 priv->enabled_ports);
622 val->value.s = priv->buf;
627 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
629 struct b53_device *priv = sw_to_b53(dev);
631 *val = priv->ports[port].pvid;
636 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
638 struct b53_device *priv = sw_to_b53(dev);
640 if (val > 15 && is5325(priv))
642 if (val == 4095 && !priv->allow_vid_4095)
645 priv->ports[port].pvid = val;
650 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
652 struct b53_device *priv = sw_to_b53(dev);
653 struct switch_port *port = &val->value.ports[0];
654 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
662 for (i = 0; i < dev->ports; i++) {
663 if (!(vlan->members & BIT(i)))
667 if (!(vlan->untag & BIT(i)))
668 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
680 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
682 struct b53_device *priv = sw_to_b53(dev);
683 struct switch_port *port;
684 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
687 /* only BCM5325 and BCM5365 supports VID 0 */
688 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
691 /* VLAN 4095 needs special handling */
692 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
695 port = &val->value.ports[0];
698 for (i = 0; i < val->len; i++, port++) {
699 vlan->members |= BIT(port->id);
701 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
702 vlan->untag |= BIT(port->id);
703 priv->ports[port->id].pvid = val->port_vlan;
707 /* ignore disabled ports */
708 vlan->members &= priv->enabled_ports;
709 vlan->untag &= priv->enabled_ports;
714 static int b53_port_get_link(struct switch_dev *dev, int port,
715 struct switch_port_link *link)
717 struct b53_device *priv = sw_to_b53(dev);
719 if (is_cpu_port(priv, port)) {
722 link->speed = is5325(priv) || is5365(priv) ?
723 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
725 } else if (priv->enabled_ports & BIT(port)) {
729 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
730 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
732 lnk = (lnk >> port) & 1;
733 duplex = (duplex >> port) & 1;
735 if (is5325(priv) || is5365(priv)) {
738 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
739 speed = SPEED_PORT_FE(tmp, port);
741 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
742 speed = SPEED_PORT_GE(speed, port);
747 link->duplex = duplex;
750 link->speed = SWITCH_PORT_SPEED_10;
752 case SPEED_STAT_100M:
753 link->speed = SWITCH_PORT_SPEED_100;
755 case SPEED_STAT_1000M:
756 link->speed = SWITCH_PORT_SPEED_1000;
770 static int b53_global_reset_switch(struct switch_dev *dev)
772 struct b53_device *priv = sw_to_b53(dev);
775 priv->enable_vlan = 0;
776 priv->enable_jumbo = 0;
777 priv->allow_vid_4095 = 0;
779 memset(priv->vlans, 0, sizeof(priv->vlans) * dev->vlans);
780 memset(priv->ports, 0, sizeof(priv->ports) * dev->ports);
782 return b53_switch_reset(priv);
785 static int b53_global_apply_config(struct switch_dev *dev)
787 struct b53_device *priv = sw_to_b53(dev);
789 /* disable switching */
790 b53_set_forwarding(priv, 0);
794 /* enable switching */
795 b53_set_forwarding(priv, 1);
801 static int b53_global_reset_mib(struct switch_dev *dev,
802 const struct switch_attr *attr,
803 struct switch_val *val)
805 struct b53_device *priv = sw_to_b53(dev);
808 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
810 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
812 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
818 static int b53_port_get_mib(struct switch_dev *sw_dev,
819 const struct switch_attr *attr,
820 struct switch_val *val)
822 struct b53_device *dev = sw_to_b53(sw_dev);
823 const struct b53_mib_desc *mibs;
824 int port = val->port_vlan;
827 if (!(BIT(port) & dev->enabled_ports))
835 } else if (is63xx(dev)) {
836 mibs = b53_mibs_63xx;
843 for (; mibs->size > 0; mibs++) {
846 if (mibs->size == 8) {
847 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
851 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
856 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
857 "%-20s: %llu\n", mibs->name, val);
861 val->value.s = dev->buf;
866 static struct switch_attr b53_global_ops_25[] = {
868 .type = SWITCH_TYPE_INT,
869 .name = "enable_vlan",
870 .description = "Enable VLAN mode",
871 .set = b53_global_set_vlan_enable,
872 .get = b53_global_get_vlan_enable,
876 .type = SWITCH_TYPE_STRING,
878 .description = "Available ports (as bitmask)",
879 .get = b53_global_get_ports,
883 static struct switch_attr b53_global_ops_65[] = {
885 .type = SWITCH_TYPE_INT,
886 .name = "enable_vlan",
887 .description = "Enable VLAN mode",
888 .set = b53_global_set_vlan_enable,
889 .get = b53_global_get_vlan_enable,
893 .type = SWITCH_TYPE_STRING,
895 .description = "Available ports (as bitmask)",
896 .get = b53_global_get_ports,
899 .type = SWITCH_TYPE_INT,
901 .description = "Reset MIB counters",
902 .set = b53_global_reset_mib,
906 static struct switch_attr b53_global_ops[] = {
908 .type = SWITCH_TYPE_INT,
909 .name = "enable_vlan",
910 .description = "Enable VLAN mode",
911 .set = b53_global_set_vlan_enable,
912 .get = b53_global_get_vlan_enable,
916 .type = SWITCH_TYPE_STRING,
918 .description = "Available Ports (as bitmask)",
919 .get = b53_global_get_ports,
922 .type = SWITCH_TYPE_INT,
924 .description = "Reset MIB counters",
925 .set = b53_global_reset_mib,
928 .type = SWITCH_TYPE_INT,
929 .name = "enable_jumbo",
930 .description = "Enable Jumbo Frames",
931 .set = b53_global_set_jumbo_enable,
932 .get = b53_global_get_jumbo_enable,
936 .type = SWITCH_TYPE_INT,
937 .name = "allow_vid_4095",
938 .description = "Allow VID 4095",
939 .set = b53_global_set_4095_enable,
940 .get = b53_global_get_4095_enable,
945 static struct switch_attr b53_port_ops[] = {
947 .type = SWITCH_TYPE_STRING,
949 .description = "Get port's MIB counters",
950 .get = b53_port_get_mib,
954 static struct switch_attr b53_no_ops[] = {
957 static const struct switch_dev_ops b53_switch_ops_25 = {
959 .attr = b53_global_ops_25,
960 .n_attr = ARRAY_SIZE(b53_global_ops_25),
964 .n_attr = ARRAY_SIZE(b53_no_ops),
968 .n_attr = ARRAY_SIZE(b53_no_ops),
971 .get_vlan_ports = b53_vlan_get_ports,
972 .set_vlan_ports = b53_vlan_set_ports,
973 .get_port_pvid = b53_port_get_pvid,
974 .set_port_pvid = b53_port_set_pvid,
975 .apply_config = b53_global_apply_config,
976 .reset_switch = b53_global_reset_switch,
977 .get_port_link = b53_port_get_link,
980 static const struct switch_dev_ops b53_switch_ops_65 = {
982 .attr = b53_global_ops_65,
983 .n_attr = ARRAY_SIZE(b53_global_ops_65),
986 .attr = b53_port_ops,
987 .n_attr = ARRAY_SIZE(b53_port_ops),
991 .n_attr = ARRAY_SIZE(b53_no_ops),
994 .get_vlan_ports = b53_vlan_get_ports,
995 .set_vlan_ports = b53_vlan_set_ports,
996 .get_port_pvid = b53_port_get_pvid,
997 .set_port_pvid = b53_port_set_pvid,
998 .apply_config = b53_global_apply_config,
999 .reset_switch = b53_global_reset_switch,
1000 .get_port_link = b53_port_get_link,
1003 static const struct switch_dev_ops b53_switch_ops = {
1005 .attr = b53_global_ops,
1006 .n_attr = ARRAY_SIZE(b53_global_ops),
1009 .attr = b53_port_ops,
1010 .n_attr = ARRAY_SIZE(b53_port_ops),
1014 .n_attr = ARRAY_SIZE(b53_no_ops),
1017 .get_vlan_ports = b53_vlan_get_ports,
1018 .set_vlan_ports = b53_vlan_set_ports,
1019 .get_port_pvid = b53_port_get_pvid,
1020 .set_port_pvid = b53_port_set_pvid,
1021 .apply_config = b53_global_apply_config,
1022 .reset_switch = b53_global_reset_switch,
1023 .get_port_link = b53_port_get_link,
1026 struct b53_chip_data {
1028 const char *dev_name;
1037 const struct switch_dev_ops *sw_ops;
1040 #define B53_VTA_REGS \
1041 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1042 #define B53_VTA_REGS_9798 \
1043 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1044 #define B53_VTA_REGS_63XX \
1045 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1047 static const struct b53_chip_data b53_switch_chips[] = {
1049 .chip_id = BCM5325_DEVICE_ID,
1050 .dev_name = "BCM5325",
1053 .enabled_ports = 0x1f,
1054 .cpu_port = B53_CPU_PORT_25,
1055 .duplex_reg = B53_DUPLEX_STAT_FE,
1056 .sw_ops = &b53_switch_ops_25,
1059 .chip_id = BCM5365_DEVICE_ID,
1060 .dev_name = "BCM5365",
1063 .enabled_ports = 0x1f,
1064 .cpu_port = B53_CPU_PORT_25,
1065 .duplex_reg = B53_DUPLEX_STAT_FE,
1066 .sw_ops = &b53_switch_ops_65,
1069 .chip_id = BCM5395_DEVICE_ID,
1070 .dev_name = "BCM5395",
1073 .enabled_ports = 0x1f,
1074 .cpu_port = B53_CPU_PORT,
1075 .vta_regs = B53_VTA_REGS,
1076 .duplex_reg = B53_DUPLEX_STAT_GE,
1077 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1078 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1079 .sw_ops = &b53_switch_ops,
1082 .chip_id = BCM5397_DEVICE_ID,
1083 .dev_name = "BCM5397",
1086 .enabled_ports = 0x1f,
1087 .cpu_port = B53_CPU_PORT,
1088 .vta_regs = B53_VTA_REGS_9798,
1089 .duplex_reg = B53_DUPLEX_STAT_GE,
1090 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1091 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1092 .sw_ops = &b53_switch_ops,
1095 .chip_id = BCM5398_DEVICE_ID,
1096 .dev_name = "BCM5398",
1099 .enabled_ports = 0x7f,
1100 .cpu_port = B53_CPU_PORT,
1101 .vta_regs = B53_VTA_REGS_9798,
1102 .duplex_reg = B53_DUPLEX_STAT_GE,
1103 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1104 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1105 .sw_ops = &b53_switch_ops,
1108 .chip_id = BCM53115_DEVICE_ID,
1109 .dev_name = "BCM53115",
1110 .alias = "bcm53115",
1112 .enabled_ports = 0x1f,
1113 .vta_regs = B53_VTA_REGS,
1114 .cpu_port = B53_CPU_PORT,
1115 .duplex_reg = B53_DUPLEX_STAT_GE,
1116 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1117 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1118 .sw_ops = &b53_switch_ops,
1121 .chip_id = BCM53125_DEVICE_ID,
1122 .dev_name = "BCM53125",
1123 .alias = "bcm53125",
1125 .enabled_ports = 0x1f,
1126 .cpu_port = B53_CPU_PORT,
1127 .vta_regs = B53_VTA_REGS,
1128 .duplex_reg = B53_DUPLEX_STAT_GE,
1129 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1130 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1131 .sw_ops = &b53_switch_ops,
1134 .chip_id = BCM53128_DEVICE_ID,
1135 .dev_name = "BCM53128",
1136 .alias = "bcm53128",
1138 .enabled_ports = 0x1ff,
1139 .cpu_port = B53_CPU_PORT,
1140 .vta_regs = B53_VTA_REGS,
1141 .duplex_reg = B53_DUPLEX_STAT_GE,
1142 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1143 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1144 .sw_ops = &b53_switch_ops,
1147 .chip_id = BCM63XX_DEVICE_ID,
1148 .dev_name = "BCM63xx",
1151 .enabled_ports = 0, /* pdata must provide them */
1152 .cpu_port = B53_CPU_PORT,
1153 .vta_regs = B53_VTA_REGS_63XX,
1154 .duplex_reg = B53_DUPLEX_STAT_63XX,
1155 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1156 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1157 .sw_ops = &b53_switch_ops,
1160 .chip_id = BCM53010_DEVICE_ID,
1161 .dev_name = "BCM53010",
1162 .alias = "bcm53011",
1164 .enabled_ports = 0x1f,
1165 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1166 .vta_regs = B53_VTA_REGS,
1167 .duplex_reg = B53_DUPLEX_STAT_GE,
1168 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1169 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1170 .sw_ops = &b53_switch_ops,
1173 .chip_id = BCM53011_DEVICE_ID,
1174 .dev_name = "BCM53011",
1175 .alias = "bcm53011",
1177 .enabled_ports = 0x1f,
1178 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1179 .vta_regs = B53_VTA_REGS,
1180 .duplex_reg = B53_DUPLEX_STAT_GE,
1181 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1182 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1183 .sw_ops = &b53_switch_ops,
1186 .chip_id = BCM53012_DEVICE_ID,
1187 .dev_name = "BCM53012",
1188 .alias = "bcm53011",
1190 .enabled_ports = 0x1f,
1191 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1192 .vta_regs = B53_VTA_REGS,
1193 .duplex_reg = B53_DUPLEX_STAT_GE,
1194 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1195 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1196 .sw_ops = &b53_switch_ops,
1199 .chip_id = BCM53018_DEVICE_ID,
1200 .dev_name = "BCM53018",
1201 .alias = "bcm53018",
1203 .enabled_ports = 0x1f,
1204 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1205 .vta_regs = B53_VTA_REGS,
1206 .duplex_reg = B53_DUPLEX_STAT_GE,
1207 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1208 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1209 .sw_ops = &b53_switch_ops,
1212 .chip_id = BCM53019_DEVICE_ID,
1213 .dev_name = "BCM53019",
1214 .alias = "bcm53019",
1216 .enabled_ports = 0x1f,
1217 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1218 .vta_regs = B53_VTA_REGS,
1219 .duplex_reg = B53_DUPLEX_STAT_GE,
1220 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1221 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1222 .sw_ops = &b53_switch_ops,
1226 static int b53_switch_init(struct b53_device *dev)
1228 struct switch_dev *sw_dev = &dev->sw_dev;
1232 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1233 const struct b53_chip_data *chip = &b53_switch_chips[i];
1235 if (chip->chip_id == dev->chip_id) {
1236 sw_dev->name = chip->dev_name;
1238 sw_dev->alias = chip->alias;
1239 if (!dev->enabled_ports)
1240 dev->enabled_ports = chip->enabled_ports;
1241 dev->duplex_reg = chip->duplex_reg;
1242 dev->vta_regs[0] = chip->vta_regs[0];
1243 dev->vta_regs[1] = chip->vta_regs[1];
1244 dev->vta_regs[2] = chip->vta_regs[2];
1245 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1246 sw_dev->ops = chip->sw_ops;
1247 sw_dev->cpu_port = chip->cpu_port;
1248 sw_dev->vlans = chip->vlans;
1256 /* check which BCM5325x version we have */
1260 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1262 /* check reserved bits */
1268 /* BCM5325F - do not use port 4 */
1269 dev->enabled_ports &= ~BIT(4);
1272 /* On the BCM47XX SoCs this is the supported internal switch.*/
1273 #ifndef CONFIG_BCM47XX
1280 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1283 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1284 /* use second IMP port if GMII is enabled */
1285 if (strap_value & SV_GMII_CTRL_115)
1286 sw_dev->cpu_port = 5;
1289 /* cpu port is always last */
1290 sw_dev->ports = sw_dev->cpu_port + 1;
1291 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1293 dev->ports = devm_kzalloc(dev->dev,
1294 sizeof(struct b53_port) * sw_dev->ports,
1299 dev->vlans = devm_kzalloc(dev->dev,
1300 sizeof(struct b53_vlan) * sw_dev->vlans,
1305 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1309 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1310 if (dev->reset_gpio >= 0) {
1311 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1312 GPIOF_OUT_INIT_HIGH, "robo_reset");
1317 return b53_switch_reset(dev);
1320 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1323 struct b53_device *dev;
1325 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1332 mutex_init(&dev->reg_mutex);
1336 EXPORT_SYMBOL(b53_switch_alloc);
1338 int b53_switch_detect(struct b53_device *dev)
1345 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1352 * BCM5325 and BCM5365 do not have this register so reads
1353 * return 0. But the read operation did succeed, so assume
1354 * this is one of them.
1356 * Next check if we can write to the 5325's VTA register; for
1357 * 5365 it is read only.
1360 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1361 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1364 dev->chip_id = BCM5325_DEVICE_ID;
1366 dev->chip_id = BCM5365_DEVICE_ID;
1368 case BCM5395_DEVICE_ID:
1369 case BCM5397_DEVICE_ID:
1370 case BCM5398_DEVICE_ID:
1374 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1379 case BCM53115_DEVICE_ID:
1380 case BCM53125_DEVICE_ID:
1381 case BCM53128_DEVICE_ID:
1382 case BCM53010_DEVICE_ID:
1383 case BCM53011_DEVICE_ID:
1384 case BCM53012_DEVICE_ID:
1385 case BCM53018_DEVICE_ID:
1386 case BCM53019_DEVICE_ID:
1387 dev->chip_id = id32;
1390 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1396 if (dev->chip_id == BCM5325_DEVICE_ID)
1397 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1400 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1403 EXPORT_SYMBOL(b53_switch_detect);
1405 int b53_switch_register(struct b53_device *dev)
1410 dev->chip_id = dev->pdata->chip_id;
1411 dev->enabled_ports = dev->pdata->enabled_ports;
1412 dev->sw_dev.alias = dev->pdata->alias;
1415 if (!dev->chip_id && b53_switch_detect(dev))
1418 ret = b53_switch_init(dev);
1422 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1424 return register_switch(&dev->sw_dev, NULL);
1426 EXPORT_SYMBOL(b53_switch_register);
1428 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1429 MODULE_DESCRIPTION("B53 switch library");
1430 MODULE_LICENSE("Dual BSD/GPL");