target/linux/generic/files/drivers/net/phy/ar8327.c

   1 /*
   2  * ar8327.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/list.h>
  19 #include <linux/bitops.h>
  20 #include <linux/switch.h>
  21 #include <linux/delay.h>
  22 #include <linux/phy.h>
  23 #include <linux/lockdep.h>
  24 #include <linux/ar8216_platform.h>
  25 #include <linux/workqueue.h>
  26 #include <linux/of_device.h>
  27 #include <linux/leds.h>
  28 #include <linux/mdio.h>
  29
  30 #include "ar8216.h"
  31 #include "ar8327.h"
  32
  33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
  34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
  35
  36 static u32
  37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
  38 {
  39         u32 t;
  40
  41         if (!cfg)
  42                 return 0;
  43
  44         t = 0;
  45         switch (cfg->mode) {
  46         case AR8327_PAD_NC:
  47                 break;
  48
  49         case AR8327_PAD_MAC2MAC_MII:
  50                 t = AR8327_PAD_MAC_MII_EN;
  51                 if (cfg->rxclk_sel)
  52                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
  53                 if (cfg->txclk_sel)
  54                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
  55                 break;
  56
  57         case AR8327_PAD_MAC2MAC_GMII:
  58                 t = AR8327_PAD_MAC_GMII_EN;
  59                 if (cfg->rxclk_sel)
  60                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
  61                 if (cfg->txclk_sel)
  62                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
  63                 break;
  64
  65         case AR8327_PAD_MAC_SGMII:
  66                 t = AR8327_PAD_SGMII_EN;
  67
  68                 /*
  69                  * WAR for the QUalcomm Atheros AP136 board.
  70                  * It seems that RGMII TX/RX delay settings needs to be
  71                  * applied for SGMII mode as well, The ethernet is not
  72                  * reliable without this.
  73                  */
  74                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  75                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  76                 if (cfg->rxclk_delay_en)
  77                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  78                 if (cfg->txclk_delay_en)
  79                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  80
  81                 if (cfg->sgmii_delay_en)
  82                         t |= AR8327_PAD_SGMII_DELAY_EN;
  83
  84                 break;
  85
  86         case AR8327_PAD_MAC2PHY_MII:
  87                 t = AR8327_PAD_PHY_MII_EN;
  88                 if (cfg->rxclk_sel)
  89                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
  90                 if (cfg->txclk_sel)
  91                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
  92                 break;
  93
  94         case AR8327_PAD_MAC2PHY_GMII:
  95                 t = AR8327_PAD_PHY_GMII_EN;
  96                 if (cfg->pipe_rxclk_sel)
  97                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
  98                 if (cfg->rxclk_sel)
  99                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
 100                 if (cfg->txclk_sel)
 101                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 102                 break;
 103
 104         case AR8327_PAD_MAC_RGMII:
 105                 t = AR8327_PAD_RGMII_EN;
 106                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 107                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 108                 if (cfg->rxclk_delay_en)
 109                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 110                 if (cfg->txclk_delay_en)
 111                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 112                 break;
 113
 114         case AR8327_PAD_PHY_GMII:
 115                 t = AR8327_PAD_PHYX_GMII_EN;
 116                 break;
 117
 118         case AR8327_PAD_PHY_RGMII:
 119                 t = AR8327_PAD_PHYX_RGMII_EN;
 120                 break;
 121
 122         case AR8327_PAD_PHY_MII:
 123                 t = AR8327_PAD_PHYX_MII_EN;
 124                 break;
 125         }
 126
 127         return t;
 128 }
 129
 130 static void
 131 ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev)
 132 {
 133         u16 phy_val = 0;
 134         int phyaddr = phydev->mdio.addr;
 135         struct device_node *np = phydev->mdio.dev.of_node;
 136
 137         if (!np)
 138                 return;
 139
 140         if (!of_property_read_bool(np, "qca,phy-rgmii-en")) {
 141                 pr_err("ar8327: qca,phy-rgmii-en is not specified\n");
 142                 return;
 143         }
 144         ar8xxx_phy_dbg_read(priv, phyaddr,
 145                                 AR8327_PHY_MODE_SEL, &phy_val);
 146         phy_val |= AR8327_PHY_MODE_SEL_RGMII;
 147         ar8xxx_phy_dbg_write(priv, phyaddr,
 148                                 AR8327_PHY_MODE_SEL, phy_val);
 149
 150         /* set rgmii tx clock delay if needed */
 151         if (!of_property_read_bool(np, "qca,txclk-delay-en")) {
 152                 pr_err("ar8327: qca,txclk-delay-en is not specified\n");
 153                 return;
 154         }
 155         ar8xxx_phy_dbg_read(priv, phyaddr,
 156                                 AR8327_PHY_SYS_CTRL, &phy_val);
 157         phy_val |= AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY;
 158         ar8xxx_phy_dbg_write(priv, phyaddr,
 159                                 AR8327_PHY_SYS_CTRL, phy_val);
 160
 161         /* set rgmii rx clock delay if needed */
 162         if (!of_property_read_bool(np, "qca,rxclk-delay-en")) {
 163                 pr_err("ar8327: qca,rxclk-delay-en is not specified\n");
 164                 return;
 165         }
 166         ar8xxx_phy_dbg_read(priv, phyaddr,
 167                                 AR8327_PHY_TEST_CTRL, &phy_val);
 168         phy_val |= AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY;
 169         ar8xxx_phy_dbg_write(priv, phyaddr,
 170                                 AR8327_PHY_TEST_CTRL, phy_val);
 171 }
 172
 173 static void
 174 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
 175 {
 176         switch (priv->chip_rev) {
 177         case 1:
 178                 /* For 100M waveform */
 179                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
 180                 /* Turn on Gigabit clock */
 181                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
 182                 break;
 183
 184         case 2:
 185                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);
 186                 /* fallthrough */
 187         case 4:
 188                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);
 189                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
 190                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
 191                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
 192                 break;
 193         }
 194 }
 195
 196 static u32
 197 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
 198 {
 199         u32 t;
 200
 201         if (!cfg->force_link)
 202                 return AR8216_PORT_STATUS_LINK_AUTO;
 203
 204         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
 205         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
 206         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
 207         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
 208
 209         switch (cfg->speed) {
 210         case AR8327_PORT_SPEED_10:
 211                 t |= AR8216_PORT_SPEED_10M;
 212                 break;
 213         case AR8327_PORT_SPEED_100:
 214                 t |= AR8216_PORT_SPEED_100M;
 215                 break;
 216         case AR8327_PORT_SPEED_1000:
 217                 t |= AR8216_PORT_SPEED_1000M;
 218                 break;
 219         }
 220
 221         return t;
 222 }
 223
 224 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
 225         [_num] = { .reg = (_reg), .shift = (_shift) }
 226
 227 static const struct ar8327_led_entry
 228 ar8327_led_map[AR8327_NUM_LEDS] = {
 229         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
 230         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
 231         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
 232
 233         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
 234         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
 235         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
 236
 237         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
 238         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
 239         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
 240
 241         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
 242         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
 243         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
 244
 245         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
 246         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
 247         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
 248 };
 249
 250 static void
 251 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
 252                        enum ar8327_led_pattern pattern)
 253 {
 254         const struct ar8327_led_entry *entry;
 255
 256         entry = &ar8327_led_map[led_num];
 257         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
 258                    (3 << entry->shift), pattern << entry->shift);
 259 }
 260
 261 static void
 262 ar8327_led_work_func(struct work_struct *work)
 263 {
 264         struct ar8327_led *aled;
 265         u8 pattern;
 266
 267         aled = container_of(work, struct ar8327_led, led_work);
 268
 269         pattern = aled->pattern;
 270
 271         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
 272                                pattern);
 273 }
 274
 275 static void
 276 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
 277 {
 278         if (aled->pattern == pattern)
 279                 return;
 280
 281         aled->pattern = pattern;
 282         schedule_work(&aled->led_work);
 283 }
 284
 285 static inline struct ar8327_led *
 286 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
 287 {
 288         return container_of(led_cdev, struct ar8327_led, cdev);
 289 }
 290
 291 static int
 292 ar8327_led_blink_set(struct led_classdev *led_cdev,
 293                      unsigned long *delay_on,
 294                      unsigned long *delay_off)
 295 {
 296         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 297
 298         if (*delay_on == 0 && *delay_off == 0) {
 299                 *delay_on = 125;
 300                 *delay_off = 125;
 301         }
 302
 303         if (*delay_on != 125 || *delay_off != 125) {
 304                 /*
 305                  * The hardware only supports blinking at 4Hz. Fall back
 306                  * to software implementation in other cases.
 307                  */
 308                 return -EINVAL;
 309         }
 310
 311         spin_lock(&aled->lock);
 312
 313         aled->enable_hw_mode = false;
 314         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
 315
 316         spin_unlock(&aled->lock);
 317
 318         return 0;
 319 }
 320
 321 static void
 322 ar8327_led_set_brightness(struct led_classdev *led_cdev,
 323                           enum led_brightness brightness)
 324 {
 325         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 326         u8 pattern;
 327         bool active;
 328
 329         active = (brightness != LED_OFF);
 330         active ^= aled->active_low;
 331
 332         pattern = (active) ? AR8327_LED_PATTERN_ON :
 333                              AR8327_LED_PATTERN_OFF;
 334
 335         spin_lock(&aled->lock);
 336
 337         aled->enable_hw_mode = false;
 338         ar8327_led_schedule_change(aled, pattern);
 339
 340         spin_unlock(&aled->lock);
 341 }
 342
 343 static ssize_t
 344 ar8327_led_enable_hw_mode_show(struct device *dev,
 345                                struct device_attribute *attr,
 346                                char *buf)
 347 {
 348         struct led_classdev *led_cdev = dev_get_drvdata(dev);
 349         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 350         ssize_t ret = 0;
 351
 352         ret += scnprintf(buf, PAGE_SIZE, "%d\n", aled->enable_hw_mode);
 353
 354         return ret;
 355 }
 356
 357 static ssize_t
 358 ar8327_led_enable_hw_mode_store(struct device *dev,
 359                                 struct device_attribute *attr,
 360                                 const char *buf,
 361                                 size_t size)
 362 {
 363         struct led_classdev *led_cdev = dev_get_drvdata(dev);
 364         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 365         u8 pattern;
 366         u8 value;
 367         int ret;
 368
 369         ret = kstrtou8(buf, 10, &value);
 370         if (ret < 0)
 371                 return -EINVAL;
 372
 373         spin_lock(&aled->lock);
 374
 375         aled->enable_hw_mode = !!value;
 376         if (aled->enable_hw_mode)
 377                 pattern = AR8327_LED_PATTERN_RULE;
 378         else
 379                 pattern = AR8327_LED_PATTERN_OFF;
 380
 381         ar8327_led_schedule_change(aled, pattern);
 382
 383         spin_unlock(&aled->lock);
 384
 385         return size;
 386 }
 387
 388 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
 389                    ar8327_led_enable_hw_mode_show,
 390                    ar8327_led_enable_hw_mode_store);
 391
 392 static int
 393 ar8327_led_register(struct ar8327_led *aled)
 394 {
 395         int ret;
 396
 397         ret = led_classdev_register(NULL, &aled->cdev);
 398         if (ret < 0)
 399                 return ret;
 400
 401         if (aled->mode == AR8327_LED_MODE_HW) {
 402                 ret = device_create_file(aled->cdev.dev,
 403                                          &dev_attr_enable_hw_mode);
 404                 if (ret)
 405                         goto err_unregister;
 406         }
 407
 408         return 0;
 409
 410 err_unregister:
 411         led_classdev_unregister(&aled->cdev);
 412         return ret;
 413 }
 414
 415 static void
 416 ar8327_led_unregister(struct ar8327_led *aled)
 417 {
 418         if (aled->mode == AR8327_LED_MODE_HW)
 419                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
 420
 421         led_classdev_unregister(&aled->cdev);
 422         cancel_work_sync(&aled->led_work);
 423 }
 424
 425 static int
 426 ar8327_led_create(struct ar8xxx_priv *priv,
 427                   const struct ar8327_led_info *led_info)
 428 {
 429         struct ar8327_data *data = priv->chip_data;
 430         struct ar8327_led *aled;
 431         int ret;
 432
 433         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 434                 return 0;
 435
 436         if (!led_info->name)
 437                 return -EINVAL;
 438
 439         if (led_info->led_num >= AR8327_NUM_LEDS)
 440                 return -EINVAL;
 441
 442         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
 443                        GFP_KERNEL);
 444         if (!aled)
 445                 return -ENOMEM;
 446
 447         aled->sw_priv = priv;
 448         aled->led_num = led_info->led_num;
 449         aled->active_low = led_info->active_low;
 450         aled->mode = led_info->mode;
 451
 452         if (aled->mode == AR8327_LED_MODE_HW)
 453                 aled->enable_hw_mode = true;
 454
 455         aled->name = (char *)(aled + 1);
 456         strcpy(aled->name, led_info->name);
 457
 458         aled->cdev.name = aled->name;
 459         aled->cdev.brightness_set = ar8327_led_set_brightness;
 460         aled->cdev.blink_set = ar8327_led_blink_set;
 461         aled->cdev.default_trigger = led_info->default_trigger;
 462
 463         spin_lock_init(&aled->lock);
 464         mutex_init(&aled->mutex);
 465         INIT_WORK(&aled->led_work, ar8327_led_work_func);
 466
 467         ret = ar8327_led_register(aled);
 468         if (ret)
 469                 goto err_free;
 470
 471         data->leds[data->num_leds++] = aled;
 472
 473         return 0;
 474
 475 err_free:
 476         kfree(aled);
 477         return ret;
 478 }
 479
 480 static void
 481 ar8327_led_destroy(struct ar8327_led *aled)
 482 {
 483         ar8327_led_unregister(aled);
 484         kfree(aled);
 485 }
 486
 487 static void
 488 ar8327_leds_init(struct ar8xxx_priv *priv)
 489 {
 490         struct ar8327_data *data = priv->chip_data;
 491         unsigned i;
 492
 493         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 494                 return;
 495
 496         for (i = 0; i < data->num_leds; i++) {
 497                 struct ar8327_led *aled;
 498
 499                 aled = data->leds[i];
 500
 501                 if (aled->enable_hw_mode)
 502                         aled->pattern = AR8327_LED_PATTERN_RULE;
 503                 else
 504                         aled->pattern = AR8327_LED_PATTERN_OFF;
 505
 506                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
 507         }
 508 }
 509
 510 static void
 511 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
 512 {
 513         struct ar8327_data *data = priv->chip_data;
 514         unsigned i;
 515
 516         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 517                 return;
 518
 519         for (i = 0; i < data->num_leds; i++) {
 520                 struct ar8327_led *aled;
 521
 522                 aled = data->leds[i];
 523                 ar8327_led_destroy(aled);
 524         }
 525
 526         kfree(data->leds);
 527 }
 528
 529 static int
 530 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
 531                        struct ar8327_platform_data *pdata)
 532 {
 533         struct ar8327_led_cfg *led_cfg;
 534         struct ar8327_data *data = priv->chip_data;
 535         u32 pos, new_pos;
 536         u32 t;
 537
 538         if (!pdata)
 539                 return -EINVAL;
 540
 541         priv->get_port_link = pdata->get_port_link;
 542
 543         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
 544         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
 545
 546         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
 547         if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
 548             t |= AR8337_PAD_MAC06_EXCHANGE_EN;
 549         ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
 550
 551         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
 552         ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
 553         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
 554         ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
 555
 556         pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
 557         new_pos = pos;
 558
 559         led_cfg = pdata->led_cfg;
 560         if (led_cfg) {
 561                 if (led_cfg->open_drain)
 562                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 563                 else
 564                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 565
 566                 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
 567                 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
 568                 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
 569                 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
 570
 571                 if (new_pos != pos)
 572                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
 573         }
 574
 575         if (pdata->sgmii_cfg) {
 576                 t = pdata->sgmii_cfg->sgmii_ctrl;
 577                 if (priv->chip_rev == 1)
 578                         t |= AR8327_SGMII_CTRL_EN_PLL |
 579                              AR8327_SGMII_CTRL_EN_RX |
 580                              AR8327_SGMII_CTRL_EN_TX;
 581                 else
 582                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
 583                                AR8327_SGMII_CTRL_EN_RX |
 584                                AR8327_SGMII_CTRL_EN_TX);
 585
 586                 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
 587
 588                 if (pdata->sgmii_cfg->serdes_aen)
 589                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
 590                 else
 591                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
 592         }
 593
 594         ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
 595
 596         if (pdata->leds && pdata->num_leds) {
 597                 int i;
 598
 599                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
 600                                      GFP_KERNEL);
 601                 if (!data->leds)
 602                         return -ENOMEM;
 603
 604                 for (i = 0; i < pdata->num_leds; i++)
 605                         ar8327_led_create(priv, &pdata->leds[i]);
 606         }
 607
 608         return 0;
 609 }
 610
 611 #ifdef CONFIG_OF
 612 static int
 613 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
 614 {
 615         struct ar8327_data *data = priv->chip_data;
 616         const __be32 *paddr;
 617         int len;
 618         int i;
 619
 620         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
 621         if (!paddr || len < (2 * sizeof(*paddr)))
 622                 return -EINVAL;
 623
 624         len /= sizeof(*paddr);
 625
 626         for (i = 0; i < len - 1; i += 2) {
 627                 u32 reg;
 628                 u32 val;
 629
 630                 reg = be32_to_cpup(paddr + i);
 631                 val = be32_to_cpup(paddr + i + 1);
 632
 633                 switch (reg) {
 634                 case AR8327_REG_PORT_STATUS(0):
 635                         data->port0_status = val;
 636                         break;
 637                 case AR8327_REG_PORT_STATUS(6):
 638                         data->port6_status = val;
 639                         break;
 640                 default:
 641                         ar8xxx_write(priv, reg, val);
 642                         break;
 643                 }
 644         }
 645
 646         return 0;
 647 }
 648 #else
 649 static inline int
 650 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
 651 {
 652         return -EINVAL;
 653 }
 654 #endif
 655
 656 static int
 657 ar8327_hw_init(struct ar8xxx_priv *priv)
 658 {
 659         int ret;
 660
 661         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
 662         if (!priv->chip_data)
 663                 return -ENOMEM;
 664
 665         if (priv->pdev->of_node)
 666                 ret = ar8327_hw_config_of(priv, priv->pdev->of_node);
 667         else
 668                 ret = ar8327_hw_config_pdata(priv,
 669                                              priv->phy->mdio.dev.platform_data);
 670
 671         if (ret)
 672                 return ret;
 673
 674         ar8327_leds_init(priv);
 675
 676         ar8xxx_phy_init(priv);
 677
 678         return 0;
 679 }
 680
 681 static void
 682 ar8327_cleanup(struct ar8xxx_priv *priv)
 683 {
 684         ar8327_leds_cleanup(priv);
 685 }
 686
 687 static void
 688 ar8327_init_globals(struct ar8xxx_priv *priv)
 689 {
 690         struct ar8327_data *data = priv->chip_data;
 691         u32 t;
 692         int i;
 693
 694         /* enable CPU port and disable mirror port */
 695         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
 696             AR8327_FWD_CTRL0_MIRROR_PORT;
 697         ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
 698
 699         /* forward multicast and broadcast frames to CPU */
 700         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
 701             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
 702             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
 703         ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
 704
 705         /* enable jumbo frames */
 706         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
 707                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
 708
 709         /* Enable MIB counters */
 710         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
 711                        AR8327_MODULE_EN_MIB);
 712
 713         /* Disable EEE on all phy's due to stability issues */
 714         for (i = 0; i < AR8XXX_NUM_PHYS; i++)
 715                 data->eee[i] = false;
 716 }
 717
 718 static void
 719 ar8327_init_port(struct ar8xxx_priv *priv, int port)
 720 {
 721         struct ar8327_data *data = priv->chip_data;
 722         u32 t;
 723
 724         if (port == AR8216_PORT_CPU)
 725                 t = data->port0_status;
 726         else if (port == 6)
 727                 t = data->port6_status;
 728         else
 729                 t = AR8216_PORT_STATUS_LINK_AUTO;
 730
 731         if (port != AR8216_PORT_CPU && port != 6) {
 732                 /*hw limitation:if configure mac when there is traffic,
 733                 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
 734                 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0);
 735                 msleep(100);
 736                 t |= AR8216_PORT_STATUS_FLOW_CONTROL;
 737                 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
 738         } else {
 739                 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
 740         }
 741
 742         ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
 743
 744         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0);
 745
 746         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
 747         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
 748
 749         t = AR8327_PORT_LOOKUP_LEARN;
 750         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
 751         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
 752 }
 753
 754 static u32
 755 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
 756 {
 757         u32 t;
 758
 759         t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
 760         /* map the flow control autoneg result bits to the flow control bits
 761          * used in forced mode to allow ar8216_read_port_link detect
 762          * flow control properly if autoneg is used
 763          */
 764         if (t & AR8216_PORT_STATUS_LINK_UP &&
 765             t & AR8216_PORT_STATUS_LINK_AUTO) {
 766                 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
 767                 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
 768                         t |= AR8216_PORT_STATUS_TXFLOW;
 769                 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
 770                         t |= AR8216_PORT_STATUS_RXFLOW;
 771         }
 772
 773         return t;
 774 }
 775
 776 static u32
 777 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
 778 {
 779         int phy;
 780         u16 t;
 781
 782         if (port >= priv->dev.ports)
 783                 return 0;
 784
 785         if (port == 0 || port == 6)
 786                 return 0;
 787
 788         phy = port - 1;
 789
 790         /* EEE Ability Auto-negotiation Result */
 791         t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);
 792
 793         return mmd_eee_adv_to_ethtool_adv_t(t);
 794 }
 795
 796 static int
 797 ar8327_atu_flush(struct ar8xxx_priv *priv)
 798 {
 799         int ret;
 800
 801         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
 802                               AR8327_ATU_FUNC_BUSY, 0);
 803         if (!ret)
 804                 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
 805                              AR8327_ATU_FUNC_OP_FLUSH |
 806                              AR8327_ATU_FUNC_BUSY);
 807
 808         return ret;
 809 }
 810
 811 static int
 812 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
 813 {
 814         u32 t;
 815         int ret;
 816
 817         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
 818                               AR8327_ATU_FUNC_BUSY, 0);
 819         if (!ret) {
 820                 t = (port << AR8327_ATU_PORT_NUM_S);
 821                 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
 822                 t |= AR8327_ATU_FUNC_BUSY;
 823                 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int
 830 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
 831 {
 832         u32 fwd_ctrl, frame_ack;
 833
 834         fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
 835         frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
 836                       AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
 837                       AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
 838                      AR8327_FRAME_ACK_CTRL_S(port));
 839
 840         return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
 841                         fwd_ctrl) == fwd_ctrl &&
 842                 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
 843                         frame_ack) == frame_ack;
 844 }
 845
 846 static void
 847 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
 848 {
 849         int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
 850         u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
 851                           AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
 852                           AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
 853                          AR8327_FRAME_ACK_CTRL_S(port);
 854
 855         if (enable) {
 856                 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
 857                            BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
 858                            BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
 859                 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
 860         } else {
 861                 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
 862                            BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
 863                            BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
 864                 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
 865         }
 866 }
 867
 868 static void
 869 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 870 {
 871         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
 872                             AR8327_VTU_FUNC1_BUSY, 0))
 873                 return;
 874
 875         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
 876                 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
 877
 878         op |= AR8327_VTU_FUNC1_BUSY;
 879         ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
 880 }
 881
 882 static void
 883 ar8327_vtu_flush(struct ar8xxx_priv *priv)
 884 {
 885         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
 886 }
 887
 888 static void
 889 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 890 {
 891         u32 op;
 892         u32 val;
 893         int i;
 894
 895         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
 896         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
 897         for (i = 0; i < AR8327_NUM_PORTS; i++) {
 898                 u32 mode;
 899
 900                 if ((port_mask & BIT(i)) == 0)
 901                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
 902                 else if (priv->vlan == 0)
 903                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
 904                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
 905                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
 906                 else
 907                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
 908
 909                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
 910         }
 911         ar8327_vtu_op(priv, op, val);
 912 }
 913
 914 static void
 915 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 916 {
 917         u32 t;
 918         u32 egress, ingress;
 919         u32 pvid = priv->vlan_id[priv->pvid[port]];
 920
 921         if (priv->vlan) {
 922                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
 923                 ingress = AR8216_IN_SECURE;
 924         } else {
 925                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
 926                 ingress = AR8216_IN_PORT_ONLY;
 927         }
 928
 929         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
 930         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
 931         if (priv->vlan && priv->port_vlan_prio[port]) {
 932                 u32 prio = priv->port_vlan_prio[port];
 933
 934                 t |= prio << AR8327_PORT_VLAN0_DEF_SPRI_S;
 935                 t |= prio << AR8327_PORT_VLAN0_DEF_CPRI_S;
 936         }
 937         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
 938
 939         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
 940         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
 941         if (priv->vlan && priv->port_vlan_prio[port])
 942                 t |= AR8327_PORT_VLAN1_VLAN_PRI_PROP;
 943
 944         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
 945
 946         t = members;
 947         t |= AR8327_PORT_LOOKUP_LEARN;
 948         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
 949         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
 950         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
 951 }
 952
 953 static int
 954 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 955 {
 956         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 957         u8 ports = priv->vlan_table[val->port_vlan];
 958         int i;
 959
 960         val->len = 0;
 961         for (i = 0; i < dev->ports; i++) {
 962                 struct switch_port *p;
 963
 964                 if (!(ports & (1 << i)))
 965                         continue;
 966
 967                 p = &val->value.ports[val->len++];
 968                 p->id = i;
 969                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
 970                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 971                 else
 972                         p->flags = 0;
 973         }
 974         return 0;
 975 }
 976
 977 static int
 978 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
 979 {
 980         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 981         u8 *vt = &priv->vlan_table[val->port_vlan];
 982         int i;
 983
 984         *vt = 0;
 985         for (i = 0; i < val->len; i++) {
 986                 struct switch_port *p = &val->value.ports[i];
 987
 988                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
 989                         if (val->port_vlan == priv->pvid[p->id]) {
 990                                 priv->vlan_tagged |= (1 << p->id);
 991                         }
 992                 } else {
 993                         priv->vlan_tagged &= ~(1 << p->id);
 994                         priv->pvid[p->id] = val->port_vlan;
 995                 }
 996
 997                 *vt |= 1 << p->id;
 998         }
 999         return 0;
1000 }
1001
1002 static void
1003 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1004 {
1005         int port;
1006
1007         /* reset all mirror registers */
1008         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1009                    AR8327_FWD_CTRL0_MIRROR_PORT,
1010                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1011         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1012                 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
1013                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1014
1015                 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1016                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1017         }
1018
1019         /* now enable mirroring if necessary */
1020         if (priv->source_port >= AR8327_NUM_PORTS ||
1021             priv->monitor_port >= AR8327_NUM_PORTS ||
1022             priv->source_port == priv->monitor_port) {
1023                 return;
1024         }
1025
1026         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1027                    AR8327_FWD_CTRL0_MIRROR_PORT,
1028                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1029
1030         if (priv->mirror_rx)
1031                 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1032                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1033
1034         if (priv->mirror_tx)
1035                 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1036                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1037 }
1038
1039 static int
1040 ar8327_sw_set_eee(struct switch_dev *dev,
1041                   const struct switch_attr *attr,
1042                   struct switch_val *val)
1043 {
1044         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1045         struct ar8327_data *data = priv->chip_data;
1046         int port = val->port_vlan;
1047         int phy;
1048
1049         if (port >= dev->ports)
1050                 return -EINVAL;
1051         if (port == 0 || port == 6)
1052                 return -EOPNOTSUPP;
1053
1054         phy = port - 1;
1055
1056         data->eee[phy] = !!(val->value.i);
1057
1058         return 0;
1059 }
1060
1061 static int
1062 ar8327_sw_get_eee(struct switch_dev *dev,
1063                   const struct switch_attr *attr,
1064                   struct switch_val *val)
1065 {
1066         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1067         const struct ar8327_data *data = priv->chip_data;
1068         int port = val->port_vlan;
1069         int phy;
1070
1071         if (port >= dev->ports)
1072                 return -EINVAL;
1073         if (port == 0 || port == 6)
1074                 return -EOPNOTSUPP;
1075
1076         phy = port - 1;
1077
1078         val->value.i = data->eee[phy];
1079
1080         return 0;
1081 }
1082
1083 static void
1084 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1085 {
1086         int timeout = 20;
1087
1088         while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) {
1089                 udelay(10);
1090                 cond_resched();
1091         }
1092
1093         if (!timeout)
1094                 pr_err("ar8327: timeout waiting for atu to become ready\n");
1095 }
1096
1097 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1098                                  struct arl_entry *a, u32 *status, enum arl_op op)
1099 {
1100         struct mii_bus *bus = priv->mii_bus;
1101         u16 r2, page;
1102         u16 r1_data0, r1_data1, r1_data2, r1_func;
1103         u32 val0, val1, val2;
1104
1105         split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1106         r2 |= 0x10;
1107
1108         r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1109         r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1110         r1_func  = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1111
1112         switch (op) {
1113         case AR8XXX_ARL_INITIALIZE:
1114                 /* all ATU registers are on the same page
1115                 * therefore set page only once
1116                 */
1117                 bus->write(bus, 0x18, 0, page);
1118                 wait_for_page_switch();
1119
1120                 ar8327_wait_atu_ready(priv, r2, r1_func);
1121
1122                 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1123                 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1124                 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1125                 break;
1126         case AR8XXX_ARL_GET_NEXT:
1127                 ar8xxx_mii_write32(priv, r2, r1_func,
1128                                    AR8327_ATU_FUNC_OP_GET_NEXT |
1129                                    AR8327_ATU_FUNC_BUSY);
1130                 ar8327_wait_atu_ready(priv, r2, r1_func);
1131
1132                 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1133                 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1134                 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1135
1136                 *status = val2 & AR8327_ATU_STATUS;
1137                 if (!*status)
1138                         break;
1139
1140                 a->portmap = (val1 & AR8327_ATU_PORTS) >> AR8327_ATU_PORTS_S;
1141                 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1142                 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1143                 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1144                 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1145                 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1146                 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1147                 break;
1148         }
1149 }
1150
1151 static int
1152 ar8327_sw_hw_apply(struct switch_dev *dev)
1153 {
1154         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1155         const struct ar8327_data *data = priv->chip_data;
1156         int ret, i;
1157
1158         ret = ar8xxx_sw_hw_apply(dev);
1159         if (ret)
1160                 return ret;
1161
1162         for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1163                 if (data->eee[i])
1164                         ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1165                                AR8327_EEE_CTRL_DISABLE_PHY(i));
1166                 else
1167                         ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1168                                AR8327_EEE_CTRL_DISABLE_PHY(i));
1169         }
1170
1171         return 0;
1172 }
1173
1174 int
1175 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1176                                  const struct switch_attr *attr,
1177                                  struct switch_val *val)
1178 {
1179         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1180         int port = val->port_vlan;
1181
1182         if (port >= dev->ports)
1183                 return -EINVAL;
1184
1185         mutex_lock(&priv->reg_mutex);
1186         val->value.i = ar8327_get_port_igmp(priv, port);
1187         mutex_unlock(&priv->reg_mutex);
1188
1189         return 0;
1190 }
1191
1192 int
1193 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1194                                  const struct switch_attr *attr,
1195                                  struct switch_val *val)
1196 {
1197         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1198         int port = val->port_vlan;
1199
1200         if (port >= dev->ports)
1201                 return -EINVAL;
1202
1203         mutex_lock(&priv->reg_mutex);
1204         ar8327_set_port_igmp(priv, port, val->value.i);
1205         mutex_unlock(&priv->reg_mutex);
1206
1207         return 0;
1208 }
1209
1210 int
1211 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1212                             const struct switch_attr *attr,
1213                             struct switch_val *val)
1214 {
1215         int port;
1216
1217         for (port = 0; port < dev->ports; port++) {
1218                 val->port_vlan = port;
1219                 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1220                     !val->value.i)
1221                         break;
1222         }
1223
1224         return 0;
1225 }
1226
1227 int
1228 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1229                             const struct switch_attr *attr,
1230                             struct switch_val *val)
1231 {
1232         int port;
1233
1234         for (port = 0; port < dev->ports; port++) {
1235                 val->port_vlan = port;
1236                 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1237                         break;
1238         }
1239
1240         return 0;
1241 }
1242
1243 int
1244 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1245                       const struct switch_attr *attr,
1246                       struct switch_val *val)
1247 {
1248         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1249         u32 val_reg;
1250
1251         mutex_lock(&priv->reg_mutex);
1252         val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1253         val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1254         mutex_unlock(&priv->reg_mutex);
1255
1256         return 0;
1257 }
1258
1259 int
1260 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1261                       const struct switch_attr *attr,
1262                       struct switch_val *val)
1263 {
1264         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1265
1266         mutex_lock(&priv->reg_mutex);
1267         if (val->value.i)
1268                 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1269                                AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1270         else
1271                 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1272                                  AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1273         mutex_unlock(&priv->reg_mutex);
1274
1275         return 0;
1276 }
1277
1278 static int
1279 ar8327_sw_set_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,
1280                              struct switch_val *val)
1281 {
1282         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1283         int port = val->port_vlan;
1284
1285         if (port >= dev->ports)
1286                 return -EINVAL;
1287         if (port == 0 || port == 6)
1288                 return -EOPNOTSUPP;
1289         if (val->value.i < 0 || val->value.i > 7)
1290                 return -EINVAL;
1291
1292         priv->port_vlan_prio[port] = val->value.i;
1293
1294         return 0;
1295 }
1296
1297 static int
1298 ar8327_sw_get_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,
1299                   struct switch_val *val)
1300 {
1301         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1302         int port = val->port_vlan;
1303
1304         val->value.i = priv->port_vlan_prio[port];
1305
1306         return 0;
1307 }
1308
1309 static const struct switch_attr ar8327_sw_attr_globals[] = {
1310         {
1311                 .type = SWITCH_TYPE_INT,
1312                 .name = "enable_vlan",
1313                 .description = "Enable VLAN mode",
1314                 .set = ar8xxx_sw_set_vlan,
1315                 .get = ar8xxx_sw_get_vlan,
1316                 .max = 1
1317         },
1318         {
1319                 .type = SWITCH_TYPE_NOVAL,
1320                 .name = "reset_mibs",
1321                 .description = "Reset all MIB counters",
1322                 .set = ar8xxx_sw_set_reset_mibs,
1323         },
1324         {
1325                 .type = SWITCH_TYPE_INT,
1326                 .name = "ar8xxx_mib_poll_interval",
1327                 .description = "MIB polling interval in msecs (0 to disable)",
1328                 .set = ar8xxx_sw_set_mib_poll_interval,
1329                 .get = ar8xxx_sw_get_mib_poll_interval
1330         },
1331         {
1332                 .type = SWITCH_TYPE_INT,
1333                 .name = "ar8xxx_mib_type",
1334                 .description = "MIB type (0=basic 1=extended)",
1335                 .set = ar8xxx_sw_set_mib_type,
1336                 .get = ar8xxx_sw_get_mib_type
1337         },
1338         {
1339                 .type = SWITCH_TYPE_INT,
1340                 .name = "enable_mirror_rx",
1341                 .description = "Enable mirroring of RX packets",
1342                 .set = ar8xxx_sw_set_mirror_rx_enable,
1343                 .get = ar8xxx_sw_get_mirror_rx_enable,
1344                 .max = 1
1345         },
1346         {
1347                 .type = SWITCH_TYPE_INT,
1348                 .name = "enable_mirror_tx",
1349                 .description = "Enable mirroring of TX packets",
1350                 .set = ar8xxx_sw_set_mirror_tx_enable,
1351                 .get = ar8xxx_sw_get_mirror_tx_enable,
1352                 .max = 1
1353         },
1354         {
1355                 .type = SWITCH_TYPE_INT,
1356                 .name = "mirror_monitor_port",
1357                 .description = "Mirror monitor port",
1358                 .set = ar8xxx_sw_set_mirror_monitor_port,
1359                 .get = ar8xxx_sw_get_mirror_monitor_port,
1360                 .max = AR8327_NUM_PORTS - 1
1361         },
1362         {
1363                 .type = SWITCH_TYPE_INT,
1364                 .name = "mirror_source_port",
1365                 .description = "Mirror source port",
1366                 .set = ar8xxx_sw_set_mirror_source_port,
1367                 .get = ar8xxx_sw_get_mirror_source_port,
1368                 .max = AR8327_NUM_PORTS - 1
1369         },
1370         {
1371                 .type = SWITCH_TYPE_INT,
1372                 .name = "arl_age_time",
1373                 .description = "ARL age time (secs)",
1374                 .set = ar8xxx_sw_set_arl_age_time,
1375                 .get = ar8xxx_sw_get_arl_age_time,
1376         },
1377         {
1378                 .type = SWITCH_TYPE_STRING,
1379                 .name = "arl_table",
1380                 .description = "Get ARL table",
1381                 .set = NULL,
1382                 .get = ar8xxx_sw_get_arl_table,
1383         },
1384         {
1385                 .type = SWITCH_TYPE_NOVAL,
1386                 .name = "flush_arl_table",
1387                 .description = "Flush ARL table",
1388                 .set = ar8xxx_sw_set_flush_arl_table,
1389         },
1390         {
1391                 .type = SWITCH_TYPE_INT,
1392                 .name = "igmp_snooping",
1393                 .description = "Enable IGMP Snooping",
1394                 .set = ar8327_sw_set_igmp_snooping,
1395                 .get = ar8327_sw_get_igmp_snooping,
1396                 .max = 1
1397         },
1398         {
1399                 .type = SWITCH_TYPE_INT,
1400                 .name = "igmp_v3",
1401                 .description = "Enable IGMPv3 support",
1402                 .set = ar8327_sw_set_igmp_v3,
1403                 .get = ar8327_sw_get_igmp_v3,
1404                 .max = 1
1405         },
1406 };
1407
1408 static const struct switch_attr ar8327_sw_attr_port[] = {
1409         {
1410                 .type = SWITCH_TYPE_NOVAL,
1411                 .name = "reset_mib",
1412                 .description = "Reset single port MIB counters",
1413                 .set = ar8xxx_sw_set_port_reset_mib,
1414         },
1415         {
1416                 .type = SWITCH_TYPE_STRING,
1417                 .name = "mib",
1418                 .description = "Get port's MIB counters",
1419                 .set = NULL,
1420                 .get = ar8xxx_sw_get_port_mib,
1421         },
1422         {
1423                 .type = SWITCH_TYPE_INT,
1424                 .name = "enable_eee",
1425                 .description = "Enable EEE PHY sleep mode",
1426                 .set = ar8327_sw_set_eee,
1427                 .get = ar8327_sw_get_eee,
1428                 .max = 1,
1429         },
1430         {
1431                 .type = SWITCH_TYPE_NOVAL,
1432                 .name = "flush_arl_table",
1433                 .description = "Flush port's ARL table entries",
1434                 .set = ar8xxx_sw_set_flush_port_arl_table,
1435         },
1436         {
1437                 .type = SWITCH_TYPE_INT,
1438                 .name = "igmp_snooping",
1439                 .description = "Enable port's IGMP Snooping",
1440                 .set = ar8327_sw_set_port_igmp_snooping,
1441                 .get = ar8327_sw_get_port_igmp_snooping,
1442                 .max = 1
1443         },
1444         {
1445                 .type = SWITCH_TYPE_INT,
1446                 .name = "vlan_prio",
1447                 .description = "Port VLAN default priority (VLAN PCP) (0-7)",
1448                 .set = ar8327_sw_set_port_vlan_prio,
1449                 .get = ar8327_sw_get_port_vlan_prio,
1450                 .max = 7,
1451         },
1452 };
1453
1454 static const struct switch_dev_ops ar8327_sw_ops = {
1455         .attr_global = {
1456                 .attr = ar8327_sw_attr_globals,
1457                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1458         },
1459         .attr_port = {
1460                 .attr = ar8327_sw_attr_port,
1461                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1462         },
1463         .attr_vlan = {
1464                 .attr = ar8xxx_sw_attr_vlan,
1465                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1466         },
1467         .get_port_pvid = ar8xxx_sw_get_pvid,
1468         .set_port_pvid = ar8xxx_sw_set_pvid,
1469         .get_vlan_ports = ar8327_sw_get_ports,
1470         .set_vlan_ports = ar8327_sw_set_ports,
1471         .apply_config = ar8327_sw_hw_apply,
1472         .reset_switch = ar8xxx_sw_reset_switch,
1473         .get_port_link = ar8xxx_sw_get_port_link,
1474         .get_port_stats = ar8xxx_sw_get_port_stats,
1475 };
1476
1477 const struct ar8xxx_chip ar8327_chip = {
1478         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1479         .config_at_probe = true,
1480         .mii_lo_first = true,
1481
1482         .name = "Atheros AR8327",
1483         .ports = AR8327_NUM_PORTS,
1484         .vlans = AR8X16_MAX_VLANS,
1485         .swops = &ar8327_sw_ops,
1486
1487         .reg_port_stats_start = 0x1000,
1488         .reg_port_stats_length = 0x100,
1489         .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1490
1491         .hw_init = ar8327_hw_init,
1492         .cleanup = ar8327_cleanup,
1493         .init_globals = ar8327_init_globals,
1494         .init_port = ar8327_init_port,
1495         .setup_port = ar8327_setup_port,
1496         .read_port_status = ar8327_read_port_status,
1497         .read_port_eee_status = ar8327_read_port_eee_status,
1498         .atu_flush = ar8327_atu_flush,
1499         .atu_flush_port = ar8327_atu_flush_port,
1500         .vtu_flush = ar8327_vtu_flush,
1501         .vtu_load_vlan = ar8327_vtu_load_vlan,
1502         .phy_fixup = ar8327_phy_fixup,
1503         .set_mirror_regs = ar8327_set_mirror_regs,
1504         .get_arl_entry = ar8327_get_arl_entry,
1505         .sw_hw_apply = ar8327_sw_hw_apply,
1506
1507         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1508         .mib_decs = ar8236_mibs,
1509         .mib_func = AR8327_REG_MIB_FUNC,
1510         .mib_rxb_id = AR8236_MIB_RXB_ID,
1511         .mib_txb_id = AR8236_MIB_TXB_ID,
1512 };
1513
1514 const struct ar8xxx_chip ar8337_chip = {
1515         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1516         .config_at_probe = true,
1517         .mii_lo_first = true,
1518
1519         .name = "Atheros AR8337",
1520         .ports = AR8327_NUM_PORTS,
1521         .vlans = AR8X16_MAX_VLANS,
1522         .swops = &ar8327_sw_ops,
1523
1524         .reg_port_stats_start = 0x1000,
1525         .reg_port_stats_length = 0x100,
1526         .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1527
1528         .hw_init = ar8327_hw_init,
1529         .cleanup = ar8327_cleanup,
1530         .init_globals = ar8327_init_globals,
1531         .init_port = ar8327_init_port,
1532         .setup_port = ar8327_setup_port,
1533         .read_port_status = ar8327_read_port_status,
1534         .read_port_eee_status = ar8327_read_port_eee_status,
1535         .atu_flush = ar8327_atu_flush,
1536         .atu_flush_port = ar8327_atu_flush_port,
1537         .vtu_flush = ar8327_vtu_flush,
1538         .vtu_load_vlan = ar8327_vtu_load_vlan,
1539         .phy_fixup = ar8327_phy_fixup,
1540         .set_mirror_regs = ar8327_set_mirror_regs,
1541         .get_arl_entry = ar8327_get_arl_entry,
1542         .sw_hw_apply = ar8327_sw_hw_apply,
1543         .phy_rgmii_set = ar8327_phy_rgmii_set,
1544
1545         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1546         .mib_decs = ar8236_mibs,
1547         .mib_func = AR8327_REG_MIB_FUNC,
1548         .mib_rxb_id = AR8236_MIB_RXB_ID,
1549         .mib_txb_id = AR8236_MIB_TXB_ID,
1550 };