2 * ar8327.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
49 case AR8327_PAD_MAC2MAC_MII:
50 t = AR8327_PAD_MAC_MII_EN;
52 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
54 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
57 case AR8327_PAD_MAC2MAC_GMII:
58 t = AR8327_PAD_MAC_GMII_EN;
60 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
62 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
65 case AR8327_PAD_MAC_SGMII:
66 t = AR8327_PAD_SGMII_EN;
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
74 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
75 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
76 if (cfg->rxclk_delay_en)
77 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
78 if (cfg->txclk_delay_en)
79 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
81 if (cfg->sgmii_delay_en)
82 t |= AR8327_PAD_SGMII_DELAY_EN;
86 case AR8327_PAD_MAC2PHY_MII:
87 t = AR8327_PAD_PHY_MII_EN;
89 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
91 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
94 case AR8327_PAD_MAC2PHY_GMII:
95 t = AR8327_PAD_PHY_GMII_EN;
96 if (cfg->pipe_rxclk_sel)
97 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
99 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
101 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
104 case AR8327_PAD_MAC_RGMII:
105 t = AR8327_PAD_RGMII_EN;
106 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
107 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
108 if (cfg->rxclk_delay_en)
109 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
110 if (cfg->txclk_delay_en)
111 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
114 case AR8327_PAD_PHY_GMII:
115 t = AR8327_PAD_PHYX_GMII_EN;
118 case AR8327_PAD_PHY_RGMII:
119 t = AR8327_PAD_PHYX_RGMII_EN;
122 case AR8327_PAD_PHY_MII:
123 t = AR8327_PAD_PHYX_MII_EN;
131 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
133 switch (priv->chip_rev) {
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
142 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);
145 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
158 if (!cfg->force_link)
159 return AR8216_PORT_STATUS_LINK_AUTO;
161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
166 switch (cfg->speed) {
167 case AR8327_PORT_SPEED_10:
168 t |= AR8216_PORT_SPEED_10M;
170 case AR8327_PORT_SPEED_100:
171 t |= AR8216_PORT_SPEED_100M;
173 case AR8327_PORT_SPEED_1000:
174 t |= AR8216_PORT_SPEED_1000M;
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
184 static const struct ar8327_led_entry
185 ar8327_led_map[AR8327_NUM_LEDS] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
209 enum ar8327_led_pattern pattern)
211 const struct ar8327_led_entry *entry;
213 entry = &ar8327_led_map[led_num];
214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
215 (3 << entry->shift), pattern << entry->shift);
219 ar8327_led_work_func(struct work_struct *work)
221 struct ar8327_led *aled;
224 aled = container_of(work, struct ar8327_led, led_work);
226 pattern = aled->pattern;
228 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
233 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
235 if (aled->pattern == pattern)
238 aled->pattern = pattern;
239 schedule_work(&aled->led_work);
242 static inline struct ar8327_led *
243 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
245 return container_of(led_cdev, struct ar8327_led, cdev);
249 ar8327_led_blink_set(struct led_classdev *led_cdev,
250 unsigned long *delay_on,
251 unsigned long *delay_off)
253 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
255 if (*delay_on == 0 && *delay_off == 0) {
260 if (*delay_on != 125 || *delay_off != 125) {
262 * The hardware only supports blinking at 4Hz. Fall back
263 * to software implementation in other cases.
268 spin_lock(&aled->lock);
270 aled->enable_hw_mode = false;
271 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
273 spin_unlock(&aled->lock);
279 ar8327_led_set_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
282 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
286 active = (brightness != LED_OFF);
287 active ^= aled->active_low;
289 pattern = (active) ? AR8327_LED_PATTERN_ON :
290 AR8327_LED_PATTERN_OFF;
292 spin_lock(&aled->lock);
294 aled->enable_hw_mode = false;
295 ar8327_led_schedule_change(aled, pattern);
297 spin_unlock(&aled->lock);
301 ar8327_led_enable_hw_mode_show(struct device *dev,
302 struct device_attribute *attr,
305 struct led_classdev *led_cdev = dev_get_drvdata(dev);
306 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
309 ret += scnprintf(buf, PAGE_SIZE, "%d\n", aled->enable_hw_mode);
315 ar8327_led_enable_hw_mode_store(struct device *dev,
316 struct device_attribute *attr,
320 struct led_classdev *led_cdev = dev_get_drvdata(dev);
321 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
326 ret = kstrtou8(buf, 10, &value);
330 spin_lock(&aled->lock);
332 aled->enable_hw_mode = !!value;
333 if (aled->enable_hw_mode)
334 pattern = AR8327_LED_PATTERN_RULE;
336 pattern = AR8327_LED_PATTERN_OFF;
338 ar8327_led_schedule_change(aled, pattern);
340 spin_unlock(&aled->lock);
345 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
346 ar8327_led_enable_hw_mode_show,
347 ar8327_led_enable_hw_mode_store);
350 ar8327_led_register(struct ar8327_led *aled)
354 ret = led_classdev_register(NULL, &aled->cdev);
358 if (aled->mode == AR8327_LED_MODE_HW) {
359 ret = device_create_file(aled->cdev.dev,
360 &dev_attr_enable_hw_mode);
368 led_classdev_unregister(&aled->cdev);
373 ar8327_led_unregister(struct ar8327_led *aled)
375 if (aled->mode == AR8327_LED_MODE_HW)
376 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
378 led_classdev_unregister(&aled->cdev);
379 cancel_work_sync(&aled->led_work);
383 ar8327_led_create(struct ar8xxx_priv *priv,
384 const struct ar8327_led_info *led_info)
386 struct ar8327_data *data = priv->chip_data;
387 struct ar8327_led *aled;
390 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
396 if (led_info->led_num >= AR8327_NUM_LEDS)
399 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
404 aled->sw_priv = priv;
405 aled->led_num = led_info->led_num;
406 aled->active_low = led_info->active_low;
407 aled->mode = led_info->mode;
409 if (aled->mode == AR8327_LED_MODE_HW)
410 aled->enable_hw_mode = true;
412 aled->name = (char *)(aled + 1);
413 strcpy(aled->name, led_info->name);
415 aled->cdev.name = aled->name;
416 aled->cdev.brightness_set = ar8327_led_set_brightness;
417 aled->cdev.blink_set = ar8327_led_blink_set;
418 aled->cdev.default_trigger = led_info->default_trigger;
420 spin_lock_init(&aled->lock);
421 mutex_init(&aled->mutex);
422 INIT_WORK(&aled->led_work, ar8327_led_work_func);
424 ret = ar8327_led_register(aled);
428 data->leds[data->num_leds++] = aled;
438 ar8327_led_destroy(struct ar8327_led *aled)
440 ar8327_led_unregister(aled);
445 ar8327_leds_init(struct ar8xxx_priv *priv)
447 struct ar8327_data *data = priv->chip_data;
450 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
453 for (i = 0; i < data->num_leds; i++) {
454 struct ar8327_led *aled;
456 aled = data->leds[i];
458 if (aled->enable_hw_mode)
459 aled->pattern = AR8327_LED_PATTERN_RULE;
461 aled->pattern = AR8327_LED_PATTERN_OFF;
463 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
468 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
470 struct ar8327_data *data = priv->chip_data;
473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
476 for (i = 0; i < data->num_leds; i++) {
477 struct ar8327_led *aled;
479 aled = data->leds[i];
480 ar8327_led_destroy(aled);
487 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
488 struct ar8327_platform_data *pdata)
490 struct ar8327_led_cfg *led_cfg;
491 struct ar8327_data *data = priv->chip_data;
498 priv->get_port_link = pdata->get_port_link;
500 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
501 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
503 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
504 if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
505 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
506 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
508 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
509 if (chip_is_ar8337(priv)) {
511 * Workaround: RGMII RX delay setting needs to be
512 * always specified for AR8337 to avoid port 5
513 * RX hang on high traffic / flood conditions
515 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
517 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
518 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
519 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
521 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
524 led_cfg = pdata->led_cfg;
526 if (led_cfg->open_drain)
527 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
529 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
531 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
532 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
533 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
534 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
537 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
540 if (pdata->sgmii_cfg) {
541 t = pdata->sgmii_cfg->sgmii_ctrl;
542 if (priv->chip_rev == 1)
543 t |= AR8327_SGMII_CTRL_EN_PLL |
544 AR8327_SGMII_CTRL_EN_RX |
545 AR8327_SGMII_CTRL_EN_TX;
547 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
548 AR8327_SGMII_CTRL_EN_RX |
549 AR8327_SGMII_CTRL_EN_TX);
551 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
553 if (pdata->sgmii_cfg->serdes_aen)
554 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
556 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
559 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
561 if (pdata->leds && pdata->num_leds) {
564 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
569 for (i = 0; i < pdata->num_leds; i++)
570 ar8327_led_create(priv, &pdata->leds[i]);
578 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
580 struct ar8327_data *data = priv->chip_data;
585 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
586 if (!paddr || len < (2 * sizeof(*paddr)))
589 len /= sizeof(*paddr);
591 for (i = 0; i < len - 1; i += 2) {
595 reg = be32_to_cpup(paddr + i);
596 val = be32_to_cpup(paddr + i + 1);
599 case AR8327_REG_PORT_STATUS(0):
600 data->port0_status = val;
602 case AR8327_REG_PORT_STATUS(6):
603 data->port6_status = val;
606 ar8xxx_write(priv, reg, val);
615 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
622 ar8327_hw_init(struct ar8xxx_priv *priv)
626 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
627 if (!priv->chip_data)
630 if (priv->phy->mdio.dev.of_node)
631 ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node);
633 ret = ar8327_hw_config_pdata(priv,
634 priv->phy->mdio.dev.platform_data);
639 ar8327_leds_init(priv);
641 ar8xxx_phy_init(priv);
647 ar8327_cleanup(struct ar8xxx_priv *priv)
649 ar8327_leds_cleanup(priv);
653 ar8327_init_globals(struct ar8xxx_priv *priv)
655 struct ar8327_data *data = priv->chip_data;
659 /* enable CPU port and disable mirror port */
660 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
661 AR8327_FWD_CTRL0_MIRROR_PORT;
662 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
664 /* forward multicast and broadcast frames to CPU */
665 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
666 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
667 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
668 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
670 /* enable jumbo frames */
671 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
672 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
674 /* Enable MIB counters */
675 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
676 AR8327_MODULE_EN_MIB);
678 /* Disable EEE on all phy's due to stability issues */
679 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
680 data->eee[i] = false;
682 if (chip_is_ar8337(priv)) {
683 /* Update HOL registers with values suggested by QCA switch team */
684 for (i = 0; i < AR8327_NUM_PORTS; i++) {
685 if (i == AR8216_PORT_CPU || i == 5 || i == 6) {
686 t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S;
687 t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S;
688 t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S;
689 t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S;
690 t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S;
691 t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S;
692 t |= 0x1e << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S;
694 t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S;
695 t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S;
696 t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S;
697 t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S;
698 t |= 0x19 << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S;
700 ar8xxx_write(priv, AR8327_REG_PORT_HOL_CTRL0(i), t);
702 t = 0x6 << AR8327_PORT_HOL_CTRL1_ING_BUF_S;
703 t |= AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN;
704 t |= AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN;
705 t |= AR8327_PORT_HOL_CTRL1_WRED_EN;
706 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(i),
707 AR8327_PORT_HOL_CTRL1_ING_BUF |
708 AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
709 AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
710 AR8327_PORT_HOL_CTRL1_WRED_EN,
717 ar8327_init_port(struct ar8xxx_priv *priv, int port)
719 struct ar8327_data *data = priv->chip_data;
722 if (port == AR8216_PORT_CPU)
723 t = data->port0_status;
725 t = data->port6_status;
727 t = AR8216_PORT_STATUS_LINK_AUTO;
729 if (port != AR8216_PORT_CPU && port != 6) {
730 /*hw limitation:if configure mac when there is traffic,
731 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
732 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0);
734 t |= AR8216_PORT_STATUS_FLOW_CONTROL;
735 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
737 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
740 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
742 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0);
744 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
745 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
747 t = AR8327_PORT_LOOKUP_LEARN;
748 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
749 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
753 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
757 t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
758 /* map the flow control autoneg result bits to the flow control bits
759 * used in forced mode to allow ar8216_read_port_link detect
760 * flow control properly if autoneg is used
762 if (t & AR8216_PORT_STATUS_LINK_UP &&
763 t & AR8216_PORT_STATUS_LINK_AUTO) {
764 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
765 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
766 t |= AR8216_PORT_STATUS_TXFLOW;
767 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
768 t |= AR8216_PORT_STATUS_RXFLOW;
775 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
780 if (port >= priv->dev.ports)
783 if (port == 0 || port == 6)
788 /* EEE Ability Auto-negotiation Result */
789 t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);
791 return mmd_eee_adv_to_ethtool_adv_t(t);
795 ar8327_atu_flush(struct ar8xxx_priv *priv)
799 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
800 AR8327_ATU_FUNC_BUSY, 0);
802 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
803 AR8327_ATU_FUNC_OP_FLUSH |
804 AR8327_ATU_FUNC_BUSY);
810 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
815 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
816 AR8327_ATU_FUNC_BUSY, 0);
818 t = (port << AR8327_ATU_PORT_NUM_S);
819 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
820 t |= AR8327_ATU_FUNC_BUSY;
821 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
828 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
830 u32 fwd_ctrl, frame_ack;
832 fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
833 frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
834 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
835 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
836 AR8327_FRAME_ACK_CTRL_S(port));
838 return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
839 fwd_ctrl) == fwd_ctrl &&
840 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
841 frame_ack) == frame_ack;
845 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
847 int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
848 u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
849 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
850 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
851 AR8327_FRAME_ACK_CTRL_S(port);
854 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
855 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
856 BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
857 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
859 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
860 BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
861 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
862 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
867 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
869 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
870 AR8327_VTU_FUNC1_BUSY, 0))
873 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
874 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
876 op |= AR8327_VTU_FUNC1_BUSY;
877 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
881 ar8327_vtu_flush(struct ar8xxx_priv *priv)
883 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
887 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
893 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
894 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
895 for (i = 0; i < AR8327_NUM_PORTS; i++) {
898 if ((port_mask & BIT(i)) == 0)
899 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
900 else if (priv->vlan == 0)
901 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
902 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
903 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
905 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
907 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
909 ar8327_vtu_op(priv, op, val);
913 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
917 u32 pvid = priv->vlan_id[priv->pvid[port]];
920 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
921 ingress = AR8216_IN_SECURE;
923 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
924 ingress = AR8216_IN_PORT_ONLY;
927 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
928 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
929 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
931 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
932 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
933 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
936 t |= AR8327_PORT_LOOKUP_LEARN;
937 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
938 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
939 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
943 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
945 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
946 u8 ports = priv->vlan_table[val->port_vlan];
950 for (i = 0; i < dev->ports; i++) {
951 struct switch_port *p;
953 if (!(ports & (1 << i)))
956 p = &val->value.ports[val->len++];
958 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
959 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
967 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
969 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
970 u8 *vt = &priv->vlan_table[val->port_vlan];
974 for (i = 0; i < val->len; i++) {
975 struct switch_port *p = &val->value.ports[i];
977 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
978 if (val->port_vlan == priv->pvid[p->id]) {
979 priv->vlan_tagged |= (1 << p->id);
982 priv->vlan_tagged &= ~(1 << p->id);
983 priv->pvid[p->id] = val->port_vlan;
992 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
996 /* reset all mirror registers */
997 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
998 AR8327_FWD_CTRL0_MIRROR_PORT,
999 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1000 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1001 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
1002 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1004 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1005 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1008 /* now enable mirroring if necessary */
1009 if (priv->source_port >= AR8327_NUM_PORTS ||
1010 priv->monitor_port >= AR8327_NUM_PORTS ||
1011 priv->source_port == priv->monitor_port) {
1015 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1016 AR8327_FWD_CTRL0_MIRROR_PORT,
1017 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1019 if (priv->mirror_rx)
1020 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1021 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1023 if (priv->mirror_tx)
1024 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1025 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1029 ar8327_sw_set_eee(struct switch_dev *dev,
1030 const struct switch_attr *attr,
1031 struct switch_val *val)
1033 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1034 struct ar8327_data *data = priv->chip_data;
1035 int port = val->port_vlan;
1038 if (port >= dev->ports)
1040 if (port == 0 || port == 6)
1045 data->eee[phy] = !!(val->value.i);
1051 ar8327_sw_get_eee(struct switch_dev *dev,
1052 const struct switch_attr *attr,
1053 struct switch_val *val)
1055 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1056 const struct ar8327_data *data = priv->chip_data;
1057 int port = val->port_vlan;
1060 if (port >= dev->ports)
1062 if (port == 0 || port == 6)
1067 val->value.i = data->eee[phy];
1073 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1077 while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout)
1081 pr_err("ar8327: timeout waiting for atu to become ready\n");
1084 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1085 struct arl_entry *a, u32 *status, enum arl_op op)
1087 struct mii_bus *bus = priv->mii_bus;
1089 u16 r1_data0, r1_data1, r1_data2, r1_func;
1090 u32 t, val0, val1, val2;
1093 split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1096 r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1097 r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1098 r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1101 case AR8XXX_ARL_INITIALIZE:
1102 /* all ATU registers are on the same page
1103 * therefore set page only once
1105 bus->write(bus, 0x18, 0, page);
1106 wait_for_page_switch();
1108 ar8327_wait_atu_ready(priv, r2, r1_func);
1110 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1111 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1112 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1114 case AR8XXX_ARL_GET_NEXT:
1115 ar8xxx_mii_write32(priv, r2, r1_func,
1116 AR8327_ATU_FUNC_OP_GET_NEXT |
1117 AR8327_ATU_FUNC_BUSY);
1118 ar8327_wait_atu_ready(priv, r2, r1_func);
1120 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1121 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1122 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1124 *status = val2 & AR8327_ATU_STATUS;
1129 t = AR8327_ATU_PORT0;
1130 while (!(val1 & t) && ++i < AR8327_NUM_PORTS)
1134 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1135 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1136 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1137 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1138 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1139 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1145 ar8327_sw_hw_apply(struct switch_dev *dev)
1147 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1148 const struct ar8327_data *data = priv->chip_data;
1151 ret = ar8xxx_sw_hw_apply(dev);
1155 for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1157 ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1158 AR8327_EEE_CTRL_DISABLE_PHY(i));
1160 ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1161 AR8327_EEE_CTRL_DISABLE_PHY(i));
1168 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1169 const struct switch_attr *attr,
1170 struct switch_val *val)
1172 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1173 int port = val->port_vlan;
1175 if (port >= dev->ports)
1178 mutex_lock(&priv->reg_mutex);
1179 val->value.i = ar8327_get_port_igmp(priv, port);
1180 mutex_unlock(&priv->reg_mutex);
1186 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1187 const struct switch_attr *attr,
1188 struct switch_val *val)
1190 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1191 int port = val->port_vlan;
1193 if (port >= dev->ports)
1196 mutex_lock(&priv->reg_mutex);
1197 ar8327_set_port_igmp(priv, port, val->value.i);
1198 mutex_unlock(&priv->reg_mutex);
1204 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1205 const struct switch_attr *attr,
1206 struct switch_val *val)
1210 for (port = 0; port < dev->ports; port++) {
1211 val->port_vlan = port;
1212 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1221 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1222 const struct switch_attr *attr,
1223 struct switch_val *val)
1227 for (port = 0; port < dev->ports; port++) {
1228 val->port_vlan = port;
1229 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1237 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1241 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1244 mutex_lock(&priv->reg_mutex);
1245 val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1246 val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1247 mutex_unlock(&priv->reg_mutex);
1253 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1254 const struct switch_attr *attr,
1255 struct switch_val *val)
1257 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1259 mutex_lock(&priv->reg_mutex);
1261 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1262 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1264 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1265 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1266 mutex_unlock(&priv->reg_mutex);
1271 static const struct switch_attr ar8327_sw_attr_globals[] = {
1273 .type = SWITCH_TYPE_INT,
1274 .name = "enable_vlan",
1275 .description = "Enable VLAN mode",
1276 .set = ar8xxx_sw_set_vlan,
1277 .get = ar8xxx_sw_get_vlan,
1281 .type = SWITCH_TYPE_NOVAL,
1282 .name = "reset_mibs",
1283 .description = "Reset all MIB counters",
1284 .set = ar8xxx_sw_set_reset_mibs,
1287 .type = SWITCH_TYPE_INT,
1288 .name = "enable_mirror_rx",
1289 .description = "Enable mirroring of RX packets",
1290 .set = ar8xxx_sw_set_mirror_rx_enable,
1291 .get = ar8xxx_sw_get_mirror_rx_enable,
1295 .type = SWITCH_TYPE_INT,
1296 .name = "enable_mirror_tx",
1297 .description = "Enable mirroring of TX packets",
1298 .set = ar8xxx_sw_set_mirror_tx_enable,
1299 .get = ar8xxx_sw_get_mirror_tx_enable,
1303 .type = SWITCH_TYPE_INT,
1304 .name = "mirror_monitor_port",
1305 .description = "Mirror monitor port",
1306 .set = ar8xxx_sw_set_mirror_monitor_port,
1307 .get = ar8xxx_sw_get_mirror_monitor_port,
1308 .max = AR8327_NUM_PORTS - 1
1311 .type = SWITCH_TYPE_INT,
1312 .name = "mirror_source_port",
1313 .description = "Mirror source port",
1314 .set = ar8xxx_sw_set_mirror_source_port,
1315 .get = ar8xxx_sw_get_mirror_source_port,
1316 .max = AR8327_NUM_PORTS - 1
1319 .type = SWITCH_TYPE_INT,
1320 .name = "arl_age_time",
1321 .description = "ARL age time (secs)",
1322 .set = ar8xxx_sw_set_arl_age_time,
1323 .get = ar8xxx_sw_get_arl_age_time,
1326 .type = SWITCH_TYPE_STRING,
1327 .name = "arl_table",
1328 .description = "Get ARL table",
1330 .get = ar8xxx_sw_get_arl_table,
1333 .type = SWITCH_TYPE_NOVAL,
1334 .name = "flush_arl_table",
1335 .description = "Flush ARL table",
1336 .set = ar8xxx_sw_set_flush_arl_table,
1339 .type = SWITCH_TYPE_INT,
1340 .name = "igmp_snooping",
1341 .description = "Enable IGMP Snooping",
1342 .set = ar8327_sw_set_igmp_snooping,
1343 .get = ar8327_sw_get_igmp_snooping,
1347 .type = SWITCH_TYPE_INT,
1349 .description = "Enable IGMPv3 support",
1350 .set = ar8327_sw_set_igmp_v3,
1351 .get = ar8327_sw_get_igmp_v3,
1356 static const struct switch_attr ar8327_sw_attr_port[] = {
1358 .type = SWITCH_TYPE_NOVAL,
1359 .name = "reset_mib",
1360 .description = "Reset single port MIB counters",
1361 .set = ar8xxx_sw_set_port_reset_mib,
1364 .type = SWITCH_TYPE_STRING,
1366 .description = "Get port's MIB counters",
1368 .get = ar8xxx_sw_get_port_mib,
1371 .type = SWITCH_TYPE_INT,
1372 .name = "enable_eee",
1373 .description = "Enable EEE PHY sleep mode",
1374 .set = ar8327_sw_set_eee,
1375 .get = ar8327_sw_get_eee,
1379 .type = SWITCH_TYPE_NOVAL,
1380 .name = "flush_arl_table",
1381 .description = "Flush port's ARL table entries",
1382 .set = ar8xxx_sw_set_flush_port_arl_table,
1385 .type = SWITCH_TYPE_INT,
1386 .name = "igmp_snooping",
1387 .description = "Enable port's IGMP Snooping",
1388 .set = ar8327_sw_set_port_igmp_snooping,
1389 .get = ar8327_sw_get_port_igmp_snooping,
1394 static const struct switch_dev_ops ar8327_sw_ops = {
1396 .attr = ar8327_sw_attr_globals,
1397 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1400 .attr = ar8327_sw_attr_port,
1401 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1404 .attr = ar8xxx_sw_attr_vlan,
1405 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1407 .get_port_pvid = ar8xxx_sw_get_pvid,
1408 .set_port_pvid = ar8xxx_sw_set_pvid,
1409 .get_vlan_ports = ar8327_sw_get_ports,
1410 .set_vlan_ports = ar8327_sw_set_ports,
1411 .apply_config = ar8327_sw_hw_apply,
1412 .reset_switch = ar8xxx_sw_reset_switch,
1413 .get_port_link = ar8xxx_sw_get_port_link,
1414 /* The following op is disabled as it hogs the CPU and degrades performance.
1415 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1418 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1419 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1420 the request to update the MIB counter is cleared. */
1422 .get_port_stats = ar8xxx_sw_get_port_stats,
1426 const struct ar8xxx_chip ar8327_chip = {
1427 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1428 .config_at_probe = true,
1429 .mii_lo_first = true,
1431 .name = "Atheros AR8327",
1432 .ports = AR8327_NUM_PORTS,
1433 .vlans = AR8X16_MAX_VLANS,
1434 .swops = &ar8327_sw_ops,
1436 .reg_port_stats_start = 0x1000,
1437 .reg_port_stats_length = 0x100,
1438 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1440 .hw_init = ar8327_hw_init,
1441 .cleanup = ar8327_cleanup,
1442 .init_globals = ar8327_init_globals,
1443 .init_port = ar8327_init_port,
1444 .setup_port = ar8327_setup_port,
1445 .read_port_status = ar8327_read_port_status,
1446 .read_port_eee_status = ar8327_read_port_eee_status,
1447 .atu_flush = ar8327_atu_flush,
1448 .atu_flush_port = ar8327_atu_flush_port,
1449 .vtu_flush = ar8327_vtu_flush,
1450 .vtu_load_vlan = ar8327_vtu_load_vlan,
1451 .set_mirror_regs = ar8327_set_mirror_regs,
1452 .get_arl_entry = ar8327_get_arl_entry,
1453 .sw_hw_apply = ar8327_sw_hw_apply,
1455 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1456 .mib_decs = ar8236_mibs,
1457 .mib_func = AR8327_REG_MIB_FUNC
1460 const struct ar8xxx_chip ar8337_chip = {
1461 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1462 .config_at_probe = true,
1463 .mii_lo_first = true,
1465 .name = "Atheros AR8337",
1466 .ports = AR8327_NUM_PORTS,
1467 .vlans = AR8X16_MAX_VLANS,
1468 .swops = &ar8327_sw_ops,
1470 .reg_port_stats_start = 0x1000,
1471 .reg_port_stats_length = 0x100,
1472 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1474 .hw_init = ar8327_hw_init,
1475 .cleanup = ar8327_cleanup,
1476 .init_globals = ar8327_init_globals,
1477 .init_port = ar8327_init_port,
1478 .setup_port = ar8327_setup_port,
1479 .read_port_status = ar8327_read_port_status,
1480 .read_port_eee_status = ar8327_read_port_eee_status,
1481 .atu_flush = ar8327_atu_flush,
1482 .atu_flush_port = ar8327_atu_flush_port,
1483 .vtu_flush = ar8327_vtu_flush,
1484 .vtu_load_vlan = ar8327_vtu_load_vlan,
1485 .phy_fixup = ar8327_phy_fixup,
1486 .set_mirror_regs = ar8327_set_mirror_regs,
1487 .get_arl_entry = ar8327_get_arl_entry,
1488 .sw_hw_apply = ar8327_sw_hw_apply,
1490 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1491 .mib_decs = ar8236_mibs,
1492 .mib_func = AR8327_REG_MIB_FUNC