2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/list.h>
21 #include <linux/if_ether.h>
22 #include <linux/skbuff.h>
23 #include <linux/netdevice.h>
24 #include <linux/netlink.h>
25 #include <linux/bitops.h>
26 #include <net/genetlink.h>
27 #include <linux/switch.h>
28 #include <linux/delay.h>
29 #include <linux/phy.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
34 /* size of the vlan table */
35 #define AR8X16_MAX_VLANS 128
36 #define AR8X16_PROBE_RETRIES 10
39 struct switch_dev dev;
40 struct phy_device *phy;
41 u32 (*read)(struct ar8216_priv *priv, int reg);
42 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
43 const struct net_device_ops *ndo_old;
44 struct net_device_ops ndo;
45 struct mutex reg_mutex;
53 /* all fields below are cleared on reset */
55 u16 vlan_id[AR8X16_MAX_VLANS];
56 u8 vlan_table[AR8X16_MAX_VLANS];
58 u16 pvid[AR8216_NUM_PORTS];
61 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
64 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
73 *page = regaddr & 0x1ff;
77 ar8216_mii_read(struct ar8216_priv *priv, int reg)
79 struct phy_device *phy = priv->phy;
80 struct mii_bus *bus = phy->bus;
84 split_addr((u32) reg, &r1, &r2, &page);
86 mutex_lock(&bus->mdio_lock);
88 bus->write(bus, 0x18, 0, page);
89 msleep(1); /* wait for the page switch to propagate */
90 lo = bus->read(bus, 0x10 | r2, r1);
91 hi = bus->read(bus, 0x10 | r2, r1 + 1);
93 mutex_unlock(&bus->mdio_lock);
95 return (hi << 16) | lo;
99 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
101 struct phy_device *phy = priv->phy;
102 struct mii_bus *bus = phy->bus;
106 split_addr((u32) reg, &r1, &r2, &r3);
108 hi = (u16) (val >> 16);
110 mutex_lock(&bus->mdio_lock);
112 bus->write(bus, 0x18, 0, r3);
113 msleep(1); /* wait for the page switch to propagate */
114 bus->write(bus, 0x10 | r2, r1 + 1, hi);
115 bus->write(bus, 0x10 | r2, r1, lo);
117 mutex_unlock(&bus->mdio_lock);
121 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
125 v = priv->read(priv, reg);
128 priv->write(priv, reg, v);
134 ar8216_id_chip(struct ar8216_priv *priv)
140 priv->chip = UNKNOWN;
142 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
146 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
147 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
150 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
154 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
172 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
173 (int)(id >> AR8216_CTRL_VERSION_S),
174 (int)(id & AR8216_CTRL_REVISION),
175 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
176 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
185 ar8216_read_port_link(struct ar8216_priv *priv, int port,
186 struct switch_port_link *link)
191 memset(link, '\0', sizeof(*link));
193 status = priv->read(priv, AR8216_REG_PORT_STATUS(port));
195 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
197 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
204 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
205 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
206 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
208 speed = (status & AR8216_PORT_STATUS_SPEED) >>
209 AR8216_PORT_STATUS_SPEED_S;
212 case AR8216_PORT_SPEED_10M:
213 link->speed = SWITCH_PORT_SPEED_10;
215 case AR8216_PORT_SPEED_100M:
216 link->speed = SWITCH_PORT_SPEED_100;
218 case AR8216_PORT_SPEED_1000M:
219 link->speed = SWITCH_PORT_SPEED_1000;
222 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
228 ar8216_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
229 struct switch_val *val)
231 struct ar8216_priv *priv = to_ar8216(dev);
232 priv->vlan = !!val->value.i;
237 ar8216_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
238 struct switch_val *val)
240 struct ar8216_priv *priv = to_ar8216(dev);
241 val->value.i = priv->vlan;
247 ar8216_set_pvid(struct switch_dev *dev, int port, int vlan)
249 struct ar8216_priv *priv = to_ar8216(dev);
251 /* make sure no invalid PVIDs get set */
253 if (vlan >= dev->vlans)
256 priv->pvid[port] = vlan;
261 ar8216_get_pvid(struct switch_dev *dev, int port, int *vlan)
263 struct ar8216_priv *priv = to_ar8216(dev);
264 *vlan = priv->pvid[port];
269 ar8216_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
270 struct switch_val *val)
272 struct ar8216_priv *priv = to_ar8216(dev);
273 priv->vlan_id[val->port_vlan] = val->value.i;
278 ar8216_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
279 struct switch_val *val)
281 struct ar8216_priv *priv = to_ar8216(dev);
282 val->value.i = priv->vlan_id[val->port_vlan];
287 ar8216_get_port_link(struct switch_dev *dev, int port,
288 struct switch_port_link *link)
290 struct ar8216_priv *priv = to_ar8216(dev);
292 ar8216_read_port_link(priv, port, link);
297 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
299 struct ar8216_priv *priv = dev->phy_ptr;
308 if (unlikely(skb_headroom(skb) < 2)) {
309 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
313 buf = skb_push(skb, 2);
318 return priv->ndo_old->ndo_start_xmit(skb, dev);
321 dev_kfree_skb_any(skb);
326 ar8216_mangle_rx(struct sk_buff *skb, int napi)
328 struct ar8216_priv *priv;
329 struct net_device *dev;
341 /* don't strip the header if vlan mode is disabled */
345 /* strip header, get vlan id */
349 /* check for vlan header presence */
350 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
355 /* no need to fix up packets coming from a tagged source */
356 if (priv->vlan_tagged & (1 << port))
359 /* lookup port vid from local table, the switch passes an invalid vlan id */
360 vlan = priv->vlan_id[priv->pvid[port]];
363 buf[14 + 2] |= vlan >> 8;
364 buf[15 + 2] = vlan & 0xff;
367 skb->protocol = eth_type_trans(skb, skb->dev);
370 return netif_receive_skb(skb);
372 return netif_rx(skb);
375 /* no vlan? eat the packet! */
376 dev_kfree_skb_any(skb);
381 ar8216_netif_rx(struct sk_buff *skb)
383 return ar8216_mangle_rx(skb, 0);
387 ar8216_netif_receive_skb(struct sk_buff *skb)
389 return ar8216_mangle_rx(skb, 1);
393 static struct switch_attr ar8216_globals[] = {
395 .type = SWITCH_TYPE_INT,
396 .name = "enable_vlan",
397 .description = "Enable VLAN mode",
398 .set = ar8216_set_vlan,
399 .get = ar8216_get_vlan,
404 static struct switch_attr ar8216_port[] = {
407 static struct switch_attr ar8216_vlan[] = {
409 .type = SWITCH_TYPE_INT,
411 .description = "VLAN ID (0-4094)",
412 .set = ar8216_set_vid,
413 .get = ar8216_get_vid,
420 ar8216_get_ports(struct switch_dev *dev, struct switch_val *val)
422 struct ar8216_priv *priv = to_ar8216(dev);
423 u8 ports = priv->vlan_table[val->port_vlan];
427 for (i = 0; i < AR8216_NUM_PORTS; i++) {
428 struct switch_port *p;
430 if (!(ports & (1 << i)))
433 p = &val->value.ports[val->len++];
435 if (priv->vlan_tagged & (1 << i))
436 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
444 ar8216_set_ports(struct switch_dev *dev, struct switch_val *val)
446 struct ar8216_priv *priv = to_ar8216(dev);
447 u8 *vt = &priv->vlan_table[val->port_vlan];
451 for (i = 0; i < val->len; i++) {
452 struct switch_port *p = &val->value.ports[i];
454 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
455 priv->vlan_tagged |= (1 << p->id);
457 priv->vlan_tagged &= ~(1 << p->id);
458 priv->pvid[p->id] = val->port_vlan;
460 /* make sure that an untagged port does not
461 * appear in other vlans */
462 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
463 if (j == val->port_vlan)
465 priv->vlan_table[j] &= ~(1 << p->id);
475 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
481 t = priv->read(priv, reg);
482 if ((t & mask) == val)
491 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
492 (unsigned int) reg, t, mask, val);
497 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
499 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
501 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
502 val &= AR8216_VTUDATA_MEMBER;
503 val |= AR8216_VTUDATA_VALID;
504 priv->write(priv, AR8216_REG_VTU_DATA, val);
506 op |= AR8216_VTU_ACTIVE;
507 priv->write(priv, AR8216_REG_VTU, op);
511 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
512 u32 members, u32 pvid)
516 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip == AR8216)
517 header = AR8216_PORT_CTRL_HEADER;
521 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
522 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
523 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
524 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
525 AR8216_PORT_CTRL_LEARN | header |
526 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
527 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
529 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
530 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
531 AR8216_PORT_VLAN_DEFAULT_ID,
532 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
533 (ingress << AR8216_PORT_VLAN_MODE_S) |
534 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
538 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
539 u32 members, u32 pvid)
541 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
542 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
543 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
544 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
545 AR8216_PORT_CTRL_LEARN |
546 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
547 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
549 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
550 AR8236_PORT_VLAN_DEFAULT_ID,
551 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
553 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
554 AR8236_PORT_VLAN2_VLAN_MODE |
555 AR8236_PORT_VLAN2_MEMBER,
556 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
557 (members << AR8236_PORT_VLAN2_MEMBER_S));
561 ar8216_hw_apply(struct switch_dev *dev)
563 struct ar8216_priv *priv = to_ar8216(dev);
564 u8 portmask[AR8216_NUM_PORTS];
567 mutex_lock(&priv->reg_mutex);
568 /* flush all vlan translation unit entries */
569 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
571 memset(portmask, 0, sizeof(portmask));
573 /* calculate the port destination masks and load vlans
574 * into the vlan translation unit */
575 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
576 u8 vp = priv->vlan_table[j];
581 for (i = 0; i < AR8216_NUM_PORTS; i++) {
584 portmask[i] |= vp & ~mask;
589 (priv->vlan_id[j] << AR8216_VTU_VID_S),
590 priv->vlan_table[j]);
594 * isolate all ports, but connect them to the cpu port */
595 for (i = 0; i < AR8216_NUM_PORTS; i++) {
596 if (i == AR8216_PORT_CPU)
599 portmask[i] = 1 << AR8216_PORT_CPU;
600 portmask[AR8216_PORT_CPU] |= (1 << i);
604 /* update the port destination mask registers and tag settings */
605 for (i = 0; i < AR8216_NUM_PORTS; i++) {
610 pvid = priv->vlan_id[priv->pvid[i]];
616 if (priv->vlan_tagged & (1 << i))
617 egress = AR8216_OUT_ADD_VLAN;
619 egress = AR8216_OUT_STRIP_VLAN;
621 egress = AR8216_OUT_KEEP;
624 ingress = AR8216_IN_SECURE;
626 ingress = AR8216_IN_PORT_ONLY;
629 if (priv->chip == AR8236)
630 ar8236_setup_port(priv, i, egress, ingress, portmask[i],
633 ar8216_setup_port(priv, i, egress, ingress, portmask[i],
636 mutex_unlock(&priv->reg_mutex);
641 ar8216_hw_init(struct ar8216_priv *priv)
643 /* XXX: undocumented magic from atheros, required! */
644 priv->write(priv, 0x38, 0xc000050e);
646 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
647 AR8216_GCTRL_MTU, 1518 + 8 + 2);
652 ar8236_hw_init(struct ar8216_priv *priv) {
656 if (priv->initialized)
659 /* Initialize the PHYs */
660 bus = priv->phy->bus;
661 for (i = 0; i < 5; i++) {
662 mdiobus_write(bus, i, MII_ADVERTISE,
663 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
664 ADVERTISE_PAUSE_ASYM);
665 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
669 /* enable jumbo frames */
670 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
671 AR8316_GCTRL_MTU, 9018 + 8 + 2);
673 priv->initialized = true;
678 ar8316_hw_init(struct ar8216_priv *priv) {
683 val = priv->read(priv, 0x8);
685 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
686 if (priv->port4_phy) {
687 /* value taken from Ubiquiti RouterStation Pro */
689 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
692 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
694 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
695 /* value taken from AVM Fritz!Box 7390 sources */
698 /* no known value for phy interface */
699 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
700 priv->phy->interface);
707 priv->write(priv, 0x8, newval);
709 /* standard atheros magic */
710 priv->write(priv, 0x38, 0xc000050e);
712 /* Initialize the ports */
713 bus = priv->phy->bus;
714 for (i = 0; i < 5; i++) {
715 if ((i == 4) && priv->port4_phy &&
716 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
717 /* work around for phy4 rgmii mode */
718 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12);
719 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c);
721 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0);
722 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e);
724 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5);
725 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
729 /* initialize the port itself */
730 mdiobus_write(bus, i, MII_ADVERTISE,
731 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
732 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
733 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
737 /* enable jumbo frames */
738 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
739 AR8316_GCTRL_MTU, 9018 + 8 + 2);
741 /* enable cpu port to receive multicast and broadcast frames */
742 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
745 priv->initialized = true;
750 ar8216_init_port(struct ar8216_priv *priv, int port)
752 /* Enable port learning and tx */
753 priv->write(priv, AR8216_REG_PORT_CTRL(port),
754 AR8216_PORT_CTRL_LEARN |
755 (4 << AR8216_PORT_CTRL_STATE_S));
757 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
759 if (port == AR8216_PORT_CPU) {
760 priv->write(priv, AR8216_REG_PORT_STATUS(port),
761 AR8216_PORT_STATUS_LINK_UP |
762 ((priv->chip == AR8316) ?
763 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
764 AR8216_PORT_STATUS_TXMAC |
765 AR8216_PORT_STATUS_RXMAC |
766 ((priv->chip == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
767 ((priv->chip == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
768 AR8216_PORT_STATUS_DUPLEX);
770 priv->write(priv, AR8216_REG_PORT_STATUS(port),
771 AR8216_PORT_STATUS_LINK_AUTO);
776 ar8216_reset_switch(struct switch_dev *dev)
778 struct ar8216_priv *priv = to_ar8216(dev);
781 mutex_lock(&priv->reg_mutex);
782 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
783 offsetof(struct ar8216_priv, vlan));
784 for (i = 0; i < AR8X16_MAX_VLANS; i++) {
785 priv->vlan_id[i] = i;
788 /* Configure all ports */
789 for (i = 0; i < AR8216_NUM_PORTS; i++)
790 ar8216_init_port(priv, i);
792 mutex_unlock(&priv->reg_mutex);
793 return ar8216_hw_apply(dev);
797 static const struct switch_dev_ops ar8216_ops = {
799 .attr = ar8216_globals,
800 .n_attr = ARRAY_SIZE(ar8216_globals),
804 .n_attr = ARRAY_SIZE(ar8216_port),
808 .n_attr = ARRAY_SIZE(ar8216_vlan),
810 .get_port_pvid = ar8216_get_pvid,
811 .set_port_pvid = ar8216_set_pvid,
812 .get_vlan_ports = ar8216_get_ports,
813 .set_vlan_ports = ar8216_set_ports,
814 .apply_config = ar8216_hw_apply,
815 .reset_switch = ar8216_reset_switch,
816 .get_port_link = ar8216_get_port_link,
820 ar8216_config_init(struct phy_device *pdev)
822 struct ar8216_priv *priv = pdev->priv;
823 struct net_device *dev = pdev->attached_dev;
824 struct switch_dev *swdev;
828 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
835 ret = ar8216_id_chip(priv);
839 if (pdev->addr != 0) {
840 if (priv->chip == AR8316) {
841 pdev->supported |= SUPPORTED_1000baseT_Full;
842 pdev->advertising |= ADVERTISED_1000baseT_Full;
844 /* check if we're attaching to the switch twice */
845 pdev = pdev->bus->phy_map[0];
851 /* switch device has not been initialized, reuse priv */
853 priv->port4_phy = true;
860 /* switch device has been initialized, reinit */
862 priv->dev.ports = (AR8216_NUM_PORTS - 1);
863 priv->initialized = false;
864 priv->port4_phy = true;
865 ar8316_hw_init(priv);
873 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
874 pdev->attached_dev->name, priv->chip);
876 pdev->supported = priv->chip == AR8316 ?
877 SUPPORTED_1000baseT_Full : SUPPORTED_100baseT_Full;
878 pdev->advertising = pdev->supported;
880 mutex_init(&priv->reg_mutex);
881 priv->read = ar8216_mii_read;
882 priv->write = ar8216_mii_write;
887 swdev->cpu_port = AR8216_PORT_CPU;
888 swdev->ops = &ar8216_ops;
889 swdev->ports = AR8216_NUM_PORTS;
891 if (priv->chip == AR8316) {
892 swdev->name = "Atheros AR8316";
893 swdev->vlans = AR8X16_MAX_VLANS;
895 if (priv->port4_phy) {
896 /* port 5 connected to the other mac, therefore unusable */
897 swdev->ports = (AR8216_NUM_PORTS - 1);
899 } else if (priv->chip == AR8236) {
900 swdev->name = "Atheros AR8236";
901 swdev->vlans = AR8216_NUM_VLANS;
902 swdev->ports = AR8216_NUM_PORTS;
904 swdev->name = "Atheros AR8216";
905 swdev->vlans = AR8216_NUM_VLANS;
908 ret = register_switch(&priv->dev, pdev->attached_dev);
915 if (priv->chip == AR8216)
916 ret = ar8216_hw_init(priv);
917 else if (priv->chip == AR8236)
918 ret = ar8236_hw_init(priv);
919 else if (priv->chip == AR8316)
920 ret = ar8316_hw_init(priv);
925 ret = ar8216_reset_switch(&priv->dev);
931 /* VID fixup only needed on ar8216 */
932 if (pdev->addr == 0 && priv->chip == AR8216) {
934 pdev->netif_receive_skb = ar8216_netif_receive_skb;
935 pdev->netif_rx = ar8216_netif_rx;
936 priv->ndo_old = dev->netdev_ops;
937 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
938 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
939 dev->netdev_ops = &priv->ndo;
952 ar8216_read_status(struct phy_device *phydev)
954 struct ar8216_priv *priv = phydev->priv;
955 struct switch_port_link link;
957 if (phydev->addr != 0) {
958 return genphy_read_status(phydev);
961 ar8216_read_port_link(priv, phydev->addr, &link);
962 phydev->link = !!link.link;
966 switch (link.speed) {
967 case SWITCH_PORT_SPEED_10:
968 phydev->speed = SPEED_10;
970 case SWITCH_PORT_SPEED_100:
971 phydev->speed = SPEED_100;
973 case SWITCH_PORT_SPEED_1000:
974 phydev->speed = SPEED_1000;
979 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
981 /* flush the address translation unit */
982 mutex_lock(&priv->reg_mutex);
983 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
985 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
986 mutex_unlock(&priv->reg_mutex);
988 phydev->state = PHY_RUNNING;
989 netif_carrier_on(phydev->attached_dev);
990 phydev->adjust_link(phydev->attached_dev);
996 ar8216_config_aneg(struct phy_device *phydev)
998 if (phydev->addr == 0)
1001 return genphy_config_aneg(phydev);
1005 ar8216_probe(struct phy_device *pdev)
1007 struct ar8216_priv priv;
1010 return ar8216_id_chip(&priv);
1014 ar8216_remove(struct phy_device *pdev)
1016 struct ar8216_priv *priv = pdev->priv;
1017 struct net_device *dev = pdev->attached_dev;
1022 if (priv->ndo_old && dev)
1023 dev->netdev_ops = priv->ndo_old;
1024 if (pdev->addr == 0)
1025 unregister_switch(&priv->dev);
1029 static struct phy_driver ar8216_driver = {
1030 .phy_id = 0x004d0000,
1031 .name = "Atheros AR8216/AR8236/AR8316",
1032 .phy_id_mask = 0xffff0000,
1033 .features = PHY_BASIC_FEATURES,
1034 .probe = ar8216_probe,
1035 .remove = ar8216_remove,
1036 .config_init = &ar8216_config_init,
1037 .config_aneg = &ar8216_config_aneg,
1038 .read_status = &ar8216_read_status,
1039 .driver = { .owner = THIS_MODULE },
1045 return phy_driver_register(&ar8216_driver);
1051 phy_driver_unregister(&ar8216_driver);
1054 module_init(ar8216_init);
1055 module_exit(ar8216_exit);
1056 MODULE_LICENSE("GPL");