2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/list.h>
21 #include <linux/if_ether.h>
22 #include <linux/skbuff.h>
23 #include <linux/netdevice.h>
24 #include <linux/netlink.h>
25 #include <linux/bitops.h>
26 #include <net/genetlink.h>
27 #include <linux/switch.h>
28 #include <linux/delay.h>
29 #include <linux/phy.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/lockdep.h>
35 /* size of the vlan table */
36 #define AR8X16_MAX_VLANS 128
37 #define AR8X16_PROBE_RETRIES 10
40 struct switch_dev dev;
41 struct phy_device *phy;
42 u32 (*read)(struct ar8216_priv *priv, int reg);
43 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
44 const struct net_device_ops *ndo_old;
45 struct net_device_ops ndo;
46 struct mutex reg_mutex;
54 /* all fields below are cleared on reset */
56 u16 vlan_id[AR8X16_MAX_VLANS];
57 u8 vlan_table[AR8X16_MAX_VLANS];
59 u16 pvid[AR8216_NUM_PORTS];
62 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
65 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
74 *page = regaddr & 0x1ff;
78 ar8216_mii_read(struct ar8216_priv *priv, int reg)
80 struct phy_device *phy = priv->phy;
81 struct mii_bus *bus = phy->bus;
85 split_addr((u32) reg, &r1, &r2, &page);
87 mutex_lock(&bus->mdio_lock);
89 bus->write(bus, 0x18, 0, page);
90 msleep(1); /* wait for the page switch to propagate */
91 lo = bus->read(bus, 0x10 | r2, r1);
92 hi = bus->read(bus, 0x10 | r2, r1 + 1);
94 mutex_unlock(&bus->mdio_lock);
96 return (hi << 16) | lo;
100 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
102 struct phy_device *phy = priv->phy;
103 struct mii_bus *bus = phy->bus;
107 split_addr((u32) reg, &r1, &r2, &r3);
109 hi = (u16) (val >> 16);
111 mutex_lock(&bus->mdio_lock);
113 bus->write(bus, 0x18, 0, r3);
114 msleep(1); /* wait for the page switch to propagate */
115 bus->write(bus, 0x10 | r2, r1 + 1, hi);
116 bus->write(bus, 0x10 | r2, r1, lo);
118 mutex_unlock(&bus->mdio_lock);
122 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
126 lockdep_assert_held(&priv->reg_mutex);
128 v = priv->read(priv, reg);
131 priv->write(priv, reg, v);
137 ar8216_id_chip(struct ar8216_priv *priv)
143 priv->chip = UNKNOWN;
145 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
149 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
150 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
153 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
157 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
175 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
176 (int)(id >> AR8216_CTRL_VERSION_S),
177 (int)(id & AR8216_CTRL_REVISION),
178 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
179 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
188 ar8216_read_port_link(struct ar8216_priv *priv, int port,
189 struct switch_port_link *link)
194 memset(link, '\0', sizeof(*link));
196 status = priv->read(priv, AR8216_REG_PORT_STATUS(port));
198 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
200 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
207 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
208 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
209 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
211 speed = (status & AR8216_PORT_STATUS_SPEED) >>
212 AR8216_PORT_STATUS_SPEED_S;
215 case AR8216_PORT_SPEED_10M:
216 link->speed = SWITCH_PORT_SPEED_10;
218 case AR8216_PORT_SPEED_100M:
219 link->speed = SWITCH_PORT_SPEED_100;
221 case AR8216_PORT_SPEED_1000M:
222 link->speed = SWITCH_PORT_SPEED_1000;
225 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
231 ar8216_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
232 struct switch_val *val)
234 struct ar8216_priv *priv = to_ar8216(dev);
235 priv->vlan = !!val->value.i;
240 ar8216_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
241 struct switch_val *val)
243 struct ar8216_priv *priv = to_ar8216(dev);
244 val->value.i = priv->vlan;
250 ar8216_set_pvid(struct switch_dev *dev, int port, int vlan)
252 struct ar8216_priv *priv = to_ar8216(dev);
254 /* make sure no invalid PVIDs get set */
256 if (vlan >= dev->vlans)
259 priv->pvid[port] = vlan;
264 ar8216_get_pvid(struct switch_dev *dev, int port, int *vlan)
266 struct ar8216_priv *priv = to_ar8216(dev);
267 *vlan = priv->pvid[port];
272 ar8216_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
273 struct switch_val *val)
275 struct ar8216_priv *priv = to_ar8216(dev);
276 priv->vlan_id[val->port_vlan] = val->value.i;
281 ar8216_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
282 struct switch_val *val)
284 struct ar8216_priv *priv = to_ar8216(dev);
285 val->value.i = priv->vlan_id[val->port_vlan];
290 ar8216_get_port_link(struct switch_dev *dev, int port,
291 struct switch_port_link *link)
293 struct ar8216_priv *priv = to_ar8216(dev);
295 ar8216_read_port_link(priv, port, link);
300 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
302 struct ar8216_priv *priv = dev->phy_ptr;
311 if (unlikely(skb_headroom(skb) < 2)) {
312 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
316 buf = skb_push(skb, 2);
321 return priv->ndo_old->ndo_start_xmit(skb, dev);
324 dev_kfree_skb_any(skb);
329 ar8216_mangle_rx(struct sk_buff *skb, int napi)
331 struct ar8216_priv *priv;
332 struct net_device *dev;
344 /* don't strip the header if vlan mode is disabled */
348 /* strip header, get vlan id */
352 /* check for vlan header presence */
353 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
358 /* no need to fix up packets coming from a tagged source */
359 if (priv->vlan_tagged & (1 << port))
362 /* lookup port vid from local table, the switch passes an invalid vlan id */
363 vlan = priv->vlan_id[priv->pvid[port]];
366 buf[14 + 2] |= vlan >> 8;
367 buf[15 + 2] = vlan & 0xff;
370 skb->protocol = eth_type_trans(skb, skb->dev);
373 return netif_receive_skb(skb);
375 return netif_rx(skb);
378 /* no vlan? eat the packet! */
379 dev_kfree_skb_any(skb);
384 ar8216_netif_rx(struct sk_buff *skb)
386 return ar8216_mangle_rx(skb, 0);
390 ar8216_netif_receive_skb(struct sk_buff *skb)
392 return ar8216_mangle_rx(skb, 1);
396 static struct switch_attr ar8216_globals[] = {
398 .type = SWITCH_TYPE_INT,
399 .name = "enable_vlan",
400 .description = "Enable VLAN mode",
401 .set = ar8216_set_vlan,
402 .get = ar8216_get_vlan,
407 static struct switch_attr ar8216_port[] = {
410 static struct switch_attr ar8216_vlan[] = {
412 .type = SWITCH_TYPE_INT,
414 .description = "VLAN ID (0-4094)",
415 .set = ar8216_set_vid,
416 .get = ar8216_get_vid,
423 ar8216_get_ports(struct switch_dev *dev, struct switch_val *val)
425 struct ar8216_priv *priv = to_ar8216(dev);
426 u8 ports = priv->vlan_table[val->port_vlan];
430 for (i = 0; i < AR8216_NUM_PORTS; i++) {
431 struct switch_port *p;
433 if (!(ports & (1 << i)))
436 p = &val->value.ports[val->len++];
438 if (priv->vlan_tagged & (1 << i))
439 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
447 ar8216_set_ports(struct switch_dev *dev, struct switch_val *val)
449 struct ar8216_priv *priv = to_ar8216(dev);
450 u8 *vt = &priv->vlan_table[val->port_vlan];
454 for (i = 0; i < val->len; i++) {
455 struct switch_port *p = &val->value.ports[i];
457 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
458 priv->vlan_tagged |= (1 << p->id);
460 priv->vlan_tagged &= ~(1 << p->id);
461 priv->pvid[p->id] = val->port_vlan;
463 /* make sure that an untagged port does not
464 * appear in other vlans */
465 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
466 if (j == val->port_vlan)
468 priv->vlan_table[j] &= ~(1 << p->id);
478 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
484 t = priv->read(priv, reg);
485 if ((t & mask) == val)
494 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
495 (unsigned int) reg, t, mask, val);
500 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
502 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
504 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
505 val &= AR8216_VTUDATA_MEMBER;
506 val |= AR8216_VTUDATA_VALID;
507 priv->write(priv, AR8216_REG_VTU_DATA, val);
509 op |= AR8216_VTU_ACTIVE;
510 priv->write(priv, AR8216_REG_VTU, op);
514 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
515 u32 members, u32 pvid)
519 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip == AR8216)
520 header = AR8216_PORT_CTRL_HEADER;
524 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
525 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
526 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
527 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
528 AR8216_PORT_CTRL_LEARN | header |
529 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
530 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
532 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
533 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
534 AR8216_PORT_VLAN_DEFAULT_ID,
535 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
536 (ingress << AR8216_PORT_VLAN_MODE_S) |
537 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
541 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
542 u32 members, u32 pvid)
544 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
545 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
546 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
547 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
548 AR8216_PORT_CTRL_LEARN |
549 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
550 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
552 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
553 AR8236_PORT_VLAN_DEFAULT_ID,
554 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
556 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
557 AR8236_PORT_VLAN2_VLAN_MODE |
558 AR8236_PORT_VLAN2_MEMBER,
559 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
560 (members << AR8236_PORT_VLAN2_MEMBER_S));
564 ar8216_hw_apply(struct switch_dev *dev)
566 struct ar8216_priv *priv = to_ar8216(dev);
567 u8 portmask[AR8216_NUM_PORTS];
570 mutex_lock(&priv->reg_mutex);
571 /* flush all vlan translation unit entries */
572 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
574 memset(portmask, 0, sizeof(portmask));
576 /* calculate the port destination masks and load vlans
577 * into the vlan translation unit */
578 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
579 u8 vp = priv->vlan_table[j];
584 for (i = 0; i < AR8216_NUM_PORTS; i++) {
587 portmask[i] |= vp & ~mask;
592 (priv->vlan_id[j] << AR8216_VTU_VID_S),
593 priv->vlan_table[j]);
597 * isolate all ports, but connect them to the cpu port */
598 for (i = 0; i < AR8216_NUM_PORTS; i++) {
599 if (i == AR8216_PORT_CPU)
602 portmask[i] = 1 << AR8216_PORT_CPU;
603 portmask[AR8216_PORT_CPU] |= (1 << i);
607 /* update the port destination mask registers and tag settings */
608 for (i = 0; i < AR8216_NUM_PORTS; i++) {
613 pvid = priv->vlan_id[priv->pvid[i]];
618 if (priv->vlan_tagged & (1 << i))
619 egress = AR8216_OUT_ADD_VLAN;
621 egress = AR8216_OUT_STRIP_VLAN;
623 egress = AR8216_OUT_KEEP;
627 ingress = AR8216_IN_SECURE;
629 ingress = AR8216_IN_PORT_ONLY;
631 if (priv->chip == AR8236)
632 ar8236_setup_port(priv, i, egress, ingress, portmask[i],
635 ar8216_setup_port(priv, i, egress, ingress, portmask[i],
638 mutex_unlock(&priv->reg_mutex);
643 ar8216_hw_init(struct ar8216_priv *priv)
645 /* XXX: undocumented magic from atheros, required! */
646 priv->write(priv, 0x38, 0xc000050e);
648 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
649 AR8216_GCTRL_MTU, 1518 + 8 + 2);
654 ar8236_hw_init(struct ar8216_priv *priv)
659 if (priv->initialized)
662 /* Initialize the PHYs */
663 bus = priv->phy->bus;
664 for (i = 0; i < 5; i++) {
665 mdiobus_write(bus, i, MII_ADVERTISE,
666 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
667 ADVERTISE_PAUSE_ASYM);
668 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
672 /* enable jumbo frames */
673 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
674 AR8316_GCTRL_MTU, 9018 + 8 + 2);
676 priv->initialized = true;
681 ar8316_hw_init(struct ar8216_priv *priv)
687 val = priv->read(priv, 0x8);
689 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
690 if (priv->port4_phy) {
691 /* value taken from Ubiquiti RouterStation Pro */
693 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
696 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
698 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
699 /* value taken from AVM Fritz!Box 7390 sources */
702 /* no known value for phy interface */
703 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
704 priv->phy->interface);
711 priv->write(priv, 0x8, newval);
713 /* standard atheros magic */
714 priv->write(priv, 0x38, 0xc000050e);
716 /* Initialize the ports */
717 bus = priv->phy->bus;
718 for (i = 0; i < 5; i++) {
719 if ((i == 4) && priv->port4_phy &&
720 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
721 /* work around for phy4 rgmii mode */
722 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12);
723 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c);
725 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0);
726 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e);
728 mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5);
729 mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
733 /* initialize the port itself */
734 mdiobus_write(bus, i, MII_ADVERTISE,
735 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
736 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
737 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
741 /* enable jumbo frames */
742 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
743 AR8316_GCTRL_MTU, 9018 + 8 + 2);
745 /* enable cpu port to receive multicast and broadcast frames */
746 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
749 priv->initialized = true;
754 ar8216_init_port(struct ar8216_priv *priv, int port)
756 /* Enable port learning and tx */
757 priv->write(priv, AR8216_REG_PORT_CTRL(port),
758 AR8216_PORT_CTRL_LEARN |
759 (4 << AR8216_PORT_CTRL_STATE_S));
761 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
763 if (port == AR8216_PORT_CPU) {
764 priv->write(priv, AR8216_REG_PORT_STATUS(port),
765 AR8216_PORT_STATUS_LINK_UP |
766 ((priv->chip == AR8316) ?
767 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
768 AR8216_PORT_STATUS_TXMAC |
769 AR8216_PORT_STATUS_RXMAC |
770 ((priv->chip == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
771 ((priv->chip == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
772 AR8216_PORT_STATUS_DUPLEX);
774 priv->write(priv, AR8216_REG_PORT_STATUS(port),
775 AR8216_PORT_STATUS_LINK_AUTO);
780 ar8216_reset_switch(struct switch_dev *dev)
782 struct ar8216_priv *priv = to_ar8216(dev);
785 mutex_lock(&priv->reg_mutex);
786 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
787 offsetof(struct ar8216_priv, vlan));
789 for (i = 0; i < AR8X16_MAX_VLANS; i++)
790 priv->vlan_id[i] = i;
792 /* Configure all ports */
793 for (i = 0; i < AR8216_NUM_PORTS; i++)
794 ar8216_init_port(priv, i);
796 mutex_unlock(&priv->reg_mutex);
797 return ar8216_hw_apply(dev);
801 static const struct switch_dev_ops ar8216_ops = {
803 .attr = ar8216_globals,
804 .n_attr = ARRAY_SIZE(ar8216_globals),
808 .n_attr = ARRAY_SIZE(ar8216_port),
812 .n_attr = ARRAY_SIZE(ar8216_vlan),
814 .get_port_pvid = ar8216_get_pvid,
815 .set_port_pvid = ar8216_set_pvid,
816 .get_vlan_ports = ar8216_get_ports,
817 .set_vlan_ports = ar8216_set_ports,
818 .apply_config = ar8216_hw_apply,
819 .reset_switch = ar8216_reset_switch,
820 .get_port_link = ar8216_get_port_link,
824 ar8216_config_init(struct phy_device *pdev)
826 struct ar8216_priv *priv = pdev->priv;
827 struct net_device *dev = pdev->attached_dev;
828 struct switch_dev *swdev;
832 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
839 ret = ar8216_id_chip(priv);
843 if (pdev->addr != 0) {
844 if (priv->chip == AR8316) {
845 pdev->supported |= SUPPORTED_1000baseT_Full;
846 pdev->advertising |= ADVERTISED_1000baseT_Full;
848 /* check if we're attaching to the switch twice */
849 pdev = pdev->bus->phy_map[0];
855 /* switch device has not been initialized, reuse priv */
857 priv->port4_phy = true;
864 /* switch device has been initialized, reinit */
866 priv->dev.ports = (AR8216_NUM_PORTS - 1);
867 priv->initialized = false;
868 priv->port4_phy = true;
869 ar8316_hw_init(priv);
877 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
878 pdev->attached_dev->name, priv->chip);
880 pdev->supported = priv->chip == AR8316 ?
881 SUPPORTED_1000baseT_Full : SUPPORTED_100baseT_Full;
882 pdev->advertising = pdev->supported;
884 mutex_init(&priv->reg_mutex);
885 priv->read = ar8216_mii_read;
886 priv->write = ar8216_mii_write;
891 swdev->cpu_port = AR8216_PORT_CPU;
892 swdev->ops = &ar8216_ops;
893 swdev->ports = AR8216_NUM_PORTS;
895 if (priv->chip == AR8316) {
896 swdev->name = "Atheros AR8316";
897 swdev->vlans = AR8X16_MAX_VLANS;
899 if (priv->port4_phy) {
900 /* port 5 connected to the other mac, therefore unusable */
901 swdev->ports = (AR8216_NUM_PORTS - 1);
903 } else if (priv->chip == AR8236) {
904 swdev->name = "Atheros AR8236";
905 swdev->vlans = AR8216_NUM_VLANS;
906 swdev->ports = AR8216_NUM_PORTS;
908 swdev->name = "Atheros AR8216";
909 swdev->vlans = AR8216_NUM_VLANS;
912 ret = register_switch(&priv->dev, pdev->attached_dev);
919 if (priv->chip == AR8216)
920 ret = ar8216_hw_init(priv);
921 else if (priv->chip == AR8236)
922 ret = ar8236_hw_init(priv);
923 else if (priv->chip == AR8316)
924 ret = ar8316_hw_init(priv);
929 ret = ar8216_reset_switch(&priv->dev);
935 /* VID fixup only needed on ar8216 */
936 if (pdev->addr == 0 && priv->chip == AR8216) {
938 pdev->netif_receive_skb = ar8216_netif_receive_skb;
939 pdev->netif_rx = ar8216_netif_rx;
940 priv->ndo_old = dev->netdev_ops;
941 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
942 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
943 dev->netdev_ops = &priv->ndo;
956 ar8216_read_status(struct phy_device *phydev)
958 struct ar8216_priv *priv = phydev->priv;
959 struct switch_port_link link;
962 if (phydev->addr != 0)
963 return genphy_read_status(phydev);
965 ar8216_read_port_link(priv, phydev->addr, &link);
966 phydev->link = !!link.link;
970 switch (link.speed) {
971 case SWITCH_PORT_SPEED_10:
972 phydev->speed = SPEED_10;
974 case SWITCH_PORT_SPEED_100:
975 phydev->speed = SPEED_100;
977 case SWITCH_PORT_SPEED_1000:
978 phydev->speed = SPEED_1000;
983 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
985 /* flush the address translation unit */
986 mutex_lock(&priv->reg_mutex);
987 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
989 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
990 mutex_unlock(&priv->reg_mutex);
992 phydev->state = PHY_RUNNING;
993 netif_carrier_on(phydev->attached_dev);
994 phydev->adjust_link(phydev->attached_dev);
1000 ar8216_config_aneg(struct phy_device *phydev)
1002 if (phydev->addr == 0)
1005 return genphy_config_aneg(phydev);
1009 ar8216_probe(struct phy_device *pdev)
1011 struct ar8216_priv priv;
1014 return ar8216_id_chip(&priv);
1018 ar8216_remove(struct phy_device *pdev)
1020 struct ar8216_priv *priv = pdev->priv;
1021 struct net_device *dev = pdev->attached_dev;
1026 if (priv->ndo_old && dev)
1027 dev->netdev_ops = priv->ndo_old;
1028 if (pdev->addr == 0)
1029 unregister_switch(&priv->dev);
1033 static struct phy_driver ar8216_driver = {
1034 .phy_id = 0x004d0000,
1035 .name = "Atheros AR8216/AR8236/AR8316",
1036 .phy_id_mask = 0xffff0000,
1037 .features = PHY_BASIC_FEATURES,
1038 .probe = ar8216_probe,
1039 .remove = ar8216_remove,
1040 .config_init = &ar8216_config_init,
1041 .config_aneg = &ar8216_config_aneg,
1042 .read_status = &ar8216_read_status,
1043 .driver = { .owner = THIS_MODULE },
1049 return phy_driver_register(&ar8216_driver);
1055 phy_driver_unregister(&ar8216_driver);
1058 module_init(ar8216_init);
1059 module_exit(ar8216_exit);
1060 MODULE_LICENSE("GPL");