2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/list.h>
21 #include <linux/if_ether.h>
22 #include <linux/skbuff.h>
23 #include <linux/netdevice.h>
24 #include <linux/netlink.h>
25 #include <linux/bitops.h>
26 #include <net/genetlink.h>
27 #include <linux/switch.h>
28 #include <linux/delay.h>
29 #include <linux/phy.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/lockdep.h>
35 /* size of the vlan table */
36 #define AR8X16_MAX_VLANS 128
37 #define AR8X16_PROBE_RETRIES 10
42 int (*hw_init)(struct ar8216_priv *priv);
43 void (*init_port)(struct ar8216_priv *priv, int port);
44 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
45 u32 ingress, u32 members, u32 pvid);
46 int (*atu_flush)(struct ar8216_priv *priv);
50 struct switch_dev dev;
51 struct phy_device *phy;
52 u32 (*read)(struct ar8216_priv *priv, int reg);
53 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
54 const struct net_device_ops *ndo_old;
55 struct net_device_ops ndo;
56 struct mutex reg_mutex;
58 const struct ar8xxx_chip *chip;
65 /* all fields below are cleared on reset */
67 u16 vlan_id[AR8X16_MAX_VLANS];
68 u8 vlan_table[AR8X16_MAX_VLANS];
70 u16 pvid[AR8216_NUM_PORTS];
73 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
76 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
85 *page = regaddr & 0x1ff;
89 ar8216_mii_read(struct ar8216_priv *priv, int reg)
91 struct phy_device *phy = priv->phy;
92 struct mii_bus *bus = phy->bus;
96 split_addr((u32) reg, &r1, &r2, &page);
98 mutex_lock(&bus->mdio_lock);
100 bus->write(bus, 0x18, 0, page);
101 usleep_range(1000, 2000); /* wait for the page switch to propagate */
102 lo = bus->read(bus, 0x10 | r2, r1);
103 hi = bus->read(bus, 0x10 | r2, r1 + 1);
105 mutex_unlock(&bus->mdio_lock);
107 return (hi << 16) | lo;
111 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
113 struct phy_device *phy = priv->phy;
114 struct mii_bus *bus = phy->bus;
118 split_addr((u32) reg, &r1, &r2, &r3);
120 hi = (u16) (val >> 16);
122 mutex_lock(&bus->mdio_lock);
124 bus->write(bus, 0x18, 0, r3);
125 usleep_range(1000, 2000); /* wait for the page switch to propagate */
126 bus->write(bus, 0x10 | r2, r1 + 1, hi);
127 bus->write(bus, 0x10 | r2, r1, lo);
129 mutex_unlock(&bus->mdio_lock);
133 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
134 u16 dbg_addr, u16 dbg_data)
136 struct mii_bus *bus = priv->phy->bus;
138 mutex_lock(&bus->mdio_lock);
139 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
140 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
141 mutex_unlock(&bus->mdio_lock);
145 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
149 lockdep_assert_held(&priv->reg_mutex);
151 v = priv->read(priv, reg);
154 priv->write(priv, reg, v);
160 ar8216_read_port_link(struct ar8216_priv *priv, int port,
161 struct switch_port_link *link)
166 memset(link, '\0', sizeof(*link));
168 status = priv->read(priv, AR8216_REG_PORT_STATUS(port));
170 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
172 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
179 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
180 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
181 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
183 speed = (status & AR8216_PORT_STATUS_SPEED) >>
184 AR8216_PORT_STATUS_SPEED_S;
187 case AR8216_PORT_SPEED_10M:
188 link->speed = SWITCH_PORT_SPEED_10;
190 case AR8216_PORT_SPEED_100M:
191 link->speed = SWITCH_PORT_SPEED_100;
193 case AR8216_PORT_SPEED_1000M:
194 link->speed = SWITCH_PORT_SPEED_1000;
197 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
203 ar8216_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
204 struct switch_val *val)
206 struct ar8216_priv *priv = to_ar8216(dev);
207 priv->vlan = !!val->value.i;
212 ar8216_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
213 struct switch_val *val)
215 struct ar8216_priv *priv = to_ar8216(dev);
216 val->value.i = priv->vlan;
222 ar8216_set_pvid(struct switch_dev *dev, int port, int vlan)
224 struct ar8216_priv *priv = to_ar8216(dev);
226 /* make sure no invalid PVIDs get set */
228 if (vlan >= dev->vlans)
231 priv->pvid[port] = vlan;
236 ar8216_get_pvid(struct switch_dev *dev, int port, int *vlan)
238 struct ar8216_priv *priv = to_ar8216(dev);
239 *vlan = priv->pvid[port];
244 ar8216_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
245 struct switch_val *val)
247 struct ar8216_priv *priv = to_ar8216(dev);
248 priv->vlan_id[val->port_vlan] = val->value.i;
253 ar8216_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
254 struct switch_val *val)
256 struct ar8216_priv *priv = to_ar8216(dev);
257 val->value.i = priv->vlan_id[val->port_vlan];
262 ar8216_get_port_link(struct switch_dev *dev, int port,
263 struct switch_port_link *link)
265 struct ar8216_priv *priv = to_ar8216(dev);
267 ar8216_read_port_link(priv, port, link);
272 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
274 struct ar8216_priv *priv = dev->phy_ptr;
283 if (unlikely(skb_headroom(skb) < 2)) {
284 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
288 buf = skb_push(skb, 2);
293 return priv->ndo_old->ndo_start_xmit(skb, dev);
296 dev_kfree_skb_any(skb);
301 ar8216_mangle_rx(struct sk_buff *skb, int napi)
303 struct ar8216_priv *priv;
304 struct net_device *dev;
316 /* don't strip the header if vlan mode is disabled */
320 /* strip header, get vlan id */
324 /* check for vlan header presence */
325 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
330 /* no need to fix up packets coming from a tagged source */
331 if (priv->vlan_tagged & (1 << port))
334 /* lookup port vid from local table, the switch passes an invalid vlan id */
335 vlan = priv->vlan_id[priv->pvid[port]];
338 buf[14 + 2] |= vlan >> 8;
339 buf[15 + 2] = vlan & 0xff;
342 skb->protocol = eth_type_trans(skb, skb->dev);
345 return netif_receive_skb(skb);
347 return netif_rx(skb);
350 /* no vlan? eat the packet! */
351 dev_kfree_skb_any(skb);
356 ar8216_netif_rx(struct sk_buff *skb)
358 return ar8216_mangle_rx(skb, 0);
362 ar8216_netif_receive_skb(struct sk_buff *skb)
364 return ar8216_mangle_rx(skb, 1);
368 static struct switch_attr ar8216_globals[] = {
370 .type = SWITCH_TYPE_INT,
371 .name = "enable_vlan",
372 .description = "Enable VLAN mode",
373 .set = ar8216_set_vlan,
374 .get = ar8216_get_vlan,
379 static struct switch_attr ar8216_port[] = {
382 static struct switch_attr ar8216_vlan[] = {
384 .type = SWITCH_TYPE_INT,
386 .description = "VLAN ID (0-4094)",
387 .set = ar8216_set_vid,
388 .get = ar8216_get_vid,
395 ar8216_get_ports(struct switch_dev *dev, struct switch_val *val)
397 struct ar8216_priv *priv = to_ar8216(dev);
398 u8 ports = priv->vlan_table[val->port_vlan];
402 for (i = 0; i < AR8216_NUM_PORTS; i++) {
403 struct switch_port *p;
405 if (!(ports & (1 << i)))
408 p = &val->value.ports[val->len++];
410 if (priv->vlan_tagged & (1 << i))
411 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
419 ar8216_set_ports(struct switch_dev *dev, struct switch_val *val)
421 struct ar8216_priv *priv = to_ar8216(dev);
422 u8 *vt = &priv->vlan_table[val->port_vlan];
426 for (i = 0; i < val->len; i++) {
427 struct switch_port *p = &val->value.ports[i];
429 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
430 priv->vlan_tagged |= (1 << p->id);
432 priv->vlan_tagged &= ~(1 << p->id);
433 priv->pvid[p->id] = val->port_vlan;
435 /* make sure that an untagged port does not
436 * appear in other vlans */
437 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
438 if (j == val->port_vlan)
440 priv->vlan_table[j] &= ~(1 << p->id);
450 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
456 t = priv->read(priv, reg);
457 if ((t & mask) == val)
466 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
467 (unsigned int) reg, t, mask, val);
472 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
474 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
476 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
477 val &= AR8216_VTUDATA_MEMBER;
478 val |= AR8216_VTUDATA_VALID;
479 priv->write(priv, AR8216_REG_VTU_DATA, val);
481 op |= AR8216_VTU_ACTIVE;
482 priv->write(priv, AR8216_REG_VTU, op);
486 ar8216_atu_flush(struct ar8216_priv *priv)
490 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
492 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
498 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
499 u32 members, u32 pvid)
503 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
504 header = AR8216_PORT_CTRL_HEADER;
508 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
509 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
510 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
511 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
512 AR8216_PORT_CTRL_LEARN | header |
513 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
514 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
516 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
517 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
518 AR8216_PORT_VLAN_DEFAULT_ID,
519 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
520 (ingress << AR8216_PORT_VLAN_MODE_S) |
521 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
525 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
526 u32 members, u32 pvid)
528 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
529 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
530 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
531 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
532 AR8216_PORT_CTRL_LEARN |
533 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
534 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
536 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
537 AR8236_PORT_VLAN_DEFAULT_ID,
538 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
540 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
541 AR8236_PORT_VLAN2_VLAN_MODE |
542 AR8236_PORT_VLAN2_MEMBER,
543 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
544 (members << AR8236_PORT_VLAN2_MEMBER_S));
548 ar8216_hw_apply(struct switch_dev *dev)
550 struct ar8216_priv *priv = to_ar8216(dev);
551 u8 portmask[AR8216_NUM_PORTS];
554 mutex_lock(&priv->reg_mutex);
555 /* flush all vlan translation unit entries */
556 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
558 memset(portmask, 0, sizeof(portmask));
560 /* calculate the port destination masks and load vlans
561 * into the vlan translation unit */
562 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
563 u8 vp = priv->vlan_table[j];
568 for (i = 0; i < AR8216_NUM_PORTS; i++) {
571 portmask[i] |= vp & ~mask;
576 (priv->vlan_id[j] << AR8216_VTU_VID_S),
577 priv->vlan_table[j]);
581 * isolate all ports, but connect them to the cpu port */
582 for (i = 0; i < AR8216_NUM_PORTS; i++) {
583 if (i == AR8216_PORT_CPU)
586 portmask[i] = 1 << AR8216_PORT_CPU;
587 portmask[AR8216_PORT_CPU] |= (1 << i);
591 /* update the port destination mask registers and tag settings */
592 for (i = 0; i < AR8216_NUM_PORTS; i++) {
597 pvid = priv->vlan_id[priv->pvid[i]];
598 if (priv->vlan_tagged & (1 << i))
599 egress = AR8216_OUT_ADD_VLAN;
601 egress = AR8216_OUT_STRIP_VLAN;
602 ingress = AR8216_IN_SECURE;
605 egress = AR8216_OUT_KEEP;
606 ingress = AR8216_IN_PORT_ONLY;
609 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
612 mutex_unlock(&priv->reg_mutex);
617 ar8216_hw_init(struct ar8216_priv *priv)
623 ar8236_hw_init(struct ar8216_priv *priv)
628 if (priv->initialized)
631 /* Initialize the PHYs */
632 bus = priv->phy->bus;
633 for (i = 0; i < 5; i++) {
634 mdiobus_write(bus, i, MII_ADVERTISE,
635 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
636 ADVERTISE_PAUSE_ASYM);
637 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
641 priv->initialized = true;
646 ar8316_hw_init(struct ar8216_priv *priv)
652 val = priv->read(priv, 0x8);
654 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
655 if (priv->port4_phy) {
656 /* value taken from Ubiquiti RouterStation Pro */
658 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
661 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
663 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
664 /* value taken from AVM Fritz!Box 7390 sources */
667 /* no known value for phy interface */
668 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
669 priv->phy->interface);
676 priv->write(priv, 0x8, newval);
678 /* Initialize the ports */
679 bus = priv->phy->bus;
680 for (i = 0; i < 5; i++) {
681 if ((i == 4) && priv->port4_phy &&
682 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
683 /* work around for phy4 rgmii mode */
684 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
686 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
688 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
692 /* initialize the port itself */
693 mdiobus_write(bus, i, MII_ADVERTISE,
694 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
695 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
696 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
701 priv->initialized = true;
706 ar8216_init_globals(struct ar8216_priv *priv)
708 switch (priv->chip_type) {
710 /* standard atheros magic */
711 priv->write(priv, 0x38, 0xc000050e);
713 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
714 AR8216_GCTRL_MTU, 1518 + 8 + 2);
717 /* standard atheros magic */
718 priv->write(priv, 0x38, 0xc000050e);
720 /* enable cpu port to receive multicast and broadcast frames */
721 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
725 /* enable jumbo frames */
726 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
727 AR8316_GCTRL_MTU, 9018 + 8 + 2);
733 ar8216_init_port(struct ar8216_priv *priv, int port)
735 /* Enable port learning and tx */
736 priv->write(priv, AR8216_REG_PORT_CTRL(port),
737 AR8216_PORT_CTRL_LEARN |
738 (4 << AR8216_PORT_CTRL_STATE_S));
740 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
742 if (port == AR8216_PORT_CPU) {
743 priv->write(priv, AR8216_REG_PORT_STATUS(port),
744 AR8216_PORT_STATUS_LINK_UP |
745 ((priv->chip_type == AR8316) ?
746 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
747 AR8216_PORT_STATUS_TXMAC |
748 AR8216_PORT_STATUS_RXMAC |
749 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
750 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
751 AR8216_PORT_STATUS_DUPLEX);
753 priv->write(priv, AR8216_REG_PORT_STATUS(port),
754 AR8216_PORT_STATUS_LINK_AUTO);
758 static const struct ar8xxx_chip ar8216_chip = {
759 .hw_init = ar8216_hw_init,
760 .init_port = ar8216_init_port,
761 .setup_port = ar8216_setup_port,
762 .atu_flush = ar8216_atu_flush,
765 static const struct ar8xxx_chip ar8236_chip = {
766 .hw_init = ar8236_hw_init,
767 .init_port = ar8216_init_port,
768 .setup_port = ar8236_setup_port,
769 .atu_flush = ar8216_atu_flush,
772 static const struct ar8xxx_chip ar8316_chip = {
773 .hw_init = ar8316_hw_init,
774 .init_port = ar8216_init_port,
775 .setup_port = ar8216_setup_port,
776 .atu_flush = ar8216_atu_flush,
780 ar8216_reset_switch(struct switch_dev *dev)
782 struct ar8216_priv *priv = to_ar8216(dev);
785 mutex_lock(&priv->reg_mutex);
786 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
787 offsetof(struct ar8216_priv, vlan));
789 for (i = 0; i < AR8X16_MAX_VLANS; i++)
790 priv->vlan_id[i] = i;
792 /* Configure all ports */
793 for (i = 0; i < AR8216_NUM_PORTS; i++)
794 priv->chip->init_port(priv, i);
796 ar8216_init_globals(priv);
797 mutex_unlock(&priv->reg_mutex);
799 return ar8216_hw_apply(dev);
802 static const struct switch_dev_ops ar8216_sw_ops = {
804 .attr = ar8216_globals,
805 .n_attr = ARRAY_SIZE(ar8216_globals),
809 .n_attr = ARRAY_SIZE(ar8216_port),
813 .n_attr = ARRAY_SIZE(ar8216_vlan),
815 .get_port_pvid = ar8216_get_pvid,
816 .set_port_pvid = ar8216_set_pvid,
817 .get_vlan_ports = ar8216_get_ports,
818 .set_vlan_ports = ar8216_set_ports,
819 .apply_config = ar8216_hw_apply,
820 .reset_switch = ar8216_reset_switch,
821 .get_port_link = ar8216_get_port_link,
825 ar8216_id_chip(struct ar8216_priv *priv)
831 priv->chip_type = UNKNOWN;
833 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
837 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
838 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
841 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
845 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
852 priv->chip_type = AR8216;
853 priv->chip = &ar8216_chip;
856 priv->chip_type = AR8236;
857 priv->chip = &ar8236_chip;
861 priv->chip_type = AR8316;
862 priv->chip = &ar8316_chip;
866 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
867 (int)(id >> AR8216_CTRL_VERSION_S),
868 (int)(id & AR8216_CTRL_REVISION),
869 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
870 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
879 ar8216_config_init(struct phy_device *pdev)
881 struct ar8216_priv *priv = pdev->priv;
882 struct net_device *dev = pdev->attached_dev;
883 struct switch_dev *swdev;
887 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
894 ret = ar8216_id_chip(priv);
898 if (pdev->addr != 0) {
899 if (priv->chip_type == AR8316) {
900 pdev->supported |= SUPPORTED_1000baseT_Full;
901 pdev->advertising |= ADVERTISED_1000baseT_Full;
903 /* check if we're attaching to the switch twice */
904 pdev = pdev->bus->phy_map[0];
910 /* switch device has not been initialized, reuse priv */
912 priv->port4_phy = true;
919 /* switch device has been initialized, reinit */
921 priv->dev.ports = (AR8216_NUM_PORTS - 1);
922 priv->initialized = false;
923 priv->port4_phy = true;
924 ar8316_hw_init(priv);
932 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
933 pdev->attached_dev->name, priv->chip_type);
935 pdev->supported = priv->chip_type == AR8316 ?
936 SUPPORTED_1000baseT_Full : SUPPORTED_100baseT_Full;
937 pdev->advertising = pdev->supported;
939 mutex_init(&priv->reg_mutex);
940 priv->read = ar8216_mii_read;
941 priv->write = ar8216_mii_write;
946 swdev->cpu_port = AR8216_PORT_CPU;
947 swdev->ops = &ar8216_sw_ops;
948 swdev->ports = AR8216_NUM_PORTS;
950 if (priv->chip_type == AR8316) {
951 swdev->name = "Atheros AR8316";
952 swdev->vlans = AR8X16_MAX_VLANS;
954 if (priv->port4_phy) {
955 /* port 5 connected to the other mac, therefore unusable */
956 swdev->ports = (AR8216_NUM_PORTS - 1);
958 } else if (priv->chip_type == AR8236) {
959 swdev->name = "Atheros AR8236";
960 swdev->vlans = AR8216_NUM_VLANS;
961 swdev->ports = AR8216_NUM_PORTS;
963 swdev->name = "Atheros AR8216";
964 swdev->vlans = AR8216_NUM_VLANS;
967 ret = register_switch(&priv->dev, pdev->attached_dev);
973 ret = priv->chip->hw_init(priv);
977 ret = ar8216_reset_switch(&priv->dev);
983 /* VID fixup only needed on ar8216 */
984 if (pdev->addr == 0 && priv->chip_type == AR8216) {
986 pdev->netif_receive_skb = ar8216_netif_receive_skb;
987 pdev->netif_rx = ar8216_netif_rx;
988 priv->ndo_old = dev->netdev_ops;
989 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
990 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
991 dev->netdev_ops = &priv->ndo;
1004 ar8216_read_status(struct phy_device *phydev)
1006 struct ar8216_priv *priv = phydev->priv;
1007 struct switch_port_link link;
1010 if (phydev->addr != 0)
1011 return genphy_read_status(phydev);
1013 ar8216_read_port_link(priv, phydev->addr, &link);
1014 phydev->link = !!link.link;
1018 switch (link.speed) {
1019 case SWITCH_PORT_SPEED_10:
1020 phydev->speed = SPEED_10;
1022 case SWITCH_PORT_SPEED_100:
1023 phydev->speed = SPEED_100;
1025 case SWITCH_PORT_SPEED_1000:
1026 phydev->speed = SPEED_1000;
1031 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1033 /* flush the address translation unit */
1034 mutex_lock(&priv->reg_mutex);
1035 ret = priv->chip->atu_flush(priv);
1036 mutex_unlock(&priv->reg_mutex);
1038 phydev->state = PHY_RUNNING;
1039 netif_carrier_on(phydev->attached_dev);
1040 phydev->adjust_link(phydev->attached_dev);
1046 ar8216_config_aneg(struct phy_device *phydev)
1048 if (phydev->addr == 0)
1051 return genphy_config_aneg(phydev);
1055 ar8216_probe(struct phy_device *pdev)
1057 struct ar8216_priv priv;
1060 return ar8216_id_chip(&priv);
1064 ar8216_remove(struct phy_device *pdev)
1066 struct ar8216_priv *priv = pdev->priv;
1067 struct net_device *dev = pdev->attached_dev;
1072 if (priv->ndo_old && dev)
1073 dev->netdev_ops = priv->ndo_old;
1074 if (pdev->addr == 0)
1075 unregister_switch(&priv->dev);
1079 static struct phy_driver ar8216_driver = {
1080 .phy_id = 0x004d0000,
1081 .name = "Atheros AR8216/AR8236/AR8316",
1082 .phy_id_mask = 0xffff0000,
1083 .features = PHY_BASIC_FEATURES,
1084 .probe = ar8216_probe,
1085 .remove = ar8216_remove,
1086 .config_init = &ar8216_config_init,
1087 .config_aneg = &ar8216_config_aneg,
1088 .read_status = &ar8216_read_status,
1089 .driver = { .owner = THIS_MODULE },
1095 return phy_driver_register(&ar8216_driver);
1101 phy_driver_unregister(&ar8216_driver);
1104 module_init(ar8216_init);
1105 module_exit(ar8216_exit);
1106 MODULE_LICENSE("GPL");