2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 #define AR8XXX_NUM_PHYS 5
57 static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
58 static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
61 AR8XXX_VER_AR8216 = 0x01,
62 AR8XXX_VER_AR8236 = 0x03,
63 AR8XXX_VER_AR8316 = 0x10,
64 AR8XXX_VER_AR8327 = 0x12,
65 AR8XXX_VER_AR8337 = 0x13,
68 struct ar8xxx_mib_desc {
79 int (*hw_init)(struct ar8xxx_priv *priv);
80 void (*cleanup)(struct ar8xxx_priv *priv);
82 void (*init_globals)(struct ar8xxx_priv *priv);
83 void (*init_port)(struct ar8xxx_priv *priv, int port);
84 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
85 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
86 int (*atu_flush)(struct ar8xxx_priv *priv);
87 void (*vtu_flush)(struct ar8xxx_priv *priv);
88 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
89 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
90 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
92 const struct ar8xxx_mib_desc *mib_decs;
97 enum ar8327_led_pattern {
98 AR8327_LED_PATTERN_OFF = 0,
99 AR8327_LED_PATTERN_BLINK,
100 AR8327_LED_PATTERN_ON,
101 AR8327_LED_PATTERN_RULE,
104 struct ar8327_led_entry {
110 struct led_classdev cdev;
111 struct ar8xxx_priv *sw_priv;
116 enum ar8327_led_mode mode;
120 struct work_struct led_work;
122 enum ar8327_led_pattern pattern;
129 struct ar8327_led **leds;
130 unsigned int num_leds;
134 struct switch_dev dev;
135 struct mii_bus *mii_bus;
136 struct phy_device *phy;
138 u32 (*read)(struct ar8xxx_priv *priv, int reg);
139 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
140 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
142 int (*get_port_link)(unsigned port);
144 const struct net_device_ops *ndo_old;
145 struct net_device_ops ndo;
146 struct mutex reg_mutex;
149 const struct ar8xxx_chip *chip;
157 struct mutex mib_lock;
158 struct delayed_work mib_work;
162 struct list_head list;
163 unsigned int use_count;
165 /* all fields below are cleared on reset */
167 u16 vlan_id[AR8X16_MAX_VLANS];
168 u8 vlan_table[AR8X16_MAX_VLANS];
170 u16 pvid[AR8X16_MAX_PORTS];
179 #define MIB_DESC(_s , _o, _n) \
186 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
187 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
188 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
189 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
190 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
191 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
192 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
193 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
194 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
195 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
196 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
197 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
198 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
199 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
200 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
201 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
202 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
203 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
204 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
205 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
206 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
207 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
208 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
209 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
210 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
211 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
212 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
213 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
214 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
215 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
216 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
217 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
218 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
219 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
220 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
221 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
222 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
223 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
226 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
227 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
228 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
229 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
230 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
231 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
232 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
233 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
234 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
235 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
236 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
237 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
238 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
239 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
240 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
241 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
242 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
243 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
244 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
245 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
246 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
247 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
248 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
249 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
250 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
251 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
252 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
253 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
254 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
255 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
256 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
257 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
258 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
259 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
260 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
261 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
262 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
263 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
264 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
265 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
268 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
269 static LIST_HEAD(ar8xxx_dev_list);
271 static inline struct ar8xxx_priv *
272 swdev_to_ar8xxx(struct switch_dev *swdev)
274 return container_of(swdev, struct ar8xxx_priv, dev);
277 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
279 return priv->chip->caps & AR8XXX_CAP_GIGE;
282 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
284 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
287 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
289 return priv->chip_ver == AR8XXX_VER_AR8216;
292 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
294 return priv->chip_ver == AR8XXX_VER_AR8236;
297 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
299 return priv->chip_ver == AR8XXX_VER_AR8316;
302 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
304 return priv->chip_ver == AR8XXX_VER_AR8327;
307 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
309 return priv->chip_ver == AR8XXX_VER_AR8337;
313 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
316 *r1 = regaddr & 0x1e;
322 *page = regaddr & 0x1ff;
325 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
327 ar8xxx_phy_poll_reset(struct mii_bus *bus)
329 unsigned int sleep_msecs = 20;
332 for (elapsed = sleep_msecs; elapsed <= 600;
333 elapsed += sleep_msecs) {
335 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
336 ret = mdiobus_read(bus, i, MII_BMCR);
339 if (ret & BMCR_RESET)
341 if (i == AR8XXX_NUM_PHYS - 1) {
342 usleep_range(1000, 2000);
351 ar8xxx_phy_check_aneg(struct phy_device *phydev)
355 if (phydev->autoneg != AUTONEG_ENABLE)
358 * BMCR_ANENABLE might have been cleared
359 * by phy_init_hw in certain kernel versions
360 * therefore check for it
362 ret = phy_read(phydev, MII_BMCR);
365 if (ret & BMCR_ANENABLE)
368 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
369 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
370 return phy_write(phydev, MII_BMCR, ret);
374 ar8xxx_phy_init(struct ar8xxx_priv *priv)
380 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
381 if (priv->chip->phy_fixup)
382 priv->chip->phy_fixup(priv, i);
384 /* initialize the port itself */
385 mdiobus_write(bus, i, MII_ADVERTISE,
386 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
387 if (ar8xxx_has_gige(priv))
388 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
389 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
392 ar8xxx_phy_poll_reset(bus);
396 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
398 struct mii_bus *bus = priv->mii_bus;
402 split_addr((u32) reg, &r1, &r2, &page);
404 mutex_lock(&bus->mdio_lock);
406 bus->write(bus, 0x18, 0, page);
407 usleep_range(1000, 2000); /* wait for the page switch to propagate */
408 lo = bus->read(bus, 0x10 | r2, r1);
409 hi = bus->read(bus, 0x10 | r2, r1 + 1);
411 mutex_unlock(&bus->mdio_lock);
413 return (hi << 16) | lo;
417 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
419 struct mii_bus *bus = priv->mii_bus;
423 split_addr((u32) reg, &r1, &r2, &r3);
425 hi = (u16) (val >> 16);
427 mutex_lock(&bus->mdio_lock);
429 bus->write(bus, 0x18, 0, r3);
430 usleep_range(1000, 2000); /* wait for the page switch to propagate */
431 if (priv->chip->mii_lo_first) {
432 bus->write(bus, 0x10 | r2, r1, lo);
433 bus->write(bus, 0x10 | r2, r1 + 1, hi);
435 bus->write(bus, 0x10 | r2, r1 + 1, hi);
436 bus->write(bus, 0x10 | r2, r1, lo);
439 mutex_unlock(&bus->mdio_lock);
443 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
445 struct mii_bus *bus = priv->mii_bus;
450 split_addr((u32) reg, &r1, &r2, &page);
452 mutex_lock(&bus->mdio_lock);
454 bus->write(bus, 0x18, 0, page);
455 usleep_range(1000, 2000); /* wait for the page switch to propagate */
457 lo = bus->read(bus, 0x10 | r2, r1);
458 hi = bus->read(bus, 0x10 | r2, r1 + 1);
465 hi = (u16) (ret >> 16);
467 if (priv->chip->mii_lo_first) {
468 bus->write(bus, 0x10 | r2, r1, lo);
469 bus->write(bus, 0x10 | r2, r1 + 1, hi);
471 bus->write(bus, 0x10 | r2, r1 + 1, hi);
472 bus->write(bus, 0x10 | r2, r1, lo);
475 mutex_unlock(&bus->mdio_lock);
482 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
483 u16 dbg_addr, u16 dbg_data)
485 struct mii_bus *bus = priv->mii_bus;
487 mutex_lock(&bus->mdio_lock);
488 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
489 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
490 mutex_unlock(&bus->mdio_lock);
494 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
496 struct mii_bus *bus = priv->mii_bus;
498 mutex_lock(&bus->mdio_lock);
499 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
500 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
501 mutex_unlock(&bus->mdio_lock);
505 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
507 return priv->rmw(priv, reg, mask, val);
511 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
513 priv->rmw(priv, reg, 0, val);
517 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
522 for (i = 0; i < timeout; i++) {
525 t = priv->read(priv, reg);
526 if ((t & mask) == val)
529 usleep_range(1000, 2000);
536 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
538 unsigned mib_func = priv->chip->mib_func;
541 lockdep_assert_held(&priv->mib_lock);
543 /* Capture the hardware statistics for all ports */
544 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
546 /* Wait for the capturing to complete. */
547 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
558 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
560 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
564 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
566 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
570 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
576 WARN_ON(port >= priv->dev.ports);
578 lockdep_assert_held(&priv->mib_lock);
580 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
581 base = AR8327_REG_PORT_STATS_BASE(port);
582 else if (chip_is_ar8236(priv) ||
583 chip_is_ar8316(priv))
584 base = AR8236_REG_PORT_STATS_BASE(port);
586 base = AR8216_REG_PORT_STATS_BASE(port);
588 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
589 for (i = 0; i < priv->chip->num_mibs; i++) {
590 const struct ar8xxx_mib_desc *mib;
593 mib = &priv->chip->mib_decs[i];
594 t = priv->read(priv, base + mib->offset);
595 if (mib->size == 2) {
598 hi = priv->read(priv, base + mib->offset + 4);
610 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
611 struct switch_port_link *link)
616 memset(link, '\0', sizeof(*link));
618 status = priv->chip->read_port_status(priv, port);
620 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
622 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
626 if (priv->get_port_link) {
629 err = priv->get_port_link(port);
638 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
639 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
640 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
642 speed = (status & AR8216_PORT_STATUS_SPEED) >>
643 AR8216_PORT_STATUS_SPEED_S;
646 case AR8216_PORT_SPEED_10M:
647 link->speed = SWITCH_PORT_SPEED_10;
649 case AR8216_PORT_SPEED_100M:
650 link->speed = SWITCH_PORT_SPEED_100;
652 case AR8216_PORT_SPEED_1000M:
653 link->speed = SWITCH_PORT_SPEED_1000;
656 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
661 static struct sk_buff *
662 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
664 struct ar8xxx_priv *priv = dev->phy_ptr;
673 if (unlikely(skb_headroom(skb) < 2)) {
674 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
678 buf = skb_push(skb, 2);
686 dev_kfree_skb_any(skb);
691 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
693 struct ar8xxx_priv *priv;
701 /* don't strip the header if vlan mode is disabled */
705 /* strip header, get vlan id */
709 /* check for vlan header presence */
710 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
715 /* no need to fix up packets coming from a tagged source */
716 if (priv->vlan_tagged & (1 << port))
719 /* lookup port vid from local table, the switch passes an invalid vlan id */
720 vlan = priv->vlan_id[priv->pvid[port]];
723 buf[14 + 2] |= vlan >> 8;
724 buf[15 + 2] = vlan & 0xff;
728 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
734 t = priv->read(priv, reg);
735 if ((t & mask) == val)
744 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
745 (unsigned int) reg, t, mask, val);
750 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
752 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
754 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
755 val &= AR8216_VTUDATA_MEMBER;
756 val |= AR8216_VTUDATA_VALID;
757 priv->write(priv, AR8216_REG_VTU_DATA, val);
759 op |= AR8216_VTU_ACTIVE;
760 priv->write(priv, AR8216_REG_VTU, op);
764 ar8216_vtu_flush(struct ar8xxx_priv *priv)
766 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
770 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
774 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
775 ar8216_vtu_op(priv, op, port_mask);
779 ar8216_atu_flush(struct ar8xxx_priv *priv)
783 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
785 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
791 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
793 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
797 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
804 pvid = priv->vlan_id[priv->pvid[port]];
805 if (priv->vlan_tagged & (1 << port))
806 egress = AR8216_OUT_ADD_VLAN;
808 egress = AR8216_OUT_STRIP_VLAN;
809 ingress = AR8216_IN_SECURE;
812 egress = AR8216_OUT_KEEP;
813 ingress = AR8216_IN_PORT_ONLY;
816 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
817 header = AR8216_PORT_CTRL_HEADER;
821 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
822 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
823 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
824 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
825 AR8216_PORT_CTRL_LEARN | header |
826 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
827 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
829 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
830 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
831 AR8216_PORT_VLAN_DEFAULT_ID,
832 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
833 (ingress << AR8216_PORT_VLAN_MODE_S) |
834 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
838 ar8216_hw_init(struct ar8xxx_priv *priv)
840 if (priv->initialized)
843 ar8xxx_phy_init(priv);
845 priv->initialized = true;
850 ar8216_init_globals(struct ar8xxx_priv *priv)
852 /* standard atheros magic */
853 priv->write(priv, 0x38, 0xc000050e);
855 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
856 AR8216_GCTRL_MTU, 1518 + 8 + 2);
860 ar8216_init_port(struct ar8xxx_priv *priv, int port)
862 /* Enable port learning and tx */
863 priv->write(priv, AR8216_REG_PORT_CTRL(port),
864 AR8216_PORT_CTRL_LEARN |
865 (4 << AR8216_PORT_CTRL_STATE_S));
867 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
869 if (port == AR8216_PORT_CPU) {
870 priv->write(priv, AR8216_REG_PORT_STATUS(port),
871 AR8216_PORT_STATUS_LINK_UP |
872 (ar8xxx_has_gige(priv) ?
873 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
874 AR8216_PORT_STATUS_TXMAC |
875 AR8216_PORT_STATUS_RXMAC |
876 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
877 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
878 AR8216_PORT_STATUS_DUPLEX);
880 priv->write(priv, AR8216_REG_PORT_STATUS(port),
881 AR8216_PORT_STATUS_LINK_AUTO);
885 static const struct ar8xxx_chip ar8216_chip = {
886 .caps = AR8XXX_CAP_MIB_COUNTERS,
888 .hw_init = ar8216_hw_init,
889 .init_globals = ar8216_init_globals,
890 .init_port = ar8216_init_port,
891 .setup_port = ar8216_setup_port,
892 .read_port_status = ar8216_read_port_status,
893 .atu_flush = ar8216_atu_flush,
894 .vtu_flush = ar8216_vtu_flush,
895 .vtu_load_vlan = ar8216_vtu_load_vlan,
896 .set_mirror_regs = ar8216_set_mirror_regs,
898 .num_mibs = ARRAY_SIZE(ar8216_mibs),
899 .mib_decs = ar8216_mibs,
900 .mib_func = AR8216_REG_MIB_FUNC
904 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
910 pvid = priv->vlan_id[priv->pvid[port]];
911 if (priv->vlan_tagged & (1 << port))
912 egress = AR8216_OUT_ADD_VLAN;
914 egress = AR8216_OUT_STRIP_VLAN;
915 ingress = AR8216_IN_SECURE;
918 egress = AR8216_OUT_KEEP;
919 ingress = AR8216_IN_PORT_ONLY;
922 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
923 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
924 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
925 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
926 AR8216_PORT_CTRL_LEARN |
927 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
928 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
930 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
931 AR8236_PORT_VLAN_DEFAULT_ID,
932 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
934 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
935 AR8236_PORT_VLAN2_VLAN_MODE |
936 AR8236_PORT_VLAN2_MEMBER,
937 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
938 (members << AR8236_PORT_VLAN2_MEMBER_S));
942 ar8236_init_globals(struct ar8xxx_priv *priv)
944 /* enable jumbo frames */
945 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
946 AR8316_GCTRL_MTU, 9018 + 8 + 2);
948 /* Enable MIB counters */
949 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
950 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
954 static const struct ar8xxx_chip ar8236_chip = {
955 .caps = AR8XXX_CAP_MIB_COUNTERS,
956 .hw_init = ar8216_hw_init,
957 .init_globals = ar8236_init_globals,
958 .init_port = ar8216_init_port,
959 .setup_port = ar8236_setup_port,
960 .read_port_status = ar8216_read_port_status,
961 .atu_flush = ar8216_atu_flush,
962 .vtu_flush = ar8216_vtu_flush,
963 .vtu_load_vlan = ar8216_vtu_load_vlan,
964 .set_mirror_regs = ar8216_set_mirror_regs,
966 .num_mibs = ARRAY_SIZE(ar8236_mibs),
967 .mib_decs = ar8236_mibs,
968 .mib_func = AR8216_REG_MIB_FUNC
972 ar8316_hw_init(struct ar8xxx_priv *priv)
976 val = priv->read(priv, AR8316_REG_POSTRIP);
978 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
979 if (priv->port4_phy) {
980 /* value taken from Ubiquiti RouterStation Pro */
982 pr_info("ar8316: Using port 4 as PHY\n");
985 pr_info("ar8316: Using port 4 as switch port\n");
987 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
988 /* value taken from AVM Fritz!Box 7390 sources */
991 /* no known value for phy interface */
992 pr_err("ar8316: unsupported mii mode: %d.\n",
993 priv->phy->interface);
1000 priv->write(priv, AR8316_REG_POSTRIP, newval);
1002 if (priv->port4_phy &&
1003 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1004 /* work around for phy4 rgmii mode */
1005 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1007 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1009 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1013 ar8xxx_phy_init(priv);
1016 priv->initialized = true;
1021 ar8316_init_globals(struct ar8xxx_priv *priv)
1023 /* standard atheros magic */
1024 priv->write(priv, 0x38, 0xc000050e);
1026 /* enable cpu port to receive multicast and broadcast frames */
1027 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1029 /* enable jumbo frames */
1030 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1031 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1033 /* Enable MIB counters */
1034 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1035 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1039 static const struct ar8xxx_chip ar8316_chip = {
1040 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1041 .hw_init = ar8316_hw_init,
1042 .init_globals = ar8316_init_globals,
1043 .init_port = ar8216_init_port,
1044 .setup_port = ar8216_setup_port,
1045 .read_port_status = ar8216_read_port_status,
1046 .atu_flush = ar8216_atu_flush,
1047 .vtu_flush = ar8216_vtu_flush,
1048 .vtu_load_vlan = ar8216_vtu_load_vlan,
1049 .set_mirror_regs = ar8216_set_mirror_regs,
1051 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1052 .mib_decs = ar8236_mibs,
1053 .mib_func = AR8216_REG_MIB_FUNC
1057 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1065 switch (cfg->mode) {
1069 case AR8327_PAD_MAC2MAC_MII:
1070 t = AR8327_PAD_MAC_MII_EN;
1072 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1074 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1077 case AR8327_PAD_MAC2MAC_GMII:
1078 t = AR8327_PAD_MAC_GMII_EN;
1080 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1082 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1085 case AR8327_PAD_MAC_SGMII:
1086 t = AR8327_PAD_SGMII_EN;
1089 * WAR for the QUalcomm Atheros AP136 board.
1090 * It seems that RGMII TX/RX delay settings needs to be
1091 * applied for SGMII mode as well, The ethernet is not
1092 * reliable without this.
1094 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1095 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1096 if (cfg->rxclk_delay_en)
1097 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1098 if (cfg->txclk_delay_en)
1099 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1101 if (cfg->sgmii_delay_en)
1102 t |= AR8327_PAD_SGMII_DELAY_EN;
1106 case AR8327_PAD_MAC2PHY_MII:
1107 t = AR8327_PAD_PHY_MII_EN;
1109 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1111 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1114 case AR8327_PAD_MAC2PHY_GMII:
1115 t = AR8327_PAD_PHY_GMII_EN;
1116 if (cfg->pipe_rxclk_sel)
1117 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1119 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1121 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1124 case AR8327_PAD_MAC_RGMII:
1125 t = AR8327_PAD_RGMII_EN;
1126 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1127 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1128 if (cfg->rxclk_delay_en)
1129 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1130 if (cfg->txclk_delay_en)
1131 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1134 case AR8327_PAD_PHY_GMII:
1135 t = AR8327_PAD_PHYX_GMII_EN;
1138 case AR8327_PAD_PHY_RGMII:
1139 t = AR8327_PAD_PHYX_RGMII_EN;
1142 case AR8327_PAD_PHY_MII:
1143 t = AR8327_PAD_PHYX_MII_EN;
1151 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1153 switch (priv->chip_rev) {
1155 /* For 100M waveform */
1156 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1157 /* Turn on Gigabit clock */
1158 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1162 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1163 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1166 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1167 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1169 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1170 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1171 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1177 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1181 if (!cfg->force_link)
1182 return AR8216_PORT_STATUS_LINK_AUTO;
1184 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1185 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1186 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1187 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1189 switch (cfg->speed) {
1190 case AR8327_PORT_SPEED_10:
1191 t |= AR8216_PORT_SPEED_10M;
1193 case AR8327_PORT_SPEED_100:
1194 t |= AR8216_PORT_SPEED_100M;
1196 case AR8327_PORT_SPEED_1000:
1197 t |= AR8216_PORT_SPEED_1000M;
1204 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1205 [_num] = { .reg = (_reg), .shift = (_shift) }
1207 static const struct ar8327_led_entry
1208 ar8327_led_map[AR8327_NUM_LEDS] = {
1209 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1210 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1211 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1213 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1214 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1215 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1217 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1218 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1219 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1221 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1222 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1223 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1225 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1226 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1227 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1231 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1232 enum ar8327_led_pattern pattern)
1234 const struct ar8327_led_entry *entry;
1236 entry = &ar8327_led_map[led_num];
1237 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1238 (3 << entry->shift), pattern << entry->shift);
1242 ar8327_led_work_func(struct work_struct *work)
1244 struct ar8327_led *aled;
1247 aled = container_of(work, struct ar8327_led, led_work);
1249 spin_lock(&aled->lock);
1250 pattern = aled->pattern;
1251 spin_unlock(&aled->lock);
1253 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1258 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1260 if (aled->pattern == pattern)
1263 aled->pattern = pattern;
1264 schedule_work(&aled->led_work);
1267 static inline struct ar8327_led *
1268 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1270 return container_of(led_cdev, struct ar8327_led, cdev);
1274 ar8327_led_blink_set(struct led_classdev *led_cdev,
1275 unsigned long *delay_on,
1276 unsigned long *delay_off)
1278 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1280 if (*delay_on == 0 && *delay_off == 0) {
1285 if (*delay_on != 125 || *delay_off != 125) {
1287 * The hardware only supports blinking at 4Hz. Fall back
1288 * to software implementation in other cases.
1293 spin_lock(&aled->lock);
1295 aled->enable_hw_mode = false;
1296 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1298 spin_unlock(&aled->lock);
1304 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1305 enum led_brightness brightness)
1307 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1311 active = (brightness != LED_OFF);
1312 active ^= aled->active_low;
1314 pattern = (active) ? AR8327_LED_PATTERN_ON :
1315 AR8327_LED_PATTERN_OFF;
1317 spin_lock(&aled->lock);
1319 aled->enable_hw_mode = false;
1320 ar8327_led_schedule_change(aled, pattern);
1322 spin_unlock(&aled->lock);
1326 ar8327_led_enable_hw_mode_show(struct device *dev,
1327 struct device_attribute *attr,
1330 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1331 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1334 spin_lock(&aled->lock);
1335 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1336 spin_unlock(&aled->lock);
1342 ar8327_led_enable_hw_mode_store(struct device *dev,
1343 struct device_attribute *attr,
1347 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1348 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1353 ret = kstrtou8(buf, 10, &value);
1357 spin_lock(&aled->lock);
1359 aled->enable_hw_mode = !!value;
1360 if (aled->enable_hw_mode)
1361 pattern = AR8327_LED_PATTERN_RULE;
1363 pattern = AR8327_LED_PATTERN_OFF;
1365 ar8327_led_schedule_change(aled, pattern);
1367 spin_unlock(&aled->lock);
1372 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1373 ar8327_led_enable_hw_mode_show,
1374 ar8327_led_enable_hw_mode_store);
1377 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1381 ret = led_classdev_register(NULL, &aled->cdev);
1385 if (aled->mode == AR8327_LED_MODE_HW) {
1386 ret = device_create_file(aled->cdev.dev,
1387 &dev_attr_enable_hw_mode);
1389 goto err_unregister;
1395 led_classdev_unregister(&aled->cdev);
1400 ar8327_led_unregister(struct ar8327_led *aled)
1402 if (aled->mode == AR8327_LED_MODE_HW)
1403 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1405 led_classdev_unregister(&aled->cdev);
1406 cancel_work_sync(&aled->led_work);
1410 ar8327_led_create(struct ar8xxx_priv *priv,
1411 const struct ar8327_led_info *led_info)
1413 struct ar8327_data *data = priv->chip_data;
1414 struct ar8327_led *aled;
1417 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1420 if (!led_info->name)
1423 if (led_info->led_num >= AR8327_NUM_LEDS)
1426 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1431 aled->sw_priv = priv;
1432 aled->led_num = led_info->led_num;
1433 aled->active_low = led_info->active_low;
1434 aled->mode = led_info->mode;
1436 if (aled->mode == AR8327_LED_MODE_HW)
1437 aled->enable_hw_mode = true;
1439 aled->name = (char *)(aled + 1);
1440 strcpy(aled->name, led_info->name);
1442 aled->cdev.name = aled->name;
1443 aled->cdev.brightness_set = ar8327_led_set_brightness;
1444 aled->cdev.blink_set = ar8327_led_blink_set;
1445 aled->cdev.default_trigger = led_info->default_trigger;
1447 spin_lock_init(&aled->lock);
1448 mutex_init(&aled->mutex);
1449 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1451 ret = ar8327_led_register(priv, aled);
1455 data->leds[data->num_leds++] = aled;
1465 ar8327_led_destroy(struct ar8327_led *aled)
1467 ar8327_led_unregister(aled);
1472 ar8327_leds_init(struct ar8xxx_priv *priv)
1474 struct ar8327_data *data = priv->chip_data;
1477 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1480 for (i = 0; i < data->num_leds; i++) {
1481 struct ar8327_led *aled;
1483 aled = data->leds[i];
1485 if (aled->enable_hw_mode)
1486 aled->pattern = AR8327_LED_PATTERN_RULE;
1488 aled->pattern = AR8327_LED_PATTERN_OFF;
1490 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1495 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1497 struct ar8327_data *data = priv->chip_data;
1500 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1503 for (i = 0; i < data->num_leds; i++) {
1504 struct ar8327_led *aled;
1506 aled = data->leds[i];
1507 ar8327_led_destroy(aled);
1514 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1515 struct ar8327_platform_data *pdata)
1517 struct ar8327_led_cfg *led_cfg;
1518 struct ar8327_data *data = priv->chip_data;
1525 priv->get_port_link = pdata->get_port_link;
1527 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1528 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1530 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1531 if (chip_is_ar8337(priv))
1532 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1534 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1535 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1536 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1537 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1538 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1540 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1543 led_cfg = pdata->led_cfg;
1545 if (led_cfg->open_drain)
1546 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1548 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1550 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1551 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1552 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1553 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1556 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1559 if (pdata->sgmii_cfg) {
1560 t = pdata->sgmii_cfg->sgmii_ctrl;
1561 if (priv->chip_rev == 1)
1562 t |= AR8327_SGMII_CTRL_EN_PLL |
1563 AR8327_SGMII_CTRL_EN_RX |
1564 AR8327_SGMII_CTRL_EN_TX;
1566 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1567 AR8327_SGMII_CTRL_EN_RX |
1568 AR8327_SGMII_CTRL_EN_TX);
1570 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1572 if (pdata->sgmii_cfg->serdes_aen)
1573 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1575 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1578 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1580 if (pdata->leds && pdata->num_leds) {
1583 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1588 for (i = 0; i < pdata->num_leds; i++)
1589 ar8327_led_create(priv, &pdata->leds[i]);
1597 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1599 struct ar8327_data *data = priv->chip_data;
1600 const __be32 *paddr;
1604 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1605 if (!paddr || len < (2 * sizeof(*paddr)))
1608 len /= sizeof(*paddr);
1610 for (i = 0; i < len - 1; i += 2) {
1614 reg = be32_to_cpup(paddr + i);
1615 val = be32_to_cpup(paddr + i + 1);
1618 case AR8327_REG_PORT_STATUS(0):
1619 data->port0_status = val;
1621 case AR8327_REG_PORT_STATUS(6):
1622 data->port6_status = val;
1625 priv->write(priv, reg, val);
1634 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1641 ar8327_hw_init(struct ar8xxx_priv *priv)
1645 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1646 if (!priv->chip_data)
1649 if (priv->phy->dev.of_node)
1650 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1652 ret = ar8327_hw_config_pdata(priv,
1653 priv->phy->dev.platform_data);
1658 ar8327_leds_init(priv);
1660 ar8xxx_phy_init(priv);
1666 ar8327_cleanup(struct ar8xxx_priv *priv)
1668 ar8327_leds_cleanup(priv);
1672 ar8327_init_globals(struct ar8xxx_priv *priv)
1676 /* enable CPU port and disable mirror port */
1677 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1678 AR8327_FWD_CTRL0_MIRROR_PORT;
1679 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1681 /* forward multicast and broadcast frames to CPU */
1682 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1683 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1684 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1685 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1687 /* enable jumbo frames */
1688 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1689 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1691 /* Enable MIB counters */
1692 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1693 AR8327_MODULE_EN_MIB);
1695 /* Disable EEE on all ports due to stability issues */
1696 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1697 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1698 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1699 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1700 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1701 AR8327_EEE_CTRL_DISABLE_PHY(4);
1702 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1706 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1708 struct ar8327_data *data = priv->chip_data;
1711 if (port == AR8216_PORT_CPU)
1712 t = data->port0_status;
1714 t = data->port6_status;
1716 t = AR8216_PORT_STATUS_LINK_AUTO;
1718 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1719 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1721 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1722 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1723 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1725 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1726 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1728 t = AR8327_PORT_LOOKUP_LEARN;
1729 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1730 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1734 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1736 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1740 ar8327_atu_flush(struct ar8xxx_priv *priv)
1744 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1745 AR8327_ATU_FUNC_BUSY, 0);
1747 priv->write(priv, AR8327_REG_ATU_FUNC,
1748 AR8327_ATU_FUNC_OP_FLUSH);
1754 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1756 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1757 AR8327_VTU_FUNC1_BUSY, 0))
1760 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1761 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1763 op |= AR8327_VTU_FUNC1_BUSY;
1764 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1768 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1770 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1774 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1780 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1781 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1782 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1785 if ((port_mask & BIT(i)) == 0)
1786 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1787 else if (priv->vlan == 0)
1788 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1789 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1790 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1792 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1794 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1796 ar8327_vtu_op(priv, op, val);
1800 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1803 u32 egress, ingress;
1804 u32 pvid = priv->vlan_id[priv->pvid[port]];
1807 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1808 ingress = AR8216_IN_SECURE;
1810 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1811 ingress = AR8216_IN_PORT_ONLY;
1814 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1815 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1816 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1818 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1819 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1820 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1823 t |= AR8327_PORT_LOOKUP_LEARN;
1824 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1825 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1826 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1829 static const struct ar8xxx_chip ar8327_chip = {
1830 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1831 .config_at_probe = true,
1832 .mii_lo_first = true,
1834 .hw_init = ar8327_hw_init,
1835 .cleanup = ar8327_cleanup,
1836 .init_globals = ar8327_init_globals,
1837 .init_port = ar8327_init_port,
1838 .setup_port = ar8327_setup_port,
1839 .read_port_status = ar8327_read_port_status,
1840 .atu_flush = ar8327_atu_flush,
1841 .vtu_flush = ar8327_vtu_flush,
1842 .vtu_load_vlan = ar8327_vtu_load_vlan,
1843 .phy_fixup = ar8327_phy_fixup,
1844 .set_mirror_regs = ar8327_set_mirror_regs,
1846 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1847 .mib_decs = ar8236_mibs,
1848 .mib_func = AR8327_REG_MIB_FUNC
1852 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1853 struct switch_val *val)
1855 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1856 priv->vlan = !!val->value.i;
1861 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1862 struct switch_val *val)
1864 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1865 val->value.i = priv->vlan;
1871 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1873 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1875 /* make sure no invalid PVIDs get set */
1877 if (vlan >= dev->vlans)
1880 priv->pvid[port] = vlan;
1885 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1887 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1888 *vlan = priv->pvid[port];
1893 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1894 struct switch_val *val)
1896 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1897 priv->vlan_id[val->port_vlan] = val->value.i;
1902 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1903 struct switch_val *val)
1905 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1906 val->value.i = priv->vlan_id[val->port_vlan];
1911 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1912 struct switch_port_link *link)
1914 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1916 ar8216_read_port_link(priv, port, link);
1921 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1923 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1924 u8 ports = priv->vlan_table[val->port_vlan];
1928 for (i = 0; i < dev->ports; i++) {
1929 struct switch_port *p;
1931 if (!(ports & (1 << i)))
1934 p = &val->value.ports[val->len++];
1936 if (priv->vlan_tagged & (1 << i))
1937 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1945 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1947 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1948 u8 ports = priv->vlan_table[val->port_vlan];
1952 for (i = 0; i < dev->ports; i++) {
1953 struct switch_port *p;
1955 if (!(ports & (1 << i)))
1958 p = &val->value.ports[val->len++];
1960 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1961 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1969 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1971 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1972 u8 *vt = &priv->vlan_table[val->port_vlan];
1976 for (i = 0; i < val->len; i++) {
1977 struct switch_port *p = &val->value.ports[i];
1979 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1980 priv->vlan_tagged |= (1 << p->id);
1982 priv->vlan_tagged &= ~(1 << p->id);
1983 priv->pvid[p->id] = val->port_vlan;
1985 /* make sure that an untagged port does not
1986 * appear in other vlans */
1987 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1988 if (j == val->port_vlan)
1990 priv->vlan_table[j] &= ~(1 << p->id);
2000 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
2002 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2003 u8 *vt = &priv->vlan_table[val->port_vlan];
2007 for (i = 0; i < val->len; i++) {
2008 struct switch_port *p = &val->value.ports[i];
2010 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2011 if (val->port_vlan == priv->pvid[p->id]) {
2012 priv->vlan_tagged |= (1 << p->id);
2015 priv->vlan_tagged &= ~(1 << p->id);
2016 priv->pvid[p->id] = val->port_vlan;
2025 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2029 /* reset all mirror registers */
2030 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2031 AR8327_FWD_CTRL0_MIRROR_PORT,
2032 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2033 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2034 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2035 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2038 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2039 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2043 /* now enable mirroring if necessary */
2044 if (priv->source_port >= AR8327_NUM_PORTS ||
2045 priv->monitor_port >= AR8327_NUM_PORTS ||
2046 priv->source_port == priv->monitor_port) {
2050 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2051 AR8327_FWD_CTRL0_MIRROR_PORT,
2052 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2054 if (priv->mirror_rx)
2055 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2056 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2057 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2059 if (priv->mirror_tx)
2060 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2061 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2062 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2066 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2070 /* reset all mirror registers */
2071 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2072 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2073 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2074 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2075 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2076 AR8216_PORT_CTRL_MIRROR_RX,
2079 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2080 AR8216_PORT_CTRL_MIRROR_TX,
2084 /* now enable mirroring if necessary */
2085 if (priv->source_port >= AR8216_NUM_PORTS ||
2086 priv->monitor_port >= AR8216_NUM_PORTS ||
2087 priv->source_port == priv->monitor_port) {
2091 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2092 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2093 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2095 if (priv->mirror_rx)
2096 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2097 AR8216_PORT_CTRL_MIRROR_RX,
2098 AR8216_PORT_CTRL_MIRROR_RX);
2100 if (priv->mirror_tx)
2101 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2102 AR8216_PORT_CTRL_MIRROR_TX,
2103 AR8216_PORT_CTRL_MIRROR_TX);
2107 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2109 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2110 u8 portmask[AR8X16_MAX_PORTS];
2113 mutex_lock(&priv->reg_mutex);
2114 /* flush all vlan translation unit entries */
2115 priv->chip->vtu_flush(priv);
2117 memset(portmask, 0, sizeof(portmask));
2119 /* calculate the port destination masks and load vlans
2120 * into the vlan translation unit */
2121 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2122 u8 vp = priv->vlan_table[j];
2127 for (i = 0; i < dev->ports; i++) {
2130 portmask[i] |= vp & ~mask;
2133 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2134 priv->vlan_table[j]);
2138 * isolate all ports, but connect them to the cpu port */
2139 for (i = 0; i < dev->ports; i++) {
2140 if (i == AR8216_PORT_CPU)
2143 portmask[i] = 1 << AR8216_PORT_CPU;
2144 portmask[AR8216_PORT_CPU] |= (1 << i);
2148 /* update the port destination mask registers and tag settings */
2149 for (i = 0; i < dev->ports; i++) {
2150 priv->chip->setup_port(priv, i, portmask[i]);
2153 priv->chip->set_mirror_regs(priv);
2155 mutex_unlock(&priv->reg_mutex);
2160 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2162 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2165 mutex_lock(&priv->reg_mutex);
2166 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2167 offsetof(struct ar8xxx_priv, vlan));
2169 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2170 priv->vlan_id[i] = i;
2172 /* Configure all ports */
2173 for (i = 0; i < dev->ports; i++)
2174 priv->chip->init_port(priv, i);
2176 priv->mirror_rx = false;
2177 priv->mirror_tx = false;
2178 priv->source_port = 0;
2179 priv->monitor_port = 0;
2181 priv->chip->init_globals(priv);
2183 mutex_unlock(&priv->reg_mutex);
2185 return ar8xxx_sw_hw_apply(dev);
2189 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2190 const struct switch_attr *attr,
2191 struct switch_val *val)
2193 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2197 if (!ar8xxx_has_mib_counters(priv))
2200 mutex_lock(&priv->mib_lock);
2202 len = priv->dev.ports * priv->chip->num_mibs *
2203 sizeof(*priv->mib_stats);
2204 memset(priv->mib_stats, '\0', len);
2205 ret = ar8xxx_mib_flush(priv);
2212 mutex_unlock(&priv->mib_lock);
2217 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2218 const struct switch_attr *attr,
2219 struct switch_val *val)
2221 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2223 mutex_lock(&priv->reg_mutex);
2224 priv->mirror_rx = !!val->value.i;
2225 priv->chip->set_mirror_regs(priv);
2226 mutex_unlock(&priv->reg_mutex);
2232 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2233 const struct switch_attr *attr,
2234 struct switch_val *val)
2236 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2237 val->value.i = priv->mirror_rx;
2242 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2243 const struct switch_attr *attr,
2244 struct switch_val *val)
2246 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2248 mutex_lock(&priv->reg_mutex);
2249 priv->mirror_tx = !!val->value.i;
2250 priv->chip->set_mirror_regs(priv);
2251 mutex_unlock(&priv->reg_mutex);
2257 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2258 const struct switch_attr *attr,
2259 struct switch_val *val)
2261 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2262 val->value.i = priv->mirror_tx;
2267 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2268 const struct switch_attr *attr,
2269 struct switch_val *val)
2271 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2273 mutex_lock(&priv->reg_mutex);
2274 priv->monitor_port = val->value.i;
2275 priv->chip->set_mirror_regs(priv);
2276 mutex_unlock(&priv->reg_mutex);
2282 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2283 const struct switch_attr *attr,
2284 struct switch_val *val)
2286 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2287 val->value.i = priv->monitor_port;
2292 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2293 const struct switch_attr *attr,
2294 struct switch_val *val)
2296 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2298 mutex_lock(&priv->reg_mutex);
2299 priv->source_port = val->value.i;
2300 priv->chip->set_mirror_regs(priv);
2301 mutex_unlock(&priv->reg_mutex);
2307 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2308 const struct switch_attr *attr,
2309 struct switch_val *val)
2311 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2312 val->value.i = priv->source_port;
2317 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2318 const struct switch_attr *attr,
2319 struct switch_val *val)
2321 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2325 if (!ar8xxx_has_mib_counters(priv))
2328 port = val->port_vlan;
2329 if (port >= dev->ports)
2332 mutex_lock(&priv->mib_lock);
2333 ret = ar8xxx_mib_capture(priv);
2337 ar8xxx_mib_fetch_port_stat(priv, port, true);
2342 mutex_unlock(&priv->mib_lock);
2347 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2348 const struct switch_attr *attr,
2349 struct switch_val *val)
2351 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2352 const struct ar8xxx_chip *chip = priv->chip;
2356 char *buf = priv->buf;
2359 if (!ar8xxx_has_mib_counters(priv))
2362 port = val->port_vlan;
2363 if (port >= dev->ports)
2366 mutex_lock(&priv->mib_lock);
2367 ret = ar8xxx_mib_capture(priv);
2371 ar8xxx_mib_fetch_port_stat(priv, port, false);
2373 len += snprintf(buf + len, sizeof(priv->buf) - len,
2374 "Port %d MIB counters\n",
2377 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2378 for (i = 0; i < chip->num_mibs; i++)
2379 len += snprintf(buf + len, sizeof(priv->buf) - len,
2381 chip->mib_decs[i].name,
2390 mutex_unlock(&priv->mib_lock);
2394 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2396 .type = SWITCH_TYPE_INT,
2397 .name = "enable_vlan",
2398 .description = "Enable VLAN mode",
2399 .set = ar8xxx_sw_set_vlan,
2400 .get = ar8xxx_sw_get_vlan,
2404 .type = SWITCH_TYPE_NOVAL,
2405 .name = "reset_mibs",
2406 .description = "Reset all MIB counters",
2407 .set = ar8xxx_sw_set_reset_mibs,
2410 .type = SWITCH_TYPE_INT,
2411 .name = "enable_mirror_rx",
2412 .description = "Enable mirroring of RX packets",
2413 .set = ar8xxx_sw_set_mirror_rx_enable,
2414 .get = ar8xxx_sw_get_mirror_rx_enable,
2418 .type = SWITCH_TYPE_INT,
2419 .name = "enable_mirror_tx",
2420 .description = "Enable mirroring of TX packets",
2421 .set = ar8xxx_sw_set_mirror_tx_enable,
2422 .get = ar8xxx_sw_get_mirror_tx_enable,
2426 .type = SWITCH_TYPE_INT,
2427 .name = "mirror_monitor_port",
2428 .description = "Mirror monitor port",
2429 .set = ar8xxx_sw_set_mirror_monitor_port,
2430 .get = ar8xxx_sw_get_mirror_monitor_port,
2431 .max = AR8216_NUM_PORTS - 1
2434 .type = SWITCH_TYPE_INT,
2435 .name = "mirror_source_port",
2436 .description = "Mirror source port",
2437 .set = ar8xxx_sw_set_mirror_source_port,
2438 .get = ar8xxx_sw_get_mirror_source_port,
2439 .max = AR8216_NUM_PORTS - 1
2443 static struct switch_attr ar8327_sw_attr_globals[] = {
2445 .type = SWITCH_TYPE_INT,
2446 .name = "enable_vlan",
2447 .description = "Enable VLAN mode",
2448 .set = ar8xxx_sw_set_vlan,
2449 .get = ar8xxx_sw_get_vlan,
2453 .type = SWITCH_TYPE_NOVAL,
2454 .name = "reset_mibs",
2455 .description = "Reset all MIB counters",
2456 .set = ar8xxx_sw_set_reset_mibs,
2459 .type = SWITCH_TYPE_INT,
2460 .name = "enable_mirror_rx",
2461 .description = "Enable mirroring of RX packets",
2462 .set = ar8xxx_sw_set_mirror_rx_enable,
2463 .get = ar8xxx_sw_get_mirror_rx_enable,
2467 .type = SWITCH_TYPE_INT,
2468 .name = "enable_mirror_tx",
2469 .description = "Enable mirroring of TX packets",
2470 .set = ar8xxx_sw_set_mirror_tx_enable,
2471 .get = ar8xxx_sw_get_mirror_tx_enable,
2475 .type = SWITCH_TYPE_INT,
2476 .name = "mirror_monitor_port",
2477 .description = "Mirror monitor port",
2478 .set = ar8xxx_sw_set_mirror_monitor_port,
2479 .get = ar8xxx_sw_get_mirror_monitor_port,
2480 .max = AR8327_NUM_PORTS - 1
2483 .type = SWITCH_TYPE_INT,
2484 .name = "mirror_source_port",
2485 .description = "Mirror source port",
2486 .set = ar8xxx_sw_set_mirror_source_port,
2487 .get = ar8xxx_sw_get_mirror_source_port,
2488 .max = AR8327_NUM_PORTS - 1
2492 static struct switch_attr ar8xxx_sw_attr_port[] = {
2494 .type = SWITCH_TYPE_NOVAL,
2495 .name = "reset_mib",
2496 .description = "Reset single port MIB counters",
2497 .set = ar8xxx_sw_set_port_reset_mib,
2500 .type = SWITCH_TYPE_STRING,
2502 .description = "Get port's MIB counters",
2504 .get = ar8xxx_sw_get_port_mib,
2508 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2510 .type = SWITCH_TYPE_INT,
2512 .description = "VLAN ID (0-4094)",
2513 .set = ar8xxx_sw_set_vid,
2514 .get = ar8xxx_sw_get_vid,
2519 static const struct switch_dev_ops ar8xxx_sw_ops = {
2521 .attr = ar8xxx_sw_attr_globals,
2522 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2525 .attr = ar8xxx_sw_attr_port,
2526 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2529 .attr = ar8xxx_sw_attr_vlan,
2530 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2532 .get_port_pvid = ar8xxx_sw_get_pvid,
2533 .set_port_pvid = ar8xxx_sw_set_pvid,
2534 .get_vlan_ports = ar8xxx_sw_get_ports,
2535 .set_vlan_ports = ar8xxx_sw_set_ports,
2536 .apply_config = ar8xxx_sw_hw_apply,
2537 .reset_switch = ar8xxx_sw_reset_switch,
2538 .get_port_link = ar8xxx_sw_get_port_link,
2541 static const struct switch_dev_ops ar8327_sw_ops = {
2543 .attr = ar8327_sw_attr_globals,
2544 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2547 .attr = ar8xxx_sw_attr_port,
2548 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2551 .attr = ar8xxx_sw_attr_vlan,
2552 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2554 .get_port_pvid = ar8xxx_sw_get_pvid,
2555 .set_port_pvid = ar8xxx_sw_set_pvid,
2556 .get_vlan_ports = ar8327_sw_get_ports,
2557 .set_vlan_ports = ar8327_sw_set_ports,
2558 .apply_config = ar8xxx_sw_hw_apply,
2559 .reset_switch = ar8xxx_sw_reset_switch,
2560 .get_port_link = ar8xxx_sw_get_port_link,
2564 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2570 val = priv->read(priv, AR8216_REG_CTRL);
2574 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2575 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2578 val = priv->read(priv, AR8216_REG_CTRL);
2582 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2587 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2588 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2590 switch (priv->chip_ver) {
2591 case AR8XXX_VER_AR8216:
2592 priv->chip = &ar8216_chip;
2594 case AR8XXX_VER_AR8236:
2595 priv->chip = &ar8236_chip;
2597 case AR8XXX_VER_AR8316:
2598 priv->chip = &ar8316_chip;
2600 case AR8XXX_VER_AR8327:
2601 priv->chip = &ar8327_chip;
2603 case AR8XXX_VER_AR8337:
2604 priv->chip = &ar8327_chip;
2607 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2608 priv->chip_ver, priv->chip_rev);
2617 ar8xxx_mib_work_func(struct work_struct *work)
2619 struct ar8xxx_priv *priv;
2622 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2624 mutex_lock(&priv->mib_lock);
2626 err = ar8xxx_mib_capture(priv);
2630 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2633 priv->mib_next_port++;
2634 if (priv->mib_next_port >= priv->dev.ports)
2635 priv->mib_next_port = 0;
2637 mutex_unlock(&priv->mib_lock);
2638 schedule_delayed_work(&priv->mib_work,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2643 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2647 if (!ar8xxx_has_mib_counters(priv))
2650 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2652 len = priv->dev.ports * priv->chip->num_mibs *
2653 sizeof(*priv->mib_stats);
2654 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2656 if (!priv->mib_stats)
2663 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2665 if (!ar8xxx_has_mib_counters(priv))
2668 schedule_delayed_work(&priv->mib_work,
2669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2673 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2675 if (!ar8xxx_has_mib_counters(priv))
2678 cancel_delayed_work(&priv->mib_work);
2681 static struct ar8xxx_priv *
2684 struct ar8xxx_priv *priv;
2686 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2690 mutex_init(&priv->reg_mutex);
2691 mutex_init(&priv->mib_lock);
2692 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2698 ar8xxx_free(struct ar8xxx_priv *priv)
2700 if (priv->chip && priv->chip->cleanup)
2701 priv->chip->cleanup(priv);
2703 kfree(priv->chip_data);
2704 kfree(priv->mib_stats);
2708 static struct ar8xxx_priv *
2709 ar8xxx_create_mii(struct mii_bus *bus)
2711 struct ar8xxx_priv *priv;
2713 priv = ar8xxx_create();
2715 priv->mii_bus = bus;
2716 priv->read = ar8xxx_mii_read;
2717 priv->write = ar8xxx_mii_write;
2718 priv->rmw = ar8xxx_mii_rmw;
2725 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2727 struct switch_dev *swdev;
2730 ret = ar8xxx_id_chip(priv);
2735 swdev->cpu_port = AR8216_PORT_CPU;
2736 swdev->ops = &ar8xxx_sw_ops;
2738 if (chip_is_ar8316(priv)) {
2739 swdev->name = "Atheros AR8316";
2740 swdev->vlans = AR8X16_MAX_VLANS;
2741 swdev->ports = AR8216_NUM_PORTS;
2742 } else if (chip_is_ar8236(priv)) {
2743 swdev->name = "Atheros AR8236";
2744 swdev->vlans = AR8216_NUM_VLANS;
2745 swdev->ports = AR8216_NUM_PORTS;
2746 } else if (chip_is_ar8327(priv)) {
2747 swdev->name = "Atheros AR8327";
2748 swdev->vlans = AR8X16_MAX_VLANS;
2749 swdev->ports = AR8327_NUM_PORTS;
2750 swdev->ops = &ar8327_sw_ops;
2751 } else if (chip_is_ar8337(priv)) {
2752 swdev->name = "Atheros AR8337";
2753 swdev->vlans = AR8X16_MAX_VLANS;
2754 swdev->ports = AR8327_NUM_PORTS;
2755 swdev->ops = &ar8327_sw_ops;
2757 swdev->name = "Atheros AR8216";
2758 swdev->vlans = AR8216_NUM_VLANS;
2759 swdev->ports = AR8216_NUM_PORTS;
2762 ret = ar8xxx_mib_init(priv);
2770 ar8xxx_start(struct ar8xxx_priv *priv)
2776 ret = priv->chip->hw_init(priv);
2780 ret = ar8xxx_sw_reset_switch(&priv->dev);
2786 ar8xxx_mib_start(priv);
2792 ar8xxx_phy_config_init(struct phy_device *phydev)
2794 struct ar8xxx_priv *priv = phydev->priv;
2795 struct net_device *dev = phydev->attached_dev;
2801 if (priv->chip->config_at_probe)
2802 return ar8xxx_phy_check_aneg(phydev);
2806 if (phydev->addr != 0) {
2807 if (chip_is_ar8316(priv)) {
2808 /* switch device has been initialized, reinit */
2809 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2810 priv->initialized = false;
2811 priv->port4_phy = true;
2812 ar8316_hw_init(priv);
2819 ret = ar8xxx_start(priv);
2823 /* VID fixup only needed on ar8216 */
2824 if (chip_is_ar8216(priv)) {
2825 dev->phy_ptr = priv;
2826 dev->priv_flags |= IFF_NO_IP_ALIGN;
2827 dev->eth_mangle_rx = ar8216_mangle_rx;
2828 dev->eth_mangle_tx = ar8216_mangle_tx;
2835 ar8xxx_phy_read_status(struct phy_device *phydev)
2837 struct ar8xxx_priv *priv = phydev->priv;
2838 struct switch_port_link link;
2841 if (phydev->addr != 0)
2842 return genphy_read_status(phydev);
2844 ar8216_read_port_link(priv, phydev->addr, &link);
2845 phydev->link = !!link.link;
2849 switch (link.speed) {
2850 case SWITCH_PORT_SPEED_10:
2851 phydev->speed = SPEED_10;
2853 case SWITCH_PORT_SPEED_100:
2854 phydev->speed = SPEED_100;
2856 case SWITCH_PORT_SPEED_1000:
2857 phydev->speed = SPEED_1000;
2862 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2864 /* flush the address translation unit */
2865 mutex_lock(&priv->reg_mutex);
2866 ret = priv->chip->atu_flush(priv);
2867 mutex_unlock(&priv->reg_mutex);
2869 phydev->state = PHY_RUNNING;
2870 netif_carrier_on(phydev->attached_dev);
2871 phydev->adjust_link(phydev->attached_dev);
2877 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2879 if (phydev->addr == 0)
2882 return genphy_config_aneg(phydev);
2885 static const u32 ar8xxx_phy_ids[] = {
2887 0x004dd034, /* AR8327 */
2888 0x004dd036, /* AR8337 */
2891 0x004dd043, /* AR8236 */
2895 ar8xxx_phy_match(u32 phy_id)
2899 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2900 if (phy_id == ar8xxx_phy_ids[i])
2907 ar8xxx_is_possible(struct mii_bus *bus)
2911 for (i = 0; i < 4; i++) {
2914 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2915 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2916 if (!ar8xxx_phy_match(phy_id)) {
2917 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2918 dev_name(&bus->dev), i, phy_id);
2927 ar8xxx_phy_probe(struct phy_device *phydev)
2929 struct ar8xxx_priv *priv;
2930 struct switch_dev *swdev;
2933 /* skip PHYs at unused adresses */
2934 if (phydev->addr != 0 && phydev->addr != 4)
2937 if (!ar8xxx_is_possible(phydev->bus))
2940 mutex_lock(&ar8xxx_dev_list_lock);
2941 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2942 if (priv->mii_bus == phydev->bus)
2945 priv = ar8xxx_create_mii(phydev->bus);
2951 ret = ar8xxx_probe_switch(priv);
2956 swdev->alias = dev_name(&priv->mii_bus->dev);
2957 ret = register_switch(swdev, NULL);
2961 pr_info("%s: %s rev. %u switch registered on %s\n",
2962 swdev->devname, swdev->name, priv->chip_rev,
2963 dev_name(&priv->mii_bus->dev));
2968 if (phydev->addr == 0) {
2969 if (ar8xxx_has_gige(priv)) {
2970 phydev->supported = SUPPORTED_1000baseT_Full;
2971 phydev->advertising = ADVERTISED_1000baseT_Full;
2973 phydev->supported = SUPPORTED_100baseT_Full;
2974 phydev->advertising = ADVERTISED_100baseT_Full;
2977 if (priv->chip->config_at_probe) {
2980 ret = ar8xxx_start(priv);
2982 goto err_unregister_switch;
2985 if (ar8xxx_has_gige(priv)) {
2986 phydev->supported |= SUPPORTED_1000baseT_Full;
2987 phydev->advertising |= ADVERTISED_1000baseT_Full;
2991 phydev->priv = priv;
2993 list_add(&priv->list, &ar8xxx_dev_list);
2995 mutex_unlock(&ar8xxx_dev_list_lock);
2999 err_unregister_switch:
3000 if (--priv->use_count)
3003 unregister_switch(&priv->dev);
3008 mutex_unlock(&ar8xxx_dev_list_lock);
3013 ar8xxx_phy_detach(struct phy_device *phydev)
3015 struct net_device *dev = phydev->attached_dev;
3020 dev->phy_ptr = NULL;
3021 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3022 dev->eth_mangle_rx = NULL;
3023 dev->eth_mangle_tx = NULL;
3027 ar8xxx_phy_remove(struct phy_device *phydev)
3029 struct ar8xxx_priv *priv = phydev->priv;
3034 phydev->priv = NULL;
3035 if (--priv->use_count > 0)
3038 mutex_lock(&ar8xxx_dev_list_lock);
3039 list_del(&priv->list);
3040 mutex_unlock(&ar8xxx_dev_list_lock);
3042 unregister_switch(&priv->dev);
3043 ar8xxx_mib_stop(priv);
3047 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3049 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3051 /* we don't need an extra reset */
3056 static struct phy_driver ar8xxx_phy_driver = {
3057 .phy_id = 0x004d0000,
3058 .name = "Atheros AR8216/AR8236/AR8316",
3059 .phy_id_mask = 0xffff0000,
3060 .features = PHY_BASIC_FEATURES,
3061 .probe = ar8xxx_phy_probe,
3062 .remove = ar8xxx_phy_remove,
3063 .detach = ar8xxx_phy_detach,
3064 .config_init = ar8xxx_phy_config_init,
3065 .config_aneg = ar8xxx_phy_config_aneg,
3066 .read_status = ar8xxx_phy_read_status,
3067 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3068 .soft_reset = ar8xxx_phy_soft_reset,
3070 .driver = { .owner = THIS_MODULE },
3076 return phy_driver_register(&ar8xxx_phy_driver);
3082 phy_driver_unregister(&ar8xxx_phy_driver);
3085 module_init(ar8xxx_init);
3086 module_exit(ar8xxx_exit);
3087 MODULE_LICENSE("GPL");