target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39
  40 #include "ar8216.h"
  41
  42 /* size of the vlan table */
  43 #define AR8X16_MAX_VLANS        128
  44 #define AR8X16_PROBE_RETRIES    10
  45 #define AR8X16_MAX_PORTS        8
  46
  47 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  48
  49 struct ar8xxx_priv;
  50
  51 #define AR8XXX_CAP_GIGE                 BIT(0)
  52 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  53
  54 #define AR8XXX_NUM_PHYS         5
  55
  56 enum {
  57         AR8XXX_VER_AR8216 = 0x01,
  58         AR8XXX_VER_AR8236 = 0x03,
  59         AR8XXX_VER_AR8316 = 0x10,
  60         AR8XXX_VER_AR8327 = 0x12,
  61         AR8XXX_VER_AR8337 = 0x13,
  62 };
  63
  64 struct ar8xxx_mib_desc {
  65         unsigned int size;
  66         unsigned int offset;
  67         const char *name;
  68 };
  69
  70 struct ar8xxx_chip {
  71         unsigned long caps;
  72
  73         int (*hw_init)(struct ar8xxx_priv *priv);
  74         void (*cleanup)(struct ar8xxx_priv *priv);
  75
  76         void (*init_globals)(struct ar8xxx_priv *priv);
  77         void (*init_port)(struct ar8xxx_priv *priv, int port);
  78         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  79         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  80         int (*atu_flush)(struct ar8xxx_priv *priv);
  81         void (*vtu_flush)(struct ar8xxx_priv *priv);
  82         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  83
  84         const struct ar8xxx_mib_desc *mib_decs;
  85         unsigned num_mibs;
  86 };
  87
  88 enum ar8327_led_pattern {
  89         AR8327_LED_PATTERN_OFF = 0,
  90         AR8327_LED_PATTERN_BLINK,
  91         AR8327_LED_PATTERN_ON,
  92         AR8327_LED_PATTERN_RULE,
  93 };
  94
  95 struct ar8327_led_entry {
  96         unsigned reg;
  97         unsigned shift;
  98 };
  99
 100 struct ar8327_led {
 101         struct led_classdev cdev;
 102         struct ar8xxx_priv *sw_priv;
 103
 104         char *name;
 105         bool active_low;
 106         u8 led_num;
 107         enum ar8327_led_mode mode;
 108
 109         struct mutex mutex;
 110         spinlock_t lock;
 111         struct work_struct led_work;
 112         bool enable_hw_mode;
 113         enum ar8327_led_pattern pattern;
 114 };
 115
 116 struct ar8327_data {
 117         u32 port0_status;
 118         u32 port6_status;
 119
 120         struct ar8327_led **leds;
 121         unsigned int num_leds;
 122 };
 123
 124 struct ar8xxx_priv {
 125         struct switch_dev dev;
 126         struct mii_bus *mii_bus;
 127         struct phy_device *phy;
 128
 129         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 130         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 131         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 132
 133         int (*get_port_link)(unsigned port);
 134
 135         const struct net_device_ops *ndo_old;
 136         struct net_device_ops ndo;
 137         struct mutex reg_mutex;
 138         u8 chip_ver;
 139         u8 chip_rev;
 140         const struct ar8xxx_chip *chip;
 141         union {
 142                 struct ar8327_data ar8327;
 143         } chip_data;
 144         bool initialized;
 145         bool port4_phy;
 146         char buf[2048];
 147
 148         bool init;
 149         bool mii_lo_first;
 150
 151         struct mutex mib_lock;
 152         struct delayed_work mib_work;
 153         int mib_next_port;
 154         u64 *mib_stats;
 155
 156         struct list_head list;
 157         unsigned int use_count;
 158
 159         /* all fields below are cleared on reset */
 160         bool vlan;
 161         u16 vlan_id[AR8X16_MAX_VLANS];
 162         u8 vlan_table[AR8X16_MAX_VLANS];
 163         u8 vlan_tagged;
 164         u16 pvid[AR8X16_MAX_PORTS];
 165
 166         /* mirroring */
 167         bool mirror_rx;
 168         bool mirror_tx;
 169         int source_port;
 170         int monitor_port;
 171 };
 172
 173 #define MIB_DESC(_s , _o, _n)   \
 174         {                       \
 175                 .size = (_s),   \
 176                 .offset = (_o), \
 177                 .name = (_n),   \
 178         }
 179
 180 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 181         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 182         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 183         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 184         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 185         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 186         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 187         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 188         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 189         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 190         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 191         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 192         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 193         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 194         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 195         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 196         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 197         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 198         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 199         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 200         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 201         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 202         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 203         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 204         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 205         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 206         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 207         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 208         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 209         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 210         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 211         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 212         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 213         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 214         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 215         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 216         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 217         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 218 };
 219
 220 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 221         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 222         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 223         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 224         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 225         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 226         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 227         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 228         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 229         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 230         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 231         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 232         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 233         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 234         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 235         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 236         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 237         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 238         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 239         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 240         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 241         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 242         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 243         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 244         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 245         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 246         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 247         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 248         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 249         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 250         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 251         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 252         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 253         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 254         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 255         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 256         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 257         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 258         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 259         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 260 };
 261
 262 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 263 static LIST_HEAD(ar8xxx_dev_list);
 264
 265 static inline struct ar8xxx_priv *
 266 swdev_to_ar8xxx(struct switch_dev *swdev)
 267 {
 268         return container_of(swdev, struct ar8xxx_priv, dev);
 269 }
 270
 271 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 272 {
 273         return priv->chip->caps & AR8XXX_CAP_GIGE;
 274 }
 275
 276 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 277 {
 278         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 279 }
 280
 281 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 282 {
 283         return priv->chip_ver == AR8XXX_VER_AR8216;
 284 }
 285
 286 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 287 {
 288         return priv->chip_ver == AR8XXX_VER_AR8236;
 289 }
 290
 291 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 292 {
 293         return priv->chip_ver == AR8XXX_VER_AR8316;
 294 }
 295
 296 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 297 {
 298         return priv->chip_ver == AR8XXX_VER_AR8327;
 299 }
 300
 301 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 302 {
 303         return priv->chip_ver == AR8XXX_VER_AR8337;
 304 }
 305
 306 static inline void
 307 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 308 {
 309         regaddr >>= 1;
 310         *r1 = regaddr & 0x1e;
 311
 312         regaddr >>= 5;
 313         *r2 = regaddr & 0x7;
 314
 315         regaddr >>= 3;
 316         *page = regaddr & 0x1ff;
 317 }
 318
 319 static u32
 320 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 321 {
 322         struct mii_bus *bus = priv->mii_bus;
 323         u16 r1, r2, page;
 324         u16 lo, hi;
 325
 326         split_addr((u32) reg, &r1, &r2, &page);
 327
 328         mutex_lock(&bus->mdio_lock);
 329
 330         bus->write(bus, 0x18, 0, page);
 331         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 332         lo = bus->read(bus, 0x10 | r2, r1);
 333         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 334
 335         mutex_unlock(&bus->mdio_lock);
 336
 337         return (hi << 16) | lo;
 338 }
 339
 340 static void
 341 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 342 {
 343         struct mii_bus *bus = priv->mii_bus;
 344         u16 r1, r2, r3;
 345         u16 lo, hi;
 346
 347         split_addr((u32) reg, &r1, &r2, &r3);
 348         lo = val & 0xffff;
 349         hi = (u16) (val >> 16);
 350
 351         mutex_lock(&bus->mdio_lock);
 352
 353         bus->write(bus, 0x18, 0, r3);
 354         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 355         if (priv->mii_lo_first) {
 356                 bus->write(bus, 0x10 | r2, r1, lo);
 357                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 358         } else {
 359                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 360                 bus->write(bus, 0x10 | r2, r1, lo);
 361         }
 362
 363         mutex_unlock(&bus->mdio_lock);
 364 }
 365
 366 static u32
 367 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 368 {
 369         struct mii_bus *bus = priv->mii_bus;
 370         u16 r1, r2, page;
 371         u16 lo, hi;
 372         u32 ret;
 373
 374         split_addr((u32) reg, &r1, &r2, &page);
 375
 376         mutex_lock(&bus->mdio_lock);
 377
 378         bus->write(bus, 0x18, 0, page);
 379         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 380
 381         lo = bus->read(bus, 0x10 | r2, r1);
 382         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 383
 384         ret = hi << 16 | lo;
 385         ret &= ~mask;
 386         ret |= val;
 387
 388         lo = ret & 0xffff;
 389         hi = (u16) (ret >> 16);
 390
 391         if (priv->mii_lo_first) {
 392                 bus->write(bus, 0x10 | r2, r1, lo);
 393                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 394         } else {
 395                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 396                 bus->write(bus, 0x10 | r2, r1, lo);
 397         }
 398
 399         mutex_unlock(&bus->mdio_lock);
 400
 401         return ret;
 402 }
 403
 404
 405 static void
 406 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 407                      u16 dbg_addr, u16 dbg_data)
 408 {
 409         struct mii_bus *bus = priv->mii_bus;
 410
 411         mutex_lock(&bus->mdio_lock);
 412         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 413         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 414         mutex_unlock(&bus->mdio_lock);
 415 }
 416
 417 static void
 418 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 419 {
 420         struct mii_bus *bus = priv->mii_bus;
 421
 422         mutex_lock(&bus->mdio_lock);
 423         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 424         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 425         mutex_unlock(&bus->mdio_lock);
 426 }
 427
 428 static inline u32
 429 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 430 {
 431         return priv->rmw(priv, reg, mask, val);
 432 }
 433
 434 static inline void
 435 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 436 {
 437         priv->rmw(priv, reg, 0, val);
 438 }
 439
 440 static int
 441 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 442                 unsigned timeout)
 443 {
 444         int i;
 445
 446         for (i = 0; i < timeout; i++) {
 447                 u32 t;
 448
 449                 t = priv->read(priv, reg);
 450                 if ((t & mask) == val)
 451                         return 0;
 452
 453                 usleep_range(1000, 2000);
 454         }
 455
 456         return -ETIMEDOUT;
 457 }
 458
 459 static int
 460 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 461 {
 462         unsigned mib_func;
 463         int ret;
 464
 465         lockdep_assert_held(&priv->mib_lock);
 466
 467         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 468                 mib_func = AR8327_REG_MIB_FUNC;
 469         else
 470                 mib_func = AR8216_REG_MIB_FUNC;
 471
 472         /* Capture the hardware statistics for all ports */
 473         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 474
 475         /* Wait for the capturing to complete. */
 476         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 477         if (ret)
 478                 goto out;
 479
 480         ret = 0;
 481
 482 out:
 483         return ret;
 484 }
 485
 486 static int
 487 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 488 {
 489         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 490 }
 491
 492 static int
 493 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 494 {
 495         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 496 }
 497
 498 static void
 499 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 500 {
 501         unsigned int base;
 502         u64 *mib_stats;
 503         int i;
 504
 505         WARN_ON(port >= priv->dev.ports);
 506
 507         lockdep_assert_held(&priv->mib_lock);
 508
 509         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 510                 base = AR8327_REG_PORT_STATS_BASE(port);
 511         else if (chip_is_ar8236(priv) ||
 512                  chip_is_ar8316(priv))
 513                 base = AR8236_REG_PORT_STATS_BASE(port);
 514         else
 515                 base = AR8216_REG_PORT_STATS_BASE(port);
 516
 517         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 518         for (i = 0; i < priv->chip->num_mibs; i++) {
 519                 const struct ar8xxx_mib_desc *mib;
 520                 u64 t;
 521
 522                 mib = &priv->chip->mib_decs[i];
 523                 t = priv->read(priv, base + mib->offset);
 524                 if (mib->size == 2) {
 525                         u64 hi;
 526
 527                         hi = priv->read(priv, base + mib->offset + 4);
 528                         t |= hi << 32;
 529                 }
 530
 531                 if (flush)
 532                         mib_stats[i] = 0;
 533                 else
 534                         mib_stats[i] += t;
 535         }
 536 }
 537
 538 static void
 539 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 540                       struct switch_port_link *link)
 541 {
 542         u32 status;
 543         u32 speed;
 544
 545         memset(link, '\0', sizeof(*link));
 546
 547         status = priv->chip->read_port_status(priv, port);
 548
 549         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 550         if (link->aneg) {
 551                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 552         } else {
 553                 link->link = true;
 554
 555                 if (priv->get_port_link) {
 556                         int err;
 557
 558                         err = priv->get_port_link(port);
 559                         if (err >= 0)
 560                                 link->link = !!err;
 561                 }
 562         }
 563
 564         if (!link->link)
 565                 return;
 566
 567         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 568         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 569         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 570
 571         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 572                  AR8216_PORT_STATUS_SPEED_S;
 573
 574         switch (speed) {
 575         case AR8216_PORT_SPEED_10M:
 576                 link->speed = SWITCH_PORT_SPEED_10;
 577                 break;
 578         case AR8216_PORT_SPEED_100M:
 579                 link->speed = SWITCH_PORT_SPEED_100;
 580                 break;
 581         case AR8216_PORT_SPEED_1000M:
 582                 link->speed = SWITCH_PORT_SPEED_1000;
 583                 break;
 584         default:
 585                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 586                 break;
 587         }
 588 }
 589
 590 static struct sk_buff *
 591 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 592 {
 593         struct ar8xxx_priv *priv = dev->phy_ptr;
 594         unsigned char *buf;
 595
 596         if (unlikely(!priv))
 597                 goto error;
 598
 599         if (!priv->vlan)
 600                 goto send;
 601
 602         if (unlikely(skb_headroom(skb) < 2)) {
 603                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 604                         goto error;
 605         }
 606
 607         buf = skb_push(skb, 2);
 608         buf[0] = 0x10;
 609         buf[1] = 0x80;
 610
 611 send:
 612         return skb;
 613
 614 error:
 615         dev_kfree_skb_any(skb);
 616         return NULL;
 617 }
 618
 619 static void
 620 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 621 {
 622         struct ar8xxx_priv *priv;
 623         unsigned char *buf;
 624         int port, vlan;
 625
 626         priv = dev->phy_ptr;
 627         if (!priv)
 628                 return;
 629
 630         /* don't strip the header if vlan mode is disabled */
 631         if (!priv->vlan)
 632                 return;
 633
 634         /* strip header, get vlan id */
 635         buf = skb->data;
 636         skb_pull(skb, 2);
 637
 638         /* check for vlan header presence */
 639         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 640                 return;
 641
 642         port = buf[0] & 0xf;
 643
 644         /* no need to fix up packets coming from a tagged source */
 645         if (priv->vlan_tagged & (1 << port))
 646                 return;
 647
 648         /* lookup port vid from local table, the switch passes an invalid vlan id */
 649         vlan = priv->vlan_id[priv->pvid[port]];
 650
 651         buf[14 + 2] &= 0xf0;
 652         buf[14 + 2] |= vlan >> 8;
 653         buf[15 + 2] = vlan & 0xff;
 654 }
 655
 656 static int
 657 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 658 {
 659         int timeout = 20;
 660         u32 t = 0;
 661
 662         while (1) {
 663                 t = priv->read(priv, reg);
 664                 if ((t & mask) == val)
 665                         return 0;
 666
 667                 if (timeout-- <= 0)
 668                         break;
 669
 670                 udelay(10);
 671         }
 672
 673         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 674                (unsigned int) reg, t, mask, val);
 675         return -ETIMEDOUT;
 676 }
 677
 678 static void
 679 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 680 {
 681         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 682                 return;
 683         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 684                 val &= AR8216_VTUDATA_MEMBER;
 685                 val |= AR8216_VTUDATA_VALID;
 686                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 687         }
 688         op |= AR8216_VTU_ACTIVE;
 689         priv->write(priv, AR8216_REG_VTU, op);
 690 }
 691
 692 static void
 693 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 694 {
 695         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 696 }
 697
 698 static void
 699 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 700 {
 701         u32 op;
 702
 703         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 704         ar8216_vtu_op(priv, op, port_mask);
 705 }
 706
 707 static int
 708 ar8216_atu_flush(struct ar8xxx_priv *priv)
 709 {
 710         int ret;
 711
 712         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 713         if (!ret)
 714                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 715
 716         return ret;
 717 }
 718
 719 static u32
 720 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 721 {
 722         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 723 }
 724
 725 static void
 726 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 727 {
 728         u32 header;
 729         u32 egress, ingress;
 730         u32 pvid;
 731
 732         if (priv->vlan) {
 733                 pvid = priv->vlan_id[priv->pvid[port]];
 734                 if (priv->vlan_tagged & (1 << port))
 735                         egress = AR8216_OUT_ADD_VLAN;
 736                 else
 737                         egress = AR8216_OUT_STRIP_VLAN;
 738                 ingress = AR8216_IN_SECURE;
 739         } else {
 740                 pvid = port;
 741                 egress = AR8216_OUT_KEEP;
 742                 ingress = AR8216_IN_PORT_ONLY;
 743         }
 744
 745         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 746                 header = AR8216_PORT_CTRL_HEADER;
 747         else
 748                 header = 0;
 749
 750         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 751                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 752                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 753                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 754                    AR8216_PORT_CTRL_LEARN | header |
 755                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 756                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 757
 758         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 759                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 760                    AR8216_PORT_VLAN_DEFAULT_ID,
 761                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 762                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 763                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 764 }
 765
 766 static int
 767 ar8216_hw_init(struct ar8xxx_priv *priv)
 768 {
 769         return 0;
 770 }
 771
 772 static void
 773 ar8216_init_globals(struct ar8xxx_priv *priv)
 774 {
 775         /* standard atheros magic */
 776         priv->write(priv, 0x38, 0xc000050e);
 777
 778         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 779                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 780 }
 781
 782 static void
 783 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 784 {
 785         /* Enable port learning and tx */
 786         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 787                 AR8216_PORT_CTRL_LEARN |
 788                 (4 << AR8216_PORT_CTRL_STATE_S));
 789
 790         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 791
 792         if (port == AR8216_PORT_CPU) {
 793                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 794                         AR8216_PORT_STATUS_LINK_UP |
 795                         (ar8xxx_has_gige(priv) ?
 796                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 797                         AR8216_PORT_STATUS_TXMAC |
 798                         AR8216_PORT_STATUS_RXMAC |
 799                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 800                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 801                         AR8216_PORT_STATUS_DUPLEX);
 802         } else {
 803                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 804                         AR8216_PORT_STATUS_LINK_AUTO);
 805         }
 806 }
 807
 808 static const struct ar8xxx_chip ar8216_chip = {
 809         .caps = AR8XXX_CAP_MIB_COUNTERS,
 810
 811         .hw_init = ar8216_hw_init,
 812         .init_globals = ar8216_init_globals,
 813         .init_port = ar8216_init_port,
 814         .setup_port = ar8216_setup_port,
 815         .read_port_status = ar8216_read_port_status,
 816         .atu_flush = ar8216_atu_flush,
 817         .vtu_flush = ar8216_vtu_flush,
 818         .vtu_load_vlan = ar8216_vtu_load_vlan,
 819
 820         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 821         .mib_decs = ar8216_mibs,
 822 };
 823
 824 static void
 825 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 826 {
 827         u32 egress, ingress;
 828         u32 pvid;
 829
 830         if (priv->vlan) {
 831                 pvid = priv->vlan_id[priv->pvid[port]];
 832                 if (priv->vlan_tagged & (1 << port))
 833                         egress = AR8216_OUT_ADD_VLAN;
 834                 else
 835                         egress = AR8216_OUT_STRIP_VLAN;
 836                 ingress = AR8216_IN_SECURE;
 837         } else {
 838                 pvid = port;
 839                 egress = AR8216_OUT_KEEP;
 840                 ingress = AR8216_IN_PORT_ONLY;
 841         }
 842
 843         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 844                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 845                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 846                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 847                    AR8216_PORT_CTRL_LEARN |
 848                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 849                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 850
 851         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 852                    AR8236_PORT_VLAN_DEFAULT_ID,
 853                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 854
 855         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 856                    AR8236_PORT_VLAN2_VLAN_MODE |
 857                    AR8236_PORT_VLAN2_MEMBER,
 858                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 859                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 860 }
 861
 862 static int
 863 ar8236_hw_init(struct ar8xxx_priv *priv)
 864 {
 865         int i;
 866         struct mii_bus *bus;
 867
 868         if (priv->initialized)
 869                 return 0;
 870
 871         /* Initialize the PHYs */
 872         bus = priv->mii_bus;
 873         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 874                 mdiobus_write(bus, i, MII_ADVERTISE,
 875                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 876                               ADVERTISE_PAUSE_ASYM);
 877                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 878         }
 879         msleep(1000);
 880
 881         priv->initialized = true;
 882         return 0;
 883 }
 884
 885 static void
 886 ar8236_init_globals(struct ar8xxx_priv *priv)
 887 {
 888         /* enable jumbo frames */
 889         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 890                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 891
 892         /* Enable MIB counters */
 893         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 894                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 895                    AR8236_MIB_EN);
 896 }
 897
 898 static const struct ar8xxx_chip ar8236_chip = {
 899         .caps = AR8XXX_CAP_MIB_COUNTERS,
 900         .hw_init = ar8236_hw_init,
 901         .init_globals = ar8236_init_globals,
 902         .init_port = ar8216_init_port,
 903         .setup_port = ar8236_setup_port,
 904         .read_port_status = ar8216_read_port_status,
 905         .atu_flush = ar8216_atu_flush,
 906         .vtu_flush = ar8216_vtu_flush,
 907         .vtu_load_vlan = ar8216_vtu_load_vlan,
 908
 909         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 910         .mib_decs = ar8236_mibs,
 911 };
 912
 913 static int
 914 ar8316_hw_init(struct ar8xxx_priv *priv)
 915 {
 916         int i;
 917         u32 val, newval;
 918         struct mii_bus *bus;
 919
 920         val = priv->read(priv, AR8316_REG_POSTRIP);
 921
 922         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 923                 if (priv->port4_phy) {
 924                         /* value taken from Ubiquiti RouterStation Pro */
 925                         newval = 0x81461bea;
 926                         pr_info("ar8316: Using port 4 as PHY\n");
 927                 } else {
 928                         newval = 0x01261be2;
 929                         pr_info("ar8316: Using port 4 as switch port\n");
 930                 }
 931         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 932                 /* value taken from AVM Fritz!Box 7390 sources */
 933                 newval = 0x010e5b71;
 934         } else {
 935                 /* no known value for phy interface */
 936                 pr_err("ar8316: unsupported mii mode: %d.\n",
 937                        priv->phy->interface);
 938                 return -EINVAL;
 939         }
 940
 941         if (val == newval)
 942                 goto out;
 943
 944         priv->write(priv, AR8316_REG_POSTRIP, newval);
 945
 946         if (priv->port4_phy &&
 947             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 948                 /* work around for phy4 rgmii mode */
 949                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 950                 /* rx delay */
 951                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 952                 /* tx delay */
 953                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 954                 msleep(1000);
 955         }
 956
 957         /* Initialize the ports */
 958         bus = priv->mii_bus;
 959         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 960                 /* initialize the port itself */
 961                 mdiobus_write(bus, i, MII_ADVERTISE,
 962                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 963                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 964                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 965         }
 966
 967         msleep(1000);
 968
 969 out:
 970         priv->initialized = true;
 971         return 0;
 972 }
 973
 974 static void
 975 ar8316_init_globals(struct ar8xxx_priv *priv)
 976 {
 977         /* standard atheros magic */
 978         priv->write(priv, 0x38, 0xc000050e);
 979
 980         /* enable cpu port to receive multicast and broadcast frames */
 981         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 982
 983         /* enable jumbo frames */
 984         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 985                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 986
 987         /* Enable MIB counters */
 988         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 989                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 990                    AR8236_MIB_EN);
 991 }
 992
 993 static const struct ar8xxx_chip ar8316_chip = {
 994         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 995         .hw_init = ar8316_hw_init,
 996         .init_globals = ar8316_init_globals,
 997         .init_port = ar8216_init_port,
 998         .setup_port = ar8216_setup_port,
 999         .read_port_status = ar8216_read_port_status,
1000         .atu_flush = ar8216_atu_flush,
1001         .vtu_flush = ar8216_vtu_flush,
1002         .vtu_load_vlan = ar8216_vtu_load_vlan,
1003
1004         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1005         .mib_decs = ar8236_mibs,
1006 };
1007
1008 static u32
1009 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1010 {
1011         u32 t;
1012
1013         if (!cfg)
1014                 return 0;
1015
1016         t = 0;
1017         switch (cfg->mode) {
1018         case AR8327_PAD_NC:
1019                 break;
1020
1021         case AR8327_PAD_MAC2MAC_MII:
1022                 t = AR8327_PAD_MAC_MII_EN;
1023                 if (cfg->rxclk_sel)
1024                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1025                 if (cfg->txclk_sel)
1026                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1027                 break;
1028
1029         case AR8327_PAD_MAC2MAC_GMII:
1030                 t = AR8327_PAD_MAC_GMII_EN;
1031                 if (cfg->rxclk_sel)
1032                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1033                 if (cfg->txclk_sel)
1034                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1035                 break;
1036
1037         case AR8327_PAD_MAC_SGMII:
1038                 t = AR8327_PAD_SGMII_EN;
1039
1040                 /*
1041                  * WAR for the QUalcomm Atheros AP136 board.
1042                  * It seems that RGMII TX/RX delay settings needs to be
1043                  * applied for SGMII mode as well, The ethernet is not
1044                  * reliable without this.
1045                  */
1046                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1047                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1048                 if (cfg->rxclk_delay_en)
1049                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1050                 if (cfg->txclk_delay_en)
1051                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1052
1053                 if (cfg->sgmii_delay_en)
1054                         t |= AR8327_PAD_SGMII_DELAY_EN;
1055
1056                 break;
1057
1058         case AR8327_PAD_MAC2PHY_MII:
1059                 t = AR8327_PAD_PHY_MII_EN;
1060                 if (cfg->rxclk_sel)
1061                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1062                 if (cfg->txclk_sel)
1063                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1064                 break;
1065
1066         case AR8327_PAD_MAC2PHY_GMII:
1067                 t = AR8327_PAD_PHY_GMII_EN;
1068                 if (cfg->pipe_rxclk_sel)
1069                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1070                 if (cfg->rxclk_sel)
1071                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1072                 if (cfg->txclk_sel)
1073                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1074                 break;
1075
1076         case AR8327_PAD_MAC_RGMII:
1077                 t = AR8327_PAD_RGMII_EN;
1078                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1079                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1080                 if (cfg->rxclk_delay_en)
1081                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1082                 if (cfg->txclk_delay_en)
1083                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1084                 break;
1085
1086         case AR8327_PAD_PHY_GMII:
1087                 t = AR8327_PAD_PHYX_GMII_EN;
1088                 break;
1089
1090         case AR8327_PAD_PHY_RGMII:
1091                 t = AR8327_PAD_PHYX_RGMII_EN;
1092                 break;
1093
1094         case AR8327_PAD_PHY_MII:
1095                 t = AR8327_PAD_PHYX_MII_EN;
1096                 break;
1097         }
1098
1099         return t;
1100 }
1101
1102 static void
1103 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1104 {
1105         switch (priv->chip_rev) {
1106         case 1:
1107                 /* For 100M waveform */
1108                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1109                 /* Turn on Gigabit clock */
1110                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1111                 break;
1112
1113         case 2:
1114                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1115                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1116                 /* fallthrough */
1117         case 4:
1118                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1119                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1120
1121                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1122                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1123                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1124                 break;
1125         }
1126 }
1127
1128 static u32
1129 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1130 {
1131         u32 t;
1132
1133         if (!cfg->force_link)
1134                 return AR8216_PORT_STATUS_LINK_AUTO;
1135
1136         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1137         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1138         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1139         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1140
1141         switch (cfg->speed) {
1142         case AR8327_PORT_SPEED_10:
1143                 t |= AR8216_PORT_SPEED_10M;
1144                 break;
1145         case AR8327_PORT_SPEED_100:
1146                 t |= AR8216_PORT_SPEED_100M;
1147                 break;
1148         case AR8327_PORT_SPEED_1000:
1149                 t |= AR8216_PORT_SPEED_1000M;
1150                 break;
1151         }
1152
1153         return t;
1154 }
1155
1156 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1157         [_num] = { .reg = (_reg), .shift = (_shift) }
1158
1159 static const struct ar8327_led_entry
1160 ar8327_led_map[AR8327_NUM_LEDS] = {
1161         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1162         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1163         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1164
1165         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1166         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1167         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1168
1169         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1170         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1171         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1172
1173         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1174         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1175         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1176
1177         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1178         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1179         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1180 };
1181
1182 static void
1183 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1184                        enum ar8327_led_pattern pattern)
1185 {
1186         const struct ar8327_led_entry *entry;
1187
1188         entry = &ar8327_led_map[led_num];
1189         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1190                    (3 << entry->shift), pattern << entry->shift);
1191 }
1192
1193 static void
1194 ar8327_led_work_func(struct work_struct *work)
1195 {
1196         struct ar8327_led *aled;
1197         u8 pattern;
1198
1199         aled = container_of(work, struct ar8327_led, led_work);
1200
1201         spin_lock(&aled->lock);
1202         pattern = aled->pattern;
1203         spin_unlock(&aled->lock);
1204
1205         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1206                                pattern);
1207 }
1208
1209 static void
1210 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1211 {
1212         if (aled->pattern == pattern)
1213                 return;
1214
1215         aled->pattern = pattern;
1216         schedule_work(&aled->led_work);
1217 }
1218
1219 static inline struct ar8327_led *
1220 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1221 {
1222         return container_of(led_cdev, struct ar8327_led, cdev);
1223 }
1224
1225 static int
1226 ar8327_led_blink_set(struct led_classdev *led_cdev,
1227                      unsigned long *delay_on,
1228                      unsigned long *delay_off)
1229 {
1230         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1231
1232         if (*delay_on == 0 && *delay_off == 0) {
1233                 *delay_on = 125;
1234                 *delay_off = 125;
1235         }
1236
1237         if (*delay_on != 125 || *delay_off != 125) {
1238                 /*
1239                  * The hardware only supports blinking at 4Hz. Fall back
1240                  * to software implementation in other cases.
1241                  */
1242                 return -EINVAL;
1243         }
1244
1245         spin_lock(&aled->lock);
1246
1247         aled->enable_hw_mode = false;
1248         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1249
1250         spin_unlock(&aled->lock);
1251
1252         return 0;
1253 }
1254
1255 static void
1256 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1257                           enum led_brightness brightness)
1258 {
1259         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1260         u8 pattern;
1261         bool active;
1262
1263         active = (brightness != LED_OFF);
1264         active ^= aled->active_low;
1265
1266         pattern = (active) ? AR8327_LED_PATTERN_ON :
1267                              AR8327_LED_PATTERN_OFF;
1268
1269         spin_lock(&aled->lock);
1270
1271         aled->enable_hw_mode = false;
1272         ar8327_led_schedule_change(aled, pattern);
1273
1274         spin_unlock(&aled->lock);
1275 }
1276
1277 static ssize_t
1278 ar8327_led_enable_hw_mode_show(struct device *dev,
1279                                struct device_attribute *attr,
1280                                char *buf)
1281 {
1282         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1283         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1284         ssize_t ret = 0;
1285
1286         spin_lock(&aled->lock);
1287         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1288         spin_unlock(&aled->lock);
1289
1290         return ret;
1291 }
1292
1293 static ssize_t
1294 ar8327_led_enable_hw_mode_store(struct device *dev,
1295                                 struct device_attribute *attr,
1296                                 const char *buf,
1297                                 size_t size)
1298 {
1299         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1300         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1301         u8 pattern;
1302         u8 value;
1303         int ret;
1304
1305         ret = kstrtou8(buf, 10, &value);
1306         if (ret < 0)
1307                 return -EINVAL;
1308
1309         spin_lock(&aled->lock);
1310
1311         aled->enable_hw_mode = !!value;
1312         if (aled->enable_hw_mode)
1313                 pattern = AR8327_LED_PATTERN_RULE;
1314         else
1315                 pattern = AR8327_LED_PATTERN_OFF;
1316
1317         ar8327_led_schedule_change(aled, pattern);
1318
1319         spin_unlock(&aled->lock);
1320
1321         return size;
1322 }
1323
1324 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1325                    ar8327_led_enable_hw_mode_show,
1326                    ar8327_led_enable_hw_mode_store);
1327
1328 static int
1329 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1330 {
1331         int ret;
1332
1333         ret = led_classdev_register(NULL, &aled->cdev);
1334         if (ret < 0)
1335                 return ret;
1336
1337         if (aled->mode == AR8327_LED_MODE_HW) {
1338                 ret = device_create_file(aled->cdev.dev,
1339                                          &dev_attr_enable_hw_mode);
1340                 if (ret)
1341                         goto err_unregister;
1342         }
1343
1344         return 0;
1345
1346 err_unregister:
1347         led_classdev_unregister(&aled->cdev);
1348         return ret;
1349 }
1350
1351 static void
1352 ar8327_led_unregister(struct ar8327_led *aled)
1353 {
1354         if (aled->mode == AR8327_LED_MODE_HW)
1355                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1356
1357         led_classdev_unregister(&aled->cdev);
1358         cancel_work_sync(&aled->led_work);
1359 }
1360
1361 static int
1362 ar8327_led_create(struct ar8xxx_priv *priv,
1363                   const struct ar8327_led_info *led_info)
1364 {
1365         struct ar8327_data *data = &priv->chip_data.ar8327;
1366         struct ar8327_led *aled;
1367         int ret;
1368
1369         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1370                 return 0;
1371
1372         if (!led_info->name)
1373                 return -EINVAL;
1374
1375         if (led_info->led_num >= AR8327_NUM_LEDS)
1376                 return -EINVAL;
1377
1378         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1379                        GFP_KERNEL);
1380         if (!aled)
1381                 return -ENOMEM;
1382
1383         aled->sw_priv = priv;
1384         aled->led_num = led_info->led_num;
1385         aled->active_low = led_info->active_low;
1386         aled->mode = led_info->mode;
1387
1388         if (aled->mode == AR8327_LED_MODE_HW)
1389                 aled->enable_hw_mode = true;
1390
1391         aled->name = (char *)(aled + 1);
1392         strcpy(aled->name, led_info->name);
1393
1394         aled->cdev.name = aled->name;
1395         aled->cdev.brightness_set = ar8327_led_set_brightness;
1396         aled->cdev.blink_set = ar8327_led_blink_set;
1397         aled->cdev.default_trigger = led_info->default_trigger;
1398
1399         spin_lock_init(&aled->lock);
1400         mutex_init(&aled->mutex);
1401         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1402
1403         ret = ar8327_led_register(priv, aled);
1404         if (ret)
1405                 goto err_free;
1406
1407         data->leds[data->num_leds++] = aled;
1408
1409         return 0;
1410
1411 err_free:
1412         kfree(aled);
1413         return ret;
1414 }
1415
1416 static void
1417 ar8327_led_destroy(struct ar8327_led *aled)
1418 {
1419         ar8327_led_unregister(aled);
1420         kfree(aled);
1421 }
1422
1423 static void
1424 ar8327_leds_init(struct ar8xxx_priv *priv)
1425 {
1426         struct ar8327_data *data;
1427         unsigned i;
1428
1429         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1430                 return;
1431
1432         data = &priv->chip_data.ar8327;
1433
1434         for (i = 0; i < data->num_leds; i++) {
1435                 struct ar8327_led *aled;
1436
1437                 aled = data->leds[i];
1438
1439                 if (aled->enable_hw_mode)
1440                         aled->pattern = AR8327_LED_PATTERN_RULE;
1441                 else
1442                         aled->pattern = AR8327_LED_PATTERN_OFF;
1443
1444                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1445         }
1446 }
1447
1448 static void
1449 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1450 {
1451         struct ar8327_data *data = &priv->chip_data.ar8327;
1452         unsigned i;
1453
1454         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1455                 return;
1456
1457         for (i = 0; i < data->num_leds; i++) {
1458                 struct ar8327_led *aled;
1459
1460                 aled = data->leds[i];
1461                 ar8327_led_destroy(aled);
1462         }
1463
1464         kfree(data->leds);
1465 }
1466
1467 static int
1468 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1469                        struct ar8327_platform_data *pdata)
1470 {
1471         struct ar8327_led_cfg *led_cfg;
1472         struct ar8327_data *data;
1473         u32 pos, new_pos;
1474         u32 t;
1475
1476         if (!pdata)
1477                 return -EINVAL;
1478
1479         priv->get_port_link = pdata->get_port_link;
1480
1481         data = &priv->chip_data.ar8327;
1482
1483         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1484         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1485
1486         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1487         if (chip_is_ar8337(priv))
1488                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1489
1490         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1491         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1492         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1493         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1494         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1495
1496         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1497         new_pos = pos;
1498
1499         led_cfg = pdata->led_cfg;
1500         if (led_cfg) {
1501                 if (led_cfg->open_drain)
1502                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1503                 else
1504                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1505
1506                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1507                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1508                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1509                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1510
1511                 if (new_pos != pos)
1512                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1513         }
1514
1515         if (pdata->sgmii_cfg) {
1516                 t = pdata->sgmii_cfg->sgmii_ctrl;
1517                 if (priv->chip_rev == 1)
1518                         t |= AR8327_SGMII_CTRL_EN_PLL |
1519                              AR8327_SGMII_CTRL_EN_RX |
1520                              AR8327_SGMII_CTRL_EN_TX;
1521                 else
1522                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1523                                AR8327_SGMII_CTRL_EN_RX |
1524                                AR8327_SGMII_CTRL_EN_TX);
1525
1526                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1527
1528                 if (pdata->sgmii_cfg->serdes_aen)
1529                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1530                 else
1531                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1532         }
1533
1534         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1535
1536         if (pdata->leds && pdata->num_leds) {
1537                 int i;
1538
1539                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1540                                      GFP_KERNEL);
1541                 if (!data->leds)
1542                         return -ENOMEM;
1543
1544                 for (i = 0; i < pdata->num_leds; i++)
1545                         ar8327_led_create(priv, &pdata->leds[i]);
1546         }
1547
1548         return 0;
1549 }
1550
1551 #ifdef CONFIG_OF
1552 static int
1553 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1554 {
1555         const __be32 *paddr;
1556         int len;
1557         int i;
1558
1559         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1560         if (!paddr || len < (2 * sizeof(*paddr)))
1561                 return -EINVAL;
1562
1563         len /= sizeof(*paddr);
1564
1565         for (i = 0; i < len - 1; i += 2) {
1566                 u32 reg;
1567                 u32 val;
1568
1569                 reg = be32_to_cpup(paddr + i);
1570                 val = be32_to_cpup(paddr + i + 1);
1571
1572                 switch (reg) {
1573                 case AR8327_REG_PORT_STATUS(0):
1574                         priv->chip_data.ar8327.port0_status = val;
1575                         break;
1576                 case AR8327_REG_PORT_STATUS(6):
1577                         priv->chip_data.ar8327.port6_status = val;
1578                         break;
1579                 default:
1580                         priv->write(priv, reg, val);
1581                         break;
1582                 }
1583         }
1584
1585         return 0;
1586 }
1587 #else
1588 static inline int
1589 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1590 {
1591         return -EINVAL;
1592 }
1593 #endif
1594
1595 static int
1596 ar8327_hw_init(struct ar8xxx_priv *priv)
1597 {
1598         struct mii_bus *bus;
1599         int ret;
1600         int i;
1601
1602         if (priv->phy->dev.of_node)
1603                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1604         else
1605                 ret = ar8327_hw_config_pdata(priv,
1606                                              priv->phy->dev.platform_data);
1607
1608         if (ret)
1609                 return ret;
1610
1611         ar8327_leds_init(priv);
1612
1613         bus = priv->mii_bus;
1614         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
1615                 ar8327_phy_fixup(priv, i);
1616
1617                 /* start aneg on the PHY */
1618                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1619                                                      ADVERTISE_PAUSE_CAP |
1620                                                      ADVERTISE_PAUSE_ASYM);
1621                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1622                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1623         }
1624
1625         msleep(1000);
1626
1627         return 0;
1628 }
1629
1630 static void
1631 ar8327_cleanup(struct ar8xxx_priv *priv)
1632 {
1633         ar8327_leds_cleanup(priv);
1634 }
1635
1636 static void
1637 ar8327_init_globals(struct ar8xxx_priv *priv)
1638 {
1639         u32 t;
1640
1641         /* enable CPU port and disable mirror port */
1642         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1643             AR8327_FWD_CTRL0_MIRROR_PORT;
1644         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1645
1646         /* forward multicast and broadcast frames to CPU */
1647         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1648             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1649             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1650         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1651
1652         /* enable jumbo frames */
1653         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1654                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1655
1656         /* Enable MIB counters */
1657         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1658                        AR8327_MODULE_EN_MIB);
1659
1660         /* Disable EEE on all ports due to stability issues */
1661         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1662         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1663              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1664              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1665              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1666              AR8327_EEE_CTRL_DISABLE_PHY(4);
1667         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1668 }
1669
1670 static void
1671 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1672 {
1673         u32 t;
1674
1675         if (port == AR8216_PORT_CPU)
1676                 t = priv->chip_data.ar8327.port0_status;
1677         else if (port == 6)
1678                 t = priv->chip_data.ar8327.port6_status;
1679         else
1680                 t = AR8216_PORT_STATUS_LINK_AUTO;
1681
1682         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1683         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1684
1685         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1686         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1687         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1688
1689         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1690         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1691
1692         t = AR8327_PORT_LOOKUP_LEARN;
1693         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1694         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1695 }
1696
1697 static u32
1698 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1699 {
1700         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1701 }
1702
1703 static int
1704 ar8327_atu_flush(struct ar8xxx_priv *priv)
1705 {
1706         int ret;
1707
1708         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1709                               AR8327_ATU_FUNC_BUSY, 0);
1710         if (!ret)
1711                 priv->write(priv, AR8327_REG_ATU_FUNC,
1712                             AR8327_ATU_FUNC_OP_FLUSH);
1713
1714         return ret;
1715 }
1716
1717 static void
1718 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1719 {
1720         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1721                             AR8327_VTU_FUNC1_BUSY, 0))
1722                 return;
1723
1724         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1725                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1726
1727         op |= AR8327_VTU_FUNC1_BUSY;
1728         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1729 }
1730
1731 static void
1732 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1733 {
1734         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1735 }
1736
1737 static void
1738 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1739 {
1740         u32 op;
1741         u32 val;
1742         int i;
1743
1744         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1745         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1746         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1747                 u32 mode;
1748
1749                 if ((port_mask & BIT(i)) == 0)
1750                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1751                 else if (priv->vlan == 0)
1752                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1753                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1754                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1755                 else
1756                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1757
1758                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1759         }
1760         ar8327_vtu_op(priv, op, val);
1761 }
1762
1763 static void
1764 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1765 {
1766         u32 t;
1767         u32 egress, ingress;
1768         u32 pvid = priv->vlan_id[priv->pvid[port]];
1769
1770         if (priv->vlan) {
1771                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1772                 ingress = AR8216_IN_SECURE;
1773         } else {
1774                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1775                 ingress = AR8216_IN_PORT_ONLY;
1776         }
1777
1778         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1779         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1780         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1781
1782         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1783         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1784         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1785
1786         t = members;
1787         t |= AR8327_PORT_LOOKUP_LEARN;
1788         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1789         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1790         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1791 }
1792
1793 static const struct ar8xxx_chip ar8327_chip = {
1794         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1795         .hw_init = ar8327_hw_init,
1796         .cleanup = ar8327_cleanup,
1797         .init_globals = ar8327_init_globals,
1798         .init_port = ar8327_init_port,
1799         .setup_port = ar8327_setup_port,
1800         .read_port_status = ar8327_read_port_status,
1801         .atu_flush = ar8327_atu_flush,
1802         .vtu_flush = ar8327_vtu_flush,
1803         .vtu_load_vlan = ar8327_vtu_load_vlan,
1804
1805         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1806         .mib_decs = ar8236_mibs,
1807 };
1808
1809 static int
1810 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1811                    struct switch_val *val)
1812 {
1813         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1814         priv->vlan = !!val->value.i;
1815         return 0;
1816 }
1817
1818 static int
1819 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1820                    struct switch_val *val)
1821 {
1822         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1823         val->value.i = priv->vlan;
1824         return 0;
1825 }
1826
1827
1828 static int
1829 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1830 {
1831         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1832
1833         /* make sure no invalid PVIDs get set */
1834
1835         if (vlan >= dev->vlans)
1836                 return -EINVAL;
1837
1838         priv->pvid[port] = vlan;
1839         return 0;
1840 }
1841
1842 static int
1843 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1844 {
1845         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1846         *vlan = priv->pvid[port];
1847         return 0;
1848 }
1849
1850 static int
1851 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1852                   struct switch_val *val)
1853 {
1854         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1855         priv->vlan_id[val->port_vlan] = val->value.i;
1856         return 0;
1857 }
1858
1859 static int
1860 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1861                   struct switch_val *val)
1862 {
1863         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1864         val->value.i = priv->vlan_id[val->port_vlan];
1865         return 0;
1866 }
1867
1868 static int
1869 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1870                         struct switch_port_link *link)
1871 {
1872         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1873
1874         ar8216_read_port_link(priv, port, link);
1875         return 0;
1876 }
1877
1878 static int
1879 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1880 {
1881         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1882         u8 ports = priv->vlan_table[val->port_vlan];
1883         int i;
1884
1885         val->len = 0;
1886         for (i = 0; i < dev->ports; i++) {
1887                 struct switch_port *p;
1888
1889                 if (!(ports & (1 << i)))
1890                         continue;
1891
1892                 p = &val->value.ports[val->len++];
1893                 p->id = i;
1894                 if (priv->vlan_tagged & (1 << i))
1895                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1896                 else
1897                         p->flags = 0;
1898         }
1899         return 0;
1900 }
1901
1902 static int
1903 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1904 {
1905         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1906         u8 ports = priv->vlan_table[val->port_vlan];
1907         int i;
1908
1909         val->len = 0;
1910         for (i = 0; i < dev->ports; i++) {
1911                 struct switch_port *p;
1912
1913                 if (!(ports & (1 << i)))
1914                         continue;
1915
1916                 p = &val->value.ports[val->len++];
1917                 p->id = i;
1918                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1919                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1920                 else
1921                         p->flags = 0;
1922         }
1923         return 0;
1924 }
1925
1926 static int
1927 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1928 {
1929         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1930         u8 *vt = &priv->vlan_table[val->port_vlan];
1931         int i, j;
1932
1933         *vt = 0;
1934         for (i = 0; i < val->len; i++) {
1935                 struct switch_port *p = &val->value.ports[i];
1936
1937                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1938                         priv->vlan_tagged |= (1 << p->id);
1939                 } else {
1940                         priv->vlan_tagged &= ~(1 << p->id);
1941                         priv->pvid[p->id] = val->port_vlan;
1942
1943                         /* make sure that an untagged port does not
1944                          * appear in other vlans */
1945                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1946                                 if (j == val->port_vlan)
1947                                         continue;
1948                                 priv->vlan_table[j] &= ~(1 << p->id);
1949                         }
1950                 }
1951
1952                 *vt |= 1 << p->id;
1953         }
1954         return 0;
1955 }
1956
1957 static int
1958 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1959 {
1960         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1961         u8 *vt = &priv->vlan_table[val->port_vlan];
1962         int i;
1963
1964         *vt = 0;
1965         for (i = 0; i < val->len; i++) {
1966                 struct switch_port *p = &val->value.ports[i];
1967
1968                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1969                         if (val->port_vlan == priv->pvid[p->id]) {
1970                                 priv->vlan_tagged |= (1 << p->id);
1971                         }
1972                 } else {
1973                         priv->vlan_tagged &= ~(1 << p->id);
1974                         priv->pvid[p->id] = val->port_vlan;
1975                 }
1976
1977                 *vt |= 1 << p->id;
1978         }
1979         return 0;
1980 }
1981
1982 static void
1983 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1984 {
1985         int port;
1986
1987         /* reset all mirror registers */
1988         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1989                    AR8327_FWD_CTRL0_MIRROR_PORT,
1990                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1991         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1992                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1993                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1994                            0);
1995
1996                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1997                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1998                            0);
1999         }
2000
2001         /* now enable mirroring if necessary */
2002         if (priv->source_port >= AR8327_NUM_PORTS ||
2003             priv->monitor_port >= AR8327_NUM_PORTS ||
2004             priv->source_port == priv->monitor_port) {
2005                 return;
2006         }
2007
2008         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2009                    AR8327_FWD_CTRL0_MIRROR_PORT,
2010                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2011
2012         if (priv->mirror_rx)
2013                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2014                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2015                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2016
2017         if (priv->mirror_tx)
2018                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2019                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2020                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2021 }
2022
2023 static void
2024 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2025 {
2026         int port;
2027
2028         /* reset all mirror registers */
2029         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2030                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2031                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2032         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2033                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2034                            AR8216_PORT_CTRL_MIRROR_RX,
2035                            0);
2036
2037                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2038                            AR8216_PORT_CTRL_MIRROR_TX,
2039                            0);
2040         }
2041
2042         /* now enable mirroring if necessary */
2043         if (priv->source_port >= AR8216_NUM_PORTS ||
2044             priv->monitor_port >= AR8216_NUM_PORTS ||
2045             priv->source_port == priv->monitor_port) {
2046                 return;
2047         }
2048
2049         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2050                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2051                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2052
2053         if (priv->mirror_rx)
2054                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2055                            AR8216_PORT_CTRL_MIRROR_RX,
2056                            AR8216_PORT_CTRL_MIRROR_RX);
2057
2058         if (priv->mirror_tx)
2059                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2060                            AR8216_PORT_CTRL_MIRROR_TX,
2061                            AR8216_PORT_CTRL_MIRROR_TX);
2062 }
2063
2064 static void
2065 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2066 {
2067         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2068                 ar8327_set_mirror_regs(priv);
2069         } else {
2070                 ar8216_set_mirror_regs(priv);
2071         }
2072 }
2073
2074 static int
2075 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2076 {
2077         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2078         u8 portmask[AR8X16_MAX_PORTS];
2079         int i, j;
2080
2081         mutex_lock(&priv->reg_mutex);
2082         /* flush all vlan translation unit entries */
2083         priv->chip->vtu_flush(priv);
2084
2085         memset(portmask, 0, sizeof(portmask));
2086         if (!priv->init) {
2087                 /* calculate the port destination masks and load vlans
2088                  * into the vlan translation unit */
2089                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2090                         u8 vp = priv->vlan_table[j];
2091
2092                         if (!vp)
2093                                 continue;
2094
2095                         for (i = 0; i < dev->ports; i++) {
2096                                 u8 mask = (1 << i);
2097                                 if (vp & mask)
2098                                         portmask[i] |= vp & ~mask;
2099                         }
2100
2101                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2102                                                  priv->vlan_table[j]);
2103                 }
2104         } else {
2105                 /* vlan disabled:
2106                  * isolate all ports, but connect them to the cpu port */
2107                 for (i = 0; i < dev->ports; i++) {
2108                         if (i == AR8216_PORT_CPU)
2109                                 continue;
2110
2111                         portmask[i] = 1 << AR8216_PORT_CPU;
2112                         portmask[AR8216_PORT_CPU] |= (1 << i);
2113                 }
2114         }
2115
2116         /* update the port destination mask registers and tag settings */
2117         for (i = 0; i < dev->ports; i++) {
2118                 priv->chip->setup_port(priv, i, portmask[i]);
2119         }
2120
2121         ar8xxx_set_mirror_regs(priv);
2122
2123         mutex_unlock(&priv->reg_mutex);
2124         return 0;
2125 }
2126
2127 static int
2128 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2129 {
2130         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2131         int i;
2132
2133         mutex_lock(&priv->reg_mutex);
2134         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2135                 offsetof(struct ar8xxx_priv, vlan));
2136
2137         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2138                 priv->vlan_id[i] = i;
2139
2140         /* Configure all ports */
2141         for (i = 0; i < dev->ports; i++)
2142                 priv->chip->init_port(priv, i);
2143
2144         priv->mirror_rx = false;
2145         priv->mirror_tx = false;
2146         priv->source_port = 0;
2147         priv->monitor_port = 0;
2148
2149         priv->chip->init_globals(priv);
2150
2151         mutex_unlock(&priv->reg_mutex);
2152
2153         return ar8xxx_sw_hw_apply(dev);
2154 }
2155
2156 static int
2157 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2158                          const struct switch_attr *attr,
2159                          struct switch_val *val)
2160 {
2161         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2162         unsigned int len;
2163         int ret;
2164
2165         if (!ar8xxx_has_mib_counters(priv))
2166                 return -EOPNOTSUPP;
2167
2168         mutex_lock(&priv->mib_lock);
2169
2170         len = priv->dev.ports * priv->chip->num_mibs *
2171               sizeof(*priv->mib_stats);
2172         memset(priv->mib_stats, '\0', len);
2173         ret = ar8xxx_mib_flush(priv);
2174         if (ret)
2175                 goto unlock;
2176
2177         ret = 0;
2178
2179 unlock:
2180         mutex_unlock(&priv->mib_lock);
2181         return ret;
2182 }
2183
2184 static int
2185 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2186                                const struct switch_attr *attr,
2187                                struct switch_val *val)
2188 {
2189         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2190
2191         mutex_lock(&priv->reg_mutex);
2192         priv->mirror_rx = !!val->value.i;
2193         ar8xxx_set_mirror_regs(priv);
2194         mutex_unlock(&priv->reg_mutex);
2195
2196         return 0;
2197 }
2198
2199 static int
2200 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2201                                const struct switch_attr *attr,
2202                                struct switch_val *val)
2203 {
2204         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2205         val->value.i = priv->mirror_rx;
2206         return 0;
2207 }
2208
2209 static int
2210 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2211                                const struct switch_attr *attr,
2212                                struct switch_val *val)
2213 {
2214         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2215
2216         mutex_lock(&priv->reg_mutex);
2217         priv->mirror_tx = !!val->value.i;
2218         ar8xxx_set_mirror_regs(priv);
2219         mutex_unlock(&priv->reg_mutex);
2220
2221         return 0;
2222 }
2223
2224 static int
2225 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2226                                const struct switch_attr *attr,
2227                                struct switch_val *val)
2228 {
2229         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2230         val->value.i = priv->mirror_tx;
2231         return 0;
2232 }
2233
2234 static int
2235 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2236                                   const struct switch_attr *attr,
2237                                   struct switch_val *val)
2238 {
2239         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2240
2241         mutex_lock(&priv->reg_mutex);
2242         priv->monitor_port = val->value.i;
2243         ar8xxx_set_mirror_regs(priv);
2244         mutex_unlock(&priv->reg_mutex);
2245
2246         return 0;
2247 }
2248
2249 static int
2250 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2251                                   const struct switch_attr *attr,
2252                                   struct switch_val *val)
2253 {
2254         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2255         val->value.i = priv->monitor_port;
2256         return 0;
2257 }
2258
2259 static int
2260 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2261                                  const struct switch_attr *attr,
2262                                  struct switch_val *val)
2263 {
2264         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2265
2266         mutex_lock(&priv->reg_mutex);
2267         priv->source_port = val->value.i;
2268         ar8xxx_set_mirror_regs(priv);
2269         mutex_unlock(&priv->reg_mutex);
2270
2271         return 0;
2272 }
2273
2274 static int
2275 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2276                                  const struct switch_attr *attr,
2277                                  struct switch_val *val)
2278 {
2279         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2280         val->value.i = priv->source_port;
2281         return 0;
2282 }
2283
2284 static int
2285 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2286                              const struct switch_attr *attr,
2287                              struct switch_val *val)
2288 {
2289         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2290         int port;
2291         int ret;
2292
2293         if (!ar8xxx_has_mib_counters(priv))
2294                 return -EOPNOTSUPP;
2295
2296         port = val->port_vlan;
2297         if (port >= dev->ports)
2298                 return -EINVAL;
2299
2300         mutex_lock(&priv->mib_lock);
2301         ret = ar8xxx_mib_capture(priv);
2302         if (ret)
2303                 goto unlock;
2304
2305         ar8xxx_mib_fetch_port_stat(priv, port, true);
2306
2307         ret = 0;
2308
2309 unlock:
2310         mutex_unlock(&priv->mib_lock);
2311         return ret;
2312 }
2313
2314 static int
2315 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2316                        const struct switch_attr *attr,
2317                        struct switch_val *val)
2318 {
2319         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2320         const struct ar8xxx_chip *chip = priv->chip;
2321         u64 *mib_stats;
2322         int port;
2323         int ret;
2324         char *buf = priv->buf;
2325         int i, len = 0;
2326
2327         if (!ar8xxx_has_mib_counters(priv))
2328                 return -EOPNOTSUPP;
2329
2330         port = val->port_vlan;
2331         if (port >= dev->ports)
2332                 return -EINVAL;
2333
2334         mutex_lock(&priv->mib_lock);
2335         ret = ar8xxx_mib_capture(priv);
2336         if (ret)
2337                 goto unlock;
2338
2339         ar8xxx_mib_fetch_port_stat(priv, port, false);
2340
2341         len += snprintf(buf + len, sizeof(priv->buf) - len,
2342                         "Port %d MIB counters\n",
2343                         port);
2344
2345         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2346         for (i = 0; i < chip->num_mibs; i++)
2347                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2348                                 "%-12s: %llu\n",
2349                                 chip->mib_decs[i].name,
2350                                 mib_stats[i]);
2351
2352         val->value.s = buf;
2353         val->len = len;
2354
2355         ret = 0;
2356
2357 unlock:
2358         mutex_unlock(&priv->mib_lock);
2359         return ret;
2360 }
2361
2362 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2363         {
2364                 .type = SWITCH_TYPE_INT,
2365                 .name = "enable_vlan",
2366                 .description = "Enable VLAN mode",
2367                 .set = ar8xxx_sw_set_vlan,
2368                 .get = ar8xxx_sw_get_vlan,
2369                 .max = 1
2370         },
2371         {
2372                 .type = SWITCH_TYPE_NOVAL,
2373                 .name = "reset_mibs",
2374                 .description = "Reset all MIB counters",
2375                 .set = ar8xxx_sw_set_reset_mibs,
2376         },
2377         {
2378                 .type = SWITCH_TYPE_INT,
2379                 .name = "enable_mirror_rx",
2380                 .description = "Enable mirroring of RX packets",
2381                 .set = ar8xxx_sw_set_mirror_rx_enable,
2382                 .get = ar8xxx_sw_get_mirror_rx_enable,
2383                 .max = 1
2384         },
2385         {
2386                 .type = SWITCH_TYPE_INT,
2387                 .name = "enable_mirror_tx",
2388                 .description = "Enable mirroring of TX packets",
2389                 .set = ar8xxx_sw_set_mirror_tx_enable,
2390                 .get = ar8xxx_sw_get_mirror_tx_enable,
2391                 .max = 1
2392         },
2393         {
2394                 .type = SWITCH_TYPE_INT,
2395                 .name = "mirror_monitor_port",
2396                 .description = "Mirror monitor port",
2397                 .set = ar8xxx_sw_set_mirror_monitor_port,
2398                 .get = ar8xxx_sw_get_mirror_monitor_port,
2399                 .max = AR8216_NUM_PORTS - 1
2400         },
2401         {
2402                 .type = SWITCH_TYPE_INT,
2403                 .name = "mirror_source_port",
2404                 .description = "Mirror source port",
2405                 .set = ar8xxx_sw_set_mirror_source_port,
2406                 .get = ar8xxx_sw_get_mirror_source_port,
2407                 .max = AR8216_NUM_PORTS - 1
2408         },
2409 };
2410
2411 static struct switch_attr ar8327_sw_attr_globals[] = {
2412         {
2413                 .type = SWITCH_TYPE_INT,
2414                 .name = "enable_vlan",
2415                 .description = "Enable VLAN mode",
2416                 .set = ar8xxx_sw_set_vlan,
2417                 .get = ar8xxx_sw_get_vlan,
2418                 .max = 1
2419         },
2420         {
2421                 .type = SWITCH_TYPE_NOVAL,
2422                 .name = "reset_mibs",
2423                 .description = "Reset all MIB counters",
2424                 .set = ar8xxx_sw_set_reset_mibs,
2425         },
2426         {
2427                 .type = SWITCH_TYPE_INT,
2428                 .name = "enable_mirror_rx",
2429                 .description = "Enable mirroring of RX packets",
2430                 .set = ar8xxx_sw_set_mirror_rx_enable,
2431                 .get = ar8xxx_sw_get_mirror_rx_enable,
2432                 .max = 1
2433         },
2434         {
2435                 .type = SWITCH_TYPE_INT,
2436                 .name = "enable_mirror_tx",
2437                 .description = "Enable mirroring of TX packets",
2438                 .set = ar8xxx_sw_set_mirror_tx_enable,
2439                 .get = ar8xxx_sw_get_mirror_tx_enable,
2440                 .max = 1
2441         },
2442         {
2443                 .type = SWITCH_TYPE_INT,
2444                 .name = "mirror_monitor_port",
2445                 .description = "Mirror monitor port",
2446                 .set = ar8xxx_sw_set_mirror_monitor_port,
2447                 .get = ar8xxx_sw_get_mirror_monitor_port,
2448                 .max = AR8327_NUM_PORTS - 1
2449         },
2450         {
2451                 .type = SWITCH_TYPE_INT,
2452                 .name = "mirror_source_port",
2453                 .description = "Mirror source port",
2454                 .set = ar8xxx_sw_set_mirror_source_port,
2455                 .get = ar8xxx_sw_get_mirror_source_port,
2456                 .max = AR8327_NUM_PORTS - 1
2457         },
2458 };
2459
2460 static struct switch_attr ar8xxx_sw_attr_port[] = {
2461         {
2462                 .type = SWITCH_TYPE_NOVAL,
2463                 .name = "reset_mib",
2464                 .description = "Reset single port MIB counters",
2465                 .set = ar8xxx_sw_set_port_reset_mib,
2466         },
2467         {
2468                 .type = SWITCH_TYPE_STRING,
2469                 .name = "mib",
2470                 .description = "Get port's MIB counters",
2471                 .set = NULL,
2472                 .get = ar8xxx_sw_get_port_mib,
2473         },
2474 };
2475
2476 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2477         {
2478                 .type = SWITCH_TYPE_INT,
2479                 .name = "vid",
2480                 .description = "VLAN ID (0-4094)",
2481                 .set = ar8xxx_sw_set_vid,
2482                 .get = ar8xxx_sw_get_vid,
2483                 .max = 4094,
2484         },
2485 };
2486
2487 static const struct switch_dev_ops ar8xxx_sw_ops = {
2488         .attr_global = {
2489                 .attr = ar8xxx_sw_attr_globals,
2490                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2491         },
2492         .attr_port = {
2493                 .attr = ar8xxx_sw_attr_port,
2494                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2495         },
2496         .attr_vlan = {
2497                 .attr = ar8xxx_sw_attr_vlan,
2498                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2499         },
2500         .get_port_pvid = ar8xxx_sw_get_pvid,
2501         .set_port_pvid = ar8xxx_sw_set_pvid,
2502         .get_vlan_ports = ar8xxx_sw_get_ports,
2503         .set_vlan_ports = ar8xxx_sw_set_ports,
2504         .apply_config = ar8xxx_sw_hw_apply,
2505         .reset_switch = ar8xxx_sw_reset_switch,
2506         .get_port_link = ar8xxx_sw_get_port_link,
2507 };
2508
2509 static const struct switch_dev_ops ar8327_sw_ops = {
2510         .attr_global = {
2511                 .attr = ar8327_sw_attr_globals,
2512                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2513         },
2514         .attr_port = {
2515                 .attr = ar8xxx_sw_attr_port,
2516                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2517         },
2518         .attr_vlan = {
2519                 .attr = ar8xxx_sw_attr_vlan,
2520                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2521         },
2522         .get_port_pvid = ar8xxx_sw_get_pvid,
2523         .set_port_pvid = ar8xxx_sw_set_pvid,
2524         .get_vlan_ports = ar8327_sw_get_ports,
2525         .set_vlan_ports = ar8327_sw_set_ports,
2526         .apply_config = ar8xxx_sw_hw_apply,
2527         .reset_switch = ar8xxx_sw_reset_switch,
2528         .get_port_link = ar8xxx_sw_get_port_link,
2529 };
2530
2531 static int
2532 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2533 {
2534         u32 val;
2535         u16 id;
2536         int i;
2537
2538         val = priv->read(priv, AR8216_REG_CTRL);
2539         if (val == ~0)
2540                 return -ENODEV;
2541
2542         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2543         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2544                 u16 t;
2545
2546                 val = priv->read(priv, AR8216_REG_CTRL);
2547                 if (val == ~0)
2548                         return -ENODEV;
2549
2550                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2551                 if (t != id)
2552                         return -ENODEV;
2553         }
2554
2555         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2556         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2557
2558         switch (priv->chip_ver) {
2559         case AR8XXX_VER_AR8216:
2560                 priv->chip = &ar8216_chip;
2561                 break;
2562         case AR8XXX_VER_AR8236:
2563                 priv->chip = &ar8236_chip;
2564                 break;
2565         case AR8XXX_VER_AR8316:
2566                 priv->chip = &ar8316_chip;
2567                 break;
2568         case AR8XXX_VER_AR8327:
2569                 priv->mii_lo_first = true;
2570                 priv->chip = &ar8327_chip;
2571                 break;
2572         case AR8XXX_VER_AR8337:
2573                 priv->mii_lo_first = true;
2574                 priv->chip = &ar8327_chip;
2575                 break;
2576         default:
2577                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2578                        priv->chip_ver, priv->chip_rev);
2579
2580                 return -ENODEV;
2581         }
2582
2583         return 0;
2584 }
2585
2586 static void
2587 ar8xxx_mib_work_func(struct work_struct *work)
2588 {
2589         struct ar8xxx_priv *priv;
2590         int err;
2591
2592         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2593
2594         mutex_lock(&priv->mib_lock);
2595
2596         err = ar8xxx_mib_capture(priv);
2597         if (err)
2598                 goto next_port;
2599
2600         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2601
2602 next_port:
2603         priv->mib_next_port++;
2604         if (priv->mib_next_port >= priv->dev.ports)
2605                 priv->mib_next_port = 0;
2606
2607         mutex_unlock(&priv->mib_lock);
2608         schedule_delayed_work(&priv->mib_work,
2609                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2610 }
2611
2612 static int
2613 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2614 {
2615         unsigned int len;
2616
2617         if (!ar8xxx_has_mib_counters(priv))
2618                 return 0;
2619
2620         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2621
2622         len = priv->dev.ports * priv->chip->num_mibs *
2623               sizeof(*priv->mib_stats);
2624         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2625
2626         if (!priv->mib_stats)
2627                 return -ENOMEM;
2628
2629         return 0;
2630 }
2631
2632 static void
2633 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2634 {
2635         if (!ar8xxx_has_mib_counters(priv))
2636                 return;
2637
2638         schedule_delayed_work(&priv->mib_work,
2639                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2640 }
2641
2642 static void
2643 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2644 {
2645         if (!ar8xxx_has_mib_counters(priv))
2646                 return;
2647
2648         cancel_delayed_work(&priv->mib_work);
2649 }
2650
2651 static struct ar8xxx_priv *
2652 ar8xxx_create(void)
2653 {
2654         struct ar8xxx_priv *priv;
2655
2656         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2657         if (priv == NULL)
2658                 return NULL;
2659
2660         mutex_init(&priv->reg_mutex);
2661         mutex_init(&priv->mib_lock);
2662         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2663
2664         return priv;
2665 }
2666
2667 static void
2668 ar8xxx_free(struct ar8xxx_priv *priv)
2669 {
2670         if (priv->chip && priv->chip->cleanup)
2671                 priv->chip->cleanup(priv);
2672
2673         kfree(priv->mib_stats);
2674         kfree(priv);
2675 }
2676
2677 static struct ar8xxx_priv *
2678 ar8xxx_create_mii(struct mii_bus *bus)
2679 {
2680         struct ar8xxx_priv *priv;
2681
2682         priv = ar8xxx_create();
2683         if (priv) {
2684                 priv->mii_bus = bus;
2685                 priv->read = ar8xxx_mii_read;
2686                 priv->write = ar8xxx_mii_write;
2687                 priv->rmw = ar8xxx_mii_rmw;
2688         }
2689
2690         return priv;
2691 }
2692
2693 static int
2694 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2695 {
2696         struct switch_dev *swdev;
2697         int ret;
2698
2699         ret = ar8xxx_id_chip(priv);
2700         if (ret)
2701                 return ret;
2702
2703         swdev = &priv->dev;
2704         swdev->cpu_port = AR8216_PORT_CPU;
2705         swdev->ops = &ar8xxx_sw_ops;
2706
2707         if (chip_is_ar8316(priv)) {
2708                 swdev->name = "Atheros AR8316";
2709                 swdev->vlans = AR8X16_MAX_VLANS;
2710                 swdev->ports = AR8216_NUM_PORTS;
2711         } else if (chip_is_ar8236(priv)) {
2712                 swdev->name = "Atheros AR8236";
2713                 swdev->vlans = AR8216_NUM_VLANS;
2714                 swdev->ports = AR8216_NUM_PORTS;
2715         } else if (chip_is_ar8327(priv)) {
2716                 swdev->name = "Atheros AR8327";
2717                 swdev->vlans = AR8X16_MAX_VLANS;
2718                 swdev->ports = AR8327_NUM_PORTS;
2719                 swdev->ops = &ar8327_sw_ops;
2720         } else if (chip_is_ar8337(priv)) {
2721                 swdev->name = "Atheros AR8337";
2722                 swdev->vlans = AR8X16_MAX_VLANS;
2723                 swdev->ports = AR8327_NUM_PORTS;
2724                 swdev->ops = &ar8327_sw_ops;
2725         } else {
2726                 swdev->name = "Atheros AR8216";
2727                 swdev->vlans = AR8216_NUM_VLANS;
2728                 swdev->ports = AR8216_NUM_PORTS;
2729         }
2730
2731         ret = ar8xxx_mib_init(priv);
2732         if (ret)
2733                 return ret;
2734
2735         return 0;
2736 }
2737
2738 static int
2739 ar8xxx_start(struct ar8xxx_priv *priv)
2740 {
2741         int ret;
2742
2743         priv->init = true;
2744
2745         ret = priv->chip->hw_init(priv);
2746         if (ret)
2747                 return ret;
2748
2749         ret = ar8xxx_sw_reset_switch(&priv->dev);
2750         if (ret)
2751                 return ret;
2752
2753         priv->init = false;
2754
2755         ar8xxx_mib_start(priv);
2756
2757         return 0;
2758 }
2759
2760 static int
2761 ar8xxx_phy_config_init(struct phy_device *phydev)
2762 {
2763         struct ar8xxx_priv *priv = phydev->priv;
2764         struct net_device *dev = phydev->attached_dev;
2765         int ret;
2766
2767         if (WARN_ON(!priv))
2768                 return -ENODEV;
2769
2770         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2771                 return 0;
2772
2773         priv->phy = phydev;
2774
2775         if (phydev->addr != 0) {
2776                 if (chip_is_ar8316(priv)) {
2777                         /* switch device has been initialized, reinit */
2778                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2779                         priv->initialized = false;
2780                         priv->port4_phy = true;
2781                         ar8316_hw_init(priv);
2782                         return 0;
2783                 }
2784
2785                 return 0;
2786         }
2787
2788         ret = ar8xxx_start(priv);
2789         if (ret)
2790                 return ret;
2791
2792         /* VID fixup only needed on ar8216 */
2793         if (chip_is_ar8216(priv)) {
2794                 dev->phy_ptr = priv;
2795                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2796                 dev->eth_mangle_rx = ar8216_mangle_rx;
2797                 dev->eth_mangle_tx = ar8216_mangle_tx;
2798         }
2799
2800         return 0;
2801 }
2802
2803 static int
2804 ar8xxx_phy_read_status(struct phy_device *phydev)
2805 {
2806         struct ar8xxx_priv *priv = phydev->priv;
2807         struct switch_port_link link;
2808         int ret;
2809
2810         if (phydev->addr != 0)
2811                 return genphy_read_status(phydev);
2812
2813         ar8216_read_port_link(priv, phydev->addr, &link);
2814         phydev->link = !!link.link;
2815         if (!phydev->link)
2816                 return 0;
2817
2818         switch (link.speed) {
2819         case SWITCH_PORT_SPEED_10:
2820                 phydev->speed = SPEED_10;
2821                 break;
2822         case SWITCH_PORT_SPEED_100:
2823                 phydev->speed = SPEED_100;
2824                 break;
2825         case SWITCH_PORT_SPEED_1000:
2826                 phydev->speed = SPEED_1000;
2827                 break;
2828         default:
2829                 phydev->speed = 0;
2830         }
2831         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2832
2833         /* flush the address translation unit */
2834         mutex_lock(&priv->reg_mutex);
2835         ret = priv->chip->atu_flush(priv);
2836         mutex_unlock(&priv->reg_mutex);
2837
2838         phydev->state = PHY_RUNNING;
2839         netif_carrier_on(phydev->attached_dev);
2840         phydev->adjust_link(phydev->attached_dev);
2841
2842         return ret;
2843 }
2844
2845 static int
2846 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2847 {
2848         if (phydev->addr == 0)
2849                 return 0;
2850
2851         return genphy_config_aneg(phydev);
2852 }
2853
2854 static const u32 ar8xxx_phy_ids[] = {
2855         0x004dd033,
2856         0x004dd034, /* AR8327 */
2857         0x004dd036, /* AR8337 */
2858         0x004dd041,
2859         0x004dd042,
2860         0x004dd043, /* AR8236 */
2861 };
2862
2863 static bool
2864 ar8xxx_phy_match(u32 phy_id)
2865 {
2866         int i;
2867
2868         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2869                 if (phy_id == ar8xxx_phy_ids[i])
2870                         return true;
2871
2872         return false;
2873 }
2874
2875 static bool
2876 ar8xxx_is_possible(struct mii_bus *bus)
2877 {
2878         unsigned i;
2879
2880         for (i = 0; i < 4; i++) {
2881                 u32 phy_id;
2882
2883                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2884                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2885                 if (!ar8xxx_phy_match(phy_id)) {
2886                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2887                                  dev_name(&bus->dev), i, phy_id);
2888                         return false;
2889                 }
2890         }
2891
2892         return true;
2893 }
2894
2895 static int
2896 ar8xxx_phy_probe(struct phy_device *phydev)
2897 {
2898         struct ar8xxx_priv *priv;
2899         struct switch_dev *swdev;
2900         int ret;
2901
2902         /* skip PHYs at unused adresses */
2903         if (phydev->addr != 0 && phydev->addr != 4)
2904                 return -ENODEV;
2905
2906         if (!ar8xxx_is_possible(phydev->bus))
2907                 return -ENODEV;
2908
2909         mutex_lock(&ar8xxx_dev_list_lock);
2910         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2911                 if (priv->mii_bus == phydev->bus)
2912                         goto found;
2913
2914         priv = ar8xxx_create_mii(phydev->bus);
2915         if (priv == NULL) {
2916                 ret = -ENOMEM;
2917                 goto unlock;
2918         }
2919
2920         ret = ar8xxx_probe_switch(priv);
2921         if (ret)
2922                 goto free_priv;
2923
2924         swdev = &priv->dev;
2925         swdev->alias = dev_name(&priv->mii_bus->dev);
2926         ret = register_switch(swdev, NULL);
2927         if (ret)
2928                 goto free_priv;
2929
2930         pr_info("%s: %s rev. %u switch registered on %s\n",
2931                 swdev->devname, swdev->name, priv->chip_rev,
2932                 dev_name(&priv->mii_bus->dev));
2933
2934 found:
2935         priv->use_count++;
2936
2937         if (phydev->addr == 0) {
2938                 if (ar8xxx_has_gige(priv)) {
2939                         phydev->supported = SUPPORTED_1000baseT_Full;
2940                         phydev->advertising = ADVERTISED_1000baseT_Full;
2941                 } else {
2942                         phydev->supported = SUPPORTED_100baseT_Full;
2943                         phydev->advertising = ADVERTISED_100baseT_Full;
2944                 }
2945
2946                 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2947                         priv->phy = phydev;
2948
2949                         ret = ar8xxx_start(priv);
2950                         if (ret)
2951                                 goto err_unregister_switch;
2952                 }
2953         } else {
2954                 if (ar8xxx_has_gige(priv)) {
2955                         phydev->supported |= SUPPORTED_1000baseT_Full;
2956                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2957                 }
2958         }
2959
2960         phydev->priv = priv;
2961
2962         list_add(&priv->list, &ar8xxx_dev_list);
2963
2964         mutex_unlock(&ar8xxx_dev_list_lock);
2965
2966         return 0;
2967
2968 err_unregister_switch:
2969         if (--priv->use_count)
2970                 goto unlock;
2971
2972         unregister_switch(&priv->dev);
2973
2974 free_priv:
2975         ar8xxx_free(priv);
2976 unlock:
2977         mutex_unlock(&ar8xxx_dev_list_lock);
2978         return ret;
2979 }
2980
2981 static void
2982 ar8xxx_phy_detach(struct phy_device *phydev)
2983 {
2984         struct net_device *dev = phydev->attached_dev;
2985
2986         if (!dev)
2987                 return;
2988
2989         dev->phy_ptr = NULL;
2990         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2991         dev->eth_mangle_rx = NULL;
2992         dev->eth_mangle_tx = NULL;
2993 }
2994
2995 static void
2996 ar8xxx_phy_remove(struct phy_device *phydev)
2997 {
2998         struct ar8xxx_priv *priv = phydev->priv;
2999
3000         if (WARN_ON(!priv))
3001                 return;
3002
3003         phydev->priv = NULL;
3004         if (--priv->use_count > 0)
3005                 return;
3006
3007         mutex_lock(&ar8xxx_dev_list_lock);
3008         list_del(&priv->list);
3009         mutex_unlock(&ar8xxx_dev_list_lock);
3010
3011         unregister_switch(&priv->dev);
3012         ar8xxx_mib_stop(priv);
3013         ar8xxx_free(priv);
3014 }
3015
3016 static struct phy_driver ar8xxx_phy_driver = {
3017         .phy_id         = 0x004d0000,
3018         .name           = "Atheros AR8216/AR8236/AR8316",
3019         .phy_id_mask    = 0xffff0000,
3020         .features       = PHY_BASIC_FEATURES,
3021         .probe          = ar8xxx_phy_probe,
3022         .remove         = ar8xxx_phy_remove,
3023         .detach         = ar8xxx_phy_detach,
3024         .config_init    = ar8xxx_phy_config_init,
3025         .config_aneg    = ar8xxx_phy_config_aneg,
3026         .read_status    = ar8xxx_phy_read_status,
3027         .driver         = { .owner = THIS_MODULE },
3028 };
3029
3030 int __init
3031 ar8xxx_init(void)
3032 {
3033         return phy_driver_register(&ar8xxx_phy_driver);
3034 }
3035
3036 void __exit
3037 ar8xxx_exit(void)
3038 {
3039         phy_driver_unregister(&ar8xxx_phy_driver);
3040 }
3041
3042 module_init(ar8xxx_init);
3043 module_exit(ar8xxx_exit);
3044 MODULE_LICENSE("GPL");
3045