target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39 #include <linux/version.h>
  40
  41 #include "ar8216.h"
  42
  43 /* size of the vlan table */
  44 #define AR8X16_MAX_VLANS        128
  45 #define AR8X16_PROBE_RETRIES    10
  46 #define AR8X16_MAX_PORTS        8
  47
  48 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  49
  50 struct ar8xxx_priv;
  51
  52 #define AR8XXX_CAP_GIGE                 BIT(0)
  53 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  54
  55 #define AR8XXX_NUM_PHYS         5
  56
  57 static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
  58 static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
  59
  60 enum {
  61         AR8XXX_VER_AR8216 = 0x01,
  62         AR8XXX_VER_AR8236 = 0x03,
  63         AR8XXX_VER_AR8316 = 0x10,
  64         AR8XXX_VER_AR8327 = 0x12,
  65         AR8XXX_VER_AR8337 = 0x13,
  66 };
  67
  68 struct ar8xxx_mib_desc {
  69         unsigned int size;
  70         unsigned int offset;
  71         const char *name;
  72 };
  73
  74 struct ar8xxx_chip {
  75         unsigned long caps;
  76         bool config_at_probe;
  77         bool mii_lo_first;
  78
  79         /* parameters to calculate REG_PORT_STATS_BASE */
  80         unsigned reg_port_stats_start;
  81         unsigned reg_port_stats_length;
  82
  83         int (*hw_init)(struct ar8xxx_priv *priv);
  84         void (*cleanup)(struct ar8xxx_priv *priv);
  85
  86         void (*init_globals)(struct ar8xxx_priv *priv);
  87         void (*init_port)(struct ar8xxx_priv *priv, int port);
  88         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  89         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  90         int (*atu_flush)(struct ar8xxx_priv *priv);
  91         void (*vtu_flush)(struct ar8xxx_priv *priv);
  92         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  93         void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
  94         void (*set_mirror_regs)(struct ar8xxx_priv *priv);
  95
  96         const struct ar8xxx_mib_desc *mib_decs;
  97         unsigned num_mibs;
  98         unsigned mib_func;
  99 };
 100
 101 enum ar8327_led_pattern {
 102         AR8327_LED_PATTERN_OFF = 0,
 103         AR8327_LED_PATTERN_BLINK,
 104         AR8327_LED_PATTERN_ON,
 105         AR8327_LED_PATTERN_RULE,
 106 };
 107
 108 struct ar8327_led_entry {
 109         unsigned reg;
 110         unsigned shift;
 111 };
 112
 113 struct ar8327_led {
 114         struct led_classdev cdev;
 115         struct ar8xxx_priv *sw_priv;
 116
 117         char *name;
 118         bool active_low;
 119         u8 led_num;
 120         enum ar8327_led_mode mode;
 121
 122         struct mutex mutex;
 123         spinlock_t lock;
 124         struct work_struct led_work;
 125         bool enable_hw_mode;
 126         enum ar8327_led_pattern pattern;
 127 };
 128
 129 struct ar8327_data {
 130         u32 port0_status;
 131         u32 port6_status;
 132
 133         struct ar8327_led **leds;
 134         unsigned int num_leds;
 135 };
 136
 137 struct ar8xxx_priv {
 138         struct switch_dev dev;
 139         struct mii_bus *mii_bus;
 140         struct phy_device *phy;
 141
 142         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 143         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 144         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 145
 146         int (*get_port_link)(unsigned port);
 147
 148         const struct net_device_ops *ndo_old;
 149         struct net_device_ops ndo;
 150         struct mutex reg_mutex;
 151         u8 chip_ver;
 152         u8 chip_rev;
 153         const struct ar8xxx_chip *chip;
 154         void *chip_data;
 155         bool initialized;
 156         bool port4_phy;
 157         char buf[2048];
 158
 159         bool init;
 160
 161         struct mutex mib_lock;
 162         struct delayed_work mib_work;
 163         int mib_next_port;
 164         u64 *mib_stats;
 165
 166         struct list_head list;
 167         unsigned int use_count;
 168
 169         /* all fields below are cleared on reset */
 170         bool vlan;
 171         u16 vlan_id[AR8X16_MAX_VLANS];
 172         u8 vlan_table[AR8X16_MAX_VLANS];
 173         u8 vlan_tagged;
 174         u16 pvid[AR8X16_MAX_PORTS];
 175
 176         /* mirroring */
 177         bool mirror_rx;
 178         bool mirror_tx;
 179         int source_port;
 180         int monitor_port;
 181 };
 182
 183 #define MIB_DESC(_s , _o, _n)   \
 184         {                       \
 185                 .size = (_s),   \
 186                 .offset = (_o), \
 187                 .name = (_n),   \
 188         }
 189
 190 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 191         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 192         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 193         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 194         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 195         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 196         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 197         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 198         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 199         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 200         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 201         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 202         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 203         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 204         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 205         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 206         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 207         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 208         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 209         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 210         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 211         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 212         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 213         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 214         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 215         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 216         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 217         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 218         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 219         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 220         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 221         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 222         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 223         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 224         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 225         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 226         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 227         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 228 };
 229
 230 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 231         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 232         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 233         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 234         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 235         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 236         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 237         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 238         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 239         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 240         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 241         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 242         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 243         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 244         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 245         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 246         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 247         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 248         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 249         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 250         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 251         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 252         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 253         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 254         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 255         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 256         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 257         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 258         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 259         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 260         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 261         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 262         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 263         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 264         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 265         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 266         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 267         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 268         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 269         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 270 };
 271
 272 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 273 static LIST_HEAD(ar8xxx_dev_list);
 274
 275 static inline struct ar8xxx_priv *
 276 swdev_to_ar8xxx(struct switch_dev *swdev)
 277 {
 278         return container_of(swdev, struct ar8xxx_priv, dev);
 279 }
 280
 281 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 282 {
 283         return priv->chip->caps & AR8XXX_CAP_GIGE;
 284 }
 285
 286 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 287 {
 288         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 289 }
 290
 291 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 292 {
 293         return priv->chip_ver == AR8XXX_VER_AR8216;
 294 }
 295
 296 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 297 {
 298         return priv->chip_ver == AR8XXX_VER_AR8236;
 299 }
 300
 301 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 302 {
 303         return priv->chip_ver == AR8XXX_VER_AR8316;
 304 }
 305
 306 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 307 {
 308         return priv->chip_ver == AR8XXX_VER_AR8327;
 309 }
 310
 311 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 312 {
 313         return priv->chip_ver == AR8XXX_VER_AR8337;
 314 }
 315
 316 static inline void
 317 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 318 {
 319         regaddr >>= 1;
 320         *r1 = regaddr & 0x1e;
 321
 322         regaddr >>= 5;
 323         *r2 = regaddr & 0x7;
 324
 325         regaddr >>= 3;
 326         *page = regaddr & 0x1ff;
 327 }
 328
 329 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 330 static int
 331 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 332 {
 333         unsigned int sleep_msecs = 20;
 334         int ret, elapsed, i;
 335
 336         for (elapsed = sleep_msecs; elapsed <= 600;
 337              elapsed += sleep_msecs) {
 338                 msleep(sleep_msecs);
 339                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 340                         ret = mdiobus_read(bus, i, MII_BMCR);
 341                         if (ret < 0)
 342                                 return ret;
 343                         if (ret & BMCR_RESET)
 344                                 break;
 345                         if (i == AR8XXX_NUM_PHYS - 1) {
 346                                 usleep_range(1000, 2000);
 347                                 return 0;
 348                         }
 349                 }
 350         }
 351         return -ETIMEDOUT;
 352 }
 353
 354 static int
 355 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 356 {
 357         int ret;
 358
 359         if (phydev->autoneg != AUTONEG_ENABLE)
 360                 return 0;
 361         /*
 362          * BMCR_ANENABLE might have been cleared
 363          * by phy_init_hw in certain kernel versions
 364          * therefore check for it
 365          */
 366         ret = phy_read(phydev, MII_BMCR);
 367         if (ret < 0)
 368                 return ret;
 369         if (ret & BMCR_ANENABLE)
 370                 return 0;
 371
 372         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 373         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 374         return phy_write(phydev, MII_BMCR, ret);
 375 }
 376
 377 static void
 378 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 379 {
 380         int i;
 381         struct mii_bus *bus;
 382
 383         bus = priv->mii_bus;
 384         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 385                 if (priv->chip->phy_fixup)
 386                         priv->chip->phy_fixup(priv, i);
 387
 388                 /* initialize the port itself */
 389                 mdiobus_write(bus, i, MII_ADVERTISE,
 390                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 391                 if (ar8xxx_has_gige(priv))
 392                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 393                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 394         }
 395
 396         ar8xxx_phy_poll_reset(bus);
 397 }
 398
 399 static u32
 400 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 401 {
 402         struct mii_bus *bus = priv->mii_bus;
 403         u16 r1, r2, page;
 404         u16 lo, hi;
 405
 406         split_addr((u32) reg, &r1, &r2, &page);
 407
 408         mutex_lock(&bus->mdio_lock);
 409
 410         bus->write(bus, 0x18, 0, page);
 411         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 412         lo = bus->read(bus, 0x10 | r2, r1);
 413         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 414
 415         mutex_unlock(&bus->mdio_lock);
 416
 417         return (hi << 16) | lo;
 418 }
 419
 420 static void
 421 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 422 {
 423         struct mii_bus *bus = priv->mii_bus;
 424         u16 r1, r2, r3;
 425         u16 lo, hi;
 426
 427         split_addr((u32) reg, &r1, &r2, &r3);
 428         lo = val & 0xffff;
 429         hi = (u16) (val >> 16);
 430
 431         mutex_lock(&bus->mdio_lock);
 432
 433         bus->write(bus, 0x18, 0, r3);
 434         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 435         if (priv->chip->mii_lo_first) {
 436                 bus->write(bus, 0x10 | r2, r1, lo);
 437                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 438         } else {
 439                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 440                 bus->write(bus, 0x10 | r2, r1, lo);
 441         }
 442
 443         mutex_unlock(&bus->mdio_lock);
 444 }
 445
 446 static u32
 447 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 448 {
 449         struct mii_bus *bus = priv->mii_bus;
 450         u16 r1, r2, page;
 451         u16 lo, hi;
 452         u32 ret;
 453
 454         split_addr((u32) reg, &r1, &r2, &page);
 455
 456         mutex_lock(&bus->mdio_lock);
 457
 458         bus->write(bus, 0x18, 0, page);
 459         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 460
 461         lo = bus->read(bus, 0x10 | r2, r1);
 462         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 463
 464         ret = hi << 16 | lo;
 465         ret &= ~mask;
 466         ret |= val;
 467
 468         lo = ret & 0xffff;
 469         hi = (u16) (ret >> 16);
 470
 471         if (priv->chip->mii_lo_first) {
 472                 bus->write(bus, 0x10 | r2, r1, lo);
 473                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 474         } else {
 475                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 476                 bus->write(bus, 0x10 | r2, r1, lo);
 477         }
 478
 479         mutex_unlock(&bus->mdio_lock);
 480
 481         return ret;
 482 }
 483
 484
 485 static void
 486 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 487                      u16 dbg_addr, u16 dbg_data)
 488 {
 489         struct mii_bus *bus = priv->mii_bus;
 490
 491         mutex_lock(&bus->mdio_lock);
 492         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 493         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 494         mutex_unlock(&bus->mdio_lock);
 495 }
 496
 497 static void
 498 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 499 {
 500         struct mii_bus *bus = priv->mii_bus;
 501
 502         mutex_lock(&bus->mdio_lock);
 503         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 504         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 505         mutex_unlock(&bus->mdio_lock);
 506 }
 507
 508 static inline u32
 509 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 510 {
 511         return priv->rmw(priv, reg, mask, val);
 512 }
 513
 514 static inline void
 515 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 516 {
 517         priv->rmw(priv, reg, 0, val);
 518 }
 519
 520 static int
 521 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 522                 unsigned timeout)
 523 {
 524         int i;
 525
 526         for (i = 0; i < timeout; i++) {
 527                 u32 t;
 528
 529                 t = priv->read(priv, reg);
 530                 if ((t & mask) == val)
 531                         return 0;
 532
 533                 usleep_range(1000, 2000);
 534         }
 535
 536         return -ETIMEDOUT;
 537 }
 538
 539 static int
 540 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 541 {
 542         unsigned mib_func = priv->chip->mib_func;
 543         int ret;
 544
 545         lockdep_assert_held(&priv->mib_lock);
 546
 547         /* Capture the hardware statistics for all ports */
 548         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 549
 550         /* Wait for the capturing to complete. */
 551         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 552         if (ret)
 553                 goto out;
 554
 555         ret = 0;
 556
 557 out:
 558         return ret;
 559 }
 560
 561 static int
 562 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 563 {
 564         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 565 }
 566
 567 static int
 568 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 569 {
 570         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 571 }
 572
 573 static void
 574 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 575 {
 576         unsigned int base;
 577         u64 *mib_stats;
 578         int i;
 579
 580         WARN_ON(port >= priv->dev.ports);
 581
 582         lockdep_assert_held(&priv->mib_lock);
 583
 584         base = priv->chip->reg_port_stats_start +
 585                priv->chip->reg_port_stats_length * port;
 586
 587         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 588         for (i = 0; i < priv->chip->num_mibs; i++) {
 589                 const struct ar8xxx_mib_desc *mib;
 590                 u64 t;
 591
 592                 mib = &priv->chip->mib_decs[i];
 593                 t = priv->read(priv, base + mib->offset);
 594                 if (mib->size == 2) {
 595                         u64 hi;
 596
 597                         hi = priv->read(priv, base + mib->offset + 4);
 598                         t |= hi << 32;
 599                 }
 600
 601                 if (flush)
 602                         mib_stats[i] = 0;
 603                 else
 604                         mib_stats[i] += t;
 605         }
 606 }
 607
 608 static void
 609 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 610                       struct switch_port_link *link)
 611 {
 612         u32 status;
 613         u32 speed;
 614
 615         memset(link, '\0', sizeof(*link));
 616
 617         status = priv->chip->read_port_status(priv, port);
 618
 619         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 620         if (link->aneg) {
 621                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 622         } else {
 623                 link->link = true;
 624
 625                 if (priv->get_port_link) {
 626                         int err;
 627
 628                         err = priv->get_port_link(port);
 629                         if (err >= 0)
 630                                 link->link = !!err;
 631                 }
 632         }
 633
 634         if (!link->link)
 635                 return;
 636
 637         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 638         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 639         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 640
 641         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 642                  AR8216_PORT_STATUS_SPEED_S;
 643
 644         switch (speed) {
 645         case AR8216_PORT_SPEED_10M:
 646                 link->speed = SWITCH_PORT_SPEED_10;
 647                 break;
 648         case AR8216_PORT_SPEED_100M:
 649                 link->speed = SWITCH_PORT_SPEED_100;
 650                 break;
 651         case AR8216_PORT_SPEED_1000M:
 652                 link->speed = SWITCH_PORT_SPEED_1000;
 653                 break;
 654         default:
 655                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 656                 break;
 657         }
 658 }
 659
 660 static struct sk_buff *
 661 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 662 {
 663         struct ar8xxx_priv *priv = dev->phy_ptr;
 664         unsigned char *buf;
 665
 666         if (unlikely(!priv))
 667                 goto error;
 668
 669         if (!priv->vlan)
 670                 goto send;
 671
 672         if (unlikely(skb_headroom(skb) < 2)) {
 673                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 674                         goto error;
 675         }
 676
 677         buf = skb_push(skb, 2);
 678         buf[0] = 0x10;
 679         buf[1] = 0x80;
 680
 681 send:
 682         return skb;
 683
 684 error:
 685         dev_kfree_skb_any(skb);
 686         return NULL;
 687 }
 688
 689 static void
 690 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 691 {
 692         struct ar8xxx_priv *priv;
 693         unsigned char *buf;
 694         int port, vlan;
 695
 696         priv = dev->phy_ptr;
 697         if (!priv)
 698                 return;
 699
 700         /* don't strip the header if vlan mode is disabled */
 701         if (!priv->vlan)
 702                 return;
 703
 704         /* strip header, get vlan id */
 705         buf = skb->data;
 706         skb_pull(skb, 2);
 707
 708         /* check for vlan header presence */
 709         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 710                 return;
 711
 712         port = buf[0] & 0xf;
 713
 714         /* no need to fix up packets coming from a tagged source */
 715         if (priv->vlan_tagged & (1 << port))
 716                 return;
 717
 718         /* lookup port vid from local table, the switch passes an invalid vlan id */
 719         vlan = priv->vlan_id[priv->pvid[port]];
 720
 721         buf[14 + 2] &= 0xf0;
 722         buf[14 + 2] |= vlan >> 8;
 723         buf[15 + 2] = vlan & 0xff;
 724 }
 725
 726 static int
 727 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 728 {
 729         int timeout = 20;
 730         u32 t = 0;
 731
 732         while (1) {
 733                 t = priv->read(priv, reg);
 734                 if ((t & mask) == val)
 735                         return 0;
 736
 737                 if (timeout-- <= 0)
 738                         break;
 739
 740                 udelay(10);
 741         }
 742
 743         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 744                (unsigned int) reg, t, mask, val);
 745         return -ETIMEDOUT;
 746 }
 747
 748 static void
 749 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 750 {
 751         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 752                 return;
 753         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 754                 val &= AR8216_VTUDATA_MEMBER;
 755                 val |= AR8216_VTUDATA_VALID;
 756                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 757         }
 758         op |= AR8216_VTU_ACTIVE;
 759         priv->write(priv, AR8216_REG_VTU, op);
 760 }
 761
 762 static void
 763 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 764 {
 765         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 766 }
 767
 768 static void
 769 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 770 {
 771         u32 op;
 772
 773         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 774         ar8216_vtu_op(priv, op, port_mask);
 775 }
 776
 777 static int
 778 ar8216_atu_flush(struct ar8xxx_priv *priv)
 779 {
 780         int ret;
 781
 782         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 783         if (!ret)
 784                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 785
 786         return ret;
 787 }
 788
 789 static u32
 790 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 791 {
 792         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 793 }
 794
 795 static void
 796 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 797 {
 798         u32 header;
 799         u32 egress, ingress;
 800         u32 pvid;
 801
 802         if (priv->vlan) {
 803                 pvid = priv->vlan_id[priv->pvid[port]];
 804                 if (priv->vlan_tagged & (1 << port))
 805                         egress = AR8216_OUT_ADD_VLAN;
 806                 else
 807                         egress = AR8216_OUT_STRIP_VLAN;
 808                 ingress = AR8216_IN_SECURE;
 809         } else {
 810                 pvid = port;
 811                 egress = AR8216_OUT_KEEP;
 812                 ingress = AR8216_IN_PORT_ONLY;
 813         }
 814
 815         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 816                 header = AR8216_PORT_CTRL_HEADER;
 817         else
 818                 header = 0;
 819
 820         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 821                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 822                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 823                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 824                    AR8216_PORT_CTRL_LEARN | header |
 825                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 826                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 827
 828         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 829                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 830                    AR8216_PORT_VLAN_DEFAULT_ID,
 831                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 832                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 833                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 834 }
 835
 836 static int
 837 ar8216_hw_init(struct ar8xxx_priv *priv)
 838 {
 839         if (priv->initialized)
 840                 return 0;
 841
 842         ar8xxx_phy_init(priv);
 843
 844         priv->initialized = true;
 845         return 0;
 846 }
 847
 848 static void
 849 ar8216_init_globals(struct ar8xxx_priv *priv)
 850 {
 851         /* standard atheros magic */
 852         priv->write(priv, 0x38, 0xc000050e);
 853
 854         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 855                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 856 }
 857
 858 static void
 859 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 860 {
 861         /* Enable port learning and tx */
 862         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 863                 AR8216_PORT_CTRL_LEARN |
 864                 (4 << AR8216_PORT_CTRL_STATE_S));
 865
 866         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 867
 868         if (port == AR8216_PORT_CPU) {
 869                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 870                         AR8216_PORT_STATUS_LINK_UP |
 871                         (ar8xxx_has_gige(priv) ?
 872                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 873                         AR8216_PORT_STATUS_TXMAC |
 874                         AR8216_PORT_STATUS_RXMAC |
 875                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 876                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 877                         AR8216_PORT_STATUS_DUPLEX);
 878         } else {
 879                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 880                         AR8216_PORT_STATUS_LINK_AUTO);
 881         }
 882 }
 883
 884 static const struct ar8xxx_chip ar8216_chip = {
 885         .caps = AR8XXX_CAP_MIB_COUNTERS,
 886
 887         .reg_port_stats_start = 0x19000,
 888         .reg_port_stats_length = 0xa0,
 889
 890         .hw_init = ar8216_hw_init,
 891         .init_globals = ar8216_init_globals,
 892         .init_port = ar8216_init_port,
 893         .setup_port = ar8216_setup_port,
 894         .read_port_status = ar8216_read_port_status,
 895         .atu_flush = ar8216_atu_flush,
 896         .vtu_flush = ar8216_vtu_flush,
 897         .vtu_load_vlan = ar8216_vtu_load_vlan,
 898         .set_mirror_regs = ar8216_set_mirror_regs,
 899
 900         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 901         .mib_decs = ar8216_mibs,
 902         .mib_func = AR8216_REG_MIB_FUNC
 903 };
 904
 905 static void
 906 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 907 {
 908         u32 egress, ingress;
 909         u32 pvid;
 910
 911         if (priv->vlan) {
 912                 pvid = priv->vlan_id[priv->pvid[port]];
 913                 if (priv->vlan_tagged & (1 << port))
 914                         egress = AR8216_OUT_ADD_VLAN;
 915                 else
 916                         egress = AR8216_OUT_STRIP_VLAN;
 917                 ingress = AR8216_IN_SECURE;
 918         } else {
 919                 pvid = port;
 920                 egress = AR8216_OUT_KEEP;
 921                 ingress = AR8216_IN_PORT_ONLY;
 922         }
 923
 924         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 925                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 926                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 927                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 928                    AR8216_PORT_CTRL_LEARN |
 929                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 930                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 931
 932         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 933                    AR8236_PORT_VLAN_DEFAULT_ID,
 934                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 935
 936         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 937                    AR8236_PORT_VLAN2_VLAN_MODE |
 938                    AR8236_PORT_VLAN2_MEMBER,
 939                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 940                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 941 }
 942
 943 static void
 944 ar8236_init_globals(struct ar8xxx_priv *priv)
 945 {
 946         /* enable jumbo frames */
 947         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 948                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 949
 950         /* enable cpu port to receive arp frames */
 951         ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
 952                    AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
 953
 954         /* enable cpu port to receive multicast and broadcast frames */
 955         ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
 956                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
 957                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 958
 959         /* Enable MIB counters */
 960         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 961                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 962                    AR8236_MIB_EN);
 963 }
 964
 965 static const struct ar8xxx_chip ar8236_chip = {
 966         .caps = AR8XXX_CAP_MIB_COUNTERS,
 967
 968         .reg_port_stats_start = 0x20000,
 969         .reg_port_stats_length = 0x100,
 970
 971         .hw_init = ar8216_hw_init,
 972         .init_globals = ar8236_init_globals,
 973         .init_port = ar8216_init_port,
 974         .setup_port = ar8236_setup_port,
 975         .read_port_status = ar8216_read_port_status,
 976         .atu_flush = ar8216_atu_flush,
 977         .vtu_flush = ar8216_vtu_flush,
 978         .vtu_load_vlan = ar8216_vtu_load_vlan,
 979         .set_mirror_regs = ar8216_set_mirror_regs,
 980
 981         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 982         .mib_decs = ar8236_mibs,
 983         .mib_func = AR8216_REG_MIB_FUNC
 984 };
 985
 986 static int
 987 ar8316_hw_init(struct ar8xxx_priv *priv)
 988 {
 989         u32 val, newval;
 990
 991         val = priv->read(priv, AR8316_REG_POSTRIP);
 992
 993         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 994                 if (priv->port4_phy) {
 995                         /* value taken from Ubiquiti RouterStation Pro */
 996                         newval = 0x81461bea;
 997                         pr_info("ar8316: Using port 4 as PHY\n");
 998                 } else {
 999                         newval = 0x01261be2;
1000                         pr_info("ar8316: Using port 4 as switch port\n");
1001                 }
1002         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1003                 /* value taken from AVM Fritz!Box 7390 sources */
1004                 newval = 0x010e5b71;
1005         } else {
1006                 /* no known value for phy interface */
1007                 pr_err("ar8316: unsupported mii mode: %d.\n",
1008                        priv->phy->interface);
1009                 return -EINVAL;
1010         }
1011
1012         if (val == newval)
1013                 goto out;
1014
1015         priv->write(priv, AR8316_REG_POSTRIP, newval);
1016
1017         if (priv->port4_phy &&
1018             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1019                 /* work around for phy4 rgmii mode */
1020                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1021                 /* rx delay */
1022                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1023                 /* tx delay */
1024                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1025                 msleep(1000);
1026         }
1027
1028         ar8xxx_phy_init(priv);
1029
1030 out:
1031         priv->initialized = true;
1032         return 0;
1033 }
1034
1035 static void
1036 ar8316_init_globals(struct ar8xxx_priv *priv)
1037 {
1038         /* standard atheros magic */
1039         priv->write(priv, 0x38, 0xc000050e);
1040
1041         /* enable cpu port to receive multicast and broadcast frames */
1042         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1043
1044         /* enable jumbo frames */
1045         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1046                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
1047
1048         /* Enable MIB counters */
1049         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1050                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1051                    AR8236_MIB_EN);
1052 }
1053
1054 static const struct ar8xxx_chip ar8316_chip = {
1055         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1056
1057         .reg_port_stats_start = 0x20000,
1058         .reg_port_stats_length = 0x100,
1059
1060         .hw_init = ar8316_hw_init,
1061         .init_globals = ar8316_init_globals,
1062         .init_port = ar8216_init_port,
1063         .setup_port = ar8216_setup_port,
1064         .read_port_status = ar8216_read_port_status,
1065         .atu_flush = ar8216_atu_flush,
1066         .vtu_flush = ar8216_vtu_flush,
1067         .vtu_load_vlan = ar8216_vtu_load_vlan,
1068         .set_mirror_regs = ar8216_set_mirror_regs,
1069
1070         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1071         .mib_decs = ar8236_mibs,
1072         .mib_func = AR8216_REG_MIB_FUNC
1073 };
1074
1075 static u32
1076 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1077 {
1078         u32 t;
1079
1080         if (!cfg)
1081                 return 0;
1082
1083         t = 0;
1084         switch (cfg->mode) {
1085         case AR8327_PAD_NC:
1086                 break;
1087
1088         case AR8327_PAD_MAC2MAC_MII:
1089                 t = AR8327_PAD_MAC_MII_EN;
1090                 if (cfg->rxclk_sel)
1091                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1092                 if (cfg->txclk_sel)
1093                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1094                 break;
1095
1096         case AR8327_PAD_MAC2MAC_GMII:
1097                 t = AR8327_PAD_MAC_GMII_EN;
1098                 if (cfg->rxclk_sel)
1099                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1100                 if (cfg->txclk_sel)
1101                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1102                 break;
1103
1104         case AR8327_PAD_MAC_SGMII:
1105                 t = AR8327_PAD_SGMII_EN;
1106
1107                 /*
1108                  * WAR for the QUalcomm Atheros AP136 board.
1109                  * It seems that RGMII TX/RX delay settings needs to be
1110                  * applied for SGMII mode as well, The ethernet is not
1111                  * reliable without this.
1112                  */
1113                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1114                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1115                 if (cfg->rxclk_delay_en)
1116                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1117                 if (cfg->txclk_delay_en)
1118                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1119
1120                 if (cfg->sgmii_delay_en)
1121                         t |= AR8327_PAD_SGMII_DELAY_EN;
1122
1123                 break;
1124
1125         case AR8327_PAD_MAC2PHY_MII:
1126                 t = AR8327_PAD_PHY_MII_EN;
1127                 if (cfg->rxclk_sel)
1128                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1129                 if (cfg->txclk_sel)
1130                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1131                 break;
1132
1133         case AR8327_PAD_MAC2PHY_GMII:
1134                 t = AR8327_PAD_PHY_GMII_EN;
1135                 if (cfg->pipe_rxclk_sel)
1136                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1137                 if (cfg->rxclk_sel)
1138                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1139                 if (cfg->txclk_sel)
1140                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1141                 break;
1142
1143         case AR8327_PAD_MAC_RGMII:
1144                 t = AR8327_PAD_RGMII_EN;
1145                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1146                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1147                 if (cfg->rxclk_delay_en)
1148                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1149                 if (cfg->txclk_delay_en)
1150                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1151                 break;
1152
1153         case AR8327_PAD_PHY_GMII:
1154                 t = AR8327_PAD_PHYX_GMII_EN;
1155                 break;
1156
1157         case AR8327_PAD_PHY_RGMII:
1158                 t = AR8327_PAD_PHYX_RGMII_EN;
1159                 break;
1160
1161         case AR8327_PAD_PHY_MII:
1162                 t = AR8327_PAD_PHYX_MII_EN;
1163                 break;
1164         }
1165
1166         return t;
1167 }
1168
1169 static void
1170 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1171 {
1172         switch (priv->chip_rev) {
1173         case 1:
1174                 /* For 100M waveform */
1175                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1176                 /* Turn on Gigabit clock */
1177                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1178                 break;
1179
1180         case 2:
1181                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1182                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1183                 /* fallthrough */
1184         case 4:
1185                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1186                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1187
1188                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1189                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1190                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1191                 break;
1192         }
1193 }
1194
1195 static u32
1196 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1197 {
1198         u32 t;
1199
1200         if (!cfg->force_link)
1201                 return AR8216_PORT_STATUS_LINK_AUTO;
1202
1203         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1204         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1205         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1206         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1207
1208         switch (cfg->speed) {
1209         case AR8327_PORT_SPEED_10:
1210                 t |= AR8216_PORT_SPEED_10M;
1211                 break;
1212         case AR8327_PORT_SPEED_100:
1213                 t |= AR8216_PORT_SPEED_100M;
1214                 break;
1215         case AR8327_PORT_SPEED_1000:
1216                 t |= AR8216_PORT_SPEED_1000M;
1217                 break;
1218         }
1219
1220         return t;
1221 }
1222
1223 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1224         [_num] = { .reg = (_reg), .shift = (_shift) }
1225
1226 static const struct ar8327_led_entry
1227 ar8327_led_map[AR8327_NUM_LEDS] = {
1228         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1229         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1230         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1231
1232         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1233         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1234         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1235
1236         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1237         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1238         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1239
1240         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1241         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1242         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1243
1244         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1245         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1246         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1247 };
1248
1249 static void
1250 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1251                        enum ar8327_led_pattern pattern)
1252 {
1253         const struct ar8327_led_entry *entry;
1254
1255         entry = &ar8327_led_map[led_num];
1256         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1257                    (3 << entry->shift), pattern << entry->shift);
1258 }
1259
1260 static void
1261 ar8327_led_work_func(struct work_struct *work)
1262 {
1263         struct ar8327_led *aled;
1264         u8 pattern;
1265
1266         aled = container_of(work, struct ar8327_led, led_work);
1267
1268         spin_lock(&aled->lock);
1269         pattern = aled->pattern;
1270         spin_unlock(&aled->lock);
1271
1272         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1273                                pattern);
1274 }
1275
1276 static void
1277 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1278 {
1279         if (aled->pattern == pattern)
1280                 return;
1281
1282         aled->pattern = pattern;
1283         schedule_work(&aled->led_work);
1284 }
1285
1286 static inline struct ar8327_led *
1287 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1288 {
1289         return container_of(led_cdev, struct ar8327_led, cdev);
1290 }
1291
1292 static int
1293 ar8327_led_blink_set(struct led_classdev *led_cdev,
1294                      unsigned long *delay_on,
1295                      unsigned long *delay_off)
1296 {
1297         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1298
1299         if (*delay_on == 0 && *delay_off == 0) {
1300                 *delay_on = 125;
1301                 *delay_off = 125;
1302         }
1303
1304         if (*delay_on != 125 || *delay_off != 125) {
1305                 /*
1306                  * The hardware only supports blinking at 4Hz. Fall back
1307                  * to software implementation in other cases.
1308                  */
1309                 return -EINVAL;
1310         }
1311
1312         spin_lock(&aled->lock);
1313
1314         aled->enable_hw_mode = false;
1315         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1316
1317         spin_unlock(&aled->lock);
1318
1319         return 0;
1320 }
1321
1322 static void
1323 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1324                           enum led_brightness brightness)
1325 {
1326         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1327         u8 pattern;
1328         bool active;
1329
1330         active = (brightness != LED_OFF);
1331         active ^= aled->active_low;
1332
1333         pattern = (active) ? AR8327_LED_PATTERN_ON :
1334                              AR8327_LED_PATTERN_OFF;
1335
1336         spin_lock(&aled->lock);
1337
1338         aled->enable_hw_mode = false;
1339         ar8327_led_schedule_change(aled, pattern);
1340
1341         spin_unlock(&aled->lock);
1342 }
1343
1344 static ssize_t
1345 ar8327_led_enable_hw_mode_show(struct device *dev,
1346                                struct device_attribute *attr,
1347                                char *buf)
1348 {
1349         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1350         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1351         ssize_t ret = 0;
1352
1353         spin_lock(&aled->lock);
1354         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1355         spin_unlock(&aled->lock);
1356
1357         return ret;
1358 }
1359
1360 static ssize_t
1361 ar8327_led_enable_hw_mode_store(struct device *dev,
1362                                 struct device_attribute *attr,
1363                                 const char *buf,
1364                                 size_t size)
1365 {
1366         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1367         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1368         u8 pattern;
1369         u8 value;
1370         int ret;
1371
1372         ret = kstrtou8(buf, 10, &value);
1373         if (ret < 0)
1374                 return -EINVAL;
1375
1376         spin_lock(&aled->lock);
1377
1378         aled->enable_hw_mode = !!value;
1379         if (aled->enable_hw_mode)
1380                 pattern = AR8327_LED_PATTERN_RULE;
1381         else
1382                 pattern = AR8327_LED_PATTERN_OFF;
1383
1384         ar8327_led_schedule_change(aled, pattern);
1385
1386         spin_unlock(&aled->lock);
1387
1388         return size;
1389 }
1390
1391 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1392                    ar8327_led_enable_hw_mode_show,
1393                    ar8327_led_enable_hw_mode_store);
1394
1395 static int
1396 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1397 {
1398         int ret;
1399
1400         ret = led_classdev_register(NULL, &aled->cdev);
1401         if (ret < 0)
1402                 return ret;
1403
1404         if (aled->mode == AR8327_LED_MODE_HW) {
1405                 ret = device_create_file(aled->cdev.dev,
1406                                          &dev_attr_enable_hw_mode);
1407                 if (ret)
1408                         goto err_unregister;
1409         }
1410
1411         return 0;
1412
1413 err_unregister:
1414         led_classdev_unregister(&aled->cdev);
1415         return ret;
1416 }
1417
1418 static void
1419 ar8327_led_unregister(struct ar8327_led *aled)
1420 {
1421         if (aled->mode == AR8327_LED_MODE_HW)
1422                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1423
1424         led_classdev_unregister(&aled->cdev);
1425         cancel_work_sync(&aled->led_work);
1426 }
1427
1428 static int
1429 ar8327_led_create(struct ar8xxx_priv *priv,
1430                   const struct ar8327_led_info *led_info)
1431 {
1432         struct ar8327_data *data = priv->chip_data;
1433         struct ar8327_led *aled;
1434         int ret;
1435
1436         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1437                 return 0;
1438
1439         if (!led_info->name)
1440                 return -EINVAL;
1441
1442         if (led_info->led_num >= AR8327_NUM_LEDS)
1443                 return -EINVAL;
1444
1445         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1446                        GFP_KERNEL);
1447         if (!aled)
1448                 return -ENOMEM;
1449
1450         aled->sw_priv = priv;
1451         aled->led_num = led_info->led_num;
1452         aled->active_low = led_info->active_low;
1453         aled->mode = led_info->mode;
1454
1455         if (aled->mode == AR8327_LED_MODE_HW)
1456                 aled->enable_hw_mode = true;
1457
1458         aled->name = (char *)(aled + 1);
1459         strcpy(aled->name, led_info->name);
1460
1461         aled->cdev.name = aled->name;
1462         aled->cdev.brightness_set = ar8327_led_set_brightness;
1463         aled->cdev.blink_set = ar8327_led_blink_set;
1464         aled->cdev.default_trigger = led_info->default_trigger;
1465
1466         spin_lock_init(&aled->lock);
1467         mutex_init(&aled->mutex);
1468         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1469
1470         ret = ar8327_led_register(priv, aled);
1471         if (ret)
1472                 goto err_free;
1473
1474         data->leds[data->num_leds++] = aled;
1475
1476         return 0;
1477
1478 err_free:
1479         kfree(aled);
1480         return ret;
1481 }
1482
1483 static void
1484 ar8327_led_destroy(struct ar8327_led *aled)
1485 {
1486         ar8327_led_unregister(aled);
1487         kfree(aled);
1488 }
1489
1490 static void
1491 ar8327_leds_init(struct ar8xxx_priv *priv)
1492 {
1493         struct ar8327_data *data = priv->chip_data;
1494         unsigned i;
1495
1496         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1497                 return;
1498
1499         for (i = 0; i < data->num_leds; i++) {
1500                 struct ar8327_led *aled;
1501
1502                 aled = data->leds[i];
1503
1504                 if (aled->enable_hw_mode)
1505                         aled->pattern = AR8327_LED_PATTERN_RULE;
1506                 else
1507                         aled->pattern = AR8327_LED_PATTERN_OFF;
1508
1509                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1510         }
1511 }
1512
1513 static void
1514 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1515 {
1516         struct ar8327_data *data = priv->chip_data;
1517         unsigned i;
1518
1519         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1520                 return;
1521
1522         for (i = 0; i < data->num_leds; i++) {
1523                 struct ar8327_led *aled;
1524
1525                 aled = data->leds[i];
1526                 ar8327_led_destroy(aled);
1527         }
1528
1529         kfree(data->leds);
1530 }
1531
1532 static int
1533 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1534                        struct ar8327_platform_data *pdata)
1535 {
1536         struct ar8327_led_cfg *led_cfg;
1537         struct ar8327_data *data = priv->chip_data;
1538         u32 pos, new_pos;
1539         u32 t;
1540
1541         if (!pdata)
1542                 return -EINVAL;
1543
1544         priv->get_port_link = pdata->get_port_link;
1545
1546         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1547         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1548
1549         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1550         if (chip_is_ar8337(priv))
1551                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1552
1553         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1554         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1555         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1556         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1557         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1558
1559         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1560         new_pos = pos;
1561
1562         led_cfg = pdata->led_cfg;
1563         if (led_cfg) {
1564                 if (led_cfg->open_drain)
1565                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1566                 else
1567                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1568
1569                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1570                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1571                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1572                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1573
1574                 if (new_pos != pos)
1575                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1576         }
1577
1578         if (pdata->sgmii_cfg) {
1579                 t = pdata->sgmii_cfg->sgmii_ctrl;
1580                 if (priv->chip_rev == 1)
1581                         t |= AR8327_SGMII_CTRL_EN_PLL |
1582                              AR8327_SGMII_CTRL_EN_RX |
1583                              AR8327_SGMII_CTRL_EN_TX;
1584                 else
1585                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1586                                AR8327_SGMII_CTRL_EN_RX |
1587                                AR8327_SGMII_CTRL_EN_TX);
1588
1589                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1590
1591                 if (pdata->sgmii_cfg->serdes_aen)
1592                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1593                 else
1594                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1595         }
1596
1597         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1598
1599         if (pdata->leds && pdata->num_leds) {
1600                 int i;
1601
1602                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1603                                      GFP_KERNEL);
1604                 if (!data->leds)
1605                         return -ENOMEM;
1606
1607                 for (i = 0; i < pdata->num_leds; i++)
1608                         ar8327_led_create(priv, &pdata->leds[i]);
1609         }
1610
1611         return 0;
1612 }
1613
1614 #ifdef CONFIG_OF
1615 static int
1616 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1617 {
1618         struct ar8327_data *data = priv->chip_data;
1619         const __be32 *paddr;
1620         int len;
1621         int i;
1622
1623         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1624         if (!paddr || len < (2 * sizeof(*paddr)))
1625                 return -EINVAL;
1626
1627         len /= sizeof(*paddr);
1628
1629         for (i = 0; i < len - 1; i += 2) {
1630                 u32 reg;
1631                 u32 val;
1632
1633                 reg = be32_to_cpup(paddr + i);
1634                 val = be32_to_cpup(paddr + i + 1);
1635
1636                 switch (reg) {
1637                 case AR8327_REG_PORT_STATUS(0):
1638                         data->port0_status = val;
1639                         break;
1640                 case AR8327_REG_PORT_STATUS(6):
1641                         data->port6_status = val;
1642                         break;
1643                 default:
1644                         priv->write(priv, reg, val);
1645                         break;
1646                 }
1647         }
1648
1649         return 0;
1650 }
1651 #else
1652 static inline int
1653 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1654 {
1655         return -EINVAL;
1656 }
1657 #endif
1658
1659 static int
1660 ar8327_hw_init(struct ar8xxx_priv *priv)
1661 {
1662         int ret;
1663
1664         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1665         if (!priv->chip_data)
1666                 return -ENOMEM;
1667
1668         if (priv->phy->dev.of_node)
1669                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1670         else
1671                 ret = ar8327_hw_config_pdata(priv,
1672                                              priv->phy->dev.platform_data);
1673
1674         if (ret)
1675                 return ret;
1676
1677         ar8327_leds_init(priv);
1678
1679         ar8xxx_phy_init(priv);
1680
1681         return 0;
1682 }
1683
1684 static void
1685 ar8327_cleanup(struct ar8xxx_priv *priv)
1686 {
1687         ar8327_leds_cleanup(priv);
1688 }
1689
1690 static void
1691 ar8327_init_globals(struct ar8xxx_priv *priv)
1692 {
1693         u32 t;
1694
1695         /* enable CPU port and disable mirror port */
1696         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1697             AR8327_FWD_CTRL0_MIRROR_PORT;
1698         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1699
1700         /* forward multicast and broadcast frames to CPU */
1701         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1702             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1703             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1704         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1705
1706         /* enable jumbo frames */
1707         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1708                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1709
1710         /* Enable MIB counters */
1711         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1712                        AR8327_MODULE_EN_MIB);
1713
1714         /* Disable EEE on all ports due to stability issues */
1715         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1716         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1717              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1718              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1719              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1720              AR8327_EEE_CTRL_DISABLE_PHY(4);
1721         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1722 }
1723
1724 static void
1725 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1726 {
1727         struct ar8327_data *data = priv->chip_data;
1728         u32 t;
1729
1730         if (port == AR8216_PORT_CPU)
1731                 t = data->port0_status;
1732         else if (port == 6)
1733                 t = data->port6_status;
1734         else
1735                 t = AR8216_PORT_STATUS_LINK_AUTO;
1736
1737         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1738         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1739
1740         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1741         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1742         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1743
1744         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1745         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1746
1747         t = AR8327_PORT_LOOKUP_LEARN;
1748         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1749         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1750 }
1751
1752 static u32
1753 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1754 {
1755         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1756 }
1757
1758 static int
1759 ar8327_atu_flush(struct ar8xxx_priv *priv)
1760 {
1761         int ret;
1762
1763         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1764                               AR8327_ATU_FUNC_BUSY, 0);
1765         if (!ret)
1766                 priv->write(priv, AR8327_REG_ATU_FUNC,
1767                             AR8327_ATU_FUNC_OP_FLUSH);
1768
1769         return ret;
1770 }
1771
1772 static void
1773 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1774 {
1775         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1776                             AR8327_VTU_FUNC1_BUSY, 0))
1777                 return;
1778
1779         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1780                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1781
1782         op |= AR8327_VTU_FUNC1_BUSY;
1783         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1784 }
1785
1786 static void
1787 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1788 {
1789         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1790 }
1791
1792 static void
1793 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1794 {
1795         u32 op;
1796         u32 val;
1797         int i;
1798
1799         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1800         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1801         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1802                 u32 mode;
1803
1804                 if ((port_mask & BIT(i)) == 0)
1805                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1806                 else if (priv->vlan == 0)
1807                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1808                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1809                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1810                 else
1811                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1812
1813                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1814         }
1815         ar8327_vtu_op(priv, op, val);
1816 }
1817
1818 static void
1819 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1820 {
1821         u32 t;
1822         u32 egress, ingress;
1823         u32 pvid = priv->vlan_id[priv->pvid[port]];
1824
1825         if (priv->vlan) {
1826                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1827                 ingress = AR8216_IN_SECURE;
1828         } else {
1829                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1830                 ingress = AR8216_IN_PORT_ONLY;
1831         }
1832
1833         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1834         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1835         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1836
1837         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1838         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1839         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1840
1841         t = members;
1842         t |= AR8327_PORT_LOOKUP_LEARN;
1843         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1844         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1845         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1846 }
1847
1848 static const struct ar8xxx_chip ar8327_chip = {
1849         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1850         .config_at_probe = true,
1851         .mii_lo_first = true,
1852
1853         .reg_port_stats_start = 0x1000,
1854         .reg_port_stats_length = 0x100,
1855
1856         .hw_init = ar8327_hw_init,
1857         .cleanup = ar8327_cleanup,
1858         .init_globals = ar8327_init_globals,
1859         .init_port = ar8327_init_port,
1860         .setup_port = ar8327_setup_port,
1861         .read_port_status = ar8327_read_port_status,
1862         .atu_flush = ar8327_atu_flush,
1863         .vtu_flush = ar8327_vtu_flush,
1864         .vtu_load_vlan = ar8327_vtu_load_vlan,
1865         .phy_fixup = ar8327_phy_fixup,
1866         .set_mirror_regs = ar8327_set_mirror_regs,
1867
1868         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1869         .mib_decs = ar8236_mibs,
1870         .mib_func = AR8327_REG_MIB_FUNC
1871 };
1872
1873 static int
1874 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1875                    struct switch_val *val)
1876 {
1877         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1878         priv->vlan = !!val->value.i;
1879         return 0;
1880 }
1881
1882 static int
1883 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1884                    struct switch_val *val)
1885 {
1886         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1887         val->value.i = priv->vlan;
1888         return 0;
1889 }
1890
1891
1892 static int
1893 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1894 {
1895         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1896
1897         /* make sure no invalid PVIDs get set */
1898
1899         if (vlan >= dev->vlans)
1900                 return -EINVAL;
1901
1902         priv->pvid[port] = vlan;
1903         return 0;
1904 }
1905
1906 static int
1907 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1908 {
1909         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1910         *vlan = priv->pvid[port];
1911         return 0;
1912 }
1913
1914 static int
1915 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1916                   struct switch_val *val)
1917 {
1918         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1919         priv->vlan_id[val->port_vlan] = val->value.i;
1920         return 0;
1921 }
1922
1923 static int
1924 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1925                   struct switch_val *val)
1926 {
1927         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1928         val->value.i = priv->vlan_id[val->port_vlan];
1929         return 0;
1930 }
1931
1932 static int
1933 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1934                         struct switch_port_link *link)
1935 {
1936         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1937
1938         ar8216_read_port_link(priv, port, link);
1939         return 0;
1940 }
1941
1942 static int
1943 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1944 {
1945         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1946         u8 ports = priv->vlan_table[val->port_vlan];
1947         int i;
1948
1949         val->len = 0;
1950         for (i = 0; i < dev->ports; i++) {
1951                 struct switch_port *p;
1952
1953                 if (!(ports & (1 << i)))
1954                         continue;
1955
1956                 p = &val->value.ports[val->len++];
1957                 p->id = i;
1958                 if (priv->vlan_tagged & (1 << i))
1959                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1960                 else
1961                         p->flags = 0;
1962         }
1963         return 0;
1964 }
1965
1966 static int
1967 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1968 {
1969         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1970         u8 ports = priv->vlan_table[val->port_vlan];
1971         int i;
1972
1973         val->len = 0;
1974         for (i = 0; i < dev->ports; i++) {
1975                 struct switch_port *p;
1976
1977                 if (!(ports & (1 << i)))
1978                         continue;
1979
1980                 p = &val->value.ports[val->len++];
1981                 p->id = i;
1982                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1983                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1984                 else
1985                         p->flags = 0;
1986         }
1987         return 0;
1988 }
1989
1990 static int
1991 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1992 {
1993         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1994         u8 *vt = &priv->vlan_table[val->port_vlan];
1995         int i, j;
1996
1997         *vt = 0;
1998         for (i = 0; i < val->len; i++) {
1999                 struct switch_port *p = &val->value.ports[i];
2000
2001                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2002                         priv->vlan_tagged |= (1 << p->id);
2003                 } else {
2004                         priv->vlan_tagged &= ~(1 << p->id);
2005                         priv->pvid[p->id] = val->port_vlan;
2006
2007                         /* make sure that an untagged port does not
2008                          * appear in other vlans */
2009                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2010                                 if (j == val->port_vlan)
2011                                         continue;
2012                                 priv->vlan_table[j] &= ~(1 << p->id);
2013                         }
2014                 }
2015
2016                 *vt |= 1 << p->id;
2017         }
2018         return 0;
2019 }
2020
2021 static int
2022 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
2023 {
2024         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2025         u8 *vt = &priv->vlan_table[val->port_vlan];
2026         int i;
2027
2028         *vt = 0;
2029         for (i = 0; i < val->len; i++) {
2030                 struct switch_port *p = &val->value.ports[i];
2031
2032                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2033                         if (val->port_vlan == priv->pvid[p->id]) {
2034                                 priv->vlan_tagged |= (1 << p->id);
2035                         }
2036                 } else {
2037                         priv->vlan_tagged &= ~(1 << p->id);
2038                         priv->pvid[p->id] = val->port_vlan;
2039                 }
2040
2041                 *vt |= 1 << p->id;
2042         }
2043         return 0;
2044 }
2045
2046 static void
2047 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2048 {
2049         int port;
2050
2051         /* reset all mirror registers */
2052         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2053                    AR8327_FWD_CTRL0_MIRROR_PORT,
2054                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2055         for (port = 0; port < AR8327_NUM_PORTS; port++) {
2056                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2057                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2058                            0);
2059
2060                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2061                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2062                            0);
2063         }
2064
2065         /* now enable mirroring if necessary */
2066         if (priv->source_port >= AR8327_NUM_PORTS ||
2067             priv->monitor_port >= AR8327_NUM_PORTS ||
2068             priv->source_port == priv->monitor_port) {
2069                 return;
2070         }
2071
2072         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2073                    AR8327_FWD_CTRL0_MIRROR_PORT,
2074                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2075
2076         if (priv->mirror_rx)
2077                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2078                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2079                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2080
2081         if (priv->mirror_tx)
2082                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2083                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2084                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2085 }
2086
2087 static void
2088 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2089 {
2090         int port;
2091
2092         /* reset all mirror registers */
2093         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2094                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2095                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2096         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2097                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2098                            AR8216_PORT_CTRL_MIRROR_RX,
2099                            0);
2100
2101                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2102                            AR8216_PORT_CTRL_MIRROR_TX,
2103                            0);
2104         }
2105
2106         /* now enable mirroring if necessary */
2107         if (priv->source_port >= AR8216_NUM_PORTS ||
2108             priv->monitor_port >= AR8216_NUM_PORTS ||
2109             priv->source_port == priv->monitor_port) {
2110                 return;
2111         }
2112
2113         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2114                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2115                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2116
2117         if (priv->mirror_rx)
2118                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2119                            AR8216_PORT_CTRL_MIRROR_RX,
2120                            AR8216_PORT_CTRL_MIRROR_RX);
2121
2122         if (priv->mirror_tx)
2123                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2124                            AR8216_PORT_CTRL_MIRROR_TX,
2125                            AR8216_PORT_CTRL_MIRROR_TX);
2126 }
2127
2128 static int
2129 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2130 {
2131         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2132         u8 portmask[AR8X16_MAX_PORTS];
2133         int i, j;
2134
2135         mutex_lock(&priv->reg_mutex);
2136         /* flush all vlan translation unit entries */
2137         priv->chip->vtu_flush(priv);
2138
2139         memset(portmask, 0, sizeof(portmask));
2140         if (!priv->init) {
2141                 /* calculate the port destination masks and load vlans
2142                  * into the vlan translation unit */
2143                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2144                         u8 vp = priv->vlan_table[j];
2145
2146                         if (!vp)
2147                                 continue;
2148
2149                         for (i = 0; i < dev->ports; i++) {
2150                                 u8 mask = (1 << i);
2151                                 if (vp & mask)
2152                                         portmask[i] |= vp & ~mask;
2153                         }
2154
2155                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2156                                                  priv->vlan_table[j]);
2157                 }
2158         } else {
2159                 /* vlan disabled:
2160                  * isolate all ports, but connect them to the cpu port */
2161                 for (i = 0; i < dev->ports; i++) {
2162                         if (i == AR8216_PORT_CPU)
2163                                 continue;
2164
2165                         portmask[i] = 1 << AR8216_PORT_CPU;
2166                         portmask[AR8216_PORT_CPU] |= (1 << i);
2167                 }
2168         }
2169
2170         /* update the port destination mask registers and tag settings */
2171         for (i = 0; i < dev->ports; i++) {
2172                 priv->chip->setup_port(priv, i, portmask[i]);
2173         }
2174
2175         priv->chip->set_mirror_regs(priv);
2176
2177         mutex_unlock(&priv->reg_mutex);
2178         return 0;
2179 }
2180
2181 static int
2182 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2183 {
2184         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2185         int i;
2186
2187         mutex_lock(&priv->reg_mutex);
2188         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2189                 offsetof(struct ar8xxx_priv, vlan));
2190
2191         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2192                 priv->vlan_id[i] = i;
2193
2194         /* Configure all ports */
2195         for (i = 0; i < dev->ports; i++)
2196                 priv->chip->init_port(priv, i);
2197
2198         priv->mirror_rx = false;
2199         priv->mirror_tx = false;
2200         priv->source_port = 0;
2201         priv->monitor_port = 0;
2202
2203         priv->chip->init_globals(priv);
2204
2205         mutex_unlock(&priv->reg_mutex);
2206
2207         return ar8xxx_sw_hw_apply(dev);
2208 }
2209
2210 static int
2211 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2212                          const struct switch_attr *attr,
2213                          struct switch_val *val)
2214 {
2215         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2216         unsigned int len;
2217         int ret;
2218
2219         if (!ar8xxx_has_mib_counters(priv))
2220                 return -EOPNOTSUPP;
2221
2222         mutex_lock(&priv->mib_lock);
2223
2224         len = priv->dev.ports * priv->chip->num_mibs *
2225               sizeof(*priv->mib_stats);
2226         memset(priv->mib_stats, '\0', len);
2227         ret = ar8xxx_mib_flush(priv);
2228         if (ret)
2229                 goto unlock;
2230
2231         ret = 0;
2232
2233 unlock:
2234         mutex_unlock(&priv->mib_lock);
2235         return ret;
2236 }
2237
2238 static int
2239 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2240                                const struct switch_attr *attr,
2241                                struct switch_val *val)
2242 {
2243         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2244
2245         mutex_lock(&priv->reg_mutex);
2246         priv->mirror_rx = !!val->value.i;
2247         priv->chip->set_mirror_regs(priv);
2248         mutex_unlock(&priv->reg_mutex);
2249
2250         return 0;
2251 }
2252
2253 static int
2254 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2255                                const struct switch_attr *attr,
2256                                struct switch_val *val)
2257 {
2258         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2259         val->value.i = priv->mirror_rx;
2260         return 0;
2261 }
2262
2263 static int
2264 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2265                                const struct switch_attr *attr,
2266                                struct switch_val *val)
2267 {
2268         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2269
2270         mutex_lock(&priv->reg_mutex);
2271         priv->mirror_tx = !!val->value.i;
2272         priv->chip->set_mirror_regs(priv);
2273         mutex_unlock(&priv->reg_mutex);
2274
2275         return 0;
2276 }
2277
2278 static int
2279 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2280                                const struct switch_attr *attr,
2281                                struct switch_val *val)
2282 {
2283         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2284         val->value.i = priv->mirror_tx;
2285         return 0;
2286 }
2287
2288 static int
2289 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2290                                   const struct switch_attr *attr,
2291                                   struct switch_val *val)
2292 {
2293         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2294
2295         mutex_lock(&priv->reg_mutex);
2296         priv->monitor_port = val->value.i;
2297         priv->chip->set_mirror_regs(priv);
2298         mutex_unlock(&priv->reg_mutex);
2299
2300         return 0;
2301 }
2302
2303 static int
2304 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2305                                   const struct switch_attr *attr,
2306                                   struct switch_val *val)
2307 {
2308         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2309         val->value.i = priv->monitor_port;
2310         return 0;
2311 }
2312
2313 static int
2314 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2315                                  const struct switch_attr *attr,
2316                                  struct switch_val *val)
2317 {
2318         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2319
2320         mutex_lock(&priv->reg_mutex);
2321         priv->source_port = val->value.i;
2322         priv->chip->set_mirror_regs(priv);
2323         mutex_unlock(&priv->reg_mutex);
2324
2325         return 0;
2326 }
2327
2328 static int
2329 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2330                                  const struct switch_attr *attr,
2331                                  struct switch_val *val)
2332 {
2333         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2334         val->value.i = priv->source_port;
2335         return 0;
2336 }
2337
2338 static int
2339 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2340                              const struct switch_attr *attr,
2341                              struct switch_val *val)
2342 {
2343         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2344         int port;
2345         int ret;
2346
2347         if (!ar8xxx_has_mib_counters(priv))
2348                 return -EOPNOTSUPP;
2349
2350         port = val->port_vlan;
2351         if (port >= dev->ports)
2352                 return -EINVAL;
2353
2354         mutex_lock(&priv->mib_lock);
2355         ret = ar8xxx_mib_capture(priv);
2356         if (ret)
2357                 goto unlock;
2358
2359         ar8xxx_mib_fetch_port_stat(priv, port, true);
2360
2361         ret = 0;
2362
2363 unlock:
2364         mutex_unlock(&priv->mib_lock);
2365         return ret;
2366 }
2367
2368 static int
2369 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2370                        const struct switch_attr *attr,
2371                        struct switch_val *val)
2372 {
2373         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2374         const struct ar8xxx_chip *chip = priv->chip;
2375         u64 *mib_stats;
2376         int port;
2377         int ret;
2378         char *buf = priv->buf;
2379         int i, len = 0;
2380
2381         if (!ar8xxx_has_mib_counters(priv))
2382                 return -EOPNOTSUPP;
2383
2384         port = val->port_vlan;
2385         if (port >= dev->ports)
2386                 return -EINVAL;
2387
2388         mutex_lock(&priv->mib_lock);
2389         ret = ar8xxx_mib_capture(priv);
2390         if (ret)
2391                 goto unlock;
2392
2393         ar8xxx_mib_fetch_port_stat(priv, port, false);
2394
2395         len += snprintf(buf + len, sizeof(priv->buf) - len,
2396                         "Port %d MIB counters\n",
2397                         port);
2398
2399         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2400         for (i = 0; i < chip->num_mibs; i++)
2401                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2402                                 "%-12s: %llu\n",
2403                                 chip->mib_decs[i].name,
2404                                 mib_stats[i]);
2405
2406         val->value.s = buf;
2407         val->len = len;
2408
2409         ret = 0;
2410
2411 unlock:
2412         mutex_unlock(&priv->mib_lock);
2413         return ret;
2414 }
2415
2416 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2417         {
2418                 .type = SWITCH_TYPE_INT,
2419                 .name = "enable_vlan",
2420                 .description = "Enable VLAN mode",
2421                 .set = ar8xxx_sw_set_vlan,
2422                 .get = ar8xxx_sw_get_vlan,
2423                 .max = 1
2424         },
2425         {
2426                 .type = SWITCH_TYPE_NOVAL,
2427                 .name = "reset_mibs",
2428                 .description = "Reset all MIB counters",
2429                 .set = ar8xxx_sw_set_reset_mibs,
2430         },
2431         {
2432                 .type = SWITCH_TYPE_INT,
2433                 .name = "enable_mirror_rx",
2434                 .description = "Enable mirroring of RX packets",
2435                 .set = ar8xxx_sw_set_mirror_rx_enable,
2436                 .get = ar8xxx_sw_get_mirror_rx_enable,
2437                 .max = 1
2438         },
2439         {
2440                 .type = SWITCH_TYPE_INT,
2441                 .name = "enable_mirror_tx",
2442                 .description = "Enable mirroring of TX packets",
2443                 .set = ar8xxx_sw_set_mirror_tx_enable,
2444                 .get = ar8xxx_sw_get_mirror_tx_enable,
2445                 .max = 1
2446         },
2447         {
2448                 .type = SWITCH_TYPE_INT,
2449                 .name = "mirror_monitor_port",
2450                 .description = "Mirror monitor port",
2451                 .set = ar8xxx_sw_set_mirror_monitor_port,
2452                 .get = ar8xxx_sw_get_mirror_monitor_port,
2453                 .max = AR8216_NUM_PORTS - 1
2454         },
2455         {
2456                 .type = SWITCH_TYPE_INT,
2457                 .name = "mirror_source_port",
2458                 .description = "Mirror source port",
2459                 .set = ar8xxx_sw_set_mirror_source_port,
2460                 .get = ar8xxx_sw_get_mirror_source_port,
2461                 .max = AR8216_NUM_PORTS - 1
2462         },
2463 };
2464
2465 static struct switch_attr ar8327_sw_attr_globals[] = {
2466         {
2467                 .type = SWITCH_TYPE_INT,
2468                 .name = "enable_vlan",
2469                 .description = "Enable VLAN mode",
2470                 .set = ar8xxx_sw_set_vlan,
2471                 .get = ar8xxx_sw_get_vlan,
2472                 .max = 1
2473         },
2474         {
2475                 .type = SWITCH_TYPE_NOVAL,
2476                 .name = "reset_mibs",
2477                 .description = "Reset all MIB counters",
2478                 .set = ar8xxx_sw_set_reset_mibs,
2479         },
2480         {
2481                 .type = SWITCH_TYPE_INT,
2482                 .name = "enable_mirror_rx",
2483                 .description = "Enable mirroring of RX packets",
2484                 .set = ar8xxx_sw_set_mirror_rx_enable,
2485                 .get = ar8xxx_sw_get_mirror_rx_enable,
2486                 .max = 1
2487         },
2488         {
2489                 .type = SWITCH_TYPE_INT,
2490                 .name = "enable_mirror_tx",
2491                 .description = "Enable mirroring of TX packets",
2492                 .set = ar8xxx_sw_set_mirror_tx_enable,
2493                 .get = ar8xxx_sw_get_mirror_tx_enable,
2494                 .max = 1
2495         },
2496         {
2497                 .type = SWITCH_TYPE_INT,
2498                 .name = "mirror_monitor_port",
2499                 .description = "Mirror monitor port",
2500                 .set = ar8xxx_sw_set_mirror_monitor_port,
2501                 .get = ar8xxx_sw_get_mirror_monitor_port,
2502                 .max = AR8327_NUM_PORTS - 1
2503         },
2504         {
2505                 .type = SWITCH_TYPE_INT,
2506                 .name = "mirror_source_port",
2507                 .description = "Mirror source port",
2508                 .set = ar8xxx_sw_set_mirror_source_port,
2509                 .get = ar8xxx_sw_get_mirror_source_port,
2510                 .max = AR8327_NUM_PORTS - 1
2511         },
2512 };
2513
2514 static struct switch_attr ar8xxx_sw_attr_port[] = {
2515         {
2516                 .type = SWITCH_TYPE_NOVAL,
2517                 .name = "reset_mib",
2518                 .description = "Reset single port MIB counters",
2519                 .set = ar8xxx_sw_set_port_reset_mib,
2520         },
2521         {
2522                 .type = SWITCH_TYPE_STRING,
2523                 .name = "mib",
2524                 .description = "Get port's MIB counters",
2525                 .set = NULL,
2526                 .get = ar8xxx_sw_get_port_mib,
2527         },
2528 };
2529
2530 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2531         {
2532                 .type = SWITCH_TYPE_INT,
2533                 .name = "vid",
2534                 .description = "VLAN ID (0-4094)",
2535                 .set = ar8xxx_sw_set_vid,
2536                 .get = ar8xxx_sw_get_vid,
2537                 .max = 4094,
2538         },
2539 };
2540
2541 static const struct switch_dev_ops ar8xxx_sw_ops = {
2542         .attr_global = {
2543                 .attr = ar8xxx_sw_attr_globals,
2544                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2545         },
2546         .attr_port = {
2547                 .attr = ar8xxx_sw_attr_port,
2548                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2549         },
2550         .attr_vlan = {
2551                 .attr = ar8xxx_sw_attr_vlan,
2552                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2553         },
2554         .get_port_pvid = ar8xxx_sw_get_pvid,
2555         .set_port_pvid = ar8xxx_sw_set_pvid,
2556         .get_vlan_ports = ar8xxx_sw_get_ports,
2557         .set_vlan_ports = ar8xxx_sw_set_ports,
2558         .apply_config = ar8xxx_sw_hw_apply,
2559         .reset_switch = ar8xxx_sw_reset_switch,
2560         .get_port_link = ar8xxx_sw_get_port_link,
2561 };
2562
2563 static const struct switch_dev_ops ar8327_sw_ops = {
2564         .attr_global = {
2565                 .attr = ar8327_sw_attr_globals,
2566                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2567         },
2568         .attr_port = {
2569                 .attr = ar8xxx_sw_attr_port,
2570                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2571         },
2572         .attr_vlan = {
2573                 .attr = ar8xxx_sw_attr_vlan,
2574                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2575         },
2576         .get_port_pvid = ar8xxx_sw_get_pvid,
2577         .set_port_pvid = ar8xxx_sw_set_pvid,
2578         .get_vlan_ports = ar8327_sw_get_ports,
2579         .set_vlan_ports = ar8327_sw_set_ports,
2580         .apply_config = ar8xxx_sw_hw_apply,
2581         .reset_switch = ar8xxx_sw_reset_switch,
2582         .get_port_link = ar8xxx_sw_get_port_link,
2583 };
2584
2585 static int
2586 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2587 {
2588         u32 val;
2589         u16 id;
2590         int i;
2591
2592         val = priv->read(priv, AR8216_REG_CTRL);
2593         if (val == ~0)
2594                 return -ENODEV;
2595
2596         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2597         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2598                 u16 t;
2599
2600                 val = priv->read(priv, AR8216_REG_CTRL);
2601                 if (val == ~0)
2602                         return -ENODEV;
2603
2604                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2605                 if (t != id)
2606                         return -ENODEV;
2607         }
2608
2609         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2610         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2611
2612         switch (priv->chip_ver) {
2613         case AR8XXX_VER_AR8216:
2614                 priv->chip = &ar8216_chip;
2615                 break;
2616         case AR8XXX_VER_AR8236:
2617                 priv->chip = &ar8236_chip;
2618                 break;
2619         case AR8XXX_VER_AR8316:
2620                 priv->chip = &ar8316_chip;
2621                 break;
2622         case AR8XXX_VER_AR8327:
2623                 priv->chip = &ar8327_chip;
2624                 break;
2625         case AR8XXX_VER_AR8337:
2626                 priv->chip = &ar8327_chip;
2627                 break;
2628         default:
2629                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2630                        priv->chip_ver, priv->chip_rev);
2631
2632                 return -ENODEV;
2633         }
2634
2635         return 0;
2636 }
2637
2638 static void
2639 ar8xxx_mib_work_func(struct work_struct *work)
2640 {
2641         struct ar8xxx_priv *priv;
2642         int err;
2643
2644         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2645
2646         mutex_lock(&priv->mib_lock);
2647
2648         err = ar8xxx_mib_capture(priv);
2649         if (err)
2650                 goto next_port;
2651
2652         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2653
2654 next_port:
2655         priv->mib_next_port++;
2656         if (priv->mib_next_port >= priv->dev.ports)
2657                 priv->mib_next_port = 0;
2658
2659         mutex_unlock(&priv->mib_lock);
2660         schedule_delayed_work(&priv->mib_work,
2661                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2662 }
2663
2664 static int
2665 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2666 {
2667         unsigned int len;
2668
2669         if (!ar8xxx_has_mib_counters(priv))
2670                 return 0;
2671
2672         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2673
2674         len = priv->dev.ports * priv->chip->num_mibs *
2675               sizeof(*priv->mib_stats);
2676         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2677
2678         if (!priv->mib_stats)
2679                 return -ENOMEM;
2680
2681         return 0;
2682 }
2683
2684 static void
2685 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2686 {
2687         if (!ar8xxx_has_mib_counters(priv))
2688                 return;
2689
2690         schedule_delayed_work(&priv->mib_work,
2691                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2692 }
2693
2694 static void
2695 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2696 {
2697         if (!ar8xxx_has_mib_counters(priv))
2698                 return;
2699
2700         cancel_delayed_work(&priv->mib_work);
2701 }
2702
2703 static struct ar8xxx_priv *
2704 ar8xxx_create(void)
2705 {
2706         struct ar8xxx_priv *priv;
2707
2708         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2709         if (priv == NULL)
2710                 return NULL;
2711
2712         mutex_init(&priv->reg_mutex);
2713         mutex_init(&priv->mib_lock);
2714         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2715
2716         return priv;
2717 }
2718
2719 static void
2720 ar8xxx_free(struct ar8xxx_priv *priv)
2721 {
2722         if (priv->chip && priv->chip->cleanup)
2723                 priv->chip->cleanup(priv);
2724
2725         kfree(priv->chip_data);
2726         kfree(priv->mib_stats);
2727         kfree(priv);
2728 }
2729
2730 static struct ar8xxx_priv *
2731 ar8xxx_create_mii(struct mii_bus *bus)
2732 {
2733         struct ar8xxx_priv *priv;
2734
2735         priv = ar8xxx_create();
2736         if (priv) {
2737                 priv->mii_bus = bus;
2738                 priv->read = ar8xxx_mii_read;
2739                 priv->write = ar8xxx_mii_write;
2740                 priv->rmw = ar8xxx_mii_rmw;
2741         }
2742
2743         return priv;
2744 }
2745
2746 static int
2747 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2748 {
2749         struct switch_dev *swdev;
2750         int ret;
2751
2752         ret = ar8xxx_id_chip(priv);
2753         if (ret)
2754                 return ret;
2755
2756         swdev = &priv->dev;
2757         swdev->cpu_port = AR8216_PORT_CPU;
2758         swdev->ops = &ar8xxx_sw_ops;
2759
2760         if (chip_is_ar8316(priv)) {
2761                 swdev->name = "Atheros AR8316";
2762                 swdev->vlans = AR8X16_MAX_VLANS;
2763                 swdev->ports = AR8216_NUM_PORTS;
2764         } else if (chip_is_ar8236(priv)) {
2765                 swdev->name = "Atheros AR8236";
2766                 swdev->vlans = AR8216_NUM_VLANS;
2767                 swdev->ports = AR8216_NUM_PORTS;
2768         } else if (chip_is_ar8327(priv)) {
2769                 swdev->name = "Atheros AR8327";
2770                 swdev->vlans = AR8X16_MAX_VLANS;
2771                 swdev->ports = AR8327_NUM_PORTS;
2772                 swdev->ops = &ar8327_sw_ops;
2773         } else if (chip_is_ar8337(priv)) {
2774                 swdev->name = "Atheros AR8337";
2775                 swdev->vlans = AR8X16_MAX_VLANS;
2776                 swdev->ports = AR8327_NUM_PORTS;
2777                 swdev->ops = &ar8327_sw_ops;
2778         } else {
2779                 swdev->name = "Atheros AR8216";
2780                 swdev->vlans = AR8216_NUM_VLANS;
2781                 swdev->ports = AR8216_NUM_PORTS;
2782         }
2783
2784         ret = ar8xxx_mib_init(priv);
2785         if (ret)
2786                 return ret;
2787
2788         return 0;
2789 }
2790
2791 static int
2792 ar8xxx_start(struct ar8xxx_priv *priv)
2793 {
2794         int ret;
2795
2796         priv->init = true;
2797
2798         ret = priv->chip->hw_init(priv);
2799         if (ret)
2800                 return ret;
2801
2802         ret = ar8xxx_sw_reset_switch(&priv->dev);
2803         if (ret)
2804                 return ret;
2805
2806         priv->init = false;
2807
2808         ar8xxx_mib_start(priv);
2809
2810         return 0;
2811 }
2812
2813 static int
2814 ar8xxx_phy_config_init(struct phy_device *phydev)
2815 {
2816         struct ar8xxx_priv *priv = phydev->priv;
2817         struct net_device *dev = phydev->attached_dev;
2818         int ret;
2819
2820         if (WARN_ON(!priv))
2821                 return -ENODEV;
2822
2823         if (priv->chip->config_at_probe)
2824                 return ar8xxx_phy_check_aneg(phydev);
2825
2826         priv->phy = phydev;
2827
2828         if (phydev->addr != 0) {
2829                 if (chip_is_ar8316(priv)) {
2830                         /* switch device has been initialized, reinit */
2831                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2832                         priv->initialized = false;
2833                         priv->port4_phy = true;
2834                         ar8316_hw_init(priv);
2835                         return 0;
2836                 }
2837
2838                 return 0;
2839         }
2840
2841         ret = ar8xxx_start(priv);
2842         if (ret)
2843                 return ret;
2844
2845         /* VID fixup only needed on ar8216 */
2846         if (chip_is_ar8216(priv)) {
2847                 dev->phy_ptr = priv;
2848                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2849                 dev->eth_mangle_rx = ar8216_mangle_rx;
2850                 dev->eth_mangle_tx = ar8216_mangle_tx;
2851         }
2852
2853         return 0;
2854 }
2855
2856 static int
2857 ar8xxx_phy_read_status(struct phy_device *phydev)
2858 {
2859         struct ar8xxx_priv *priv = phydev->priv;
2860         struct switch_port_link link;
2861         int ret;
2862
2863         if (phydev->addr != 0)
2864                 return genphy_read_status(phydev);
2865
2866         ar8216_read_port_link(priv, phydev->addr, &link);
2867         phydev->link = !!link.link;
2868         if (!phydev->link)
2869                 return 0;
2870
2871         switch (link.speed) {
2872         case SWITCH_PORT_SPEED_10:
2873                 phydev->speed = SPEED_10;
2874                 break;
2875         case SWITCH_PORT_SPEED_100:
2876                 phydev->speed = SPEED_100;
2877                 break;
2878         case SWITCH_PORT_SPEED_1000:
2879                 phydev->speed = SPEED_1000;
2880                 break;
2881         default:
2882                 phydev->speed = 0;
2883         }
2884         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2885
2886         /* flush the address translation unit */
2887         mutex_lock(&priv->reg_mutex);
2888         ret = priv->chip->atu_flush(priv);
2889         mutex_unlock(&priv->reg_mutex);
2890
2891         phydev->state = PHY_RUNNING;
2892         netif_carrier_on(phydev->attached_dev);
2893         phydev->adjust_link(phydev->attached_dev);
2894
2895         return ret;
2896 }
2897
2898 static int
2899 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2900 {
2901         if (phydev->addr == 0)
2902                 return 0;
2903
2904         return genphy_config_aneg(phydev);
2905 }
2906
2907 static const u32 ar8xxx_phy_ids[] = {
2908         0x004dd033,
2909         0x004dd034, /* AR8327 */
2910         0x004dd036, /* AR8337 */
2911         0x004dd041,
2912         0x004dd042,
2913         0x004dd043, /* AR8236 */
2914 };
2915
2916 static bool
2917 ar8xxx_phy_match(u32 phy_id)
2918 {
2919         int i;
2920
2921         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2922                 if (phy_id == ar8xxx_phy_ids[i])
2923                         return true;
2924
2925         return false;
2926 }
2927
2928 static bool
2929 ar8xxx_is_possible(struct mii_bus *bus)
2930 {
2931         unsigned i;
2932
2933         for (i = 0; i < 4; i++) {
2934                 u32 phy_id;
2935
2936                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2937                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2938                 if (!ar8xxx_phy_match(phy_id)) {
2939                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2940                                  dev_name(&bus->dev), i, phy_id);
2941                         return false;
2942                 }
2943         }
2944
2945         return true;
2946 }
2947
2948 static int
2949 ar8xxx_phy_probe(struct phy_device *phydev)
2950 {
2951         struct ar8xxx_priv *priv;
2952         struct switch_dev *swdev;
2953         int ret;
2954
2955         /* skip PHYs at unused adresses */
2956         if (phydev->addr != 0 && phydev->addr != 4)
2957                 return -ENODEV;
2958
2959         if (!ar8xxx_is_possible(phydev->bus))
2960                 return -ENODEV;
2961
2962         mutex_lock(&ar8xxx_dev_list_lock);
2963         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2964                 if (priv->mii_bus == phydev->bus)
2965                         goto found;
2966
2967         priv = ar8xxx_create_mii(phydev->bus);
2968         if (priv == NULL) {
2969                 ret = -ENOMEM;
2970                 goto unlock;
2971         }
2972
2973         ret = ar8xxx_probe_switch(priv);
2974         if (ret)
2975                 goto free_priv;
2976
2977         swdev = &priv->dev;
2978         swdev->alias = dev_name(&priv->mii_bus->dev);
2979         ret = register_switch(swdev, NULL);
2980         if (ret)
2981                 goto free_priv;
2982
2983         pr_info("%s: %s rev. %u switch registered on %s\n",
2984                 swdev->devname, swdev->name, priv->chip_rev,
2985                 dev_name(&priv->mii_bus->dev));
2986
2987 found:
2988         priv->use_count++;
2989
2990         if (phydev->addr == 0) {
2991                 if (ar8xxx_has_gige(priv)) {
2992                         phydev->supported = SUPPORTED_1000baseT_Full;
2993                         phydev->advertising = ADVERTISED_1000baseT_Full;
2994                 } else {
2995                         phydev->supported = SUPPORTED_100baseT_Full;
2996                         phydev->advertising = ADVERTISED_100baseT_Full;
2997                 }
2998
2999                 if (priv->chip->config_at_probe) {
3000                         priv->phy = phydev;
3001
3002                         ret = ar8xxx_start(priv);
3003                         if (ret)
3004                                 goto err_unregister_switch;
3005                 }
3006         } else {
3007                 if (ar8xxx_has_gige(priv)) {
3008                         phydev->supported |= SUPPORTED_1000baseT_Full;
3009                         phydev->advertising |= ADVERTISED_1000baseT_Full;
3010                 }
3011         }
3012
3013         phydev->priv = priv;
3014
3015         list_add(&priv->list, &ar8xxx_dev_list);
3016
3017         mutex_unlock(&ar8xxx_dev_list_lock);
3018
3019         return 0;
3020
3021 err_unregister_switch:
3022         if (--priv->use_count)
3023                 goto unlock;
3024
3025         unregister_switch(&priv->dev);
3026
3027 free_priv:
3028         ar8xxx_free(priv);
3029 unlock:
3030         mutex_unlock(&ar8xxx_dev_list_lock);
3031         return ret;
3032 }
3033
3034 static void
3035 ar8xxx_phy_detach(struct phy_device *phydev)
3036 {
3037         struct net_device *dev = phydev->attached_dev;
3038
3039         if (!dev)
3040                 return;
3041
3042         dev->phy_ptr = NULL;
3043         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3044         dev->eth_mangle_rx = NULL;
3045         dev->eth_mangle_tx = NULL;
3046 }
3047
3048 static void
3049 ar8xxx_phy_remove(struct phy_device *phydev)
3050 {
3051         struct ar8xxx_priv *priv = phydev->priv;
3052
3053         if (WARN_ON(!priv))
3054                 return;
3055
3056         phydev->priv = NULL;
3057         if (--priv->use_count > 0)
3058                 return;
3059
3060         mutex_lock(&ar8xxx_dev_list_lock);
3061         list_del(&priv->list);
3062         mutex_unlock(&ar8xxx_dev_list_lock);
3063
3064         unregister_switch(&priv->dev);
3065         ar8xxx_mib_stop(priv);
3066         ar8xxx_free(priv);
3067 }
3068
3069 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3070 static int
3071 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3072 {
3073         /* we don't need an extra reset */
3074         return 0;
3075 }
3076 #endif
3077
3078 static struct phy_driver ar8xxx_phy_driver = {
3079         .phy_id         = 0x004d0000,
3080         .name           = "Atheros AR8216/AR8236/AR8316",
3081         .phy_id_mask    = 0xffff0000,
3082         .features       = PHY_BASIC_FEATURES,
3083         .probe          = ar8xxx_phy_probe,
3084         .remove         = ar8xxx_phy_remove,
3085         .detach         = ar8xxx_phy_detach,
3086         .config_init    = ar8xxx_phy_config_init,
3087         .config_aneg    = ar8xxx_phy_config_aneg,
3088         .read_status    = ar8xxx_phy_read_status,
3089 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3090         .soft_reset     = ar8xxx_phy_soft_reset,
3091 #endif
3092         .driver         = { .owner = THIS_MODULE },
3093 };
3094
3095 int __init
3096 ar8xxx_init(void)
3097 {
3098         return phy_driver_register(&ar8xxx_phy_driver);
3099 }
3100
3101 void __exit
3102 ar8xxx_exit(void)
3103 {
3104         phy_driver_unregister(&ar8xxx_phy_driver);
3105 }
3106
3107 module_init(ar8xxx_init);
3108 module_exit(ar8xxx_exit);
3109 MODULE_LICENSE("GPL");
3110