2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 #define AR8XXX_NUM_PHYS 5
58 AR8XXX_VER_AR8216 = 0x01,
59 AR8XXX_VER_AR8236 = 0x03,
60 AR8XXX_VER_AR8316 = 0x10,
61 AR8XXX_VER_AR8327 = 0x12,
62 AR8XXX_VER_AR8337 = 0x13,
65 struct ar8xxx_mib_desc {
76 /* parameters to calculate REG_PORT_STATS_BASE */
77 unsigned reg_port_stats_start;
78 unsigned reg_port_stats_length;
80 int (*hw_init)(struct ar8xxx_priv *priv);
81 void (*cleanup)(struct ar8xxx_priv *priv);
86 const struct switch_dev_ops *swops;
88 void (*init_globals)(struct ar8xxx_priv *priv);
89 void (*init_port)(struct ar8xxx_priv *priv, int port);
90 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
91 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
92 int (*atu_flush)(struct ar8xxx_priv *priv);
93 void (*vtu_flush)(struct ar8xxx_priv *priv);
94 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
95 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
96 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
98 const struct ar8xxx_mib_desc *mib_decs;
103 enum ar8327_led_pattern {
104 AR8327_LED_PATTERN_OFF = 0,
105 AR8327_LED_PATTERN_BLINK,
106 AR8327_LED_PATTERN_ON,
107 AR8327_LED_PATTERN_RULE,
110 struct ar8327_led_entry {
116 struct led_classdev cdev;
117 struct ar8xxx_priv *sw_priv;
122 enum ar8327_led_mode mode;
126 struct work_struct led_work;
128 enum ar8327_led_pattern pattern;
135 struct ar8327_led **leds;
136 unsigned int num_leds;
140 struct switch_dev dev;
141 struct mii_bus *mii_bus;
142 struct phy_device *phy;
144 int (*get_port_link)(unsigned port);
146 const struct net_device_ops *ndo_old;
147 struct net_device_ops ndo;
148 struct mutex reg_mutex;
151 const struct ar8xxx_chip *chip;
159 struct mutex mib_lock;
160 struct delayed_work mib_work;
164 struct list_head list;
165 unsigned int use_count;
167 /* all fields below are cleared on reset */
169 u16 vlan_id[AR8X16_MAX_VLANS];
170 u8 vlan_table[AR8X16_MAX_VLANS];
172 u16 pvid[AR8X16_MAX_PORTS];
181 #define MIB_DESC(_s , _o, _n) \
188 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
189 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
190 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
191 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
192 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
193 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
194 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
195 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
196 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
197 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
198 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
199 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
200 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
201 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
202 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
203 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
204 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
205 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
206 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
207 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
208 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
209 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
210 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
211 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
212 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
213 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
214 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
215 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
216 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
217 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
218 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
219 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
220 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
221 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
222 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
223 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
224 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
225 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
228 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
229 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
230 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
231 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
232 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
233 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
234 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
235 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
236 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
237 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
238 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
239 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
240 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
241 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
242 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
243 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
244 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
245 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
246 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
247 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
248 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
249 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
250 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
251 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
252 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
253 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
254 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
255 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
256 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
257 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
258 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
259 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
260 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
261 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
262 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
263 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
264 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
265 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
266 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
267 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
270 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
271 static LIST_HEAD(ar8xxx_dev_list);
273 static inline struct ar8xxx_priv *
274 swdev_to_ar8xxx(struct switch_dev *swdev)
276 return container_of(swdev, struct ar8xxx_priv, dev);
279 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
281 return priv->chip->caps & AR8XXX_CAP_GIGE;
284 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
286 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
289 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
291 return priv->chip_ver == AR8XXX_VER_AR8216;
294 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
296 return priv->chip_ver == AR8XXX_VER_AR8236;
299 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
301 return priv->chip_ver == AR8XXX_VER_AR8316;
304 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
306 return priv->chip_ver == AR8XXX_VER_AR8327;
309 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
311 return priv->chip_ver == AR8XXX_VER_AR8337;
315 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
318 *r1 = regaddr & 0x1e;
324 *page = regaddr & 0x1ff;
327 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
329 ar8xxx_phy_poll_reset(struct mii_bus *bus)
331 unsigned int sleep_msecs = 20;
334 for (elapsed = sleep_msecs; elapsed <= 600;
335 elapsed += sleep_msecs) {
337 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
338 ret = mdiobus_read(bus, i, MII_BMCR);
341 if (ret & BMCR_RESET)
343 if (i == AR8XXX_NUM_PHYS - 1) {
344 usleep_range(1000, 2000);
353 ar8xxx_phy_check_aneg(struct phy_device *phydev)
357 if (phydev->autoneg != AUTONEG_ENABLE)
360 * BMCR_ANENABLE might have been cleared
361 * by phy_init_hw in certain kernel versions
362 * therefore check for it
364 ret = phy_read(phydev, MII_BMCR);
367 if (ret & BMCR_ANENABLE)
370 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
371 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
372 return phy_write(phydev, MII_BMCR, ret);
376 ar8xxx_phy_init(struct ar8xxx_priv *priv)
382 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
383 if (priv->chip->phy_fixup)
384 priv->chip->phy_fixup(priv, i);
386 /* initialize the port itself */
387 mdiobus_write(bus, i, MII_ADVERTISE,
388 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
389 if (ar8xxx_has_gige(priv))
390 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
391 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
394 ar8xxx_phy_poll_reset(bus);
398 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
400 struct mii_bus *bus = priv->mii_bus;
403 lo = bus->read(bus, phy_id, regnum);
404 hi = bus->read(bus, phy_id, regnum + 1);
406 return (hi << 16) | lo;
410 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
412 struct mii_bus *bus = priv->mii_bus;
416 hi = (u16) (val >> 16);
418 if (priv->chip->mii_lo_first)
420 bus->write(bus, phy_id, regnum, lo);
421 bus->write(bus, phy_id, regnum + 1, hi);
423 bus->write(bus, phy_id, regnum + 1, hi);
424 bus->write(bus, phy_id, regnum, lo);
429 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
431 struct mii_bus *bus = priv->mii_bus;
435 split_addr((u32) reg, &r1, &r2, &page);
437 mutex_lock(&bus->mdio_lock);
439 bus->write(bus, 0x18, 0, page);
440 usleep_range(1000, 2000); /* wait for the page switch to propagate */
441 val = mii_read32(priv, 0x10 | r2, r1);
443 mutex_unlock(&bus->mdio_lock);
449 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
451 struct mii_bus *bus = priv->mii_bus;
454 split_addr((u32) reg, &r1, &r2, &page);
456 mutex_lock(&bus->mdio_lock);
458 bus->write(bus, 0x18, 0, page);
459 usleep_range(1000, 2000); /* wait for the page switch to propagate */
460 mii_write32(priv, 0x10 | r2, r1, val);
462 mutex_unlock(&bus->mdio_lock);
466 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
468 struct mii_bus *bus = priv->mii_bus;
472 split_addr((u32) reg, &r1, &r2, &page);
474 mutex_lock(&bus->mdio_lock);
476 bus->write(bus, 0x18, 0, page);
477 usleep_range(1000, 2000); /* wait for the page switch to propagate */
479 ret = mii_read32(priv, 0x10 | r2, r1);
482 mii_write32(priv, 0x10 | r2, r1, ret);
484 mutex_unlock(&bus->mdio_lock);
490 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
491 u16 dbg_addr, u16 dbg_data)
493 struct mii_bus *bus = priv->mii_bus;
495 mutex_lock(&bus->mdio_lock);
496 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
497 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
498 mutex_unlock(&bus->mdio_lock);
502 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
504 struct mii_bus *bus = priv->mii_bus;
506 mutex_lock(&bus->mdio_lock);
507 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
508 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
509 mutex_unlock(&bus->mdio_lock);
513 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
515 ar8xxx_rmw(priv, reg, 0, val);
519 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
524 for (i = 0; i < timeout; i++) {
527 t = ar8xxx_read(priv, reg);
528 if ((t & mask) == val)
531 usleep_range(1000, 2000);
538 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
540 unsigned mib_func = priv->chip->mib_func;
543 lockdep_assert_held(&priv->mib_lock);
545 /* Capture the hardware statistics for all ports */
546 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
548 /* Wait for the capturing to complete. */
549 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
560 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
562 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
566 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
568 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
572 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
578 WARN_ON(port >= priv->dev.ports);
580 lockdep_assert_held(&priv->mib_lock);
582 base = priv->chip->reg_port_stats_start +
583 priv->chip->reg_port_stats_length * port;
585 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
586 for (i = 0; i < priv->chip->num_mibs; i++) {
587 const struct ar8xxx_mib_desc *mib;
590 mib = &priv->chip->mib_decs[i];
591 t = ar8xxx_read(priv, base + mib->offset);
592 if (mib->size == 2) {
595 hi = ar8xxx_read(priv, base + mib->offset + 4);
607 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
608 struct switch_port_link *link)
613 memset(link, '\0', sizeof(*link));
615 status = priv->chip->read_port_status(priv, port);
617 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
619 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
623 if (priv->get_port_link) {
626 err = priv->get_port_link(port);
635 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
636 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
637 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
639 speed = (status & AR8216_PORT_STATUS_SPEED) >>
640 AR8216_PORT_STATUS_SPEED_S;
643 case AR8216_PORT_SPEED_10M:
644 link->speed = SWITCH_PORT_SPEED_10;
646 case AR8216_PORT_SPEED_100M:
647 link->speed = SWITCH_PORT_SPEED_100;
649 case AR8216_PORT_SPEED_1000M:
650 link->speed = SWITCH_PORT_SPEED_1000;
653 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
658 static struct sk_buff *
659 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
661 struct ar8xxx_priv *priv = dev->phy_ptr;
670 if (unlikely(skb_headroom(skb) < 2)) {
671 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
675 buf = skb_push(skb, 2);
683 dev_kfree_skb_any(skb);
688 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
690 struct ar8xxx_priv *priv;
698 /* don't strip the header if vlan mode is disabled */
702 /* strip header, get vlan id */
706 /* check for vlan header presence */
707 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
712 /* no need to fix up packets coming from a tagged source */
713 if (priv->vlan_tagged & (1 << port))
716 /* lookup port vid from local table, the switch passes an invalid vlan id */
717 vlan = priv->vlan_id[priv->pvid[port]];
720 buf[14 + 2] |= vlan >> 8;
721 buf[15 + 2] = vlan & 0xff;
725 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
731 t = ar8xxx_read(priv, reg);
732 if ((t & mask) == val)
741 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
742 (unsigned int) reg, t, mask, val);
747 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
749 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
751 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
752 val &= AR8216_VTUDATA_MEMBER;
753 val |= AR8216_VTUDATA_VALID;
754 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
756 op |= AR8216_VTU_ACTIVE;
757 ar8xxx_write(priv, AR8216_REG_VTU, op);
761 ar8216_vtu_flush(struct ar8xxx_priv *priv)
763 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
767 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
771 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
772 ar8216_vtu_op(priv, op, port_mask);
776 ar8216_atu_flush(struct ar8xxx_priv *priv)
780 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
782 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
788 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
790 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
794 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
801 pvid = priv->vlan_id[priv->pvid[port]];
802 if (priv->vlan_tagged & (1 << port))
803 egress = AR8216_OUT_ADD_VLAN;
805 egress = AR8216_OUT_STRIP_VLAN;
806 ingress = AR8216_IN_SECURE;
809 egress = AR8216_OUT_KEEP;
810 ingress = AR8216_IN_PORT_ONLY;
813 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
814 header = AR8216_PORT_CTRL_HEADER;
818 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
819 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
820 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
821 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
822 AR8216_PORT_CTRL_LEARN | header |
823 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
824 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
826 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
827 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
828 AR8216_PORT_VLAN_DEFAULT_ID,
829 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
830 (ingress << AR8216_PORT_VLAN_MODE_S) |
831 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
835 ar8216_hw_init(struct ar8xxx_priv *priv)
837 if (priv->initialized)
840 ar8xxx_phy_init(priv);
842 priv->initialized = true;
847 ar8216_init_globals(struct ar8xxx_priv *priv)
849 /* standard atheros magic */
850 ar8xxx_write(priv, 0x38, 0xc000050e);
852 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
853 AR8216_GCTRL_MTU, 1518 + 8 + 2);
857 ar8216_init_port(struct ar8xxx_priv *priv, int port)
859 /* Enable port learning and tx */
860 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
861 AR8216_PORT_CTRL_LEARN |
862 (4 << AR8216_PORT_CTRL_STATE_S));
864 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
866 if (port == AR8216_PORT_CPU) {
867 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
868 AR8216_PORT_STATUS_LINK_UP |
869 (ar8xxx_has_gige(priv) ?
870 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
871 AR8216_PORT_STATUS_TXMAC |
872 AR8216_PORT_STATUS_RXMAC |
873 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
874 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
875 AR8216_PORT_STATUS_DUPLEX);
877 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
878 AR8216_PORT_STATUS_LINK_AUTO);
883 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
889 pvid = priv->vlan_id[priv->pvid[port]];
890 if (priv->vlan_tagged & (1 << port))
891 egress = AR8216_OUT_ADD_VLAN;
893 egress = AR8216_OUT_STRIP_VLAN;
894 ingress = AR8216_IN_SECURE;
897 egress = AR8216_OUT_KEEP;
898 ingress = AR8216_IN_PORT_ONLY;
901 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
902 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
903 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
904 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
905 AR8216_PORT_CTRL_LEARN |
906 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
907 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
909 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
910 AR8236_PORT_VLAN_DEFAULT_ID,
911 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
913 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
914 AR8236_PORT_VLAN2_VLAN_MODE |
915 AR8236_PORT_VLAN2_MEMBER,
916 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
917 (members << AR8236_PORT_VLAN2_MEMBER_S));
921 ar8236_init_globals(struct ar8xxx_priv *priv)
923 /* enable jumbo frames */
924 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
925 AR8316_GCTRL_MTU, 9018 + 8 + 2);
927 /* enable cpu port to receive arp frames */
928 ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
929 AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
931 /* enable cpu port to receive multicast and broadcast frames */
932 ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
933 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
934 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
936 /* Enable MIB counters */
937 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
938 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
943 ar8316_hw_init(struct ar8xxx_priv *priv)
947 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
949 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
950 if (priv->port4_phy) {
951 /* value taken from Ubiquiti RouterStation Pro */
953 pr_info("ar8316: Using port 4 as PHY\n");
956 pr_info("ar8316: Using port 4 as switch port\n");
958 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
959 /* value taken from AVM Fritz!Box 7390 sources */
962 /* no known value for phy interface */
963 pr_err("ar8316: unsupported mii mode: %d.\n",
964 priv->phy->interface);
971 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
973 if (priv->port4_phy &&
974 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
975 /* work around for phy4 rgmii mode */
976 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
978 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
980 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
984 ar8xxx_phy_init(priv);
987 priv->initialized = true;
992 ar8316_init_globals(struct ar8xxx_priv *priv)
994 /* standard atheros magic */
995 ar8xxx_write(priv, 0x38, 0xc000050e);
997 /* enable cpu port to receive multicast and broadcast frames */
998 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1000 /* enable jumbo frames */
1001 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1002 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1004 /* Enable MIB counters */
1005 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1006 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1011 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1019 switch (cfg->mode) {
1023 case AR8327_PAD_MAC2MAC_MII:
1024 t = AR8327_PAD_MAC_MII_EN;
1026 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1028 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1031 case AR8327_PAD_MAC2MAC_GMII:
1032 t = AR8327_PAD_MAC_GMII_EN;
1034 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1036 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1039 case AR8327_PAD_MAC_SGMII:
1040 t = AR8327_PAD_SGMII_EN;
1043 * WAR for the QUalcomm Atheros AP136 board.
1044 * It seems that RGMII TX/RX delay settings needs to be
1045 * applied for SGMII mode as well, The ethernet is not
1046 * reliable without this.
1048 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1049 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1050 if (cfg->rxclk_delay_en)
1051 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1052 if (cfg->txclk_delay_en)
1053 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1055 if (cfg->sgmii_delay_en)
1056 t |= AR8327_PAD_SGMII_DELAY_EN;
1060 case AR8327_PAD_MAC2PHY_MII:
1061 t = AR8327_PAD_PHY_MII_EN;
1063 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1065 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1068 case AR8327_PAD_MAC2PHY_GMII:
1069 t = AR8327_PAD_PHY_GMII_EN;
1070 if (cfg->pipe_rxclk_sel)
1071 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1073 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1075 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1078 case AR8327_PAD_MAC_RGMII:
1079 t = AR8327_PAD_RGMII_EN;
1080 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1081 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1082 if (cfg->rxclk_delay_en)
1083 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1084 if (cfg->txclk_delay_en)
1085 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1088 case AR8327_PAD_PHY_GMII:
1089 t = AR8327_PAD_PHYX_GMII_EN;
1092 case AR8327_PAD_PHY_RGMII:
1093 t = AR8327_PAD_PHYX_RGMII_EN;
1096 case AR8327_PAD_PHY_MII:
1097 t = AR8327_PAD_PHYX_MII_EN;
1105 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1107 switch (priv->chip_rev) {
1109 /* For 100M waveform */
1110 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1111 /* Turn on Gigabit clock */
1112 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1116 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1117 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1120 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1121 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1123 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1124 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1125 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1131 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1135 if (!cfg->force_link)
1136 return AR8216_PORT_STATUS_LINK_AUTO;
1138 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1139 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1140 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1141 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1143 switch (cfg->speed) {
1144 case AR8327_PORT_SPEED_10:
1145 t |= AR8216_PORT_SPEED_10M;
1147 case AR8327_PORT_SPEED_100:
1148 t |= AR8216_PORT_SPEED_100M;
1150 case AR8327_PORT_SPEED_1000:
1151 t |= AR8216_PORT_SPEED_1000M;
1158 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1159 [_num] = { .reg = (_reg), .shift = (_shift) }
1161 static const struct ar8327_led_entry
1162 ar8327_led_map[AR8327_NUM_LEDS] = {
1163 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1164 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1165 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1167 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1168 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1169 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1171 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1172 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1173 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1175 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1176 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1177 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1179 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1180 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1181 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1185 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1186 enum ar8327_led_pattern pattern)
1188 const struct ar8327_led_entry *entry;
1190 entry = &ar8327_led_map[led_num];
1191 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1192 (3 << entry->shift), pattern << entry->shift);
1196 ar8327_led_work_func(struct work_struct *work)
1198 struct ar8327_led *aled;
1201 aled = container_of(work, struct ar8327_led, led_work);
1203 spin_lock(&aled->lock);
1204 pattern = aled->pattern;
1205 spin_unlock(&aled->lock);
1207 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1212 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1214 if (aled->pattern == pattern)
1217 aled->pattern = pattern;
1218 schedule_work(&aled->led_work);
1221 static inline struct ar8327_led *
1222 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1224 return container_of(led_cdev, struct ar8327_led, cdev);
1228 ar8327_led_blink_set(struct led_classdev *led_cdev,
1229 unsigned long *delay_on,
1230 unsigned long *delay_off)
1232 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1234 if (*delay_on == 0 && *delay_off == 0) {
1239 if (*delay_on != 125 || *delay_off != 125) {
1241 * The hardware only supports blinking at 4Hz. Fall back
1242 * to software implementation in other cases.
1247 spin_lock(&aled->lock);
1249 aled->enable_hw_mode = false;
1250 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1252 spin_unlock(&aled->lock);
1258 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1259 enum led_brightness brightness)
1261 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1265 active = (brightness != LED_OFF);
1266 active ^= aled->active_low;
1268 pattern = (active) ? AR8327_LED_PATTERN_ON :
1269 AR8327_LED_PATTERN_OFF;
1271 spin_lock(&aled->lock);
1273 aled->enable_hw_mode = false;
1274 ar8327_led_schedule_change(aled, pattern);
1276 spin_unlock(&aled->lock);
1280 ar8327_led_enable_hw_mode_show(struct device *dev,
1281 struct device_attribute *attr,
1284 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1285 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1288 spin_lock(&aled->lock);
1289 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1290 spin_unlock(&aled->lock);
1296 ar8327_led_enable_hw_mode_store(struct device *dev,
1297 struct device_attribute *attr,
1301 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1302 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1307 ret = kstrtou8(buf, 10, &value);
1311 spin_lock(&aled->lock);
1313 aled->enable_hw_mode = !!value;
1314 if (aled->enable_hw_mode)
1315 pattern = AR8327_LED_PATTERN_RULE;
1317 pattern = AR8327_LED_PATTERN_OFF;
1319 ar8327_led_schedule_change(aled, pattern);
1321 spin_unlock(&aled->lock);
1326 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1327 ar8327_led_enable_hw_mode_show,
1328 ar8327_led_enable_hw_mode_store);
1331 ar8327_led_register(struct ar8327_led *aled)
1335 ret = led_classdev_register(NULL, &aled->cdev);
1339 if (aled->mode == AR8327_LED_MODE_HW) {
1340 ret = device_create_file(aled->cdev.dev,
1341 &dev_attr_enable_hw_mode);
1343 goto err_unregister;
1349 led_classdev_unregister(&aled->cdev);
1354 ar8327_led_unregister(struct ar8327_led *aled)
1356 if (aled->mode == AR8327_LED_MODE_HW)
1357 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1359 led_classdev_unregister(&aled->cdev);
1360 cancel_work_sync(&aled->led_work);
1364 ar8327_led_create(struct ar8xxx_priv *priv,
1365 const struct ar8327_led_info *led_info)
1367 struct ar8327_data *data = priv->chip_data;
1368 struct ar8327_led *aled;
1371 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1374 if (!led_info->name)
1377 if (led_info->led_num >= AR8327_NUM_LEDS)
1380 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1385 aled->sw_priv = priv;
1386 aled->led_num = led_info->led_num;
1387 aled->active_low = led_info->active_low;
1388 aled->mode = led_info->mode;
1390 if (aled->mode == AR8327_LED_MODE_HW)
1391 aled->enable_hw_mode = true;
1393 aled->name = (char *)(aled + 1);
1394 strcpy(aled->name, led_info->name);
1396 aled->cdev.name = aled->name;
1397 aled->cdev.brightness_set = ar8327_led_set_brightness;
1398 aled->cdev.blink_set = ar8327_led_blink_set;
1399 aled->cdev.default_trigger = led_info->default_trigger;
1401 spin_lock_init(&aled->lock);
1402 mutex_init(&aled->mutex);
1403 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1405 ret = ar8327_led_register(aled);
1409 data->leds[data->num_leds++] = aled;
1419 ar8327_led_destroy(struct ar8327_led *aled)
1421 ar8327_led_unregister(aled);
1426 ar8327_leds_init(struct ar8xxx_priv *priv)
1428 struct ar8327_data *data = priv->chip_data;
1431 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1434 for (i = 0; i < data->num_leds; i++) {
1435 struct ar8327_led *aled;
1437 aled = data->leds[i];
1439 if (aled->enable_hw_mode)
1440 aled->pattern = AR8327_LED_PATTERN_RULE;
1442 aled->pattern = AR8327_LED_PATTERN_OFF;
1444 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1449 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1451 struct ar8327_data *data = priv->chip_data;
1454 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1457 for (i = 0; i < data->num_leds; i++) {
1458 struct ar8327_led *aled;
1460 aled = data->leds[i];
1461 ar8327_led_destroy(aled);
1468 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1469 struct ar8327_platform_data *pdata)
1471 struct ar8327_led_cfg *led_cfg;
1472 struct ar8327_data *data = priv->chip_data;
1479 priv->get_port_link = pdata->get_port_link;
1481 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1482 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1484 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1485 if (chip_is_ar8337(priv))
1486 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1488 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
1489 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1490 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
1491 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1492 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
1494 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
1497 led_cfg = pdata->led_cfg;
1499 if (led_cfg->open_drain)
1500 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1502 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1504 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1505 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1506 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1507 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1510 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1513 if (pdata->sgmii_cfg) {
1514 t = pdata->sgmii_cfg->sgmii_ctrl;
1515 if (priv->chip_rev == 1)
1516 t |= AR8327_SGMII_CTRL_EN_PLL |
1517 AR8327_SGMII_CTRL_EN_RX |
1518 AR8327_SGMII_CTRL_EN_TX;
1520 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1521 AR8327_SGMII_CTRL_EN_RX |
1522 AR8327_SGMII_CTRL_EN_TX);
1524 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
1526 if (pdata->sgmii_cfg->serdes_aen)
1527 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1529 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1532 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1534 if (pdata->leds && pdata->num_leds) {
1537 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1542 for (i = 0; i < pdata->num_leds; i++)
1543 ar8327_led_create(priv, &pdata->leds[i]);
1551 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1553 struct ar8327_data *data = priv->chip_data;
1554 const __be32 *paddr;
1558 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1559 if (!paddr || len < (2 * sizeof(*paddr)))
1562 len /= sizeof(*paddr);
1564 for (i = 0; i < len - 1; i += 2) {
1568 reg = be32_to_cpup(paddr + i);
1569 val = be32_to_cpup(paddr + i + 1);
1572 case AR8327_REG_PORT_STATUS(0):
1573 data->port0_status = val;
1575 case AR8327_REG_PORT_STATUS(6):
1576 data->port6_status = val;
1579 ar8xxx_write(priv, reg, val);
1588 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1595 ar8327_hw_init(struct ar8xxx_priv *priv)
1599 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1600 if (!priv->chip_data)
1603 if (priv->phy->dev.of_node)
1604 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1606 ret = ar8327_hw_config_pdata(priv,
1607 priv->phy->dev.platform_data);
1612 ar8327_leds_init(priv);
1614 ar8xxx_phy_init(priv);
1620 ar8327_cleanup(struct ar8xxx_priv *priv)
1622 ar8327_leds_cleanup(priv);
1626 ar8327_init_globals(struct ar8xxx_priv *priv)
1630 /* enable CPU port and disable mirror port */
1631 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1632 AR8327_FWD_CTRL0_MIRROR_PORT;
1633 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
1635 /* forward multicast and broadcast frames to CPU */
1636 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1637 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1638 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1639 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
1641 /* enable jumbo frames */
1642 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1643 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1645 /* Enable MIB counters */
1646 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1647 AR8327_MODULE_EN_MIB);
1649 /* Disable EEE on all ports due to stability issues */
1650 t = ar8xxx_read(priv, AR8327_REG_EEE_CTRL);
1651 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1652 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1653 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1654 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1655 AR8327_EEE_CTRL_DISABLE_PHY(4);
1656 ar8xxx_write(priv, AR8327_REG_EEE_CTRL, t);
1660 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1662 struct ar8327_data *data = priv->chip_data;
1665 if (port == AR8216_PORT_CPU)
1666 t = data->port0_status;
1668 t = data->port6_status;
1670 t = AR8216_PORT_STATUS_LINK_AUTO;
1672 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
1673 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
1675 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1676 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1677 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1679 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1680 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1682 t = AR8327_PORT_LOOKUP_LEARN;
1683 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1684 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1688 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1690 return ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
1694 ar8327_atu_flush(struct ar8xxx_priv *priv)
1698 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1699 AR8327_ATU_FUNC_BUSY, 0);
1701 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
1702 AR8327_ATU_FUNC_OP_FLUSH);
1708 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1710 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1711 AR8327_VTU_FUNC1_BUSY, 0))
1714 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1715 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
1717 op |= AR8327_VTU_FUNC1_BUSY;
1718 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
1722 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1724 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1728 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1734 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1735 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1736 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1739 if ((port_mask & BIT(i)) == 0)
1740 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1741 else if (priv->vlan == 0)
1742 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1743 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1744 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1746 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1748 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1750 ar8327_vtu_op(priv, op, val);
1754 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1757 u32 egress, ingress;
1758 u32 pvid = priv->vlan_id[priv->pvid[port]];
1761 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1762 ingress = AR8216_IN_SECURE;
1764 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1765 ingress = AR8216_IN_PORT_ONLY;
1768 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1769 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1770 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1772 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1773 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1774 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1777 t |= AR8327_PORT_LOOKUP_LEARN;
1778 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1779 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1780 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1784 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1785 struct switch_val *val)
1787 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1788 priv->vlan = !!val->value.i;
1793 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1794 struct switch_val *val)
1796 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1797 val->value.i = priv->vlan;
1803 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1805 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1807 /* make sure no invalid PVIDs get set */
1809 if (vlan >= dev->vlans)
1812 priv->pvid[port] = vlan;
1817 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1819 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1820 *vlan = priv->pvid[port];
1825 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1826 struct switch_val *val)
1828 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1829 priv->vlan_id[val->port_vlan] = val->value.i;
1834 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1835 struct switch_val *val)
1837 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1838 val->value.i = priv->vlan_id[val->port_vlan];
1843 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1844 struct switch_port_link *link)
1846 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1848 ar8216_read_port_link(priv, port, link);
1853 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1855 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1856 u8 ports = priv->vlan_table[val->port_vlan];
1860 for (i = 0; i < dev->ports; i++) {
1861 struct switch_port *p;
1863 if (!(ports & (1 << i)))
1866 p = &val->value.ports[val->len++];
1868 if (priv->vlan_tagged & (1 << i))
1869 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1877 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1879 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1880 u8 ports = priv->vlan_table[val->port_vlan];
1884 for (i = 0; i < dev->ports; i++) {
1885 struct switch_port *p;
1887 if (!(ports & (1 << i)))
1890 p = &val->value.ports[val->len++];
1892 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1893 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1901 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1903 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1904 u8 *vt = &priv->vlan_table[val->port_vlan];
1908 for (i = 0; i < val->len; i++) {
1909 struct switch_port *p = &val->value.ports[i];
1911 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1912 priv->vlan_tagged |= (1 << p->id);
1914 priv->vlan_tagged &= ~(1 << p->id);
1915 priv->pvid[p->id] = val->port_vlan;
1917 /* make sure that an untagged port does not
1918 * appear in other vlans */
1919 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1920 if (j == val->port_vlan)
1922 priv->vlan_table[j] &= ~(1 << p->id);
1932 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1934 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1935 u8 *vt = &priv->vlan_table[val->port_vlan];
1939 for (i = 0; i < val->len; i++) {
1940 struct switch_port *p = &val->value.ports[i];
1942 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1943 if (val->port_vlan == priv->pvid[p->id]) {
1944 priv->vlan_tagged |= (1 << p->id);
1947 priv->vlan_tagged &= ~(1 << p->id);
1948 priv->pvid[p->id] = val->port_vlan;
1957 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1961 /* reset all mirror registers */
1962 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1963 AR8327_FWD_CTRL0_MIRROR_PORT,
1964 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1965 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1966 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1967 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1970 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1971 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1975 /* now enable mirroring if necessary */
1976 if (priv->source_port >= AR8327_NUM_PORTS ||
1977 priv->monitor_port >= AR8327_NUM_PORTS ||
1978 priv->source_port == priv->monitor_port) {
1982 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1983 AR8327_FWD_CTRL0_MIRROR_PORT,
1984 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1986 if (priv->mirror_rx)
1987 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1988 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1989 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1991 if (priv->mirror_tx)
1992 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1993 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1994 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1998 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2002 /* reset all mirror registers */
2003 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2004 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2005 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2006 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2007 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2008 AR8216_PORT_CTRL_MIRROR_RX,
2011 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2012 AR8216_PORT_CTRL_MIRROR_TX,
2016 /* now enable mirroring if necessary */
2017 if (priv->source_port >= AR8216_NUM_PORTS ||
2018 priv->monitor_port >= AR8216_NUM_PORTS ||
2019 priv->source_port == priv->monitor_port) {
2023 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2024 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2025 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2027 if (priv->mirror_rx)
2028 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2029 AR8216_PORT_CTRL_MIRROR_RX,
2030 AR8216_PORT_CTRL_MIRROR_RX);
2032 if (priv->mirror_tx)
2033 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2034 AR8216_PORT_CTRL_MIRROR_TX,
2035 AR8216_PORT_CTRL_MIRROR_TX);
2039 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2041 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2042 u8 portmask[AR8X16_MAX_PORTS];
2045 mutex_lock(&priv->reg_mutex);
2046 /* flush all vlan translation unit entries */
2047 priv->chip->vtu_flush(priv);
2049 memset(portmask, 0, sizeof(portmask));
2051 /* calculate the port destination masks and load vlans
2052 * into the vlan translation unit */
2053 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2054 u8 vp = priv->vlan_table[j];
2059 for (i = 0; i < dev->ports; i++) {
2062 portmask[i] |= vp & ~mask;
2065 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2066 priv->vlan_table[j]);
2070 * isolate all ports, but connect them to the cpu port */
2071 for (i = 0; i < dev->ports; i++) {
2072 if (i == AR8216_PORT_CPU)
2075 portmask[i] = 1 << AR8216_PORT_CPU;
2076 portmask[AR8216_PORT_CPU] |= (1 << i);
2080 /* update the port destination mask registers and tag settings */
2081 for (i = 0; i < dev->ports; i++) {
2082 priv->chip->setup_port(priv, i, portmask[i]);
2085 priv->chip->set_mirror_regs(priv);
2087 mutex_unlock(&priv->reg_mutex);
2092 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2094 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2097 mutex_lock(&priv->reg_mutex);
2098 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2099 offsetof(struct ar8xxx_priv, vlan));
2101 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2102 priv->vlan_id[i] = i;
2104 /* Configure all ports */
2105 for (i = 0; i < dev->ports; i++)
2106 priv->chip->init_port(priv, i);
2108 priv->mirror_rx = false;
2109 priv->mirror_tx = false;
2110 priv->source_port = 0;
2111 priv->monitor_port = 0;
2113 priv->chip->init_globals(priv);
2115 mutex_unlock(&priv->reg_mutex);
2117 return ar8xxx_sw_hw_apply(dev);
2121 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2122 const struct switch_attr *attr,
2123 struct switch_val *val)
2125 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2129 if (!ar8xxx_has_mib_counters(priv))
2132 mutex_lock(&priv->mib_lock);
2134 len = priv->dev.ports * priv->chip->num_mibs *
2135 sizeof(*priv->mib_stats);
2136 memset(priv->mib_stats, '\0', len);
2137 ret = ar8xxx_mib_flush(priv);
2144 mutex_unlock(&priv->mib_lock);
2149 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2150 const struct switch_attr *attr,
2151 struct switch_val *val)
2153 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2155 mutex_lock(&priv->reg_mutex);
2156 priv->mirror_rx = !!val->value.i;
2157 priv->chip->set_mirror_regs(priv);
2158 mutex_unlock(&priv->reg_mutex);
2164 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2165 const struct switch_attr *attr,
2166 struct switch_val *val)
2168 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2169 val->value.i = priv->mirror_rx;
2174 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2175 const struct switch_attr *attr,
2176 struct switch_val *val)
2178 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2180 mutex_lock(&priv->reg_mutex);
2181 priv->mirror_tx = !!val->value.i;
2182 priv->chip->set_mirror_regs(priv);
2183 mutex_unlock(&priv->reg_mutex);
2189 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2190 const struct switch_attr *attr,
2191 struct switch_val *val)
2193 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2194 val->value.i = priv->mirror_tx;
2199 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2200 const struct switch_attr *attr,
2201 struct switch_val *val)
2203 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2205 mutex_lock(&priv->reg_mutex);
2206 priv->monitor_port = val->value.i;
2207 priv->chip->set_mirror_regs(priv);
2208 mutex_unlock(&priv->reg_mutex);
2214 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2215 const struct switch_attr *attr,
2216 struct switch_val *val)
2218 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2219 val->value.i = priv->monitor_port;
2224 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2225 const struct switch_attr *attr,
2226 struct switch_val *val)
2228 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2230 mutex_lock(&priv->reg_mutex);
2231 priv->source_port = val->value.i;
2232 priv->chip->set_mirror_regs(priv);
2233 mutex_unlock(&priv->reg_mutex);
2239 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2240 const struct switch_attr *attr,
2241 struct switch_val *val)
2243 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2244 val->value.i = priv->source_port;
2249 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2250 const struct switch_attr *attr,
2251 struct switch_val *val)
2253 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2257 if (!ar8xxx_has_mib_counters(priv))
2260 port = val->port_vlan;
2261 if (port >= dev->ports)
2264 mutex_lock(&priv->mib_lock);
2265 ret = ar8xxx_mib_capture(priv);
2269 ar8xxx_mib_fetch_port_stat(priv, port, true);
2274 mutex_unlock(&priv->mib_lock);
2279 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2280 const struct switch_attr *attr,
2281 struct switch_val *val)
2283 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2284 const struct ar8xxx_chip *chip = priv->chip;
2288 char *buf = priv->buf;
2291 if (!ar8xxx_has_mib_counters(priv))
2294 port = val->port_vlan;
2295 if (port >= dev->ports)
2298 mutex_lock(&priv->mib_lock);
2299 ret = ar8xxx_mib_capture(priv);
2303 ar8xxx_mib_fetch_port_stat(priv, port, false);
2305 len += snprintf(buf + len, sizeof(priv->buf) - len,
2306 "Port %d MIB counters\n",
2309 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2310 for (i = 0; i < chip->num_mibs; i++)
2311 len += snprintf(buf + len, sizeof(priv->buf) - len,
2313 chip->mib_decs[i].name,
2322 mutex_unlock(&priv->mib_lock);
2326 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2328 .type = SWITCH_TYPE_INT,
2329 .name = "enable_vlan",
2330 .description = "Enable VLAN mode",
2331 .set = ar8xxx_sw_set_vlan,
2332 .get = ar8xxx_sw_get_vlan,
2336 .type = SWITCH_TYPE_NOVAL,
2337 .name = "reset_mibs",
2338 .description = "Reset all MIB counters",
2339 .set = ar8xxx_sw_set_reset_mibs,
2342 .type = SWITCH_TYPE_INT,
2343 .name = "enable_mirror_rx",
2344 .description = "Enable mirroring of RX packets",
2345 .set = ar8xxx_sw_set_mirror_rx_enable,
2346 .get = ar8xxx_sw_get_mirror_rx_enable,
2350 .type = SWITCH_TYPE_INT,
2351 .name = "enable_mirror_tx",
2352 .description = "Enable mirroring of TX packets",
2353 .set = ar8xxx_sw_set_mirror_tx_enable,
2354 .get = ar8xxx_sw_get_mirror_tx_enable,
2358 .type = SWITCH_TYPE_INT,
2359 .name = "mirror_monitor_port",
2360 .description = "Mirror monitor port",
2361 .set = ar8xxx_sw_set_mirror_monitor_port,
2362 .get = ar8xxx_sw_get_mirror_monitor_port,
2363 .max = AR8216_NUM_PORTS - 1
2366 .type = SWITCH_TYPE_INT,
2367 .name = "mirror_source_port",
2368 .description = "Mirror source port",
2369 .set = ar8xxx_sw_set_mirror_source_port,
2370 .get = ar8xxx_sw_get_mirror_source_port,
2371 .max = AR8216_NUM_PORTS - 1
2375 static struct switch_attr ar8327_sw_attr_globals[] = {
2377 .type = SWITCH_TYPE_INT,
2378 .name = "enable_vlan",
2379 .description = "Enable VLAN mode",
2380 .set = ar8xxx_sw_set_vlan,
2381 .get = ar8xxx_sw_get_vlan,
2385 .type = SWITCH_TYPE_NOVAL,
2386 .name = "reset_mibs",
2387 .description = "Reset all MIB counters",
2388 .set = ar8xxx_sw_set_reset_mibs,
2391 .type = SWITCH_TYPE_INT,
2392 .name = "enable_mirror_rx",
2393 .description = "Enable mirroring of RX packets",
2394 .set = ar8xxx_sw_set_mirror_rx_enable,
2395 .get = ar8xxx_sw_get_mirror_rx_enable,
2399 .type = SWITCH_TYPE_INT,
2400 .name = "enable_mirror_tx",
2401 .description = "Enable mirroring of TX packets",
2402 .set = ar8xxx_sw_set_mirror_tx_enable,
2403 .get = ar8xxx_sw_get_mirror_tx_enable,
2407 .type = SWITCH_TYPE_INT,
2408 .name = "mirror_monitor_port",
2409 .description = "Mirror monitor port",
2410 .set = ar8xxx_sw_set_mirror_monitor_port,
2411 .get = ar8xxx_sw_get_mirror_monitor_port,
2412 .max = AR8327_NUM_PORTS - 1
2415 .type = SWITCH_TYPE_INT,
2416 .name = "mirror_source_port",
2417 .description = "Mirror source port",
2418 .set = ar8xxx_sw_set_mirror_source_port,
2419 .get = ar8xxx_sw_get_mirror_source_port,
2420 .max = AR8327_NUM_PORTS - 1
2424 static struct switch_attr ar8xxx_sw_attr_port[] = {
2426 .type = SWITCH_TYPE_NOVAL,
2427 .name = "reset_mib",
2428 .description = "Reset single port MIB counters",
2429 .set = ar8xxx_sw_set_port_reset_mib,
2432 .type = SWITCH_TYPE_STRING,
2434 .description = "Get port's MIB counters",
2436 .get = ar8xxx_sw_get_port_mib,
2440 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2442 .type = SWITCH_TYPE_INT,
2444 .description = "VLAN ID (0-4094)",
2445 .set = ar8xxx_sw_set_vid,
2446 .get = ar8xxx_sw_get_vid,
2451 static const struct switch_dev_ops ar8xxx_sw_ops = {
2453 .attr = ar8xxx_sw_attr_globals,
2454 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2457 .attr = ar8xxx_sw_attr_port,
2458 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2461 .attr = ar8xxx_sw_attr_vlan,
2462 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2464 .get_port_pvid = ar8xxx_sw_get_pvid,
2465 .set_port_pvid = ar8xxx_sw_set_pvid,
2466 .get_vlan_ports = ar8xxx_sw_get_ports,
2467 .set_vlan_ports = ar8xxx_sw_set_ports,
2468 .apply_config = ar8xxx_sw_hw_apply,
2469 .reset_switch = ar8xxx_sw_reset_switch,
2470 .get_port_link = ar8xxx_sw_get_port_link,
2473 static const struct switch_dev_ops ar8327_sw_ops = {
2475 .attr = ar8327_sw_attr_globals,
2476 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2479 .attr = ar8xxx_sw_attr_port,
2480 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2483 .attr = ar8xxx_sw_attr_vlan,
2484 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2486 .get_port_pvid = ar8xxx_sw_get_pvid,
2487 .set_port_pvid = ar8xxx_sw_set_pvid,
2488 .get_vlan_ports = ar8327_sw_get_ports,
2489 .set_vlan_ports = ar8327_sw_set_ports,
2490 .apply_config = ar8xxx_sw_hw_apply,
2491 .reset_switch = ar8xxx_sw_reset_switch,
2492 .get_port_link = ar8xxx_sw_get_port_link,
2495 static const struct ar8xxx_chip ar8216_chip = {
2496 .caps = AR8XXX_CAP_MIB_COUNTERS,
2498 .reg_port_stats_start = 0x19000,
2499 .reg_port_stats_length = 0xa0,
2501 .name = "Atheros AR8216",
2502 .ports = AR8216_NUM_PORTS,
2503 .vlans = AR8216_NUM_VLANS,
2504 .swops = &ar8xxx_sw_ops,
2506 .hw_init = ar8216_hw_init,
2507 .init_globals = ar8216_init_globals,
2508 .init_port = ar8216_init_port,
2509 .setup_port = ar8216_setup_port,
2510 .read_port_status = ar8216_read_port_status,
2511 .atu_flush = ar8216_atu_flush,
2512 .vtu_flush = ar8216_vtu_flush,
2513 .vtu_load_vlan = ar8216_vtu_load_vlan,
2514 .set_mirror_regs = ar8216_set_mirror_regs,
2516 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2517 .mib_decs = ar8216_mibs,
2518 .mib_func = AR8216_REG_MIB_FUNC
2521 static const struct ar8xxx_chip ar8236_chip = {
2522 .caps = AR8XXX_CAP_MIB_COUNTERS,
2524 .reg_port_stats_start = 0x20000,
2525 .reg_port_stats_length = 0x100,
2527 .name = "Atheros AR8236",
2528 .ports = AR8216_NUM_PORTS,
2529 .vlans = AR8216_NUM_VLANS,
2530 .swops = &ar8xxx_sw_ops,
2532 .hw_init = ar8216_hw_init,
2533 .init_globals = ar8236_init_globals,
2534 .init_port = ar8216_init_port,
2535 .setup_port = ar8236_setup_port,
2536 .read_port_status = ar8216_read_port_status,
2537 .atu_flush = ar8216_atu_flush,
2538 .vtu_flush = ar8216_vtu_flush,
2539 .vtu_load_vlan = ar8216_vtu_load_vlan,
2540 .set_mirror_regs = ar8216_set_mirror_regs,
2542 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2543 .mib_decs = ar8236_mibs,
2544 .mib_func = AR8216_REG_MIB_FUNC
2547 static const struct ar8xxx_chip ar8316_chip = {
2548 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2550 .reg_port_stats_start = 0x20000,
2551 .reg_port_stats_length = 0x100,
2553 .name = "Atheros AR8316",
2554 .ports = AR8216_NUM_PORTS,
2555 .vlans = AR8X16_MAX_VLANS,
2556 .swops = &ar8xxx_sw_ops,
2558 .hw_init = ar8316_hw_init,
2559 .init_globals = ar8316_init_globals,
2560 .init_port = ar8216_init_port,
2561 .setup_port = ar8216_setup_port,
2562 .read_port_status = ar8216_read_port_status,
2563 .atu_flush = ar8216_atu_flush,
2564 .vtu_flush = ar8216_vtu_flush,
2565 .vtu_load_vlan = ar8216_vtu_load_vlan,
2566 .set_mirror_regs = ar8216_set_mirror_regs,
2568 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2569 .mib_decs = ar8236_mibs,
2570 .mib_func = AR8216_REG_MIB_FUNC
2573 static const struct ar8xxx_chip ar8327_chip = {
2574 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2575 .config_at_probe = true,
2576 .mii_lo_first = true,
2578 .name = "Atheros AR8327",
2579 .ports = AR8327_NUM_PORTS,
2580 .vlans = AR8X16_MAX_VLANS,
2581 .swops = &ar8327_sw_ops,
2583 .reg_port_stats_start = 0x1000,
2584 .reg_port_stats_length = 0x100,
2586 .hw_init = ar8327_hw_init,
2587 .cleanup = ar8327_cleanup,
2588 .init_globals = ar8327_init_globals,
2589 .init_port = ar8327_init_port,
2590 .setup_port = ar8327_setup_port,
2591 .read_port_status = ar8327_read_port_status,
2592 .atu_flush = ar8327_atu_flush,
2593 .vtu_flush = ar8327_vtu_flush,
2594 .vtu_load_vlan = ar8327_vtu_load_vlan,
2595 .phy_fixup = ar8327_phy_fixup,
2596 .set_mirror_regs = ar8327_set_mirror_regs,
2598 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2599 .mib_decs = ar8236_mibs,
2600 .mib_func = AR8327_REG_MIB_FUNC
2603 static const struct ar8xxx_chip ar8337_chip = {
2604 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2605 .config_at_probe = true,
2606 .mii_lo_first = true,
2608 .name = "Atheros AR8337",
2609 .ports = AR8327_NUM_PORTS,
2610 .vlans = AR8X16_MAX_VLANS,
2611 .swops = &ar8327_sw_ops,
2613 .reg_port_stats_start = 0x1000,
2614 .reg_port_stats_length = 0x100,
2616 .hw_init = ar8327_hw_init,
2617 .cleanup = ar8327_cleanup,
2618 .init_globals = ar8327_init_globals,
2619 .init_port = ar8327_init_port,
2620 .setup_port = ar8327_setup_port,
2621 .read_port_status = ar8327_read_port_status,
2622 .atu_flush = ar8327_atu_flush,
2623 .vtu_flush = ar8327_vtu_flush,
2624 .vtu_load_vlan = ar8327_vtu_load_vlan,
2625 .phy_fixup = ar8327_phy_fixup,
2626 .set_mirror_regs = ar8327_set_mirror_regs,
2628 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2629 .mib_decs = ar8236_mibs,
2630 .mib_func = AR8327_REG_MIB_FUNC
2634 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2640 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2644 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2645 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2648 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2652 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2657 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2658 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2660 switch (priv->chip_ver) {
2661 case AR8XXX_VER_AR8216:
2662 priv->chip = &ar8216_chip;
2664 case AR8XXX_VER_AR8236:
2665 priv->chip = &ar8236_chip;
2667 case AR8XXX_VER_AR8316:
2668 priv->chip = &ar8316_chip;
2670 case AR8XXX_VER_AR8327:
2671 priv->chip = &ar8327_chip;
2673 case AR8XXX_VER_AR8337:
2674 priv->chip = &ar8337_chip;
2677 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2678 priv->chip_ver, priv->chip_rev);
2687 ar8xxx_mib_work_func(struct work_struct *work)
2689 struct ar8xxx_priv *priv;
2692 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2694 mutex_lock(&priv->mib_lock);
2696 err = ar8xxx_mib_capture(priv);
2700 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2703 priv->mib_next_port++;
2704 if (priv->mib_next_port >= priv->dev.ports)
2705 priv->mib_next_port = 0;
2707 mutex_unlock(&priv->mib_lock);
2708 schedule_delayed_work(&priv->mib_work,
2709 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2713 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2717 if (!ar8xxx_has_mib_counters(priv))
2720 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2722 len = priv->dev.ports * priv->chip->num_mibs *
2723 sizeof(*priv->mib_stats);
2724 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2726 if (!priv->mib_stats)
2733 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2735 if (!ar8xxx_has_mib_counters(priv))
2738 schedule_delayed_work(&priv->mib_work,
2739 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2743 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2745 if (!ar8xxx_has_mib_counters(priv))
2748 cancel_delayed_work(&priv->mib_work);
2751 static struct ar8xxx_priv *
2754 struct ar8xxx_priv *priv;
2756 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2760 mutex_init(&priv->reg_mutex);
2761 mutex_init(&priv->mib_lock);
2762 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2768 ar8xxx_free(struct ar8xxx_priv *priv)
2770 if (priv->chip && priv->chip->cleanup)
2771 priv->chip->cleanup(priv);
2773 kfree(priv->chip_data);
2774 kfree(priv->mib_stats);
2778 static struct ar8xxx_priv *
2779 ar8xxx_create_mii(struct mii_bus *bus)
2781 struct ar8xxx_priv *priv;
2783 priv = ar8xxx_create();
2785 priv->mii_bus = bus;
2791 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2793 const struct ar8xxx_chip *chip;
2794 struct switch_dev *swdev;
2797 ret = ar8xxx_id_chip(priv);
2804 swdev->cpu_port = AR8216_PORT_CPU;
2805 swdev->name = chip->name;
2806 swdev->vlans = chip->vlans;
2807 swdev->ports = chip->ports;
2808 swdev->ops = chip->swops;
2810 ret = ar8xxx_mib_init(priv);
2818 ar8xxx_start(struct ar8xxx_priv *priv)
2824 ret = priv->chip->hw_init(priv);
2828 ret = ar8xxx_sw_reset_switch(&priv->dev);
2834 ar8xxx_mib_start(priv);
2840 ar8xxx_phy_config_init(struct phy_device *phydev)
2842 struct ar8xxx_priv *priv = phydev->priv;
2843 struct net_device *dev = phydev->attached_dev;
2849 if (priv->chip->config_at_probe)
2850 return ar8xxx_phy_check_aneg(phydev);
2854 if (phydev->addr != 0) {
2855 if (chip_is_ar8316(priv)) {
2856 /* switch device has been initialized, reinit */
2857 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2858 priv->initialized = false;
2859 priv->port4_phy = true;
2860 ar8316_hw_init(priv);
2867 ret = ar8xxx_start(priv);
2871 /* VID fixup only needed on ar8216 */
2872 if (chip_is_ar8216(priv)) {
2873 dev->phy_ptr = priv;
2874 dev->priv_flags |= IFF_NO_IP_ALIGN;
2875 dev->eth_mangle_rx = ar8216_mangle_rx;
2876 dev->eth_mangle_tx = ar8216_mangle_tx;
2883 ar8xxx_phy_read_status(struct phy_device *phydev)
2885 struct ar8xxx_priv *priv = phydev->priv;
2886 struct switch_port_link link;
2889 if (phydev->addr != 0)
2890 return genphy_read_status(phydev);
2892 ar8216_read_port_link(priv, phydev->addr, &link);
2893 phydev->link = !!link.link;
2897 switch (link.speed) {
2898 case SWITCH_PORT_SPEED_10:
2899 phydev->speed = SPEED_10;
2901 case SWITCH_PORT_SPEED_100:
2902 phydev->speed = SPEED_100;
2904 case SWITCH_PORT_SPEED_1000:
2905 phydev->speed = SPEED_1000;
2910 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2912 /* flush the address translation unit */
2913 mutex_lock(&priv->reg_mutex);
2914 ret = priv->chip->atu_flush(priv);
2915 mutex_unlock(&priv->reg_mutex);
2917 phydev->state = PHY_RUNNING;
2918 netif_carrier_on(phydev->attached_dev);
2919 phydev->adjust_link(phydev->attached_dev);
2925 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2927 if (phydev->addr == 0)
2930 return genphy_config_aneg(phydev);
2933 static const u32 ar8xxx_phy_ids[] = {
2935 0x004dd034, /* AR8327 */
2936 0x004dd036, /* AR8337 */
2939 0x004dd043, /* AR8236 */
2943 ar8xxx_phy_match(u32 phy_id)
2947 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2948 if (phy_id == ar8xxx_phy_ids[i])
2955 ar8xxx_is_possible(struct mii_bus *bus)
2959 for (i = 0; i < 4; i++) {
2962 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2963 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2964 if (!ar8xxx_phy_match(phy_id)) {
2965 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2966 dev_name(&bus->dev), i, phy_id);
2975 ar8xxx_phy_probe(struct phy_device *phydev)
2977 struct ar8xxx_priv *priv;
2978 struct switch_dev *swdev;
2981 /* skip PHYs at unused adresses */
2982 if (phydev->addr != 0 && phydev->addr != 4)
2985 if (!ar8xxx_is_possible(phydev->bus))
2988 mutex_lock(&ar8xxx_dev_list_lock);
2989 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2990 if (priv->mii_bus == phydev->bus)
2993 priv = ar8xxx_create_mii(phydev->bus);
2999 ret = ar8xxx_probe_switch(priv);
3004 swdev->alias = dev_name(&priv->mii_bus->dev);
3005 ret = register_switch(swdev, NULL);
3009 pr_info("%s: %s rev. %u switch registered on %s\n",
3010 swdev->devname, swdev->name, priv->chip_rev,
3011 dev_name(&priv->mii_bus->dev));
3016 if (phydev->addr == 0) {
3017 if (ar8xxx_has_gige(priv)) {
3018 phydev->supported = SUPPORTED_1000baseT_Full;
3019 phydev->advertising = ADVERTISED_1000baseT_Full;
3021 phydev->supported = SUPPORTED_100baseT_Full;
3022 phydev->advertising = ADVERTISED_100baseT_Full;
3025 if (priv->chip->config_at_probe) {
3028 ret = ar8xxx_start(priv);
3030 goto err_unregister_switch;
3033 if (ar8xxx_has_gige(priv)) {
3034 phydev->supported |= SUPPORTED_1000baseT_Full;
3035 phydev->advertising |= ADVERTISED_1000baseT_Full;
3039 phydev->priv = priv;
3041 list_add(&priv->list, &ar8xxx_dev_list);
3043 mutex_unlock(&ar8xxx_dev_list_lock);
3047 err_unregister_switch:
3048 if (--priv->use_count)
3051 unregister_switch(&priv->dev);
3056 mutex_unlock(&ar8xxx_dev_list_lock);
3061 ar8xxx_phy_detach(struct phy_device *phydev)
3063 struct net_device *dev = phydev->attached_dev;
3068 dev->phy_ptr = NULL;
3069 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3070 dev->eth_mangle_rx = NULL;
3071 dev->eth_mangle_tx = NULL;
3075 ar8xxx_phy_remove(struct phy_device *phydev)
3077 struct ar8xxx_priv *priv = phydev->priv;
3082 phydev->priv = NULL;
3083 if (--priv->use_count > 0)
3086 mutex_lock(&ar8xxx_dev_list_lock);
3087 list_del(&priv->list);
3088 mutex_unlock(&ar8xxx_dev_list_lock);
3090 unregister_switch(&priv->dev);
3091 ar8xxx_mib_stop(priv);
3095 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3097 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3099 /* we don't need an extra reset */
3104 static struct phy_driver ar8xxx_phy_driver = {
3105 .phy_id = 0x004d0000,
3106 .name = "Atheros AR8216/AR8236/AR8316",
3107 .phy_id_mask = 0xffff0000,
3108 .features = PHY_BASIC_FEATURES,
3109 .probe = ar8xxx_phy_probe,
3110 .remove = ar8xxx_phy_remove,
3111 .detach = ar8xxx_phy_detach,
3112 .config_init = ar8xxx_phy_config_init,
3113 .config_aneg = ar8xxx_phy_config_aneg,
3114 .read_status = ar8xxx_phy_read_status,
3115 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3116 .soft_reset = ar8xxx_phy_soft_reset,
3118 .driver = { .owner = THIS_MODULE },
3124 return phy_driver_register(&ar8xxx_phy_driver);
3130 phy_driver_unregister(&ar8xxx_phy_driver);
3133 module_init(ar8xxx_init);
3134 module_exit(ar8xxx_exit);
3135 MODULE_LICENSE("GPL");