2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54 #define AR8XXX_NUM_PHYS 5
57 AR8XXX_VER_AR8216 = 0x01,
58 AR8XXX_VER_AR8236 = 0x03,
59 AR8XXX_VER_AR8316 = 0x10,
60 AR8XXX_VER_AR8327 = 0x12,
61 AR8XXX_VER_AR8337 = 0x13,
64 struct ar8xxx_mib_desc {
73 int (*hw_init)(struct ar8xxx_priv *priv);
74 void (*cleanup)(struct ar8xxx_priv *priv);
76 void (*init_globals)(struct ar8xxx_priv *priv);
77 void (*init_port)(struct ar8xxx_priv *priv, int port);
78 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
79 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
80 int (*atu_flush)(struct ar8xxx_priv *priv);
81 void (*vtu_flush)(struct ar8xxx_priv *priv);
82 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
83 void (*fixup_phys)(struct ar8xxx_priv *priv);
85 const struct ar8xxx_mib_desc *mib_decs;
89 enum ar8327_led_pattern {
90 AR8327_LED_PATTERN_OFF = 0,
91 AR8327_LED_PATTERN_BLINK,
92 AR8327_LED_PATTERN_ON,
93 AR8327_LED_PATTERN_RULE,
96 struct ar8327_led_entry {
102 struct led_classdev cdev;
103 struct ar8xxx_priv *sw_priv;
108 enum ar8327_led_mode mode;
112 struct work_struct led_work;
114 enum ar8327_led_pattern pattern;
121 struct ar8327_led **leds;
122 unsigned int num_leds;
126 struct switch_dev dev;
127 struct mii_bus *mii_bus;
128 struct phy_device *phy;
130 u32 (*read)(struct ar8xxx_priv *priv, int reg);
131 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
132 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
134 int (*get_port_link)(unsigned port);
136 const struct net_device_ops *ndo_old;
137 struct net_device_ops ndo;
138 struct mutex reg_mutex;
141 const struct ar8xxx_chip *chip;
143 struct ar8327_data ar8327;
152 struct mutex mib_lock;
153 struct delayed_work mib_work;
157 struct list_head list;
158 unsigned int use_count;
160 /* all fields below are cleared on reset */
162 u16 vlan_id[AR8X16_MAX_VLANS];
163 u8 vlan_table[AR8X16_MAX_VLANS];
165 u16 pvid[AR8X16_MAX_PORTS];
174 #define MIB_DESC(_s , _o, _n) \
181 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
182 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
183 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
184 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
185 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
186 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
187 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
188 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
189 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
190 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
191 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
192 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
193 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
194 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
195 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
196 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
197 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
198 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
199 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
200 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
201 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
202 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
203 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
204 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
205 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
206 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
207 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
208 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
209 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
210 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
211 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
212 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
213 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
214 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
215 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
216 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
217 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
218 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
221 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
222 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
223 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
224 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
225 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
226 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
227 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
228 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
229 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
230 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
231 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
232 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
235 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
236 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
237 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
238 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
239 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
240 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
241 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
242 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
243 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
244 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
245 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
246 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
247 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
248 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
251 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
252 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
253 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
254 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
255 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
256 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
257 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
258 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
259 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
260 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
263 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
264 static LIST_HEAD(ar8xxx_dev_list);
266 static inline struct ar8xxx_priv *
267 swdev_to_ar8xxx(struct switch_dev *swdev)
269 return container_of(swdev, struct ar8xxx_priv, dev);
272 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
274 return priv->chip->caps & AR8XXX_CAP_GIGE;
277 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
279 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
282 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
284 return priv->chip_ver == AR8XXX_VER_AR8216;
287 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
289 return priv->chip_ver == AR8XXX_VER_AR8236;
292 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
294 return priv->chip_ver == AR8XXX_VER_AR8316;
297 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
299 return priv->chip_ver == AR8XXX_VER_AR8327;
302 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
304 return priv->chip_ver == AR8XXX_VER_AR8337;
308 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
311 *r1 = regaddr & 0x1e;
317 *page = regaddr & 0x1ff;
320 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
322 ar8xxx_phy_poll_reset(struct mii_bus *bus)
324 unsigned int sleep_msecs = 20;
327 for (elapsed = sleep_msecs; elapsed <= 600;
328 elapsed += sleep_msecs) {
330 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
331 ret = mdiobus_read(bus, i, MII_BMCR);
334 if (ret & BMCR_RESET)
336 if (i == AR8XXX_NUM_PHYS - 1) {
337 usleep_range(1000, 2000);
346 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
348 struct mii_bus *bus = priv->mii_bus;
352 split_addr((u32) reg, &r1, &r2, &page);
354 mutex_lock(&bus->mdio_lock);
356 bus->write(bus, 0x18, 0, page);
357 usleep_range(1000, 2000); /* wait for the page switch to propagate */
358 lo = bus->read(bus, 0x10 | r2, r1);
359 hi = bus->read(bus, 0x10 | r2, r1 + 1);
361 mutex_unlock(&bus->mdio_lock);
363 return (hi << 16) | lo;
367 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
369 struct mii_bus *bus = priv->mii_bus;
373 split_addr((u32) reg, &r1, &r2, &r3);
375 hi = (u16) (val >> 16);
377 mutex_lock(&bus->mdio_lock);
379 bus->write(bus, 0x18, 0, r3);
380 usleep_range(1000, 2000); /* wait for the page switch to propagate */
381 if (priv->mii_lo_first) {
382 bus->write(bus, 0x10 | r2, r1, lo);
383 bus->write(bus, 0x10 | r2, r1 + 1, hi);
385 bus->write(bus, 0x10 | r2, r1 + 1, hi);
386 bus->write(bus, 0x10 | r2, r1, lo);
389 mutex_unlock(&bus->mdio_lock);
393 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
395 struct mii_bus *bus = priv->mii_bus;
400 split_addr((u32) reg, &r1, &r2, &page);
402 mutex_lock(&bus->mdio_lock);
404 bus->write(bus, 0x18, 0, page);
405 usleep_range(1000, 2000); /* wait for the page switch to propagate */
407 lo = bus->read(bus, 0x10 | r2, r1);
408 hi = bus->read(bus, 0x10 | r2, r1 + 1);
415 hi = (u16) (ret >> 16);
417 if (priv->mii_lo_first) {
418 bus->write(bus, 0x10 | r2, r1, lo);
419 bus->write(bus, 0x10 | r2, r1 + 1, hi);
421 bus->write(bus, 0x10 | r2, r1 + 1, hi);
422 bus->write(bus, 0x10 | r2, r1, lo);
425 mutex_unlock(&bus->mdio_lock);
432 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
433 u16 dbg_addr, u16 dbg_data)
435 struct mii_bus *bus = priv->mii_bus;
437 mutex_lock(&bus->mdio_lock);
438 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
439 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
440 mutex_unlock(&bus->mdio_lock);
444 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
446 struct mii_bus *bus = priv->mii_bus;
448 mutex_lock(&bus->mdio_lock);
449 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
450 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
451 mutex_unlock(&bus->mdio_lock);
455 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
457 return priv->rmw(priv, reg, mask, val);
461 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
463 priv->rmw(priv, reg, 0, val);
467 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
472 for (i = 0; i < timeout; i++) {
475 t = priv->read(priv, reg);
476 if ((t & mask) == val)
479 usleep_range(1000, 2000);
486 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
491 lockdep_assert_held(&priv->mib_lock);
493 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
494 mib_func = AR8327_REG_MIB_FUNC;
496 mib_func = AR8216_REG_MIB_FUNC;
498 /* Capture the hardware statistics for all ports */
499 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
501 /* Wait for the capturing to complete. */
502 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
513 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
515 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
519 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
521 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
525 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
531 WARN_ON(port >= priv->dev.ports);
533 lockdep_assert_held(&priv->mib_lock);
535 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
536 base = AR8327_REG_PORT_STATS_BASE(port);
537 else if (chip_is_ar8236(priv) ||
538 chip_is_ar8316(priv))
539 base = AR8236_REG_PORT_STATS_BASE(port);
541 base = AR8216_REG_PORT_STATS_BASE(port);
543 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
544 for (i = 0; i < priv->chip->num_mibs; i++) {
545 const struct ar8xxx_mib_desc *mib;
548 mib = &priv->chip->mib_decs[i];
549 t = priv->read(priv, base + mib->offset);
550 if (mib->size == 2) {
553 hi = priv->read(priv, base + mib->offset + 4);
565 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
566 struct switch_port_link *link)
571 memset(link, '\0', sizeof(*link));
573 status = priv->chip->read_port_status(priv, port);
575 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
577 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
581 if (priv->get_port_link) {
584 err = priv->get_port_link(port);
593 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
594 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
595 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
597 speed = (status & AR8216_PORT_STATUS_SPEED) >>
598 AR8216_PORT_STATUS_SPEED_S;
601 case AR8216_PORT_SPEED_10M:
602 link->speed = SWITCH_PORT_SPEED_10;
604 case AR8216_PORT_SPEED_100M:
605 link->speed = SWITCH_PORT_SPEED_100;
607 case AR8216_PORT_SPEED_1000M:
608 link->speed = SWITCH_PORT_SPEED_1000;
611 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
616 static struct sk_buff *
617 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
619 struct ar8xxx_priv *priv = dev->phy_ptr;
628 if (unlikely(skb_headroom(skb) < 2)) {
629 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
633 buf = skb_push(skb, 2);
641 dev_kfree_skb_any(skb);
646 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
648 struct ar8xxx_priv *priv;
656 /* don't strip the header if vlan mode is disabled */
660 /* strip header, get vlan id */
664 /* check for vlan header presence */
665 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
670 /* no need to fix up packets coming from a tagged source */
671 if (priv->vlan_tagged & (1 << port))
674 /* lookup port vid from local table, the switch passes an invalid vlan id */
675 vlan = priv->vlan_id[priv->pvid[port]];
678 buf[14 + 2] |= vlan >> 8;
679 buf[15 + 2] = vlan & 0xff;
683 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
689 t = priv->read(priv, reg);
690 if ((t & mask) == val)
699 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
700 (unsigned int) reg, t, mask, val);
705 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
707 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
709 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
710 val &= AR8216_VTUDATA_MEMBER;
711 val |= AR8216_VTUDATA_VALID;
712 priv->write(priv, AR8216_REG_VTU_DATA, val);
714 op |= AR8216_VTU_ACTIVE;
715 priv->write(priv, AR8216_REG_VTU, op);
719 ar8216_vtu_flush(struct ar8xxx_priv *priv)
721 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
725 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
729 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
730 ar8216_vtu_op(priv, op, port_mask);
734 ar8216_atu_flush(struct ar8xxx_priv *priv)
738 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
740 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
746 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
748 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
752 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
759 pvid = priv->vlan_id[priv->pvid[port]];
760 if (priv->vlan_tagged & (1 << port))
761 egress = AR8216_OUT_ADD_VLAN;
763 egress = AR8216_OUT_STRIP_VLAN;
764 ingress = AR8216_IN_SECURE;
767 egress = AR8216_OUT_KEEP;
768 ingress = AR8216_IN_PORT_ONLY;
771 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
772 header = AR8216_PORT_CTRL_HEADER;
776 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
777 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
778 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
779 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
780 AR8216_PORT_CTRL_LEARN | header |
781 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
782 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
784 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
785 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
786 AR8216_PORT_VLAN_DEFAULT_ID,
787 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
788 (ingress << AR8216_PORT_VLAN_MODE_S) |
789 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
793 ar8216_hw_init(struct ar8xxx_priv *priv)
799 ar8216_init_globals(struct ar8xxx_priv *priv)
801 /* standard atheros magic */
802 priv->write(priv, 0x38, 0xc000050e);
804 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
805 AR8216_GCTRL_MTU, 1518 + 8 + 2);
809 ar8216_init_port(struct ar8xxx_priv *priv, int port)
811 /* Enable port learning and tx */
812 priv->write(priv, AR8216_REG_PORT_CTRL(port),
813 AR8216_PORT_CTRL_LEARN |
814 (4 << AR8216_PORT_CTRL_STATE_S));
816 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
818 if (port == AR8216_PORT_CPU) {
819 priv->write(priv, AR8216_REG_PORT_STATUS(port),
820 AR8216_PORT_STATUS_LINK_UP |
821 (ar8xxx_has_gige(priv) ?
822 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
823 AR8216_PORT_STATUS_TXMAC |
824 AR8216_PORT_STATUS_RXMAC |
825 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
826 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
827 AR8216_PORT_STATUS_DUPLEX);
829 priv->write(priv, AR8216_REG_PORT_STATUS(port),
830 AR8216_PORT_STATUS_LINK_AUTO);
834 static const struct ar8xxx_chip ar8216_chip = {
835 .caps = AR8XXX_CAP_MIB_COUNTERS,
837 .hw_init = ar8216_hw_init,
838 .init_globals = ar8216_init_globals,
839 .init_port = ar8216_init_port,
840 .setup_port = ar8216_setup_port,
841 .read_port_status = ar8216_read_port_status,
842 .atu_flush = ar8216_atu_flush,
843 .vtu_flush = ar8216_vtu_flush,
844 .vtu_load_vlan = ar8216_vtu_load_vlan,
846 .num_mibs = ARRAY_SIZE(ar8216_mibs),
847 .mib_decs = ar8216_mibs,
851 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
857 pvid = priv->vlan_id[priv->pvid[port]];
858 if (priv->vlan_tagged & (1 << port))
859 egress = AR8216_OUT_ADD_VLAN;
861 egress = AR8216_OUT_STRIP_VLAN;
862 ingress = AR8216_IN_SECURE;
865 egress = AR8216_OUT_KEEP;
866 ingress = AR8216_IN_PORT_ONLY;
869 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
870 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
871 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
872 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
873 AR8216_PORT_CTRL_LEARN |
874 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
875 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
877 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
878 AR8236_PORT_VLAN_DEFAULT_ID,
879 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
881 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
882 AR8236_PORT_VLAN2_VLAN_MODE |
883 AR8236_PORT_VLAN2_MEMBER,
884 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
885 (members << AR8236_PORT_VLAN2_MEMBER_S));
889 ar8236_hw_init(struct ar8xxx_priv *priv)
894 if (priv->initialized)
897 /* Initialize the PHYs */
899 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
900 mdiobus_write(bus, i, MII_ADVERTISE,
901 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
902 ADVERTISE_PAUSE_ASYM);
903 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
906 ar8xxx_phy_poll_reset(bus);
908 priv->initialized = true;
913 ar8236_init_globals(struct ar8xxx_priv *priv)
915 /* enable jumbo frames */
916 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
917 AR8316_GCTRL_MTU, 9018 + 8 + 2);
919 /* Enable MIB counters */
920 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
921 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
925 static const struct ar8xxx_chip ar8236_chip = {
926 .caps = AR8XXX_CAP_MIB_COUNTERS,
927 .hw_init = ar8236_hw_init,
928 .init_globals = ar8236_init_globals,
929 .init_port = ar8216_init_port,
930 .setup_port = ar8236_setup_port,
931 .read_port_status = ar8216_read_port_status,
932 .atu_flush = ar8216_atu_flush,
933 .vtu_flush = ar8216_vtu_flush,
934 .vtu_load_vlan = ar8216_vtu_load_vlan,
936 .num_mibs = ARRAY_SIZE(ar8236_mibs),
937 .mib_decs = ar8236_mibs,
941 ar8316_hw_init(struct ar8xxx_priv *priv)
947 val = priv->read(priv, AR8316_REG_POSTRIP);
949 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
950 if (priv->port4_phy) {
951 /* value taken from Ubiquiti RouterStation Pro */
953 pr_info("ar8316: Using port 4 as PHY\n");
956 pr_info("ar8316: Using port 4 as switch port\n");
958 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
959 /* value taken from AVM Fritz!Box 7390 sources */
962 /* no known value for phy interface */
963 pr_err("ar8316: unsupported mii mode: %d.\n",
964 priv->phy->interface);
971 priv->write(priv, AR8316_REG_POSTRIP, newval);
973 if (priv->port4_phy &&
974 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
975 /* work around for phy4 rgmii mode */
976 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
978 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
980 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
984 /* Initialize the ports */
986 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
987 /* initialize the port itself */
988 mdiobus_write(bus, i, MII_ADVERTISE,
989 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
990 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
991 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
994 ar8xxx_phy_poll_reset(bus);
997 priv->initialized = true;
1002 ar8316_init_globals(struct ar8xxx_priv *priv)
1004 /* standard atheros magic */
1005 priv->write(priv, 0x38, 0xc000050e);
1007 /* enable cpu port to receive multicast and broadcast frames */
1008 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1010 /* enable jumbo frames */
1011 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1012 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1014 /* Enable MIB counters */
1015 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1016 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1020 static const struct ar8xxx_chip ar8316_chip = {
1021 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1022 .hw_init = ar8316_hw_init,
1023 .init_globals = ar8316_init_globals,
1024 .init_port = ar8216_init_port,
1025 .setup_port = ar8216_setup_port,
1026 .read_port_status = ar8216_read_port_status,
1027 .atu_flush = ar8216_atu_flush,
1028 .vtu_flush = ar8216_vtu_flush,
1029 .vtu_load_vlan = ar8216_vtu_load_vlan,
1031 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1032 .mib_decs = ar8236_mibs,
1036 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1044 switch (cfg->mode) {
1048 case AR8327_PAD_MAC2MAC_MII:
1049 t = AR8327_PAD_MAC_MII_EN;
1051 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1053 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1056 case AR8327_PAD_MAC2MAC_GMII:
1057 t = AR8327_PAD_MAC_GMII_EN;
1059 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1061 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1064 case AR8327_PAD_MAC_SGMII:
1065 t = AR8327_PAD_SGMII_EN;
1068 * WAR for the QUalcomm Atheros AP136 board.
1069 * It seems that RGMII TX/RX delay settings needs to be
1070 * applied for SGMII mode as well, The ethernet is not
1071 * reliable without this.
1073 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1074 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1075 if (cfg->rxclk_delay_en)
1076 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1077 if (cfg->txclk_delay_en)
1078 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1080 if (cfg->sgmii_delay_en)
1081 t |= AR8327_PAD_SGMII_DELAY_EN;
1085 case AR8327_PAD_MAC2PHY_MII:
1086 t = AR8327_PAD_PHY_MII_EN;
1088 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1090 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1093 case AR8327_PAD_MAC2PHY_GMII:
1094 t = AR8327_PAD_PHY_GMII_EN;
1095 if (cfg->pipe_rxclk_sel)
1096 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1098 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1100 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1103 case AR8327_PAD_MAC_RGMII:
1104 t = AR8327_PAD_RGMII_EN;
1105 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1106 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1107 if (cfg->rxclk_delay_en)
1108 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1109 if (cfg->txclk_delay_en)
1110 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1113 case AR8327_PAD_PHY_GMII:
1114 t = AR8327_PAD_PHYX_GMII_EN;
1117 case AR8327_PAD_PHY_RGMII:
1118 t = AR8327_PAD_PHYX_RGMII_EN;
1121 case AR8327_PAD_PHY_MII:
1122 t = AR8327_PAD_PHYX_MII_EN;
1130 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1132 switch (priv->chip_rev) {
1134 /* For 100M waveform */
1135 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1136 /* Turn on Gigabit clock */
1137 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1141 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1142 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1145 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1146 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1148 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1149 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1150 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1156 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1160 if (!cfg->force_link)
1161 return AR8216_PORT_STATUS_LINK_AUTO;
1163 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1164 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1165 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1166 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1168 switch (cfg->speed) {
1169 case AR8327_PORT_SPEED_10:
1170 t |= AR8216_PORT_SPEED_10M;
1172 case AR8327_PORT_SPEED_100:
1173 t |= AR8216_PORT_SPEED_100M;
1175 case AR8327_PORT_SPEED_1000:
1176 t |= AR8216_PORT_SPEED_1000M;
1183 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1184 [_num] = { .reg = (_reg), .shift = (_shift) }
1186 static const struct ar8327_led_entry
1187 ar8327_led_map[AR8327_NUM_LEDS] = {
1188 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1189 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1190 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1192 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1193 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1194 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1196 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1197 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1198 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1200 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1201 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1202 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1204 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1205 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1206 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1210 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1211 enum ar8327_led_pattern pattern)
1213 const struct ar8327_led_entry *entry;
1215 entry = &ar8327_led_map[led_num];
1216 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1217 (3 << entry->shift), pattern << entry->shift);
1221 ar8327_led_work_func(struct work_struct *work)
1223 struct ar8327_led *aled;
1226 aled = container_of(work, struct ar8327_led, led_work);
1228 spin_lock(&aled->lock);
1229 pattern = aled->pattern;
1230 spin_unlock(&aled->lock);
1232 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1237 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1239 if (aled->pattern == pattern)
1242 aled->pattern = pattern;
1243 schedule_work(&aled->led_work);
1246 static inline struct ar8327_led *
1247 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1249 return container_of(led_cdev, struct ar8327_led, cdev);
1253 ar8327_led_blink_set(struct led_classdev *led_cdev,
1254 unsigned long *delay_on,
1255 unsigned long *delay_off)
1257 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1259 if (*delay_on == 0 && *delay_off == 0) {
1264 if (*delay_on != 125 || *delay_off != 125) {
1266 * The hardware only supports blinking at 4Hz. Fall back
1267 * to software implementation in other cases.
1272 spin_lock(&aled->lock);
1274 aled->enable_hw_mode = false;
1275 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1277 spin_unlock(&aled->lock);
1283 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1284 enum led_brightness brightness)
1286 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1290 active = (brightness != LED_OFF);
1291 active ^= aled->active_low;
1293 pattern = (active) ? AR8327_LED_PATTERN_ON :
1294 AR8327_LED_PATTERN_OFF;
1296 spin_lock(&aled->lock);
1298 aled->enable_hw_mode = false;
1299 ar8327_led_schedule_change(aled, pattern);
1301 spin_unlock(&aled->lock);
1305 ar8327_led_enable_hw_mode_show(struct device *dev,
1306 struct device_attribute *attr,
1309 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1310 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1313 spin_lock(&aled->lock);
1314 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1315 spin_unlock(&aled->lock);
1321 ar8327_led_enable_hw_mode_store(struct device *dev,
1322 struct device_attribute *attr,
1326 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1327 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1332 ret = kstrtou8(buf, 10, &value);
1336 spin_lock(&aled->lock);
1338 aled->enable_hw_mode = !!value;
1339 if (aled->enable_hw_mode)
1340 pattern = AR8327_LED_PATTERN_RULE;
1342 pattern = AR8327_LED_PATTERN_OFF;
1344 ar8327_led_schedule_change(aled, pattern);
1346 spin_unlock(&aled->lock);
1351 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1352 ar8327_led_enable_hw_mode_show,
1353 ar8327_led_enable_hw_mode_store);
1356 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1360 ret = led_classdev_register(NULL, &aled->cdev);
1364 if (aled->mode == AR8327_LED_MODE_HW) {
1365 ret = device_create_file(aled->cdev.dev,
1366 &dev_attr_enable_hw_mode);
1368 goto err_unregister;
1374 led_classdev_unregister(&aled->cdev);
1379 ar8327_led_unregister(struct ar8327_led *aled)
1381 if (aled->mode == AR8327_LED_MODE_HW)
1382 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1384 led_classdev_unregister(&aled->cdev);
1385 cancel_work_sync(&aled->led_work);
1389 ar8327_led_create(struct ar8xxx_priv *priv,
1390 const struct ar8327_led_info *led_info)
1392 struct ar8327_data *data = &priv->chip_data.ar8327;
1393 struct ar8327_led *aled;
1396 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1399 if (!led_info->name)
1402 if (led_info->led_num >= AR8327_NUM_LEDS)
1405 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1410 aled->sw_priv = priv;
1411 aled->led_num = led_info->led_num;
1412 aled->active_low = led_info->active_low;
1413 aled->mode = led_info->mode;
1415 if (aled->mode == AR8327_LED_MODE_HW)
1416 aled->enable_hw_mode = true;
1418 aled->name = (char *)(aled + 1);
1419 strcpy(aled->name, led_info->name);
1421 aled->cdev.name = aled->name;
1422 aled->cdev.brightness_set = ar8327_led_set_brightness;
1423 aled->cdev.blink_set = ar8327_led_blink_set;
1424 aled->cdev.default_trigger = led_info->default_trigger;
1426 spin_lock_init(&aled->lock);
1427 mutex_init(&aled->mutex);
1428 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1430 ret = ar8327_led_register(priv, aled);
1434 data->leds[data->num_leds++] = aled;
1444 ar8327_led_destroy(struct ar8327_led *aled)
1446 ar8327_led_unregister(aled);
1451 ar8327_leds_init(struct ar8xxx_priv *priv)
1453 struct ar8327_data *data;
1456 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1459 data = &priv->chip_data.ar8327;
1461 for (i = 0; i < data->num_leds; i++) {
1462 struct ar8327_led *aled;
1464 aled = data->leds[i];
1466 if (aled->enable_hw_mode)
1467 aled->pattern = AR8327_LED_PATTERN_RULE;
1469 aled->pattern = AR8327_LED_PATTERN_OFF;
1471 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1476 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1478 struct ar8327_data *data = &priv->chip_data.ar8327;
1481 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1484 for (i = 0; i < data->num_leds; i++) {
1485 struct ar8327_led *aled;
1487 aled = data->leds[i];
1488 ar8327_led_destroy(aled);
1495 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1496 struct ar8327_platform_data *pdata)
1498 struct ar8327_led_cfg *led_cfg;
1499 struct ar8327_data *data;
1506 priv->get_port_link = pdata->get_port_link;
1508 data = &priv->chip_data.ar8327;
1510 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1511 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1513 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1514 if (chip_is_ar8337(priv))
1515 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1517 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1518 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1519 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1520 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1521 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1523 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1526 led_cfg = pdata->led_cfg;
1528 if (led_cfg->open_drain)
1529 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1531 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1533 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1534 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1535 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1536 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1539 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1542 if (pdata->sgmii_cfg) {
1543 t = pdata->sgmii_cfg->sgmii_ctrl;
1544 if (priv->chip_rev == 1)
1545 t |= AR8327_SGMII_CTRL_EN_PLL |
1546 AR8327_SGMII_CTRL_EN_RX |
1547 AR8327_SGMII_CTRL_EN_TX;
1549 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1550 AR8327_SGMII_CTRL_EN_RX |
1551 AR8327_SGMII_CTRL_EN_TX);
1553 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1555 if (pdata->sgmii_cfg->serdes_aen)
1556 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1558 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1561 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1563 if (pdata->leds && pdata->num_leds) {
1566 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1571 for (i = 0; i < pdata->num_leds; i++)
1572 ar8327_led_create(priv, &pdata->leds[i]);
1580 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1582 const __be32 *paddr;
1586 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1587 if (!paddr || len < (2 * sizeof(*paddr)))
1590 len /= sizeof(*paddr);
1592 for (i = 0; i < len - 1; i += 2) {
1596 reg = be32_to_cpup(paddr + i);
1597 val = be32_to_cpup(paddr + i + 1);
1600 case AR8327_REG_PORT_STATUS(0):
1601 priv->chip_data.ar8327.port0_status = val;
1603 case AR8327_REG_PORT_STATUS(6):
1604 priv->chip_data.ar8327.port6_status = val;
1607 priv->write(priv, reg, val);
1616 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1623 ar8327_hw_init(struct ar8xxx_priv *priv)
1625 struct mii_bus *bus;
1629 if (priv->phy->dev.of_node)
1630 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1632 ret = ar8327_hw_config_pdata(priv,
1633 priv->phy->dev.platform_data);
1638 ar8327_leds_init(priv);
1640 priv->chip->fixup_phys(priv);
1642 bus = priv->mii_bus;
1643 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
1644 /* start aneg on the PHY */
1645 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1646 ADVERTISE_PAUSE_CAP |
1647 ADVERTISE_PAUSE_ASYM);
1648 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1649 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1652 ar8xxx_phy_poll_reset(bus);
1658 ar8327_cleanup(struct ar8xxx_priv *priv)
1660 ar8327_leds_cleanup(priv);
1664 ar8327_init_globals(struct ar8xxx_priv *priv)
1668 /* enable CPU port and disable mirror port */
1669 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1670 AR8327_FWD_CTRL0_MIRROR_PORT;
1671 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1673 /* forward multicast and broadcast frames to CPU */
1674 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1675 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1676 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1677 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1679 /* enable jumbo frames */
1680 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1681 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1683 /* Enable MIB counters */
1684 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1685 AR8327_MODULE_EN_MIB);
1687 /* Disable EEE on all ports due to stability issues */
1688 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1689 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1690 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1691 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1692 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1693 AR8327_EEE_CTRL_DISABLE_PHY(4);
1694 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1698 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1702 if (port == AR8216_PORT_CPU)
1703 t = priv->chip_data.ar8327.port0_status;
1705 t = priv->chip_data.ar8327.port6_status;
1707 t = AR8216_PORT_STATUS_LINK_AUTO;
1709 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1710 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1712 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1713 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1714 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1716 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1717 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1719 t = AR8327_PORT_LOOKUP_LEARN;
1720 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1721 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1725 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1727 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1731 ar8327_atu_flush(struct ar8xxx_priv *priv)
1735 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1736 AR8327_ATU_FUNC_BUSY, 0);
1738 priv->write(priv, AR8327_REG_ATU_FUNC,
1739 AR8327_ATU_FUNC_OP_FLUSH);
1745 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1747 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1748 AR8327_VTU_FUNC1_BUSY, 0))
1751 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1752 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1754 op |= AR8327_VTU_FUNC1_BUSY;
1755 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1759 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1761 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1765 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1771 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1772 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1773 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1776 if ((port_mask & BIT(i)) == 0)
1777 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1778 else if (priv->vlan == 0)
1779 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1780 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1781 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1783 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1785 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1787 ar8327_vtu_op(priv, op, val);
1791 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1794 u32 egress, ingress;
1795 u32 pvid = priv->vlan_id[priv->pvid[port]];
1798 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1799 ingress = AR8216_IN_SECURE;
1801 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1802 ingress = AR8216_IN_PORT_ONLY;
1805 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1806 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1807 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1809 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1810 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1811 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1814 t |= AR8327_PORT_LOOKUP_LEARN;
1815 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1816 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1817 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1821 ar8327_fixup_phys(struct ar8xxx_priv *priv)
1825 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
1826 ar8327_phy_fixup(priv, i);
1829 static const struct ar8xxx_chip ar8327_chip = {
1830 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1831 .hw_init = ar8327_hw_init,
1832 .cleanup = ar8327_cleanup,
1833 .init_globals = ar8327_init_globals,
1834 .init_port = ar8327_init_port,
1835 .setup_port = ar8327_setup_port,
1836 .read_port_status = ar8327_read_port_status,
1837 .atu_flush = ar8327_atu_flush,
1838 .vtu_flush = ar8327_vtu_flush,
1839 .vtu_load_vlan = ar8327_vtu_load_vlan,
1840 .fixup_phys = ar8327_fixup_phys,
1842 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1843 .mib_decs = ar8236_mibs,
1847 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1848 struct switch_val *val)
1850 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1851 priv->vlan = !!val->value.i;
1856 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1857 struct switch_val *val)
1859 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1860 val->value.i = priv->vlan;
1866 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1868 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1870 /* make sure no invalid PVIDs get set */
1872 if (vlan >= dev->vlans)
1875 priv->pvid[port] = vlan;
1880 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1882 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1883 *vlan = priv->pvid[port];
1888 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1889 struct switch_val *val)
1891 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1892 priv->vlan_id[val->port_vlan] = val->value.i;
1897 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1898 struct switch_val *val)
1900 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1901 val->value.i = priv->vlan_id[val->port_vlan];
1906 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1907 struct switch_port_link *link)
1909 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1911 ar8216_read_port_link(priv, port, link);
1916 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1918 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1919 u8 ports = priv->vlan_table[val->port_vlan];
1923 for (i = 0; i < dev->ports; i++) {
1924 struct switch_port *p;
1926 if (!(ports & (1 << i)))
1929 p = &val->value.ports[val->len++];
1931 if (priv->vlan_tagged & (1 << i))
1932 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1940 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1942 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1943 u8 ports = priv->vlan_table[val->port_vlan];
1947 for (i = 0; i < dev->ports; i++) {
1948 struct switch_port *p;
1950 if (!(ports & (1 << i)))
1953 p = &val->value.ports[val->len++];
1955 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1956 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1964 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1966 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1967 u8 *vt = &priv->vlan_table[val->port_vlan];
1971 for (i = 0; i < val->len; i++) {
1972 struct switch_port *p = &val->value.ports[i];
1974 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1975 priv->vlan_tagged |= (1 << p->id);
1977 priv->vlan_tagged &= ~(1 << p->id);
1978 priv->pvid[p->id] = val->port_vlan;
1980 /* make sure that an untagged port does not
1981 * appear in other vlans */
1982 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1983 if (j == val->port_vlan)
1985 priv->vlan_table[j] &= ~(1 << p->id);
1995 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1997 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1998 u8 *vt = &priv->vlan_table[val->port_vlan];
2002 for (i = 0; i < val->len; i++) {
2003 struct switch_port *p = &val->value.ports[i];
2005 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2006 if (val->port_vlan == priv->pvid[p->id]) {
2007 priv->vlan_tagged |= (1 << p->id);
2010 priv->vlan_tagged &= ~(1 << p->id);
2011 priv->pvid[p->id] = val->port_vlan;
2020 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2024 /* reset all mirror registers */
2025 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2026 AR8327_FWD_CTRL0_MIRROR_PORT,
2027 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2028 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2029 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2030 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2033 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2034 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2038 /* now enable mirroring if necessary */
2039 if (priv->source_port >= AR8327_NUM_PORTS ||
2040 priv->monitor_port >= AR8327_NUM_PORTS ||
2041 priv->source_port == priv->monitor_port) {
2045 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2046 AR8327_FWD_CTRL0_MIRROR_PORT,
2047 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2049 if (priv->mirror_rx)
2050 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2051 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2052 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2054 if (priv->mirror_tx)
2055 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2056 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2057 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2061 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2065 /* reset all mirror registers */
2066 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2067 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2068 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2069 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2070 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2071 AR8216_PORT_CTRL_MIRROR_RX,
2074 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2075 AR8216_PORT_CTRL_MIRROR_TX,
2079 /* now enable mirroring if necessary */
2080 if (priv->source_port >= AR8216_NUM_PORTS ||
2081 priv->monitor_port >= AR8216_NUM_PORTS ||
2082 priv->source_port == priv->monitor_port) {
2086 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2087 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2088 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2090 if (priv->mirror_rx)
2091 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2092 AR8216_PORT_CTRL_MIRROR_RX,
2093 AR8216_PORT_CTRL_MIRROR_RX);
2095 if (priv->mirror_tx)
2096 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2097 AR8216_PORT_CTRL_MIRROR_TX,
2098 AR8216_PORT_CTRL_MIRROR_TX);
2102 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2104 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2105 ar8327_set_mirror_regs(priv);
2107 ar8216_set_mirror_regs(priv);
2112 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2114 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2115 u8 portmask[AR8X16_MAX_PORTS];
2118 mutex_lock(&priv->reg_mutex);
2119 /* flush all vlan translation unit entries */
2120 priv->chip->vtu_flush(priv);
2122 memset(portmask, 0, sizeof(portmask));
2124 /* calculate the port destination masks and load vlans
2125 * into the vlan translation unit */
2126 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2127 u8 vp = priv->vlan_table[j];
2132 for (i = 0; i < dev->ports; i++) {
2135 portmask[i] |= vp & ~mask;
2138 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2139 priv->vlan_table[j]);
2143 * isolate all ports, but connect them to the cpu port */
2144 for (i = 0; i < dev->ports; i++) {
2145 if (i == AR8216_PORT_CPU)
2148 portmask[i] = 1 << AR8216_PORT_CPU;
2149 portmask[AR8216_PORT_CPU] |= (1 << i);
2153 /* update the port destination mask registers and tag settings */
2154 for (i = 0; i < dev->ports; i++) {
2155 priv->chip->setup_port(priv, i, portmask[i]);
2158 ar8xxx_set_mirror_regs(priv);
2160 mutex_unlock(&priv->reg_mutex);
2165 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2167 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2170 mutex_lock(&priv->reg_mutex);
2171 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2172 offsetof(struct ar8xxx_priv, vlan));
2174 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2175 priv->vlan_id[i] = i;
2177 /* Configure all ports */
2178 for (i = 0; i < dev->ports; i++)
2179 priv->chip->init_port(priv, i);
2181 priv->mirror_rx = false;
2182 priv->mirror_tx = false;
2183 priv->source_port = 0;
2184 priv->monitor_port = 0;
2186 priv->chip->init_globals(priv);
2188 mutex_unlock(&priv->reg_mutex);
2190 return ar8xxx_sw_hw_apply(dev);
2194 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2195 const struct switch_attr *attr,
2196 struct switch_val *val)
2198 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2202 if (!ar8xxx_has_mib_counters(priv))
2205 mutex_lock(&priv->mib_lock);
2207 len = priv->dev.ports * priv->chip->num_mibs *
2208 sizeof(*priv->mib_stats);
2209 memset(priv->mib_stats, '\0', len);
2210 ret = ar8xxx_mib_flush(priv);
2217 mutex_unlock(&priv->mib_lock);
2222 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2223 const struct switch_attr *attr,
2224 struct switch_val *val)
2226 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2228 mutex_lock(&priv->reg_mutex);
2229 priv->mirror_rx = !!val->value.i;
2230 ar8xxx_set_mirror_regs(priv);
2231 mutex_unlock(&priv->reg_mutex);
2237 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2238 const struct switch_attr *attr,
2239 struct switch_val *val)
2241 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2242 val->value.i = priv->mirror_rx;
2247 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2248 const struct switch_attr *attr,
2249 struct switch_val *val)
2251 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2253 mutex_lock(&priv->reg_mutex);
2254 priv->mirror_tx = !!val->value.i;
2255 ar8xxx_set_mirror_regs(priv);
2256 mutex_unlock(&priv->reg_mutex);
2262 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2263 const struct switch_attr *attr,
2264 struct switch_val *val)
2266 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2267 val->value.i = priv->mirror_tx;
2272 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2273 const struct switch_attr *attr,
2274 struct switch_val *val)
2276 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2278 mutex_lock(&priv->reg_mutex);
2279 priv->monitor_port = val->value.i;
2280 ar8xxx_set_mirror_regs(priv);
2281 mutex_unlock(&priv->reg_mutex);
2287 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2288 const struct switch_attr *attr,
2289 struct switch_val *val)
2291 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2292 val->value.i = priv->monitor_port;
2297 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2298 const struct switch_attr *attr,
2299 struct switch_val *val)
2301 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2303 mutex_lock(&priv->reg_mutex);
2304 priv->source_port = val->value.i;
2305 ar8xxx_set_mirror_regs(priv);
2306 mutex_unlock(&priv->reg_mutex);
2312 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2313 const struct switch_attr *attr,
2314 struct switch_val *val)
2316 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2317 val->value.i = priv->source_port;
2322 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2323 const struct switch_attr *attr,
2324 struct switch_val *val)
2326 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2330 if (!ar8xxx_has_mib_counters(priv))
2333 port = val->port_vlan;
2334 if (port >= dev->ports)
2337 mutex_lock(&priv->mib_lock);
2338 ret = ar8xxx_mib_capture(priv);
2342 ar8xxx_mib_fetch_port_stat(priv, port, true);
2347 mutex_unlock(&priv->mib_lock);
2352 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2353 const struct switch_attr *attr,
2354 struct switch_val *val)
2356 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2357 const struct ar8xxx_chip *chip = priv->chip;
2361 char *buf = priv->buf;
2364 if (!ar8xxx_has_mib_counters(priv))
2367 port = val->port_vlan;
2368 if (port >= dev->ports)
2371 mutex_lock(&priv->mib_lock);
2372 ret = ar8xxx_mib_capture(priv);
2376 ar8xxx_mib_fetch_port_stat(priv, port, false);
2378 len += snprintf(buf + len, sizeof(priv->buf) - len,
2379 "Port %d MIB counters\n",
2382 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2383 for (i = 0; i < chip->num_mibs; i++)
2384 len += snprintf(buf + len, sizeof(priv->buf) - len,
2386 chip->mib_decs[i].name,
2395 mutex_unlock(&priv->mib_lock);
2399 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2401 .type = SWITCH_TYPE_INT,
2402 .name = "enable_vlan",
2403 .description = "Enable VLAN mode",
2404 .set = ar8xxx_sw_set_vlan,
2405 .get = ar8xxx_sw_get_vlan,
2409 .type = SWITCH_TYPE_NOVAL,
2410 .name = "reset_mibs",
2411 .description = "Reset all MIB counters",
2412 .set = ar8xxx_sw_set_reset_mibs,
2415 .type = SWITCH_TYPE_INT,
2416 .name = "enable_mirror_rx",
2417 .description = "Enable mirroring of RX packets",
2418 .set = ar8xxx_sw_set_mirror_rx_enable,
2419 .get = ar8xxx_sw_get_mirror_rx_enable,
2423 .type = SWITCH_TYPE_INT,
2424 .name = "enable_mirror_tx",
2425 .description = "Enable mirroring of TX packets",
2426 .set = ar8xxx_sw_set_mirror_tx_enable,
2427 .get = ar8xxx_sw_get_mirror_tx_enable,
2431 .type = SWITCH_TYPE_INT,
2432 .name = "mirror_monitor_port",
2433 .description = "Mirror monitor port",
2434 .set = ar8xxx_sw_set_mirror_monitor_port,
2435 .get = ar8xxx_sw_get_mirror_monitor_port,
2436 .max = AR8216_NUM_PORTS - 1
2439 .type = SWITCH_TYPE_INT,
2440 .name = "mirror_source_port",
2441 .description = "Mirror source port",
2442 .set = ar8xxx_sw_set_mirror_source_port,
2443 .get = ar8xxx_sw_get_mirror_source_port,
2444 .max = AR8216_NUM_PORTS - 1
2448 static struct switch_attr ar8327_sw_attr_globals[] = {
2450 .type = SWITCH_TYPE_INT,
2451 .name = "enable_vlan",
2452 .description = "Enable VLAN mode",
2453 .set = ar8xxx_sw_set_vlan,
2454 .get = ar8xxx_sw_get_vlan,
2458 .type = SWITCH_TYPE_NOVAL,
2459 .name = "reset_mibs",
2460 .description = "Reset all MIB counters",
2461 .set = ar8xxx_sw_set_reset_mibs,
2464 .type = SWITCH_TYPE_INT,
2465 .name = "enable_mirror_rx",
2466 .description = "Enable mirroring of RX packets",
2467 .set = ar8xxx_sw_set_mirror_rx_enable,
2468 .get = ar8xxx_sw_get_mirror_rx_enable,
2472 .type = SWITCH_TYPE_INT,
2473 .name = "enable_mirror_tx",
2474 .description = "Enable mirroring of TX packets",
2475 .set = ar8xxx_sw_set_mirror_tx_enable,
2476 .get = ar8xxx_sw_get_mirror_tx_enable,
2480 .type = SWITCH_TYPE_INT,
2481 .name = "mirror_monitor_port",
2482 .description = "Mirror monitor port",
2483 .set = ar8xxx_sw_set_mirror_monitor_port,
2484 .get = ar8xxx_sw_get_mirror_monitor_port,
2485 .max = AR8327_NUM_PORTS - 1
2488 .type = SWITCH_TYPE_INT,
2489 .name = "mirror_source_port",
2490 .description = "Mirror source port",
2491 .set = ar8xxx_sw_set_mirror_source_port,
2492 .get = ar8xxx_sw_get_mirror_source_port,
2493 .max = AR8327_NUM_PORTS - 1
2497 static struct switch_attr ar8xxx_sw_attr_port[] = {
2499 .type = SWITCH_TYPE_NOVAL,
2500 .name = "reset_mib",
2501 .description = "Reset single port MIB counters",
2502 .set = ar8xxx_sw_set_port_reset_mib,
2505 .type = SWITCH_TYPE_STRING,
2507 .description = "Get port's MIB counters",
2509 .get = ar8xxx_sw_get_port_mib,
2513 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2515 .type = SWITCH_TYPE_INT,
2517 .description = "VLAN ID (0-4094)",
2518 .set = ar8xxx_sw_set_vid,
2519 .get = ar8xxx_sw_get_vid,
2524 static const struct switch_dev_ops ar8xxx_sw_ops = {
2526 .attr = ar8xxx_sw_attr_globals,
2527 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2530 .attr = ar8xxx_sw_attr_port,
2531 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2534 .attr = ar8xxx_sw_attr_vlan,
2535 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2537 .get_port_pvid = ar8xxx_sw_get_pvid,
2538 .set_port_pvid = ar8xxx_sw_set_pvid,
2539 .get_vlan_ports = ar8xxx_sw_get_ports,
2540 .set_vlan_ports = ar8xxx_sw_set_ports,
2541 .apply_config = ar8xxx_sw_hw_apply,
2542 .reset_switch = ar8xxx_sw_reset_switch,
2543 .get_port_link = ar8xxx_sw_get_port_link,
2546 static const struct switch_dev_ops ar8327_sw_ops = {
2548 .attr = ar8327_sw_attr_globals,
2549 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2552 .attr = ar8xxx_sw_attr_port,
2553 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2556 .attr = ar8xxx_sw_attr_vlan,
2557 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2559 .get_port_pvid = ar8xxx_sw_get_pvid,
2560 .set_port_pvid = ar8xxx_sw_set_pvid,
2561 .get_vlan_ports = ar8327_sw_get_ports,
2562 .set_vlan_ports = ar8327_sw_set_ports,
2563 .apply_config = ar8xxx_sw_hw_apply,
2564 .reset_switch = ar8xxx_sw_reset_switch,
2565 .get_port_link = ar8xxx_sw_get_port_link,
2569 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2575 val = priv->read(priv, AR8216_REG_CTRL);
2579 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2580 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2583 val = priv->read(priv, AR8216_REG_CTRL);
2587 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2592 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2593 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2595 switch (priv->chip_ver) {
2596 case AR8XXX_VER_AR8216:
2597 priv->chip = &ar8216_chip;
2599 case AR8XXX_VER_AR8236:
2600 priv->chip = &ar8236_chip;
2602 case AR8XXX_VER_AR8316:
2603 priv->chip = &ar8316_chip;
2605 case AR8XXX_VER_AR8327:
2606 priv->mii_lo_first = true;
2607 priv->chip = &ar8327_chip;
2609 case AR8XXX_VER_AR8337:
2610 priv->mii_lo_first = true;
2611 priv->chip = &ar8327_chip;
2614 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2615 priv->chip_ver, priv->chip_rev);
2624 ar8xxx_mib_work_func(struct work_struct *work)
2626 struct ar8xxx_priv *priv;
2629 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2631 mutex_lock(&priv->mib_lock);
2633 err = ar8xxx_mib_capture(priv);
2637 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2640 priv->mib_next_port++;
2641 if (priv->mib_next_port >= priv->dev.ports)
2642 priv->mib_next_port = 0;
2644 mutex_unlock(&priv->mib_lock);
2645 schedule_delayed_work(&priv->mib_work,
2646 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2650 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2654 if (!ar8xxx_has_mib_counters(priv))
2657 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2659 len = priv->dev.ports * priv->chip->num_mibs *
2660 sizeof(*priv->mib_stats);
2661 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2663 if (!priv->mib_stats)
2670 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2672 if (!ar8xxx_has_mib_counters(priv))
2675 schedule_delayed_work(&priv->mib_work,
2676 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2680 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2682 if (!ar8xxx_has_mib_counters(priv))
2685 cancel_delayed_work(&priv->mib_work);
2688 static struct ar8xxx_priv *
2691 struct ar8xxx_priv *priv;
2693 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2697 mutex_init(&priv->reg_mutex);
2698 mutex_init(&priv->mib_lock);
2699 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2705 ar8xxx_free(struct ar8xxx_priv *priv)
2707 if (priv->chip && priv->chip->cleanup)
2708 priv->chip->cleanup(priv);
2710 kfree(priv->mib_stats);
2714 static struct ar8xxx_priv *
2715 ar8xxx_create_mii(struct mii_bus *bus)
2717 struct ar8xxx_priv *priv;
2719 priv = ar8xxx_create();
2721 priv->mii_bus = bus;
2722 priv->read = ar8xxx_mii_read;
2723 priv->write = ar8xxx_mii_write;
2724 priv->rmw = ar8xxx_mii_rmw;
2731 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2733 struct switch_dev *swdev;
2736 ret = ar8xxx_id_chip(priv);
2741 swdev->cpu_port = AR8216_PORT_CPU;
2742 swdev->ops = &ar8xxx_sw_ops;
2744 if (chip_is_ar8316(priv)) {
2745 swdev->name = "Atheros AR8316";
2746 swdev->vlans = AR8X16_MAX_VLANS;
2747 swdev->ports = AR8216_NUM_PORTS;
2748 } else if (chip_is_ar8236(priv)) {
2749 swdev->name = "Atheros AR8236";
2750 swdev->vlans = AR8216_NUM_VLANS;
2751 swdev->ports = AR8216_NUM_PORTS;
2752 } else if (chip_is_ar8327(priv)) {
2753 swdev->name = "Atheros AR8327";
2754 swdev->vlans = AR8X16_MAX_VLANS;
2755 swdev->ports = AR8327_NUM_PORTS;
2756 swdev->ops = &ar8327_sw_ops;
2757 } else if (chip_is_ar8337(priv)) {
2758 swdev->name = "Atheros AR8337";
2759 swdev->vlans = AR8X16_MAX_VLANS;
2760 swdev->ports = AR8327_NUM_PORTS;
2761 swdev->ops = &ar8327_sw_ops;
2763 swdev->name = "Atheros AR8216";
2764 swdev->vlans = AR8216_NUM_VLANS;
2765 swdev->ports = AR8216_NUM_PORTS;
2768 ret = ar8xxx_mib_init(priv);
2776 ar8xxx_start(struct ar8xxx_priv *priv)
2782 ret = priv->chip->hw_init(priv);
2786 ret = ar8xxx_sw_reset_switch(&priv->dev);
2792 ar8xxx_mib_start(priv);
2798 ar8xxx_phy_config_init(struct phy_device *phydev)
2800 struct ar8xxx_priv *priv = phydev->priv;
2801 struct net_device *dev = phydev->attached_dev;
2807 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2812 if (phydev->addr != 0) {
2813 if (chip_is_ar8316(priv)) {
2814 /* switch device has been initialized, reinit */
2815 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2816 priv->initialized = false;
2817 priv->port4_phy = true;
2818 ar8316_hw_init(priv);
2825 ret = ar8xxx_start(priv);
2829 /* VID fixup only needed on ar8216 */
2830 if (chip_is_ar8216(priv)) {
2831 dev->phy_ptr = priv;
2832 dev->priv_flags |= IFF_NO_IP_ALIGN;
2833 dev->eth_mangle_rx = ar8216_mangle_rx;
2834 dev->eth_mangle_tx = ar8216_mangle_tx;
2841 ar8xxx_phy_read_status(struct phy_device *phydev)
2843 struct ar8xxx_priv *priv = phydev->priv;
2844 struct switch_port_link link;
2847 if (phydev->addr != 0)
2848 return genphy_read_status(phydev);
2850 ar8216_read_port_link(priv, phydev->addr, &link);
2851 phydev->link = !!link.link;
2855 switch (link.speed) {
2856 case SWITCH_PORT_SPEED_10:
2857 phydev->speed = SPEED_10;
2859 case SWITCH_PORT_SPEED_100:
2860 phydev->speed = SPEED_100;
2862 case SWITCH_PORT_SPEED_1000:
2863 phydev->speed = SPEED_1000;
2868 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2870 /* flush the address translation unit */
2871 mutex_lock(&priv->reg_mutex);
2872 ret = priv->chip->atu_flush(priv);
2873 mutex_unlock(&priv->reg_mutex);
2875 phydev->state = PHY_RUNNING;
2876 netif_carrier_on(phydev->attached_dev);
2877 phydev->adjust_link(phydev->attached_dev);
2883 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2885 if (phydev->addr == 0)
2888 return genphy_config_aneg(phydev);
2891 static const u32 ar8xxx_phy_ids[] = {
2893 0x004dd034, /* AR8327 */
2894 0x004dd036, /* AR8337 */
2897 0x004dd043, /* AR8236 */
2901 ar8xxx_phy_match(u32 phy_id)
2905 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2906 if (phy_id == ar8xxx_phy_ids[i])
2913 ar8xxx_is_possible(struct mii_bus *bus)
2917 for (i = 0; i < 4; i++) {
2920 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2921 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2922 if (!ar8xxx_phy_match(phy_id)) {
2923 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2924 dev_name(&bus->dev), i, phy_id);
2933 ar8xxx_phy_probe(struct phy_device *phydev)
2935 struct ar8xxx_priv *priv;
2936 struct switch_dev *swdev;
2939 /* skip PHYs at unused adresses */
2940 if (phydev->addr != 0 && phydev->addr != 4)
2943 if (!ar8xxx_is_possible(phydev->bus))
2946 mutex_lock(&ar8xxx_dev_list_lock);
2947 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2948 if (priv->mii_bus == phydev->bus)
2951 priv = ar8xxx_create_mii(phydev->bus);
2957 ret = ar8xxx_probe_switch(priv);
2962 swdev->alias = dev_name(&priv->mii_bus->dev);
2963 ret = register_switch(swdev, NULL);
2967 pr_info("%s: %s rev. %u switch registered on %s\n",
2968 swdev->devname, swdev->name, priv->chip_rev,
2969 dev_name(&priv->mii_bus->dev));
2974 if (phydev->addr == 0) {
2975 if (ar8xxx_has_gige(priv)) {
2976 phydev->supported = SUPPORTED_1000baseT_Full;
2977 phydev->advertising = ADVERTISED_1000baseT_Full;
2979 phydev->supported = SUPPORTED_100baseT_Full;
2980 phydev->advertising = ADVERTISED_100baseT_Full;
2983 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2986 ret = ar8xxx_start(priv);
2988 goto err_unregister_switch;
2991 if (ar8xxx_has_gige(priv)) {
2992 phydev->supported |= SUPPORTED_1000baseT_Full;
2993 phydev->advertising |= ADVERTISED_1000baseT_Full;
2997 phydev->priv = priv;
2999 list_add(&priv->list, &ar8xxx_dev_list);
3001 mutex_unlock(&ar8xxx_dev_list_lock);
3005 err_unregister_switch:
3006 if (--priv->use_count)
3009 unregister_switch(&priv->dev);
3014 mutex_unlock(&ar8xxx_dev_list_lock);
3019 ar8xxx_phy_detach(struct phy_device *phydev)
3021 struct net_device *dev = phydev->attached_dev;
3026 dev->phy_ptr = NULL;
3027 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3028 dev->eth_mangle_rx = NULL;
3029 dev->eth_mangle_tx = NULL;
3033 ar8xxx_phy_remove(struct phy_device *phydev)
3035 struct ar8xxx_priv *priv = phydev->priv;
3040 phydev->priv = NULL;
3041 if (--priv->use_count > 0)
3044 mutex_lock(&ar8xxx_dev_list_lock);
3045 list_del(&priv->list);
3046 mutex_unlock(&ar8xxx_dev_list_lock);
3048 unregister_switch(&priv->dev);
3049 ar8xxx_mib_stop(priv);
3053 static struct phy_driver ar8xxx_phy_driver = {
3054 .phy_id = 0x004d0000,
3055 .name = "Atheros AR8216/AR8236/AR8316",
3056 .phy_id_mask = 0xffff0000,
3057 .features = PHY_BASIC_FEATURES,
3058 .probe = ar8xxx_phy_probe,
3059 .remove = ar8xxx_phy_remove,
3060 .detach = ar8xxx_phy_detach,
3061 .config_init = ar8xxx_phy_config_init,
3062 .config_aneg = ar8xxx_phy_config_aneg,
3063 .read_status = ar8xxx_phy_read_status,
3064 .driver = { .owner = THIS_MODULE },
3070 return phy_driver_register(&ar8xxx_phy_driver);
3076 phy_driver_unregister(&ar8xxx_phy_driver);
3079 module_init(ar8xxx_init);
3080 module_exit(ar8xxx_exit);
3081 MODULE_LICENSE("GPL");