2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
55 AR8XXX_VER_AR8216 = 0x01,
56 AR8XXX_VER_AR8236 = 0x03,
57 AR8XXX_VER_AR8316 = 0x10,
58 AR8XXX_VER_AR8327 = 0x12,
59 AR8XXX_VER_AR8337 = 0x13,
62 struct ar8xxx_mib_desc {
71 int (*hw_init)(struct ar8xxx_priv *priv);
72 void (*cleanup)(struct ar8xxx_priv *priv);
74 void (*init_globals)(struct ar8xxx_priv *priv);
75 void (*init_port)(struct ar8xxx_priv *priv, int port);
76 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
77 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
78 int (*atu_flush)(struct ar8xxx_priv *priv);
79 void (*vtu_flush)(struct ar8xxx_priv *priv);
80 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
82 const struct ar8xxx_mib_desc *mib_decs;
86 enum ar8327_led_pattern {
87 AR8327_LED_PATTERN_OFF = 0,
88 AR8327_LED_PATTERN_BLINK,
89 AR8327_LED_PATTERN_ON,
90 AR8327_LED_PATTERN_RULE,
93 struct ar8327_led_entry {
99 struct led_classdev cdev;
100 struct ar8xxx_priv *sw_priv;
105 enum ar8327_led_mode mode;
109 struct work_struct led_work;
111 enum ar8327_led_pattern pattern;
118 struct ar8327_led **leds;
119 unsigned int num_leds;
123 struct switch_dev dev;
124 struct mii_bus *mii_bus;
125 struct phy_device *phy;
127 u32 (*read)(struct ar8xxx_priv *priv, int reg);
128 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
129 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
131 int (*get_port_link)(unsigned port);
133 const struct net_device_ops *ndo_old;
134 struct net_device_ops ndo;
135 struct mutex reg_mutex;
138 const struct ar8xxx_chip *chip;
140 struct ar8327_data ar8327;
149 struct mutex mib_lock;
150 struct delayed_work mib_work;
154 struct list_head list;
155 unsigned int use_count;
157 /* all fields below are cleared on reset */
159 u16 vlan_id[AR8X16_MAX_VLANS];
160 u8 vlan_table[AR8X16_MAX_VLANS];
162 u16 pvid[AR8X16_MAX_PORTS];
171 #define MIB_DESC(_s , _o, _n) \
178 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
179 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
180 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
181 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
182 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
183 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
184 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
185 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
186 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
187 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
188 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
189 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
190 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
191 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
192 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
193 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
194 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
195 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
196 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
197 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
198 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
199 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
200 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
201 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
202 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
203 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
204 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
205 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
206 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
207 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
208 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
209 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
210 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
211 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
212 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
213 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
214 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
215 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
218 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
219 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
220 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
221 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
222 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
223 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
224 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
225 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
226 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
227 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
228 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
229 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
230 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
231 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
232 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
233 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
234 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
235 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
236 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
237 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
238 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
239 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
240 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
241 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
242 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
243 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
244 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
245 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
246 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
247 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
248 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
249 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
250 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
251 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
252 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
253 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
254 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
255 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
256 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
257 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
260 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
261 static LIST_HEAD(ar8xxx_dev_list);
263 static inline struct ar8xxx_priv *
264 swdev_to_ar8xxx(struct switch_dev *swdev)
266 return container_of(swdev, struct ar8xxx_priv, dev);
269 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
271 return priv->chip->caps & AR8XXX_CAP_GIGE;
274 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
276 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
279 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
281 return priv->chip_ver == AR8XXX_VER_AR8216;
284 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
286 return priv->chip_ver == AR8XXX_VER_AR8236;
289 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
291 return priv->chip_ver == AR8XXX_VER_AR8316;
294 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
296 return priv->chip_ver == AR8XXX_VER_AR8327;
299 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
301 return priv->chip_ver == AR8XXX_VER_AR8337;
305 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
308 *r1 = regaddr & 0x1e;
314 *page = regaddr & 0x1ff;
318 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
320 struct mii_bus *bus = priv->mii_bus;
324 split_addr((u32) reg, &r1, &r2, &page);
326 mutex_lock(&bus->mdio_lock);
328 bus->write(bus, 0x18, 0, page);
329 usleep_range(1000, 2000); /* wait for the page switch to propagate */
330 lo = bus->read(bus, 0x10 | r2, r1);
331 hi = bus->read(bus, 0x10 | r2, r1 + 1);
333 mutex_unlock(&bus->mdio_lock);
335 return (hi << 16) | lo;
339 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
341 struct mii_bus *bus = priv->mii_bus;
345 split_addr((u32) reg, &r1, &r2, &r3);
347 hi = (u16) (val >> 16);
349 mutex_lock(&bus->mdio_lock);
351 bus->write(bus, 0x18, 0, r3);
352 usleep_range(1000, 2000); /* wait for the page switch to propagate */
353 if (priv->mii_lo_first) {
354 bus->write(bus, 0x10 | r2, r1, lo);
355 bus->write(bus, 0x10 | r2, r1 + 1, hi);
357 bus->write(bus, 0x10 | r2, r1 + 1, hi);
358 bus->write(bus, 0x10 | r2, r1, lo);
361 mutex_unlock(&bus->mdio_lock);
365 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
367 struct mii_bus *bus = priv->mii_bus;
372 split_addr((u32) reg, &r1, &r2, &page);
374 mutex_lock(&bus->mdio_lock);
376 bus->write(bus, 0x18, 0, page);
377 usleep_range(1000, 2000); /* wait for the page switch to propagate */
379 lo = bus->read(bus, 0x10 | r2, r1);
380 hi = bus->read(bus, 0x10 | r2, r1 + 1);
387 hi = (u16) (ret >> 16);
389 if (priv->mii_lo_first) {
390 bus->write(bus, 0x10 | r2, r1, lo);
391 bus->write(bus, 0x10 | r2, r1 + 1, hi);
393 bus->write(bus, 0x10 | r2, r1 + 1, hi);
394 bus->write(bus, 0x10 | r2, r1, lo);
397 mutex_unlock(&bus->mdio_lock);
404 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
405 u16 dbg_addr, u16 dbg_data)
407 struct mii_bus *bus = priv->mii_bus;
409 mutex_lock(&bus->mdio_lock);
410 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
411 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
412 mutex_unlock(&bus->mdio_lock);
416 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
418 struct mii_bus *bus = priv->mii_bus;
420 mutex_lock(&bus->mdio_lock);
421 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
422 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
423 mutex_unlock(&bus->mdio_lock);
427 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
429 return priv->rmw(priv, reg, mask, val);
433 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
435 priv->rmw(priv, reg, 0, val);
439 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
444 for (i = 0; i < timeout; i++) {
447 t = priv->read(priv, reg);
448 if ((t & mask) == val)
451 usleep_range(1000, 2000);
458 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
463 lockdep_assert_held(&priv->mib_lock);
465 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
466 mib_func = AR8327_REG_MIB_FUNC;
468 mib_func = AR8216_REG_MIB_FUNC;
470 /* Capture the hardware statistics for all ports */
471 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
473 /* Wait for the capturing to complete. */
474 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
485 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
487 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
491 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
493 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
497 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
503 WARN_ON(port >= priv->dev.ports);
505 lockdep_assert_held(&priv->mib_lock);
507 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
508 base = AR8327_REG_PORT_STATS_BASE(port);
509 else if (chip_is_ar8236(priv) ||
510 chip_is_ar8316(priv))
511 base = AR8236_REG_PORT_STATS_BASE(port);
513 base = AR8216_REG_PORT_STATS_BASE(port);
515 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
516 for (i = 0; i < priv->chip->num_mibs; i++) {
517 const struct ar8xxx_mib_desc *mib;
520 mib = &priv->chip->mib_decs[i];
521 t = priv->read(priv, base + mib->offset);
522 if (mib->size == 2) {
525 hi = priv->read(priv, base + mib->offset + 4);
537 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
538 struct switch_port_link *link)
543 memset(link, '\0', sizeof(*link));
545 status = priv->chip->read_port_status(priv, port);
547 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
549 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
553 if (priv->get_port_link) {
556 err = priv->get_port_link(port);
565 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
566 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
567 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
569 speed = (status & AR8216_PORT_STATUS_SPEED) >>
570 AR8216_PORT_STATUS_SPEED_S;
573 case AR8216_PORT_SPEED_10M:
574 link->speed = SWITCH_PORT_SPEED_10;
576 case AR8216_PORT_SPEED_100M:
577 link->speed = SWITCH_PORT_SPEED_100;
579 case AR8216_PORT_SPEED_1000M:
580 link->speed = SWITCH_PORT_SPEED_1000;
583 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
588 static struct sk_buff *
589 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
591 struct ar8xxx_priv *priv = dev->phy_ptr;
600 if (unlikely(skb_headroom(skb) < 2)) {
601 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
605 buf = skb_push(skb, 2);
613 dev_kfree_skb_any(skb);
618 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
620 struct ar8xxx_priv *priv;
628 /* don't strip the header if vlan mode is disabled */
632 /* strip header, get vlan id */
636 /* check for vlan header presence */
637 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
642 /* no need to fix up packets coming from a tagged source */
643 if (priv->vlan_tagged & (1 << port))
646 /* lookup port vid from local table, the switch passes an invalid vlan id */
647 vlan = priv->vlan_id[priv->pvid[port]];
650 buf[14 + 2] |= vlan >> 8;
651 buf[15 + 2] = vlan & 0xff;
655 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
661 t = priv->read(priv, reg);
662 if ((t & mask) == val)
671 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
672 (unsigned int) reg, t, mask, val);
677 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
679 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
681 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
682 val &= AR8216_VTUDATA_MEMBER;
683 val |= AR8216_VTUDATA_VALID;
684 priv->write(priv, AR8216_REG_VTU_DATA, val);
686 op |= AR8216_VTU_ACTIVE;
687 priv->write(priv, AR8216_REG_VTU, op);
691 ar8216_vtu_flush(struct ar8xxx_priv *priv)
693 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
697 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
701 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
702 ar8216_vtu_op(priv, op, port_mask);
706 ar8216_atu_flush(struct ar8xxx_priv *priv)
710 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
712 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
718 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
720 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
724 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
731 pvid = priv->vlan_id[priv->pvid[port]];
732 if (priv->vlan_tagged & (1 << port))
733 egress = AR8216_OUT_ADD_VLAN;
735 egress = AR8216_OUT_STRIP_VLAN;
736 ingress = AR8216_IN_SECURE;
739 egress = AR8216_OUT_KEEP;
740 ingress = AR8216_IN_PORT_ONLY;
743 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
744 header = AR8216_PORT_CTRL_HEADER;
748 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
749 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
750 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
751 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
752 AR8216_PORT_CTRL_LEARN | header |
753 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
754 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
756 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
757 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
758 AR8216_PORT_VLAN_DEFAULT_ID,
759 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
760 (ingress << AR8216_PORT_VLAN_MODE_S) |
761 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
765 ar8216_hw_init(struct ar8xxx_priv *priv)
771 ar8216_init_globals(struct ar8xxx_priv *priv)
773 /* standard atheros magic */
774 priv->write(priv, 0x38, 0xc000050e);
776 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
777 AR8216_GCTRL_MTU, 1518 + 8 + 2);
781 ar8216_init_port(struct ar8xxx_priv *priv, int port)
783 /* Enable port learning and tx */
784 priv->write(priv, AR8216_REG_PORT_CTRL(port),
785 AR8216_PORT_CTRL_LEARN |
786 (4 << AR8216_PORT_CTRL_STATE_S));
788 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
790 if (port == AR8216_PORT_CPU) {
791 priv->write(priv, AR8216_REG_PORT_STATUS(port),
792 AR8216_PORT_STATUS_LINK_UP |
793 (ar8xxx_has_gige(priv) ?
794 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
795 AR8216_PORT_STATUS_TXMAC |
796 AR8216_PORT_STATUS_RXMAC |
797 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
798 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
799 AR8216_PORT_STATUS_DUPLEX);
801 priv->write(priv, AR8216_REG_PORT_STATUS(port),
802 AR8216_PORT_STATUS_LINK_AUTO);
806 static const struct ar8xxx_chip ar8216_chip = {
807 .caps = AR8XXX_CAP_MIB_COUNTERS,
809 .hw_init = ar8216_hw_init,
810 .init_globals = ar8216_init_globals,
811 .init_port = ar8216_init_port,
812 .setup_port = ar8216_setup_port,
813 .read_port_status = ar8216_read_port_status,
814 .atu_flush = ar8216_atu_flush,
815 .vtu_flush = ar8216_vtu_flush,
816 .vtu_load_vlan = ar8216_vtu_load_vlan,
818 .num_mibs = ARRAY_SIZE(ar8216_mibs),
819 .mib_decs = ar8216_mibs,
823 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
829 pvid = priv->vlan_id[priv->pvid[port]];
830 if (priv->vlan_tagged & (1 << port))
831 egress = AR8216_OUT_ADD_VLAN;
833 egress = AR8216_OUT_STRIP_VLAN;
834 ingress = AR8216_IN_SECURE;
837 egress = AR8216_OUT_KEEP;
838 ingress = AR8216_IN_PORT_ONLY;
841 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
842 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
843 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
844 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
845 AR8216_PORT_CTRL_LEARN |
846 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
847 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
849 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
850 AR8236_PORT_VLAN_DEFAULT_ID,
851 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
853 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
854 AR8236_PORT_VLAN2_VLAN_MODE |
855 AR8236_PORT_VLAN2_MEMBER,
856 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
857 (members << AR8236_PORT_VLAN2_MEMBER_S));
861 ar8236_hw_init(struct ar8xxx_priv *priv)
866 if (priv->initialized)
869 /* Initialize the PHYs */
871 for (i = 0; i < 5; i++) {
872 mdiobus_write(bus, i, MII_ADVERTISE,
873 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
874 ADVERTISE_PAUSE_ASYM);
875 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
879 priv->initialized = true;
884 ar8236_init_globals(struct ar8xxx_priv *priv)
886 /* enable jumbo frames */
887 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
888 AR8316_GCTRL_MTU, 9018 + 8 + 2);
890 /* Enable MIB counters */
891 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
892 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
896 static const struct ar8xxx_chip ar8236_chip = {
897 .caps = AR8XXX_CAP_MIB_COUNTERS,
898 .hw_init = ar8236_hw_init,
899 .init_globals = ar8236_init_globals,
900 .init_port = ar8216_init_port,
901 .setup_port = ar8236_setup_port,
902 .read_port_status = ar8216_read_port_status,
903 .atu_flush = ar8216_atu_flush,
904 .vtu_flush = ar8216_vtu_flush,
905 .vtu_load_vlan = ar8216_vtu_load_vlan,
907 .num_mibs = ARRAY_SIZE(ar8236_mibs),
908 .mib_decs = ar8236_mibs,
912 ar8316_hw_init(struct ar8xxx_priv *priv)
918 val = priv->read(priv, AR8316_REG_POSTRIP);
920 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
921 if (priv->port4_phy) {
922 /* value taken from Ubiquiti RouterStation Pro */
924 pr_info("ar8316: Using port 4 as PHY\n");
927 pr_info("ar8316: Using port 4 as switch port\n");
929 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
930 /* value taken from AVM Fritz!Box 7390 sources */
933 /* no known value for phy interface */
934 pr_err("ar8316: unsupported mii mode: %d.\n",
935 priv->phy->interface);
942 priv->write(priv, AR8316_REG_POSTRIP, newval);
944 if (priv->port4_phy &&
945 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
946 /* work around for phy4 rgmii mode */
947 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
949 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
951 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
955 /* Initialize the ports */
957 for (i = 0; i < 5; i++) {
958 /* initialize the port itself */
959 mdiobus_write(bus, i, MII_ADVERTISE,
960 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
961 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
962 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
968 priv->initialized = true;
973 ar8316_init_globals(struct ar8xxx_priv *priv)
975 /* standard atheros magic */
976 priv->write(priv, 0x38, 0xc000050e);
978 /* enable cpu port to receive multicast and broadcast frames */
979 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
981 /* enable jumbo frames */
982 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
983 AR8316_GCTRL_MTU, 9018 + 8 + 2);
985 /* Enable MIB counters */
986 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
987 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
991 static const struct ar8xxx_chip ar8316_chip = {
992 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
993 .hw_init = ar8316_hw_init,
994 .init_globals = ar8316_init_globals,
995 .init_port = ar8216_init_port,
996 .setup_port = ar8216_setup_port,
997 .read_port_status = ar8216_read_port_status,
998 .atu_flush = ar8216_atu_flush,
999 .vtu_flush = ar8216_vtu_flush,
1000 .vtu_load_vlan = ar8216_vtu_load_vlan,
1002 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1003 .mib_decs = ar8236_mibs,
1007 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1015 switch (cfg->mode) {
1019 case AR8327_PAD_MAC2MAC_MII:
1020 t = AR8327_PAD_MAC_MII_EN;
1022 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1024 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1027 case AR8327_PAD_MAC2MAC_GMII:
1028 t = AR8327_PAD_MAC_GMII_EN;
1030 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1032 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1035 case AR8327_PAD_MAC_SGMII:
1036 t = AR8327_PAD_SGMII_EN;
1039 * WAR for the QUalcomm Atheros AP136 board.
1040 * It seems that RGMII TX/RX delay settings needs to be
1041 * applied for SGMII mode as well, The ethernet is not
1042 * reliable without this.
1044 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1045 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1046 if (cfg->rxclk_delay_en)
1047 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1048 if (cfg->txclk_delay_en)
1049 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1051 if (cfg->sgmii_delay_en)
1052 t |= AR8327_PAD_SGMII_DELAY_EN;
1056 case AR8327_PAD_MAC2PHY_MII:
1057 t = AR8327_PAD_PHY_MII_EN;
1059 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1061 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1064 case AR8327_PAD_MAC2PHY_GMII:
1065 t = AR8327_PAD_PHY_GMII_EN;
1066 if (cfg->pipe_rxclk_sel)
1067 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1069 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1071 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1074 case AR8327_PAD_MAC_RGMII:
1075 t = AR8327_PAD_RGMII_EN;
1076 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1077 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1078 if (cfg->rxclk_delay_en)
1079 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1080 if (cfg->txclk_delay_en)
1081 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1084 case AR8327_PAD_PHY_GMII:
1085 t = AR8327_PAD_PHYX_GMII_EN;
1088 case AR8327_PAD_PHY_RGMII:
1089 t = AR8327_PAD_PHYX_RGMII_EN;
1092 case AR8327_PAD_PHY_MII:
1093 t = AR8327_PAD_PHYX_MII_EN;
1101 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1103 switch (priv->chip_rev) {
1105 /* For 100M waveform */
1106 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1107 /* Turn on Gigabit clock */
1108 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1112 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1113 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1116 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1117 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1119 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1120 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1121 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1127 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1131 if (!cfg->force_link)
1132 return AR8216_PORT_STATUS_LINK_AUTO;
1134 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1135 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1136 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1137 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1139 switch (cfg->speed) {
1140 case AR8327_PORT_SPEED_10:
1141 t |= AR8216_PORT_SPEED_10M;
1143 case AR8327_PORT_SPEED_100:
1144 t |= AR8216_PORT_SPEED_100M;
1146 case AR8327_PORT_SPEED_1000:
1147 t |= AR8216_PORT_SPEED_1000M;
1154 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1155 [_num] = { .reg = (_reg), .shift = (_shift) }
1157 static const struct ar8327_led_entry
1158 ar8327_led_map[AR8327_NUM_LEDS] = {
1159 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1160 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1161 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1163 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1164 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1165 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1167 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1168 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1169 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1171 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1172 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1173 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1175 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1176 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1177 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1181 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1182 enum ar8327_led_pattern pattern)
1184 const struct ar8327_led_entry *entry;
1186 entry = &ar8327_led_map[led_num];
1187 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1188 (3 << entry->shift), pattern << entry->shift);
1192 ar8327_led_work_func(struct work_struct *work)
1194 struct ar8327_led *aled;
1197 aled = container_of(work, struct ar8327_led, led_work);
1199 spin_lock(&aled->lock);
1200 pattern = aled->pattern;
1201 spin_unlock(&aled->lock);
1203 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1208 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1210 if (aled->pattern == pattern)
1213 aled->pattern = pattern;
1214 schedule_work(&aled->led_work);
1217 static inline struct ar8327_led *
1218 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1220 return container_of(led_cdev, struct ar8327_led, cdev);
1224 ar8327_led_blink_set(struct led_classdev *led_cdev,
1225 unsigned long *delay_on,
1226 unsigned long *delay_off)
1228 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1230 if (*delay_on == 0 && *delay_off == 0) {
1235 if (*delay_on != 125 || *delay_off != 125) {
1237 * The hardware only supports blinking at 4Hz. Fall back
1238 * to software implementation in other cases.
1243 spin_lock(&aled->lock);
1245 aled->enable_hw_mode = false;
1246 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1248 spin_unlock(&aled->lock);
1254 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1255 enum led_brightness brightness)
1257 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1261 active = (brightness != LED_OFF);
1262 active ^= aled->active_low;
1264 pattern = (active) ? AR8327_LED_PATTERN_ON :
1265 AR8327_LED_PATTERN_OFF;
1267 spin_lock(&aled->lock);
1269 aled->enable_hw_mode = false;
1270 ar8327_led_schedule_change(aled, pattern);
1272 spin_unlock(&aled->lock);
1276 ar8327_led_enable_hw_mode_show(struct device *dev,
1277 struct device_attribute *attr,
1280 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1281 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1284 spin_lock(&aled->lock);
1285 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1286 spin_unlock(&aled->lock);
1292 ar8327_led_enable_hw_mode_store(struct device *dev,
1293 struct device_attribute *attr,
1297 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1298 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1303 ret = kstrtou8(buf, 10, &value);
1307 spin_lock(&aled->lock);
1309 aled->enable_hw_mode = !!value;
1310 if (aled->enable_hw_mode)
1311 pattern = AR8327_LED_PATTERN_RULE;
1313 pattern = AR8327_LED_PATTERN_OFF;
1315 ar8327_led_schedule_change(aled, pattern);
1317 spin_unlock(&aled->lock);
1322 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1323 ar8327_led_enable_hw_mode_show,
1324 ar8327_led_enable_hw_mode_store);
1327 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1331 ret = led_classdev_register(NULL, &aled->cdev);
1335 if (aled->mode == AR8327_LED_MODE_HW) {
1336 ret = device_create_file(aled->cdev.dev,
1337 &dev_attr_enable_hw_mode);
1339 goto err_unregister;
1345 led_classdev_unregister(&aled->cdev);
1350 ar8327_led_unregister(struct ar8327_led *aled)
1352 if (aled->mode == AR8327_LED_MODE_HW)
1353 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1355 led_classdev_unregister(&aled->cdev);
1356 cancel_work_sync(&aled->led_work);
1360 ar8327_led_create(struct ar8xxx_priv *priv,
1361 const struct ar8327_led_info *led_info)
1363 struct ar8327_data *data = &priv->chip_data.ar8327;
1364 struct ar8327_led *aled;
1367 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1370 if (!led_info->name)
1373 if (led_info->led_num >= AR8327_NUM_LEDS)
1376 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1381 aled->sw_priv = priv;
1382 aled->led_num = led_info->led_num;
1383 aled->active_low = led_info->active_low;
1384 aled->mode = led_info->mode;
1386 if (aled->mode == AR8327_LED_MODE_HW)
1387 aled->enable_hw_mode = true;
1389 aled->name = (char *)(aled + 1);
1390 strcpy(aled->name, led_info->name);
1392 aled->cdev.name = aled->name;
1393 aled->cdev.brightness_set = ar8327_led_set_brightness;
1394 aled->cdev.blink_set = ar8327_led_blink_set;
1395 aled->cdev.default_trigger = led_info->default_trigger;
1397 spin_lock_init(&aled->lock);
1398 mutex_init(&aled->mutex);
1399 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1401 ret = ar8327_led_register(priv, aled);
1405 data->leds[data->num_leds++] = aled;
1415 ar8327_led_destroy(struct ar8327_led *aled)
1417 ar8327_led_unregister(aled);
1422 ar8327_leds_init(struct ar8xxx_priv *priv)
1424 struct ar8327_data *data;
1427 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1430 data = &priv->chip_data.ar8327;
1432 for (i = 0; i < data->num_leds; i++) {
1433 struct ar8327_led *aled;
1435 aled = data->leds[i];
1437 if (aled->enable_hw_mode)
1438 aled->pattern = AR8327_LED_PATTERN_RULE;
1440 aled->pattern = AR8327_LED_PATTERN_OFF;
1442 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1447 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1449 struct ar8327_data *data = &priv->chip_data.ar8327;
1452 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1455 for (i = 0; i < data->num_leds; i++) {
1456 struct ar8327_led *aled;
1458 aled = data->leds[i];
1459 ar8327_led_destroy(aled);
1466 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1467 struct ar8327_platform_data *pdata)
1469 struct ar8327_led_cfg *led_cfg;
1470 struct ar8327_data *data;
1477 priv->get_port_link = pdata->get_port_link;
1479 data = &priv->chip_data.ar8327;
1481 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1482 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1484 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1485 if (chip_is_ar8337(priv))
1486 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1488 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1489 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1490 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1491 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1492 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1494 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1497 led_cfg = pdata->led_cfg;
1499 if (led_cfg->open_drain)
1500 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1502 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1504 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1505 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1506 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1507 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1510 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1513 if (pdata->sgmii_cfg) {
1514 t = pdata->sgmii_cfg->sgmii_ctrl;
1515 if (priv->chip_rev == 1)
1516 t |= AR8327_SGMII_CTRL_EN_PLL |
1517 AR8327_SGMII_CTRL_EN_RX |
1518 AR8327_SGMII_CTRL_EN_TX;
1520 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1521 AR8327_SGMII_CTRL_EN_RX |
1522 AR8327_SGMII_CTRL_EN_TX);
1524 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1526 if (pdata->sgmii_cfg->serdes_aen)
1527 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1529 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1532 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1534 if (pdata->leds && pdata->num_leds) {
1537 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1542 for (i = 0; i < pdata->num_leds; i++)
1543 ar8327_led_create(priv, &pdata->leds[i]);
1551 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1553 const __be32 *paddr;
1557 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1558 if (!paddr || len < (2 * sizeof(*paddr)))
1561 len /= sizeof(*paddr);
1563 for (i = 0; i < len - 1; i += 2) {
1567 reg = be32_to_cpup(paddr + i);
1568 val = be32_to_cpup(paddr + i + 1);
1571 case AR8327_REG_PORT_STATUS(0):
1572 priv->chip_data.ar8327.port0_status = val;
1574 case AR8327_REG_PORT_STATUS(6):
1575 priv->chip_data.ar8327.port6_status = val;
1578 priv->write(priv, reg, val);
1587 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1594 ar8327_hw_init(struct ar8xxx_priv *priv)
1596 struct mii_bus *bus;
1600 if (priv->phy->dev.of_node)
1601 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1603 ret = ar8327_hw_config_pdata(priv,
1604 priv->phy->dev.platform_data);
1609 ar8327_leds_init(priv);
1611 bus = priv->mii_bus;
1612 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1613 ar8327_phy_fixup(priv, i);
1615 /* start aneg on the PHY */
1616 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1617 ADVERTISE_PAUSE_CAP |
1618 ADVERTISE_PAUSE_ASYM);
1619 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1620 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1629 ar8327_cleanup(struct ar8xxx_priv *priv)
1631 ar8327_leds_cleanup(priv);
1635 ar8327_init_globals(struct ar8xxx_priv *priv)
1639 /* enable CPU port and disable mirror port */
1640 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1641 AR8327_FWD_CTRL0_MIRROR_PORT;
1642 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1644 /* forward multicast and broadcast frames to CPU */
1645 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1646 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1647 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1648 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1650 /* enable jumbo frames */
1651 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1652 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1654 /* Enable MIB counters */
1655 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1656 AR8327_MODULE_EN_MIB);
1658 /* Disable EEE on all ports due to stability issues */
1659 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1660 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1661 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1662 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1663 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1664 AR8327_EEE_CTRL_DISABLE_PHY(4);
1665 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1669 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1673 if (port == AR8216_PORT_CPU)
1674 t = priv->chip_data.ar8327.port0_status;
1676 t = priv->chip_data.ar8327.port6_status;
1678 t = AR8216_PORT_STATUS_LINK_AUTO;
1680 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1681 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1683 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1684 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1685 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1687 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1688 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1690 t = AR8327_PORT_LOOKUP_LEARN;
1691 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1692 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1696 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1698 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1702 ar8327_atu_flush(struct ar8xxx_priv *priv)
1706 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1707 AR8327_ATU_FUNC_BUSY, 0);
1709 priv->write(priv, AR8327_REG_ATU_FUNC,
1710 AR8327_ATU_FUNC_OP_FLUSH);
1716 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1718 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1719 AR8327_VTU_FUNC1_BUSY, 0))
1722 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1723 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1725 op |= AR8327_VTU_FUNC1_BUSY;
1726 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1730 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1732 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1736 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1742 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1743 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1744 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1747 if ((port_mask & BIT(i)) == 0)
1748 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1749 else if (priv->vlan == 0)
1750 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1751 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1752 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1754 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1756 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1758 ar8327_vtu_op(priv, op, val);
1762 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1765 u32 egress, ingress;
1766 u32 pvid = priv->vlan_id[priv->pvid[port]];
1769 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1770 ingress = AR8216_IN_SECURE;
1772 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1773 ingress = AR8216_IN_PORT_ONLY;
1776 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1777 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1778 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1780 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1781 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1782 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1785 t |= AR8327_PORT_LOOKUP_LEARN;
1786 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1787 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1788 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1791 static const struct ar8xxx_chip ar8327_chip = {
1792 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1793 .hw_init = ar8327_hw_init,
1794 .cleanup = ar8327_cleanup,
1795 .init_globals = ar8327_init_globals,
1796 .init_port = ar8327_init_port,
1797 .setup_port = ar8327_setup_port,
1798 .read_port_status = ar8327_read_port_status,
1799 .atu_flush = ar8327_atu_flush,
1800 .vtu_flush = ar8327_vtu_flush,
1801 .vtu_load_vlan = ar8327_vtu_load_vlan,
1803 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1804 .mib_decs = ar8236_mibs,
1808 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1809 struct switch_val *val)
1811 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1812 priv->vlan = !!val->value.i;
1817 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1818 struct switch_val *val)
1820 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1821 val->value.i = priv->vlan;
1827 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1829 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1831 /* make sure no invalid PVIDs get set */
1833 if (vlan >= dev->vlans)
1836 priv->pvid[port] = vlan;
1841 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1843 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1844 *vlan = priv->pvid[port];
1849 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1850 struct switch_val *val)
1852 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1853 priv->vlan_id[val->port_vlan] = val->value.i;
1858 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1859 struct switch_val *val)
1861 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1862 val->value.i = priv->vlan_id[val->port_vlan];
1867 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1868 struct switch_port_link *link)
1870 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1872 ar8216_read_port_link(priv, port, link);
1877 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1879 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1880 u8 ports = priv->vlan_table[val->port_vlan];
1884 for (i = 0; i < dev->ports; i++) {
1885 struct switch_port *p;
1887 if (!(ports & (1 << i)))
1890 p = &val->value.ports[val->len++];
1892 if (priv->vlan_tagged & (1 << i))
1893 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1901 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1903 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1904 u8 ports = priv->vlan_table[val->port_vlan];
1908 for (i = 0; i < dev->ports; i++) {
1909 struct switch_port *p;
1911 if (!(ports & (1 << i)))
1914 p = &val->value.ports[val->len++];
1916 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1917 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1925 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1927 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1928 u8 *vt = &priv->vlan_table[val->port_vlan];
1932 for (i = 0; i < val->len; i++) {
1933 struct switch_port *p = &val->value.ports[i];
1935 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1936 priv->vlan_tagged |= (1 << p->id);
1938 priv->vlan_tagged &= ~(1 << p->id);
1939 priv->pvid[p->id] = val->port_vlan;
1941 /* make sure that an untagged port does not
1942 * appear in other vlans */
1943 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1944 if (j == val->port_vlan)
1946 priv->vlan_table[j] &= ~(1 << p->id);
1956 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1958 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1959 u8 *vt = &priv->vlan_table[val->port_vlan];
1963 for (i = 0; i < val->len; i++) {
1964 struct switch_port *p = &val->value.ports[i];
1966 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1967 if (val->port_vlan == priv->pvid[p->id]) {
1968 priv->vlan_tagged |= (1 << p->id);
1971 priv->vlan_tagged &= ~(1 << p->id);
1972 priv->pvid[p->id] = val->port_vlan;
1981 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1985 /* reset all mirror registers */
1986 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1987 AR8327_FWD_CTRL0_MIRROR_PORT,
1988 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1989 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1990 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1991 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1994 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1995 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1999 /* now enable mirroring if necessary */
2000 if (priv->source_port >= AR8327_NUM_PORTS ||
2001 priv->monitor_port >= AR8327_NUM_PORTS ||
2002 priv->source_port == priv->monitor_port) {
2006 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2007 AR8327_FWD_CTRL0_MIRROR_PORT,
2008 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2010 if (priv->mirror_rx)
2011 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2012 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2013 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2015 if (priv->mirror_tx)
2016 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2017 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2018 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2022 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2026 /* reset all mirror registers */
2027 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2028 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2029 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2030 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2031 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2032 AR8216_PORT_CTRL_MIRROR_RX,
2035 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2036 AR8216_PORT_CTRL_MIRROR_TX,
2040 /* now enable mirroring if necessary */
2041 if (priv->source_port >= AR8216_NUM_PORTS ||
2042 priv->monitor_port >= AR8216_NUM_PORTS ||
2043 priv->source_port == priv->monitor_port) {
2047 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2048 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2049 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2051 if (priv->mirror_rx)
2052 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2053 AR8216_PORT_CTRL_MIRROR_RX,
2054 AR8216_PORT_CTRL_MIRROR_RX);
2056 if (priv->mirror_tx)
2057 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2058 AR8216_PORT_CTRL_MIRROR_TX,
2059 AR8216_PORT_CTRL_MIRROR_TX);
2063 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2065 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2066 ar8327_set_mirror_regs(priv);
2068 ar8216_set_mirror_regs(priv);
2073 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2075 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2076 u8 portmask[AR8X16_MAX_PORTS];
2079 mutex_lock(&priv->reg_mutex);
2080 /* flush all vlan translation unit entries */
2081 priv->chip->vtu_flush(priv);
2083 memset(portmask, 0, sizeof(portmask));
2085 /* calculate the port destination masks and load vlans
2086 * into the vlan translation unit */
2087 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2088 u8 vp = priv->vlan_table[j];
2093 for (i = 0; i < dev->ports; i++) {
2096 portmask[i] |= vp & ~mask;
2099 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2100 priv->vlan_table[j]);
2104 * isolate all ports, but connect them to the cpu port */
2105 for (i = 0; i < dev->ports; i++) {
2106 if (i == AR8216_PORT_CPU)
2109 portmask[i] = 1 << AR8216_PORT_CPU;
2110 portmask[AR8216_PORT_CPU] |= (1 << i);
2114 /* update the port destination mask registers and tag settings */
2115 for (i = 0; i < dev->ports; i++) {
2116 priv->chip->setup_port(priv, i, portmask[i]);
2119 ar8xxx_set_mirror_regs(priv);
2121 mutex_unlock(&priv->reg_mutex);
2126 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2128 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2131 mutex_lock(&priv->reg_mutex);
2132 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2133 offsetof(struct ar8xxx_priv, vlan));
2135 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2136 priv->vlan_id[i] = i;
2138 /* Configure all ports */
2139 for (i = 0; i < dev->ports; i++)
2140 priv->chip->init_port(priv, i);
2142 priv->mirror_rx = false;
2143 priv->mirror_tx = false;
2144 priv->source_port = 0;
2145 priv->monitor_port = 0;
2147 priv->chip->init_globals(priv);
2149 mutex_unlock(&priv->reg_mutex);
2151 return ar8xxx_sw_hw_apply(dev);
2155 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2156 const struct switch_attr *attr,
2157 struct switch_val *val)
2159 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2163 if (!ar8xxx_has_mib_counters(priv))
2166 mutex_lock(&priv->mib_lock);
2168 len = priv->dev.ports * priv->chip->num_mibs *
2169 sizeof(*priv->mib_stats);
2170 memset(priv->mib_stats, '\0', len);
2171 ret = ar8xxx_mib_flush(priv);
2178 mutex_unlock(&priv->mib_lock);
2183 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2184 const struct switch_attr *attr,
2185 struct switch_val *val)
2187 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2189 mutex_lock(&priv->reg_mutex);
2190 priv->mirror_rx = !!val->value.i;
2191 ar8xxx_set_mirror_regs(priv);
2192 mutex_unlock(&priv->reg_mutex);
2198 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2199 const struct switch_attr *attr,
2200 struct switch_val *val)
2202 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2203 val->value.i = priv->mirror_rx;
2208 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2209 const struct switch_attr *attr,
2210 struct switch_val *val)
2212 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2214 mutex_lock(&priv->reg_mutex);
2215 priv->mirror_tx = !!val->value.i;
2216 ar8xxx_set_mirror_regs(priv);
2217 mutex_unlock(&priv->reg_mutex);
2223 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2224 const struct switch_attr *attr,
2225 struct switch_val *val)
2227 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2228 val->value.i = priv->mirror_tx;
2233 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2234 const struct switch_attr *attr,
2235 struct switch_val *val)
2237 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2239 mutex_lock(&priv->reg_mutex);
2240 priv->monitor_port = val->value.i;
2241 ar8xxx_set_mirror_regs(priv);
2242 mutex_unlock(&priv->reg_mutex);
2248 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2249 const struct switch_attr *attr,
2250 struct switch_val *val)
2252 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2253 val->value.i = priv->monitor_port;
2258 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2259 const struct switch_attr *attr,
2260 struct switch_val *val)
2262 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2264 mutex_lock(&priv->reg_mutex);
2265 priv->source_port = val->value.i;
2266 ar8xxx_set_mirror_regs(priv);
2267 mutex_unlock(&priv->reg_mutex);
2273 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2274 const struct switch_attr *attr,
2275 struct switch_val *val)
2277 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2278 val->value.i = priv->source_port;
2283 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2284 const struct switch_attr *attr,
2285 struct switch_val *val)
2287 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2291 if (!ar8xxx_has_mib_counters(priv))
2294 port = val->port_vlan;
2295 if (port >= dev->ports)
2298 mutex_lock(&priv->mib_lock);
2299 ret = ar8xxx_mib_capture(priv);
2303 ar8xxx_mib_fetch_port_stat(priv, port, true);
2308 mutex_unlock(&priv->mib_lock);
2313 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2314 const struct switch_attr *attr,
2315 struct switch_val *val)
2317 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2318 const struct ar8xxx_chip *chip = priv->chip;
2322 char *buf = priv->buf;
2325 if (!ar8xxx_has_mib_counters(priv))
2328 port = val->port_vlan;
2329 if (port >= dev->ports)
2332 mutex_lock(&priv->mib_lock);
2333 ret = ar8xxx_mib_capture(priv);
2337 ar8xxx_mib_fetch_port_stat(priv, port, false);
2339 len += snprintf(buf + len, sizeof(priv->buf) - len,
2340 "Port %d MIB counters\n",
2343 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2344 for (i = 0; i < chip->num_mibs; i++)
2345 len += snprintf(buf + len, sizeof(priv->buf) - len,
2347 chip->mib_decs[i].name,
2356 mutex_unlock(&priv->mib_lock);
2360 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2362 .type = SWITCH_TYPE_INT,
2363 .name = "enable_vlan",
2364 .description = "Enable VLAN mode",
2365 .set = ar8xxx_sw_set_vlan,
2366 .get = ar8xxx_sw_get_vlan,
2370 .type = SWITCH_TYPE_NOVAL,
2371 .name = "reset_mibs",
2372 .description = "Reset all MIB counters",
2373 .set = ar8xxx_sw_set_reset_mibs,
2376 .type = SWITCH_TYPE_INT,
2377 .name = "enable_mirror_rx",
2378 .description = "Enable mirroring of RX packets",
2379 .set = ar8xxx_sw_set_mirror_rx_enable,
2380 .get = ar8xxx_sw_get_mirror_rx_enable,
2384 .type = SWITCH_TYPE_INT,
2385 .name = "enable_mirror_tx",
2386 .description = "Enable mirroring of TX packets",
2387 .set = ar8xxx_sw_set_mirror_tx_enable,
2388 .get = ar8xxx_sw_get_mirror_tx_enable,
2392 .type = SWITCH_TYPE_INT,
2393 .name = "mirror_monitor_port",
2394 .description = "Mirror monitor port",
2395 .set = ar8xxx_sw_set_mirror_monitor_port,
2396 .get = ar8xxx_sw_get_mirror_monitor_port,
2397 .max = AR8216_NUM_PORTS - 1
2400 .type = SWITCH_TYPE_INT,
2401 .name = "mirror_source_port",
2402 .description = "Mirror source port",
2403 .set = ar8xxx_sw_set_mirror_source_port,
2404 .get = ar8xxx_sw_get_mirror_source_port,
2405 .max = AR8216_NUM_PORTS - 1
2409 static struct switch_attr ar8327_sw_attr_globals[] = {
2411 .type = SWITCH_TYPE_INT,
2412 .name = "enable_vlan",
2413 .description = "Enable VLAN mode",
2414 .set = ar8xxx_sw_set_vlan,
2415 .get = ar8xxx_sw_get_vlan,
2419 .type = SWITCH_TYPE_NOVAL,
2420 .name = "reset_mibs",
2421 .description = "Reset all MIB counters",
2422 .set = ar8xxx_sw_set_reset_mibs,
2425 .type = SWITCH_TYPE_INT,
2426 .name = "enable_mirror_rx",
2427 .description = "Enable mirroring of RX packets",
2428 .set = ar8xxx_sw_set_mirror_rx_enable,
2429 .get = ar8xxx_sw_get_mirror_rx_enable,
2433 .type = SWITCH_TYPE_INT,
2434 .name = "enable_mirror_tx",
2435 .description = "Enable mirroring of TX packets",
2436 .set = ar8xxx_sw_set_mirror_tx_enable,
2437 .get = ar8xxx_sw_get_mirror_tx_enable,
2441 .type = SWITCH_TYPE_INT,
2442 .name = "mirror_monitor_port",
2443 .description = "Mirror monitor port",
2444 .set = ar8xxx_sw_set_mirror_monitor_port,
2445 .get = ar8xxx_sw_get_mirror_monitor_port,
2446 .max = AR8327_NUM_PORTS - 1
2449 .type = SWITCH_TYPE_INT,
2450 .name = "mirror_source_port",
2451 .description = "Mirror source port",
2452 .set = ar8xxx_sw_set_mirror_source_port,
2453 .get = ar8xxx_sw_get_mirror_source_port,
2454 .max = AR8327_NUM_PORTS - 1
2458 static struct switch_attr ar8xxx_sw_attr_port[] = {
2460 .type = SWITCH_TYPE_NOVAL,
2461 .name = "reset_mib",
2462 .description = "Reset single port MIB counters",
2463 .set = ar8xxx_sw_set_port_reset_mib,
2466 .type = SWITCH_TYPE_STRING,
2468 .description = "Get port's MIB counters",
2470 .get = ar8xxx_sw_get_port_mib,
2474 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2476 .type = SWITCH_TYPE_INT,
2478 .description = "VLAN ID (0-4094)",
2479 .set = ar8xxx_sw_set_vid,
2480 .get = ar8xxx_sw_get_vid,
2485 static const struct switch_dev_ops ar8xxx_sw_ops = {
2487 .attr = ar8xxx_sw_attr_globals,
2488 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2491 .attr = ar8xxx_sw_attr_port,
2492 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2495 .attr = ar8xxx_sw_attr_vlan,
2496 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2498 .get_port_pvid = ar8xxx_sw_get_pvid,
2499 .set_port_pvid = ar8xxx_sw_set_pvid,
2500 .get_vlan_ports = ar8xxx_sw_get_ports,
2501 .set_vlan_ports = ar8xxx_sw_set_ports,
2502 .apply_config = ar8xxx_sw_hw_apply,
2503 .reset_switch = ar8xxx_sw_reset_switch,
2504 .get_port_link = ar8xxx_sw_get_port_link,
2507 static const struct switch_dev_ops ar8327_sw_ops = {
2509 .attr = ar8327_sw_attr_globals,
2510 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2513 .attr = ar8xxx_sw_attr_port,
2514 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2517 .attr = ar8xxx_sw_attr_vlan,
2518 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2520 .get_port_pvid = ar8xxx_sw_get_pvid,
2521 .set_port_pvid = ar8xxx_sw_set_pvid,
2522 .get_vlan_ports = ar8327_sw_get_ports,
2523 .set_vlan_ports = ar8327_sw_set_ports,
2524 .apply_config = ar8xxx_sw_hw_apply,
2525 .reset_switch = ar8xxx_sw_reset_switch,
2526 .get_port_link = ar8xxx_sw_get_port_link,
2530 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2536 val = priv->read(priv, AR8216_REG_CTRL);
2540 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2541 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2544 val = priv->read(priv, AR8216_REG_CTRL);
2548 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2553 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2554 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2556 switch (priv->chip_ver) {
2557 case AR8XXX_VER_AR8216:
2558 priv->chip = &ar8216_chip;
2560 case AR8XXX_VER_AR8236:
2561 priv->chip = &ar8236_chip;
2563 case AR8XXX_VER_AR8316:
2564 priv->chip = &ar8316_chip;
2566 case AR8XXX_VER_AR8327:
2567 priv->mii_lo_first = true;
2568 priv->chip = &ar8327_chip;
2570 case AR8XXX_VER_AR8337:
2571 priv->mii_lo_first = true;
2572 priv->chip = &ar8327_chip;
2575 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2576 priv->chip_ver, priv->chip_rev);
2585 ar8xxx_mib_work_func(struct work_struct *work)
2587 struct ar8xxx_priv *priv;
2590 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2592 mutex_lock(&priv->mib_lock);
2594 err = ar8xxx_mib_capture(priv);
2598 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2601 priv->mib_next_port++;
2602 if (priv->mib_next_port >= priv->dev.ports)
2603 priv->mib_next_port = 0;
2605 mutex_unlock(&priv->mib_lock);
2606 schedule_delayed_work(&priv->mib_work,
2607 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2611 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2615 if (!ar8xxx_has_mib_counters(priv))
2618 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2620 len = priv->dev.ports * priv->chip->num_mibs *
2621 sizeof(*priv->mib_stats);
2622 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2624 if (!priv->mib_stats)
2631 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2633 if (!ar8xxx_has_mib_counters(priv))
2636 schedule_delayed_work(&priv->mib_work,
2637 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2641 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2643 if (!ar8xxx_has_mib_counters(priv))
2646 cancel_delayed_work(&priv->mib_work);
2649 static struct ar8xxx_priv *
2652 struct ar8xxx_priv *priv;
2654 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2658 mutex_init(&priv->reg_mutex);
2659 mutex_init(&priv->mib_lock);
2660 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2666 ar8xxx_free(struct ar8xxx_priv *priv)
2668 if (priv->chip && priv->chip->cleanup)
2669 priv->chip->cleanup(priv);
2671 kfree(priv->mib_stats);
2675 static struct ar8xxx_priv *
2676 ar8xxx_create_mii(struct mii_bus *bus)
2678 struct ar8xxx_priv *priv;
2680 priv = ar8xxx_create();
2682 priv->mii_bus = bus;
2683 priv->read = ar8xxx_mii_read;
2684 priv->write = ar8xxx_mii_write;
2685 priv->rmw = ar8xxx_mii_rmw;
2692 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2694 struct switch_dev *swdev;
2697 ret = ar8xxx_id_chip(priv);
2702 swdev->cpu_port = AR8216_PORT_CPU;
2703 swdev->ops = &ar8xxx_sw_ops;
2705 if (chip_is_ar8316(priv)) {
2706 swdev->name = "Atheros AR8316";
2707 swdev->vlans = AR8X16_MAX_VLANS;
2708 swdev->ports = AR8216_NUM_PORTS;
2709 } else if (chip_is_ar8236(priv)) {
2710 swdev->name = "Atheros AR8236";
2711 swdev->vlans = AR8216_NUM_VLANS;
2712 swdev->ports = AR8216_NUM_PORTS;
2713 } else if (chip_is_ar8327(priv)) {
2714 swdev->name = "Atheros AR8327";
2715 swdev->vlans = AR8X16_MAX_VLANS;
2716 swdev->ports = AR8327_NUM_PORTS;
2717 swdev->ops = &ar8327_sw_ops;
2718 } else if (chip_is_ar8337(priv)) {
2719 swdev->name = "Atheros AR8337";
2720 swdev->vlans = AR8X16_MAX_VLANS;
2721 swdev->ports = AR8327_NUM_PORTS;
2722 swdev->ops = &ar8327_sw_ops;
2724 swdev->name = "Atheros AR8216";
2725 swdev->vlans = AR8216_NUM_VLANS;
2726 swdev->ports = AR8216_NUM_PORTS;
2729 ret = ar8xxx_mib_init(priv);
2737 ar8xxx_start(struct ar8xxx_priv *priv)
2743 ret = priv->chip->hw_init(priv);
2747 ret = ar8xxx_sw_reset_switch(&priv->dev);
2753 ar8xxx_mib_start(priv);
2759 ar8xxx_phy_config_init(struct phy_device *phydev)
2761 struct ar8xxx_priv *priv = phydev->priv;
2762 struct net_device *dev = phydev->attached_dev;
2768 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2773 if (phydev->addr != 0) {
2774 if (chip_is_ar8316(priv)) {
2775 /* switch device has been initialized, reinit */
2776 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2777 priv->initialized = false;
2778 priv->port4_phy = true;
2779 ar8316_hw_init(priv);
2786 ret = ar8xxx_start(priv);
2790 /* VID fixup only needed on ar8216 */
2791 if (chip_is_ar8216(priv)) {
2792 dev->phy_ptr = priv;
2793 dev->priv_flags |= IFF_NO_IP_ALIGN;
2794 dev->eth_mangle_rx = ar8216_mangle_rx;
2795 dev->eth_mangle_tx = ar8216_mangle_tx;
2802 ar8xxx_phy_read_status(struct phy_device *phydev)
2804 struct ar8xxx_priv *priv = phydev->priv;
2805 struct switch_port_link link;
2808 if (phydev->addr != 0)
2809 return genphy_read_status(phydev);
2811 ar8216_read_port_link(priv, phydev->addr, &link);
2812 phydev->link = !!link.link;
2816 switch (link.speed) {
2817 case SWITCH_PORT_SPEED_10:
2818 phydev->speed = SPEED_10;
2820 case SWITCH_PORT_SPEED_100:
2821 phydev->speed = SPEED_100;
2823 case SWITCH_PORT_SPEED_1000:
2824 phydev->speed = SPEED_1000;
2829 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2831 /* flush the address translation unit */
2832 mutex_lock(&priv->reg_mutex);
2833 ret = priv->chip->atu_flush(priv);
2834 mutex_unlock(&priv->reg_mutex);
2836 phydev->state = PHY_RUNNING;
2837 netif_carrier_on(phydev->attached_dev);
2838 phydev->adjust_link(phydev->attached_dev);
2844 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2846 if (phydev->addr == 0)
2849 return genphy_config_aneg(phydev);
2852 static const u32 ar8xxx_phy_ids[] = {
2854 0x004dd034, /* AR8327 */
2855 0x004dd036, /* AR8337 */
2858 0x004dd043, /* AR8236 */
2862 ar8xxx_phy_match(u32 phy_id)
2866 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2867 if (phy_id == ar8xxx_phy_ids[i])
2874 ar8xxx_is_possible(struct mii_bus *bus)
2878 for (i = 0; i < 4; i++) {
2881 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2882 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2883 if (!ar8xxx_phy_match(phy_id)) {
2884 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2885 dev_name(&bus->dev), i, phy_id);
2894 ar8xxx_phy_probe(struct phy_device *phydev)
2896 struct ar8xxx_priv *priv;
2897 struct switch_dev *swdev;
2900 /* skip PHYs at unused adresses */
2901 if (phydev->addr != 0 && phydev->addr != 4)
2904 if (!ar8xxx_is_possible(phydev->bus))
2907 mutex_lock(&ar8xxx_dev_list_lock);
2908 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2909 if (priv->mii_bus == phydev->bus)
2912 priv = ar8xxx_create_mii(phydev->bus);
2918 ret = ar8xxx_probe_switch(priv);
2923 swdev->alias = dev_name(&priv->mii_bus->dev);
2924 ret = register_switch(swdev, NULL);
2928 pr_info("%s: %s rev. %u switch registered on %s\n",
2929 swdev->devname, swdev->name, priv->chip_rev,
2930 dev_name(&priv->mii_bus->dev));
2935 if (phydev->addr == 0) {
2936 if (ar8xxx_has_gige(priv)) {
2937 phydev->supported = SUPPORTED_1000baseT_Full;
2938 phydev->advertising = ADVERTISED_1000baseT_Full;
2940 phydev->supported = SUPPORTED_100baseT_Full;
2941 phydev->advertising = ADVERTISED_100baseT_Full;
2944 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2947 ret = ar8xxx_start(priv);
2949 goto err_unregister_switch;
2952 if (ar8xxx_has_gige(priv)) {
2953 phydev->supported |= SUPPORTED_1000baseT_Full;
2954 phydev->advertising |= ADVERTISED_1000baseT_Full;
2958 phydev->priv = priv;
2960 list_add(&priv->list, &ar8xxx_dev_list);
2962 mutex_unlock(&ar8xxx_dev_list_lock);
2966 err_unregister_switch:
2967 if (--priv->use_count)
2970 unregister_switch(&priv->dev);
2975 mutex_unlock(&ar8xxx_dev_list_lock);
2980 ar8xxx_phy_detach(struct phy_device *phydev)
2982 struct net_device *dev = phydev->attached_dev;
2987 dev->phy_ptr = NULL;
2988 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2989 dev->eth_mangle_rx = NULL;
2990 dev->eth_mangle_tx = NULL;
2994 ar8xxx_phy_remove(struct phy_device *phydev)
2996 struct ar8xxx_priv *priv = phydev->priv;
3001 phydev->priv = NULL;
3002 if (--priv->use_count > 0)
3005 mutex_lock(&ar8xxx_dev_list_lock);
3006 list_del(&priv->list);
3007 mutex_unlock(&ar8xxx_dev_list_lock);
3009 unregister_switch(&priv->dev);
3010 ar8xxx_mib_stop(priv);
3014 static struct phy_driver ar8xxx_phy_driver = {
3015 .phy_id = 0x004d0000,
3016 .name = "Atheros AR8216/AR8236/AR8316",
3017 .phy_id_mask = 0xffff0000,
3018 .features = PHY_BASIC_FEATURES,
3019 .probe = ar8xxx_phy_probe,
3020 .remove = ar8xxx_phy_remove,
3021 .detach = ar8xxx_phy_detach,
3022 .config_init = ar8xxx_phy_config_init,
3023 .config_aneg = ar8xxx_phy_config_aneg,
3024 .read_status = ar8xxx_phy_read_status,
3025 .driver = { .owner = THIS_MODULE },
3031 return phy_driver_register(&ar8xxx_phy_driver);
3037 phy_driver_unregister(&ar8xxx_phy_driver);
3040 module_init(ar8xxx_init);
3041 module_exit(ar8xxx_exit);
3042 MODULE_LICENSE("GPL");