2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
44 #define AR8XXX_CAP_GIGE BIT(0)
47 AR8XXX_VER_AR8216 = 0x01,
48 AR8XXX_VER_AR8236 = 0x03,
49 AR8XXX_VER_AR8316 = 0x10,
50 AR8XXX_VER_AR8327 = 0x12,
56 int (*hw_init)(struct ar8216_priv *priv);
57 void (*init_globals)(struct ar8216_priv *priv);
58 void (*init_port)(struct ar8216_priv *priv, int port);
59 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
60 u32 ingress, u32 members, u32 pvid);
61 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
62 int (*atu_flush)(struct ar8216_priv *priv);
63 void (*vtu_flush)(struct ar8216_priv *priv);
64 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
68 struct switch_dev dev;
69 struct phy_device *phy;
70 u32 (*read)(struct ar8216_priv *priv, int reg);
71 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
72 const struct net_device_ops *ndo_old;
73 struct net_device_ops ndo;
74 struct mutex reg_mutex;
77 const struct ar8xxx_chip *chip;
85 /* all fields below are cleared on reset */
87 u16 vlan_id[AR8X16_MAX_VLANS];
88 u8 vlan_table[AR8X16_MAX_VLANS];
90 u16 pvid[AR8X16_MAX_PORTS];
93 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
95 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
97 return priv->chip->caps & AR8XXX_CAP_GIGE;
100 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
102 return priv->chip_ver == AR8XXX_VER_AR8216;
105 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
107 return priv->chip_ver == AR8XXX_VER_AR8236;
110 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
112 return priv->chip_ver == AR8XXX_VER_AR8316;
115 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
117 return priv->chip_ver == AR8XXX_VER_AR8327;
121 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
124 *r1 = regaddr & 0x1e;
130 *page = regaddr & 0x1ff;
134 ar8216_mii_read(struct ar8216_priv *priv, int reg)
136 struct phy_device *phy = priv->phy;
137 struct mii_bus *bus = phy->bus;
141 split_addr((u32) reg, &r1, &r2, &page);
143 mutex_lock(&bus->mdio_lock);
145 bus->write(bus, 0x18, 0, page);
146 usleep_range(1000, 2000); /* wait for the page switch to propagate */
147 lo = bus->read(bus, 0x10 | r2, r1);
148 hi = bus->read(bus, 0x10 | r2, r1 + 1);
150 mutex_unlock(&bus->mdio_lock);
152 return (hi << 16) | lo;
156 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
158 struct phy_device *phy = priv->phy;
159 struct mii_bus *bus = phy->bus;
163 split_addr((u32) reg, &r1, &r2, &r3);
165 hi = (u16) (val >> 16);
167 mutex_lock(&bus->mdio_lock);
169 bus->write(bus, 0x18, 0, r3);
170 usleep_range(1000, 2000); /* wait for the page switch to propagate */
171 if (priv->mii_lo_first) {
172 bus->write(bus, 0x10 | r2, r1, lo);
173 bus->write(bus, 0x10 | r2, r1 + 1, hi);
175 bus->write(bus, 0x10 | r2, r1 + 1, hi);
176 bus->write(bus, 0x10 | r2, r1, lo);
179 mutex_unlock(&bus->mdio_lock);
183 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
184 u16 dbg_addr, u16 dbg_data)
186 struct mii_bus *bus = priv->phy->bus;
188 mutex_lock(&bus->mdio_lock);
189 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
190 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
191 mutex_unlock(&bus->mdio_lock);
195 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
199 lockdep_assert_held(&priv->reg_mutex);
201 v = priv->read(priv, reg);
204 priv->write(priv, reg, v);
210 ar8216_read_port_link(struct ar8216_priv *priv, int port,
211 struct switch_port_link *link)
216 memset(link, '\0', sizeof(*link));
218 status = priv->chip->read_port_status(priv, port);
220 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
222 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
229 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
230 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
231 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
233 speed = (status & AR8216_PORT_STATUS_SPEED) >>
234 AR8216_PORT_STATUS_SPEED_S;
237 case AR8216_PORT_SPEED_10M:
238 link->speed = SWITCH_PORT_SPEED_10;
240 case AR8216_PORT_SPEED_100M:
241 link->speed = SWITCH_PORT_SPEED_100;
243 case AR8216_PORT_SPEED_1000M:
244 link->speed = SWITCH_PORT_SPEED_1000;
247 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
252 static struct sk_buff *
253 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
255 struct ar8216_priv *priv = dev->phy_ptr;
264 if (unlikely(skb_headroom(skb) < 2)) {
265 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
269 buf = skb_push(skb, 2);
277 dev_kfree_skb_any(skb);
282 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
284 struct ar8216_priv *priv;
292 /* don't strip the header if vlan mode is disabled */
296 /* strip header, get vlan id */
300 /* check for vlan header presence */
301 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
306 /* no need to fix up packets coming from a tagged source */
307 if (priv->vlan_tagged & (1 << port))
310 /* lookup port vid from local table, the switch passes an invalid vlan id */
311 vlan = priv->vlan_id[priv->pvid[port]];
314 buf[14 + 2] |= vlan >> 8;
315 buf[15 + 2] = vlan & 0xff;
319 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
325 t = priv->read(priv, reg);
326 if ((t & mask) == val)
335 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
336 (unsigned int) reg, t, mask, val);
341 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
343 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
345 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
346 val &= AR8216_VTUDATA_MEMBER;
347 val |= AR8216_VTUDATA_VALID;
348 priv->write(priv, AR8216_REG_VTU_DATA, val);
350 op |= AR8216_VTU_ACTIVE;
351 priv->write(priv, AR8216_REG_VTU, op);
355 ar8216_vtu_flush(struct ar8216_priv *priv)
357 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
361 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
365 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
366 ar8216_vtu_op(priv, op, port_mask);
370 ar8216_atu_flush(struct ar8216_priv *priv)
374 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
376 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
382 ar8216_read_port_status(struct ar8216_priv *priv, int port)
384 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
388 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
389 u32 members, u32 pvid)
393 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
394 header = AR8216_PORT_CTRL_HEADER;
398 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
399 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
400 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
401 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
402 AR8216_PORT_CTRL_LEARN | header |
403 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
404 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
406 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
407 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
408 AR8216_PORT_VLAN_DEFAULT_ID,
409 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
410 (ingress << AR8216_PORT_VLAN_MODE_S) |
411 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
415 ar8216_hw_init(struct ar8216_priv *priv)
421 ar8216_init_globals(struct ar8216_priv *priv)
423 /* standard atheros magic */
424 priv->write(priv, 0x38, 0xc000050e);
426 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
427 AR8216_GCTRL_MTU, 1518 + 8 + 2);
431 ar8216_init_port(struct ar8216_priv *priv, int port)
433 /* Enable port learning and tx */
434 priv->write(priv, AR8216_REG_PORT_CTRL(port),
435 AR8216_PORT_CTRL_LEARN |
436 (4 << AR8216_PORT_CTRL_STATE_S));
438 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
440 if (port == AR8216_PORT_CPU) {
441 priv->write(priv, AR8216_REG_PORT_STATUS(port),
442 AR8216_PORT_STATUS_LINK_UP |
443 (ar8xxx_has_gige(priv) ?
444 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
445 AR8216_PORT_STATUS_TXMAC |
446 AR8216_PORT_STATUS_RXMAC |
447 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
448 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
449 AR8216_PORT_STATUS_DUPLEX);
451 priv->write(priv, AR8216_REG_PORT_STATUS(port),
452 AR8216_PORT_STATUS_LINK_AUTO);
456 static const struct ar8xxx_chip ar8216_chip = {
457 .hw_init = ar8216_hw_init,
458 .init_globals = ar8216_init_globals,
459 .init_port = ar8216_init_port,
460 .setup_port = ar8216_setup_port,
461 .read_port_status = ar8216_read_port_status,
462 .atu_flush = ar8216_atu_flush,
463 .vtu_flush = ar8216_vtu_flush,
464 .vtu_load_vlan = ar8216_vtu_load_vlan,
468 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
469 u32 members, u32 pvid)
471 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
472 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
473 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
474 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
475 AR8216_PORT_CTRL_LEARN |
476 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
477 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
479 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
480 AR8236_PORT_VLAN_DEFAULT_ID,
481 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
483 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
484 AR8236_PORT_VLAN2_VLAN_MODE |
485 AR8236_PORT_VLAN2_MEMBER,
486 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
487 (members << AR8236_PORT_VLAN2_MEMBER_S));
491 ar8236_hw_init(struct ar8216_priv *priv)
496 if (priv->initialized)
499 /* Initialize the PHYs */
500 bus = priv->phy->bus;
501 for (i = 0; i < 5; i++) {
502 mdiobus_write(bus, i, MII_ADVERTISE,
503 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
504 ADVERTISE_PAUSE_ASYM);
505 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
509 priv->initialized = true;
514 ar8236_init_globals(struct ar8216_priv *priv)
516 /* enable jumbo frames */
517 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
518 AR8316_GCTRL_MTU, 9018 + 8 + 2);
521 static const struct ar8xxx_chip ar8236_chip = {
522 .hw_init = ar8236_hw_init,
523 .init_globals = ar8236_init_globals,
524 .init_port = ar8216_init_port,
525 .setup_port = ar8236_setup_port,
526 .read_port_status = ar8216_read_port_status,
527 .atu_flush = ar8216_atu_flush,
528 .vtu_flush = ar8216_vtu_flush,
529 .vtu_load_vlan = ar8216_vtu_load_vlan,
533 ar8316_hw_init(struct ar8216_priv *priv)
539 val = priv->read(priv, 0x8);
541 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
542 if (priv->port4_phy) {
543 /* value taken from Ubiquiti RouterStation Pro */
545 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
548 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
550 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
551 /* value taken from AVM Fritz!Box 7390 sources */
554 /* no known value for phy interface */
555 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
556 priv->phy->interface);
563 priv->write(priv, 0x8, newval);
565 /* Initialize the ports */
566 bus = priv->phy->bus;
567 for (i = 0; i < 5; i++) {
568 if ((i == 4) && priv->port4_phy &&
569 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
570 /* work around for phy4 rgmii mode */
571 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
573 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
575 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
579 /* initialize the port itself */
580 mdiobus_write(bus, i, MII_ADVERTISE,
581 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
582 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
583 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
588 priv->initialized = true;
593 ar8316_init_globals(struct ar8216_priv *priv)
595 /* standard atheros magic */
596 priv->write(priv, 0x38, 0xc000050e);
598 /* enable cpu port to receive multicast and broadcast frames */
599 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
601 /* enable jumbo frames */
602 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
603 AR8316_GCTRL_MTU, 9018 + 8 + 2);
606 static const struct ar8xxx_chip ar8316_chip = {
607 .caps = AR8XXX_CAP_GIGE,
608 .hw_init = ar8316_hw_init,
609 .init_globals = ar8316_init_globals,
610 .init_port = ar8216_init_port,
611 .setup_port = ar8216_setup_port,
612 .read_port_status = ar8216_read_port_status,
613 .atu_flush = ar8216_atu_flush,
614 .vtu_flush = ar8216_vtu_flush,
615 .vtu_load_vlan = ar8216_vtu_load_vlan,
619 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
631 case AR8327_PAD_MAC2MAC_MII:
632 t = AR8327_PAD_MAC_MII_EN;
634 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
636 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
639 case AR8327_PAD_MAC2MAC_GMII:
640 t = AR8327_PAD_MAC_GMII_EN;
642 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
644 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
647 case AR8327_PAD_MAC_SGMII:
648 t = AR8327_PAD_SGMII_EN;
651 case AR8327_PAD_MAC2PHY_MII:
652 t = AR8327_PAD_PHY_MII_EN;
654 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
656 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
659 case AR8327_PAD_MAC2PHY_GMII:
660 t = AR8327_PAD_PHY_GMII_EN;
661 if (cfg->pipe_rxclk_sel)
662 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
664 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
666 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
669 case AR8327_PAD_MAC_RGMII:
670 t = AR8327_PAD_RGMII_EN;
671 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
672 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
673 if (cfg->rxclk_delay_en)
674 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
675 if (cfg->txclk_delay_en)
676 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
679 case AR8327_PAD_PHY_GMII:
680 t = AR8327_PAD_PHYX_GMII_EN;
683 case AR8327_PAD_PHY_RGMII:
684 t = AR8327_PAD_PHYX_RGMII_EN;
687 case AR8327_PAD_PHY_MII:
688 t = AR8327_PAD_PHYX_MII_EN;
696 ar8327_hw_init(struct ar8216_priv *priv)
698 struct ar8327_platform_data *pdata;
702 pdata = priv->phy->dev.platform_data;
706 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
707 priv->write(priv, AR8327_REG_PAD0_MODE, t);
708 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
709 priv->write(priv, AR8327_REG_PAD5_MODE, t);
710 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
711 priv->write(priv, AR8327_REG_PAD6_MODE, t);
713 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
716 for (i = 0; i < AR8327_NUM_PHYS; i++) {
717 /* For 100M waveform */
718 ar8216_phy_dbg_write(priv, i, 0, 0x02ea);
720 /* Turn on Gigabit clock */
721 ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0);
728 ar8327_init_globals(struct ar8216_priv *priv)
732 /* enable CPU port and disable mirror port */
733 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
734 AR8327_FWD_CTRL0_MIRROR_PORT;
735 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
737 /* forward multicast and broadcast frames to CPU */
738 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
739 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
740 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
741 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
744 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
745 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
749 ar8327_init_cpuport(struct ar8216_priv *priv)
751 struct ar8327_platform_data *pdata;
752 struct ar8327_port_cfg *cfg;
755 pdata = priv->phy->dev.platform_data;
759 cfg = &pdata->cpuport_cfg;
760 if (!cfg->force_link) {
761 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
762 AR8216_PORT_STATUS_LINK_AUTO);
766 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
767 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
768 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
769 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
770 switch (cfg->speed) {
771 case AR8327_PORT_SPEED_10:
772 t |= AR8216_PORT_SPEED_10M;
774 case AR8327_PORT_SPEED_100:
775 t |= AR8216_PORT_SPEED_100M;
777 case AR8327_PORT_SPEED_1000:
778 t |= AR8216_PORT_SPEED_1000M;
782 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
786 ar8327_init_port(struct ar8216_priv *priv, int port)
790 if (port == AR8216_PORT_CPU) {
791 ar8327_init_cpuport(priv);
793 t = AR8216_PORT_STATUS_LINK_AUTO;
794 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
797 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
799 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
801 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
802 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
804 t = AR8327_PORT_LOOKUP_LEARN;
805 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
806 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
810 ar8327_read_port_status(struct ar8216_priv *priv, int port)
812 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
816 ar8327_atu_flush(struct ar8216_priv *priv)
820 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
821 AR8327_ATU_FUNC_BUSY, 0);
823 priv->write(priv, AR8327_REG_ATU_FUNC,
824 AR8327_ATU_FUNC_OP_FLUSH);
830 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
832 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
833 AR8327_VTU_FUNC1_BUSY, 0))
836 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
837 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
839 op |= AR8327_VTU_FUNC1_BUSY;
840 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
844 ar8327_vtu_flush(struct ar8216_priv *priv)
846 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
850 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
856 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
857 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
858 for (i = 0; i < AR8327_NUM_PORTS; i++) {
861 if ((port_mask & BIT(i)) == 0)
862 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
863 else if (priv->vlan == 0)
864 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
865 else if (priv->vlan_tagged & BIT(i))
866 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
868 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
870 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
872 ar8327_vtu_op(priv, op, val);
876 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
877 u32 members, u32 pvid)
882 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
883 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
884 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
886 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
888 case AR8216_OUT_KEEP:
889 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
891 case AR8216_OUT_STRIP_VLAN:
892 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
894 case AR8216_OUT_ADD_VLAN:
895 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
899 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
900 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
901 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
904 t |= AR8327_PORT_LOOKUP_LEARN;
905 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
906 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
907 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
910 static const struct ar8xxx_chip ar8327_chip = {
911 .caps = AR8XXX_CAP_GIGE,
912 .hw_init = ar8327_hw_init,
913 .init_globals = ar8327_init_globals,
914 .init_port = ar8327_init_port,
915 .setup_port = ar8327_setup_port,
916 .read_port_status = ar8327_read_port_status,
917 .atu_flush = ar8327_atu_flush,
918 .vtu_flush = ar8327_vtu_flush,
919 .vtu_load_vlan = ar8327_vtu_load_vlan,
923 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
924 struct switch_val *val)
926 struct ar8216_priv *priv = to_ar8216(dev);
927 priv->vlan = !!val->value.i;
932 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
933 struct switch_val *val)
935 struct ar8216_priv *priv = to_ar8216(dev);
936 val->value.i = priv->vlan;
942 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
944 struct ar8216_priv *priv = to_ar8216(dev);
946 /* make sure no invalid PVIDs get set */
948 if (vlan >= dev->vlans)
951 priv->pvid[port] = vlan;
956 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
958 struct ar8216_priv *priv = to_ar8216(dev);
959 *vlan = priv->pvid[port];
964 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
965 struct switch_val *val)
967 struct ar8216_priv *priv = to_ar8216(dev);
968 priv->vlan_id[val->port_vlan] = val->value.i;
973 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
974 struct switch_val *val)
976 struct ar8216_priv *priv = to_ar8216(dev);
977 val->value.i = priv->vlan_id[val->port_vlan];
982 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
983 struct switch_port_link *link)
985 struct ar8216_priv *priv = to_ar8216(dev);
987 ar8216_read_port_link(priv, port, link);
992 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
994 struct ar8216_priv *priv = to_ar8216(dev);
995 u8 ports = priv->vlan_table[val->port_vlan];
999 for (i = 0; i < dev->ports; i++) {
1000 struct switch_port *p;
1002 if (!(ports & (1 << i)))
1005 p = &val->value.ports[val->len++];
1007 if (priv->vlan_tagged & (1 << i))
1008 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1016 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1018 struct ar8216_priv *priv = to_ar8216(dev);
1019 u8 *vt = &priv->vlan_table[val->port_vlan];
1023 for (i = 0; i < val->len; i++) {
1024 struct switch_port *p = &val->value.ports[i];
1026 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1027 priv->vlan_tagged |= (1 << p->id);
1029 priv->vlan_tagged &= ~(1 << p->id);
1030 priv->pvid[p->id] = val->port_vlan;
1032 /* make sure that an untagged port does not
1033 * appear in other vlans */
1034 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1035 if (j == val->port_vlan)
1037 priv->vlan_table[j] &= ~(1 << p->id);
1047 ar8216_sw_hw_apply(struct switch_dev *dev)
1049 struct ar8216_priv *priv = to_ar8216(dev);
1050 u8 portmask[AR8X16_MAX_PORTS];
1053 mutex_lock(&priv->reg_mutex);
1054 /* flush all vlan translation unit entries */
1055 priv->chip->vtu_flush(priv);
1057 memset(portmask, 0, sizeof(portmask));
1059 /* calculate the port destination masks and load vlans
1060 * into the vlan translation unit */
1061 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1062 u8 vp = priv->vlan_table[j];
1067 for (i = 0; i < dev->ports; i++) {
1070 portmask[i] |= vp & ~mask;
1073 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1074 priv->vlan_table[j]);
1078 * isolate all ports, but connect them to the cpu port */
1079 for (i = 0; i < dev->ports; i++) {
1080 if (i == AR8216_PORT_CPU)
1083 portmask[i] = 1 << AR8216_PORT_CPU;
1084 portmask[AR8216_PORT_CPU] |= (1 << i);
1088 /* update the port destination mask registers and tag settings */
1089 for (i = 0; i < dev->ports; i++) {
1090 int egress, ingress;
1094 pvid = priv->vlan_id[priv->pvid[i]];
1095 if (priv->vlan_tagged & (1 << i))
1096 egress = AR8216_OUT_ADD_VLAN;
1098 egress = AR8216_OUT_STRIP_VLAN;
1099 ingress = AR8216_IN_SECURE;
1102 egress = AR8216_OUT_KEEP;
1103 ingress = AR8216_IN_PORT_ONLY;
1106 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1109 mutex_unlock(&priv->reg_mutex);
1114 ar8216_sw_reset_switch(struct switch_dev *dev)
1116 struct ar8216_priv *priv = to_ar8216(dev);
1119 mutex_lock(&priv->reg_mutex);
1120 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1121 offsetof(struct ar8216_priv, vlan));
1123 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1124 priv->vlan_id[i] = i;
1126 /* Configure all ports */
1127 for (i = 0; i < dev->ports; i++)
1128 priv->chip->init_port(priv, i);
1130 priv->chip->init_globals(priv);
1131 mutex_unlock(&priv->reg_mutex);
1133 return ar8216_sw_hw_apply(dev);
1136 static struct switch_attr ar8216_globals[] = {
1138 .type = SWITCH_TYPE_INT,
1139 .name = "enable_vlan",
1140 .description = "Enable VLAN mode",
1141 .set = ar8216_sw_set_vlan,
1142 .get = ar8216_sw_get_vlan,
1147 static struct switch_attr ar8216_port[] = {
1150 static struct switch_attr ar8216_vlan[] = {
1152 .type = SWITCH_TYPE_INT,
1154 .description = "VLAN ID (0-4094)",
1155 .set = ar8216_sw_set_vid,
1156 .get = ar8216_sw_get_vid,
1161 static const struct switch_dev_ops ar8216_sw_ops = {
1163 .attr = ar8216_globals,
1164 .n_attr = ARRAY_SIZE(ar8216_globals),
1167 .attr = ar8216_port,
1168 .n_attr = ARRAY_SIZE(ar8216_port),
1171 .attr = ar8216_vlan,
1172 .n_attr = ARRAY_SIZE(ar8216_vlan),
1174 .get_port_pvid = ar8216_sw_get_pvid,
1175 .set_port_pvid = ar8216_sw_set_pvid,
1176 .get_vlan_ports = ar8216_sw_get_ports,
1177 .set_vlan_ports = ar8216_sw_set_ports,
1178 .apply_config = ar8216_sw_hw_apply,
1179 .reset_switch = ar8216_sw_reset_switch,
1180 .get_port_link = ar8216_sw_get_port_link,
1184 ar8216_id_chip(struct ar8216_priv *priv)
1190 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1194 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1195 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1198 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1202 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1207 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1208 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1210 switch (priv->chip_ver) {
1211 case AR8XXX_VER_AR8216:
1212 priv->chip = &ar8216_chip;
1214 case AR8XXX_VER_AR8236:
1215 priv->chip = &ar8236_chip;
1217 case AR8XXX_VER_AR8316:
1218 priv->chip = &ar8316_chip;
1220 case AR8XXX_VER_AR8327:
1221 priv->mii_lo_first = true;
1222 priv->chip = &ar8327_chip;
1226 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1227 priv->chip_ver, priv->chip_rev,
1228 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1229 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1238 ar8216_config_init(struct phy_device *pdev)
1240 struct ar8216_priv *priv = pdev->priv;
1241 struct net_device *dev = pdev->attached_dev;
1242 struct switch_dev *swdev;
1246 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1253 ret = ar8216_id_chip(priv);
1257 if (pdev->addr != 0) {
1258 if (ar8xxx_has_gige(priv)) {
1259 pdev->supported |= SUPPORTED_1000baseT_Full;
1260 pdev->advertising |= ADVERTISED_1000baseT_Full;
1263 if (chip_is_ar8316(priv)) {
1264 /* check if we're attaching to the switch twice */
1265 pdev = pdev->bus->phy_map[0];
1271 /* switch device has not been initialized, reuse priv */
1273 priv->port4_phy = true;
1280 /* switch device has been initialized, reinit */
1282 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1283 priv->initialized = false;
1284 priv->port4_phy = true;
1285 ar8316_hw_init(priv);
1293 if (ar8xxx_has_gige(priv))
1294 pdev->supported = SUPPORTED_1000baseT_Full;
1296 pdev->supported = SUPPORTED_100baseT_Full;
1297 pdev->advertising = pdev->supported;
1299 mutex_init(&priv->reg_mutex);
1300 priv->read = ar8216_mii_read;
1301 priv->write = ar8216_mii_write;
1306 swdev->cpu_port = AR8216_PORT_CPU;
1307 swdev->ops = &ar8216_sw_ops;
1308 swdev->ports = AR8216_NUM_PORTS;
1310 if (chip_is_ar8316(priv)) {
1311 swdev->name = "Atheros AR8316";
1312 swdev->vlans = AR8X16_MAX_VLANS;
1314 if (priv->port4_phy) {
1315 /* port 5 connected to the other mac, therefore unusable */
1316 swdev->ports = (AR8216_NUM_PORTS - 1);
1318 } else if (chip_is_ar8236(priv)) {
1319 swdev->name = "Atheros AR8236";
1320 swdev->vlans = AR8216_NUM_VLANS;
1321 swdev->ports = AR8216_NUM_PORTS;
1322 } else if (chip_is_ar8327(priv)) {
1323 swdev->name = "Atheros AR8327";
1324 swdev->vlans = AR8X16_MAX_VLANS;
1325 swdev->ports = AR8327_NUM_PORTS;
1327 swdev->name = "Atheros AR8216";
1328 swdev->vlans = AR8216_NUM_VLANS;
1331 ret = register_switch(&priv->dev, pdev->attached_dev);
1335 printk(KERN_INFO "%s: %s switch driver attached.\n",
1336 pdev->attached_dev->name, swdev->name);
1340 ret = priv->chip->hw_init(priv);
1344 ret = ar8216_sw_reset_switch(&priv->dev);
1348 dev->phy_ptr = priv;
1350 /* VID fixup only needed on ar8216 */
1351 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1352 dev->priv_flags |= IFF_NO_IP_ALIGN;
1353 dev->eth_mangle_rx = ar8216_mangle_rx;
1354 dev->eth_mangle_tx = ar8216_mangle_tx;
1367 ar8216_read_status(struct phy_device *phydev)
1369 struct ar8216_priv *priv = phydev->priv;
1370 struct switch_port_link link;
1373 if (phydev->addr != 0)
1374 return genphy_read_status(phydev);
1376 ar8216_read_port_link(priv, phydev->addr, &link);
1377 phydev->link = !!link.link;
1381 switch (link.speed) {
1382 case SWITCH_PORT_SPEED_10:
1383 phydev->speed = SPEED_10;
1385 case SWITCH_PORT_SPEED_100:
1386 phydev->speed = SPEED_100;
1388 case SWITCH_PORT_SPEED_1000:
1389 phydev->speed = SPEED_1000;
1394 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1396 /* flush the address translation unit */
1397 mutex_lock(&priv->reg_mutex);
1398 ret = priv->chip->atu_flush(priv);
1399 mutex_unlock(&priv->reg_mutex);
1401 phydev->state = PHY_RUNNING;
1402 netif_carrier_on(phydev->attached_dev);
1403 phydev->adjust_link(phydev->attached_dev);
1409 ar8216_config_aneg(struct phy_device *phydev)
1411 if (phydev->addr == 0)
1414 return genphy_config_aneg(phydev);
1418 ar8216_probe(struct phy_device *pdev)
1420 struct ar8216_priv priv;
1423 return ar8216_id_chip(&priv);
1427 ar8216_remove(struct phy_device *pdev)
1429 struct ar8216_priv *priv = pdev->priv;
1430 struct net_device *dev = pdev->attached_dev;
1435 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1436 dev->eth_mangle_rx = NULL;
1437 dev->eth_mangle_tx = NULL;
1439 if (pdev->addr == 0)
1440 unregister_switch(&priv->dev);
1444 static struct phy_driver ar8216_driver = {
1445 .phy_id = 0x004d0000,
1446 .name = "Atheros AR8216/AR8236/AR8316",
1447 .phy_id_mask = 0xffff0000,
1448 .features = PHY_BASIC_FEATURES,
1449 .probe = ar8216_probe,
1450 .remove = ar8216_remove,
1451 .config_init = &ar8216_config_init,
1452 .config_aneg = &ar8216_config_aneg,
1453 .read_status = &ar8216_read_status,
1454 .driver = { .owner = THIS_MODULE },
1460 return phy_driver_register(&ar8216_driver);
1466 phy_driver_unregister(&ar8216_driver);
1469 module_init(ar8216_init);
1470 module_exit(ar8216_exit);
1471 MODULE_LICENSE("GPL");