target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/lockdep.h>
  33 #include <linux/ar8216_platform.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/version.h>
  36
  37 #include "ar8216.h"
  38
  39 extern const struct ar8xxx_chip ar8327_chip;
  40 extern const struct ar8xxx_chip ar8337_chip;
  41
  42 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  43
  44 #define MIB_DESC(_s , _o, _n)   \
  45         {                       \
  46                 .size = (_s),   \
  47                 .offset = (_o), \
  48                 .name = (_n),   \
  49         }
  50
  51 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  52         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  53         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  54         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  55         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  56         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  57         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  58         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  59         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  60         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  64         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  65         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  66         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  67         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  68         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  69         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  70         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  71         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  72         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  73         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  74         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  75         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  79         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  80         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  81         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  82         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  83         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  84         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  85         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  86         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  87         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  89 };
  90
  91 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  92         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  93         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  94         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  95         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  96         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  97         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  98         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
  99         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 100         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 105         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 106         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 107         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 108         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 109         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 110         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 111         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 112         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 113         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 114         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 115         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 116         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 121         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 122         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 123         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 124         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 125         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 126         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 127         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 128         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 129         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 131 };
 132
 133 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 134 static LIST_HEAD(ar8xxx_dev_list);
 135
 136 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 137 static int
 138 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 139 {
 140         unsigned int sleep_msecs = 20;
 141         int ret, elapsed, i;
 142
 143         for (elapsed = sleep_msecs; elapsed <= 600;
 144              elapsed += sleep_msecs) {
 145                 msleep(sleep_msecs);
 146                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 147                         ret = mdiobus_read(bus, i, MII_BMCR);
 148                         if (ret < 0)
 149                                 return ret;
 150                         if (ret & BMCR_RESET)
 151                                 break;
 152                         if (i == AR8XXX_NUM_PHYS - 1) {
 153                                 usleep_range(1000, 2000);
 154                                 return 0;
 155                         }
 156                 }
 157         }
 158         return -ETIMEDOUT;
 159 }
 160
 161 static int
 162 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 163 {
 164         int ret;
 165
 166         if (phydev->autoneg != AUTONEG_ENABLE)
 167                 return 0;
 168         /*
 169          * BMCR_ANENABLE might have been cleared
 170          * by phy_init_hw in certain kernel versions
 171          * therefore check for it
 172          */
 173         ret = phy_read(phydev, MII_BMCR);
 174         if (ret < 0)
 175                 return ret;
 176         if (ret & BMCR_ANENABLE)
 177                 return 0;
 178
 179         dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
 180         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 181         return phy_write(phydev, MII_BMCR, ret);
 182 }
 183
 184 void
 185 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 186 {
 187         int i;
 188         struct mii_bus *bus;
 189
 190         bus = priv->mii_bus;
 191         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 192                 if (priv->chip->phy_fixup)
 193                         priv->chip->phy_fixup(priv, i);
 194
 195                 /* initialize the port itself */
 196                 mdiobus_write(bus, i, MII_ADVERTISE,
 197                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 198                 if (ar8xxx_has_gige(priv))
 199                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 200                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 201         }
 202
 203         ar8xxx_phy_poll_reset(bus);
 204 }
 205
 206 u32
 207 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 208 {
 209         struct mii_bus *bus = priv->mii_bus;
 210         u16 lo, hi;
 211
 212         lo = bus->read(bus, phy_id, regnum);
 213         hi = bus->read(bus, phy_id, regnum + 1);
 214
 215         return (hi << 16) | lo;
 216 }
 217
 218 void
 219 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 220 {
 221         struct mii_bus *bus = priv->mii_bus;
 222         u16 lo, hi;
 223
 224         lo = val & 0xffff;
 225         hi = (u16) (val >> 16);
 226
 227         if (priv->chip->mii_lo_first)
 228         {
 229                 bus->write(bus, phy_id, regnum, lo);
 230                 bus->write(bus, phy_id, regnum + 1, hi);
 231         } else {
 232                 bus->write(bus, phy_id, regnum + 1, hi);
 233                 bus->write(bus, phy_id, regnum, lo);
 234         }
 235 }
 236
 237 u32
 238 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 239 {
 240         struct mii_bus *bus = priv->mii_bus;
 241         u16 r1, r2, page;
 242         u32 val;
 243
 244         split_addr((u32) reg, &r1, &r2, &page);
 245
 246         mutex_lock(&bus->mdio_lock);
 247
 248         bus->write(bus, 0x18, 0, page);
 249         wait_for_page_switch();
 250         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 251
 252         mutex_unlock(&bus->mdio_lock);
 253
 254         return val;
 255 }
 256
 257 void
 258 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 259 {
 260         struct mii_bus *bus = priv->mii_bus;
 261         u16 r1, r2, page;
 262
 263         split_addr((u32) reg, &r1, &r2, &page);
 264
 265         mutex_lock(&bus->mdio_lock);
 266
 267         bus->write(bus, 0x18, 0, page);
 268         wait_for_page_switch();
 269         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 270
 271         mutex_unlock(&bus->mdio_lock);
 272 }
 273
 274 u32
 275 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 276 {
 277         struct mii_bus *bus = priv->mii_bus;
 278         u16 r1, r2, page;
 279         u32 ret;
 280
 281         split_addr((u32) reg, &r1, &r2, &page);
 282
 283         mutex_lock(&bus->mdio_lock);
 284
 285         bus->write(bus, 0x18, 0, page);
 286         wait_for_page_switch();
 287
 288         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 289         ret &= ~mask;
 290         ret |= val;
 291         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 292
 293         mutex_unlock(&bus->mdio_lock);
 294
 295         return ret;
 296 }
 297 void
 298 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
 299            u16 dbg_addr, u16 *dbg_data)
 300 {
 301        struct mii_bus *bus = priv->mii_bus;
 302
 303        mutex_lock(&bus->mdio_lock);
 304        bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 305        *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
 306        mutex_unlock(&bus->mdio_lock);
 307 }
 308
 309 void
 310 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 311                      u16 dbg_addr, u16 dbg_data)
 312 {
 313         struct mii_bus *bus = priv->mii_bus;
 314
 315         mutex_lock(&bus->mdio_lock);
 316         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 317         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 318         mutex_unlock(&bus->mdio_lock);
 319 }
 320
 321 static inline void
 322 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
 323 {
 324         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 325         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
 326         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
 327 }
 328
 329 void
 330 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
 331 {
 332         struct mii_bus *bus = priv->mii_bus;
 333
 334         mutex_lock(&bus->mdio_lock);
 335         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 336         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 337         mutex_unlock(&bus->mdio_lock);
 338 }
 339
 340 u16
 341 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
 342 {
 343         struct mii_bus *bus = priv->mii_bus;
 344         u16 data;
 345
 346         mutex_lock(&bus->mdio_lock);
 347         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 348         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 349         mutex_unlock(&bus->mdio_lock);
 350
 351         return data;
 352 }
 353
 354 static int
 355 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 356                 unsigned timeout)
 357 {
 358         int i;
 359
 360         for (i = 0; i < timeout; i++) {
 361                 u32 t;
 362
 363                 t = ar8xxx_read(priv, reg);
 364                 if ((t & mask) == val)
 365                         return 0;
 366
 367                 usleep_range(1000, 2000);
 368                 cond_resched();
 369         }
 370
 371         return -ETIMEDOUT;
 372 }
 373
 374 static int
 375 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 376 {
 377         unsigned mib_func = priv->chip->mib_func;
 378         int ret;
 379
 380         lockdep_assert_held(&priv->mib_lock);
 381
 382         /* Capture the hardware statistics for all ports */
 383         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 384
 385         /* Wait for the capturing to complete. */
 386         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 387         if (ret)
 388                 goto out;
 389
 390         ret = 0;
 391
 392 out:
 393         return ret;
 394 }
 395
 396 static int
 397 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 398 {
 399         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 400 }
 401
 402 static int
 403 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 404 {
 405         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 406 }
 407
 408 static void
 409 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 410 {
 411         unsigned int base;
 412         u64 *mib_stats;
 413         int i;
 414
 415         WARN_ON(port >= priv->dev.ports);
 416
 417         lockdep_assert_held(&priv->mib_lock);
 418
 419         base = priv->chip->reg_port_stats_start +
 420                priv->chip->reg_port_stats_length * port;
 421
 422         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 423         for (i = 0; i < priv->chip->num_mibs; i++) {
 424                 const struct ar8xxx_mib_desc *mib;
 425                 u64 t;
 426
 427                 mib = &priv->chip->mib_decs[i];
 428                 t = ar8xxx_read(priv, base + mib->offset);
 429                 if (mib->size == 2) {
 430                         u64 hi;
 431
 432                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 433                         t |= hi << 32;
 434                 }
 435
 436                 if (flush)
 437                         mib_stats[i] = 0;
 438                 else
 439                         mib_stats[i] += t;
 440                 cond_resched();
 441         }
 442 }
 443
 444 static void
 445 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 446                       struct switch_port_link *link)
 447 {
 448         u32 status;
 449         u32 speed;
 450
 451         memset(link, '\0', sizeof(*link));
 452
 453         status = priv->chip->read_port_status(priv, port);
 454
 455         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 456         if (link->aneg) {
 457                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 458         } else {
 459                 link->link = true;
 460
 461                 if (priv->get_port_link) {
 462                         int err;
 463
 464                         err = priv->get_port_link(port);
 465                         if (err >= 0)
 466                                 link->link = !!err;
 467                 }
 468         }
 469
 470         if (!link->link)
 471                 return;
 472
 473         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 474         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 475         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 476
 477         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 478                 link->eee = priv->chip->read_port_eee_status(priv, port);
 479
 480         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 481                  AR8216_PORT_STATUS_SPEED_S;
 482
 483         switch (speed) {
 484         case AR8216_PORT_SPEED_10M:
 485                 link->speed = SWITCH_PORT_SPEED_10;
 486                 break;
 487         case AR8216_PORT_SPEED_100M:
 488                 link->speed = SWITCH_PORT_SPEED_100;
 489                 break;
 490         case AR8216_PORT_SPEED_1000M:
 491                 link->speed = SWITCH_PORT_SPEED_1000;
 492                 break;
 493         default:
 494                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 495                 break;
 496         }
 497 }
 498
 499 static struct sk_buff *
 500 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 501 {
 502         struct ar8xxx_priv *priv = dev->phy_ptr;
 503         unsigned char *buf;
 504
 505         if (unlikely(!priv))
 506                 goto error;
 507
 508         if (!priv->vlan)
 509                 goto send;
 510
 511         if (unlikely(skb_headroom(skb) < 2)) {
 512                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 513                         goto error;
 514         }
 515
 516         buf = skb_push(skb, 2);
 517         buf[0] = 0x10;
 518         buf[1] = 0x80;
 519
 520 send:
 521         return skb;
 522
 523 error:
 524         dev_kfree_skb_any(skb);
 525         return NULL;
 526 }
 527
 528 static void
 529 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 530 {
 531         struct ar8xxx_priv *priv;
 532         unsigned char *buf;
 533         int port, vlan;
 534
 535         priv = dev->phy_ptr;
 536         if (!priv)
 537                 return;
 538
 539         /* don't strip the header if vlan mode is disabled */
 540         if (!priv->vlan)
 541                 return;
 542
 543         /* strip header, get vlan id */
 544         buf = skb->data;
 545         skb_pull(skb, 2);
 546
 547         /* check for vlan header presence */
 548         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 549                 return;
 550
 551         port = buf[0] & 0x7;
 552
 553         /* no need to fix up packets coming from a tagged source */
 554         if (priv->vlan_tagged & (1 << port))
 555                 return;
 556
 557         /* lookup port vid from local table, the switch passes an invalid vlan id */
 558         vlan = priv->vlan_id[priv->pvid[port]];
 559
 560         buf[14 + 2] &= 0xf0;
 561         buf[14 + 2] |= vlan >> 8;
 562         buf[15 + 2] = vlan & 0xff;
 563 }
 564
 565 int
 566 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 567 {
 568         int timeout = 20;
 569         u32 t = 0;
 570
 571         while (1) {
 572                 t = ar8xxx_read(priv, reg);
 573                 if ((t & mask) == val)
 574                         return 0;
 575
 576                 if (timeout-- <= 0)
 577                         break;
 578
 579                 udelay(10);
 580                 cond_resched();
 581         }
 582
 583         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 584                (unsigned int) reg, t, mask, val);
 585         return -ETIMEDOUT;
 586 }
 587
 588 static void
 589 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 590 {
 591         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 592                 return;
 593         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 594                 val &= AR8216_VTUDATA_MEMBER;
 595                 val |= AR8216_VTUDATA_VALID;
 596                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 597         }
 598         op |= AR8216_VTU_ACTIVE;
 599         ar8xxx_write(priv, AR8216_REG_VTU, op);
 600 }
 601
 602 static void
 603 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 604 {
 605         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 606 }
 607
 608 static void
 609 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 610 {
 611         u32 op;
 612
 613         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 614         ar8216_vtu_op(priv, op, port_mask);
 615 }
 616
 617 static int
 618 ar8216_atu_flush(struct ar8xxx_priv *priv)
 619 {
 620         int ret;
 621
 622         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 623         if (!ret)
 624                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 625                                                          AR8216_ATU_ACTIVE);
 626
 627         return ret;
 628 }
 629
 630 static int
 631 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 632 {
 633         u32 t;
 634         int ret;
 635
 636         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 637         if (!ret) {
 638                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 639                 t |= AR8216_ATU_ACTIVE;
 640                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 641         }
 642
 643         return ret;
 644 }
 645
 646 static u32
 647 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 648 {
 649         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 650 }
 651
 652 static void
 653 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 654 {
 655         u32 header;
 656         u32 egress, ingress;
 657         u32 pvid;
 658
 659         if (priv->vlan) {
 660                 pvid = priv->vlan_id[priv->pvid[port]];
 661                 if (priv->vlan_tagged & (1 << port))
 662                         egress = AR8216_OUT_ADD_VLAN;
 663                 else
 664                         egress = AR8216_OUT_STRIP_VLAN;
 665                 ingress = AR8216_IN_SECURE;
 666         } else {
 667                 pvid = port;
 668                 egress = AR8216_OUT_KEEP;
 669                 ingress = AR8216_IN_PORT_ONLY;
 670         }
 671
 672         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 673                 header = AR8216_PORT_CTRL_HEADER;
 674         else
 675                 header = 0;
 676
 677         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 678                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 679                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 680                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 681                    AR8216_PORT_CTRL_LEARN | header |
 682                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 683                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 684
 685         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 686                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 687                    AR8216_PORT_VLAN_DEFAULT_ID,
 688                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 689                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 690                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 691 }
 692
 693 static int
 694 ar8216_hw_init(struct ar8xxx_priv *priv)
 695 {
 696         if (priv->initialized)
 697                 return 0;
 698
 699         ar8xxx_phy_init(priv);
 700
 701         priv->initialized = true;
 702         return 0;
 703 }
 704
 705 static void
 706 ar8216_init_globals(struct ar8xxx_priv *priv)
 707 {
 708         /* standard atheros magic */
 709         ar8xxx_write(priv, 0x38, 0xc000050e);
 710
 711         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 712                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 713 }
 714
 715 static void
 716 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 717 {
 718         /* Enable port learning and tx */
 719         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 720                 AR8216_PORT_CTRL_LEARN |
 721                 (4 << AR8216_PORT_CTRL_STATE_S));
 722
 723         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 724
 725         if (port == AR8216_PORT_CPU) {
 726                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 727                         AR8216_PORT_STATUS_LINK_UP |
 728                         (ar8xxx_has_gige(priv) ?
 729                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 730                         AR8216_PORT_STATUS_TXMAC |
 731                         AR8216_PORT_STATUS_RXMAC |
 732                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 733                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 734                         AR8216_PORT_STATUS_DUPLEX);
 735         } else {
 736                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 737                         AR8216_PORT_STATUS_LINK_AUTO);
 738         }
 739 }
 740
 741 static void
 742 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 743 {
 744         int timeout = 20;
 745
 746         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
 747                 udelay(10);
 748                 cond_resched();
 749         }
 750
 751         if (!timeout)
 752                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 753 }
 754
 755 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 756                                  struct arl_entry *a, u32 *status, enum arl_op op)
 757 {
 758         struct mii_bus *bus = priv->mii_bus;
 759         u16 r2, page;
 760         u16 r1_func0, r1_func1, r1_func2;
 761         u32 t, val0, val1, val2;
 762
 763         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 764         r2 |= 0x10;
 765
 766         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 767         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 768
 769         switch (op) {
 770         case AR8XXX_ARL_INITIALIZE:
 771                 /* all ATU registers are on the same page
 772                 * therefore set page only once
 773                 */
 774                 bus->write(bus, 0x18, 0, page);
 775                 wait_for_page_switch();
 776
 777                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 778
 779                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 780                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 781                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 782                 break;
 783         case AR8XXX_ARL_GET_NEXT:
 784                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 785                 t |= AR8216_ATU_ACTIVE;
 786                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 787                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 788
 789                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 790                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 791                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 792
 793                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 794                 if (!*status)
 795                         break;
 796
 797                 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
 798                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 799                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 800                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 801                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 802                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 803                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 804                 break;
 805         }
 806 }
 807
 808 static void
 809 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 810 {
 811         u32 egress, ingress;
 812         u32 pvid;
 813
 814         if (priv->vlan) {
 815                 pvid = priv->vlan_id[priv->pvid[port]];
 816                 if (priv->vlan_tagged & (1 << port))
 817                         egress = AR8216_OUT_ADD_VLAN;
 818                 else
 819                         egress = AR8216_OUT_STRIP_VLAN;
 820                 ingress = AR8216_IN_SECURE;
 821         } else {
 822                 pvid = port;
 823                 egress = AR8216_OUT_KEEP;
 824                 ingress = AR8216_IN_PORT_ONLY;
 825         }
 826
 827         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 828                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 829                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 830                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 831                    AR8216_PORT_CTRL_LEARN |
 832                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 833                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 834
 835         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 836                    AR8236_PORT_VLAN_DEFAULT_ID,
 837                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 838
 839         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 840                    AR8236_PORT_VLAN2_VLAN_MODE |
 841                    AR8236_PORT_VLAN2_MEMBER,
 842                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 843                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 844 }
 845
 846 static void
 847 ar8236_init_globals(struct ar8xxx_priv *priv)
 848 {
 849         /* enable jumbo frames */
 850         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 851                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 852
 853         /* enable cpu port to receive arp frames */
 854         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 855                    AR8236_ATU_CTRL_RES);
 856
 857         /* enable cpu port to receive multicast and broadcast frames */
 858         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 859                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 860
 861         /* Enable MIB counters */
 862         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 863                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 864                    AR8236_MIB_EN);
 865 }
 866
 867 static int
 868 ar8316_hw_init(struct ar8xxx_priv *priv)
 869 {
 870         u32 val, newval;
 871
 872         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 873
 874         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 875                 if (priv->port4_phy) {
 876                         /* value taken from Ubiquiti RouterStation Pro */
 877                         newval = 0x81461bea;
 878                         pr_info("ar8316: Using port 4 as PHY\n");
 879                 } else {
 880                         newval = 0x01261be2;
 881                         pr_info("ar8316: Using port 4 as switch port\n");
 882                 }
 883         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 884                 /* value taken from AVM Fritz!Box 7390 sources */
 885                 newval = 0x010e5b71;
 886         } else {
 887                 /* no known value for phy interface */
 888                 pr_err("ar8316: unsupported mii mode: %d.\n",
 889                        priv->phy->interface);
 890                 return -EINVAL;
 891         }
 892
 893         if (val == newval)
 894                 goto out;
 895
 896         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 897
 898         if (priv->port4_phy &&
 899             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 900                 /* work around for phy4 rgmii mode */
 901                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 902                 /* rx delay */
 903                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 904                 /* tx delay */
 905                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 906                 msleep(1000);
 907         }
 908
 909         ar8xxx_phy_init(priv);
 910
 911 out:
 912         priv->initialized = true;
 913         return 0;
 914 }
 915
 916 static void
 917 ar8316_init_globals(struct ar8xxx_priv *priv)
 918 {
 919         /* standard atheros magic */
 920         ar8xxx_write(priv, 0x38, 0xc000050e);
 921
 922         /* enable cpu port to receive multicast and broadcast frames */
 923         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 924
 925         /* enable jumbo frames */
 926         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 927                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 928
 929         /* Enable MIB counters */
 930         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 931                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 932                    AR8236_MIB_EN);
 933 }
 934
 935 int
 936 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 937                    struct switch_val *val)
 938 {
 939         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 940         priv->vlan = !!val->value.i;
 941         return 0;
 942 }
 943
 944 int
 945 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 946                    struct switch_val *val)
 947 {
 948         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 949         val->value.i = priv->vlan;
 950         return 0;
 951 }
 952
 953
 954 int
 955 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 956 {
 957         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 958
 959         /* make sure no invalid PVIDs get set */
 960
 961         if (vlan < 0 || vlan >= dev->vlans ||
 962             port < 0 || port >= AR8X16_MAX_PORTS)
 963                 return -EINVAL;
 964
 965         priv->pvid[port] = vlan;
 966         return 0;
 967 }
 968
 969 int
 970 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 971 {
 972         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 973
 974         if (port < 0 || port >= AR8X16_MAX_PORTS)
 975                 return -EINVAL;
 976
 977         *vlan = priv->pvid[port];
 978         return 0;
 979 }
 980
 981 static int
 982 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 983                   struct switch_val *val)
 984 {
 985         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 986
 987         if (val->port_vlan >= AR8X16_MAX_VLANS)
 988                 return -EINVAL;
 989
 990         priv->vlan_id[val->port_vlan] = val->value.i;
 991         return 0;
 992 }
 993
 994 static int
 995 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 996                   struct switch_val *val)
 997 {
 998         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 999         val->value.i = priv->vlan_id[val->port_vlan];
1000         return 0;
1001 }
1002
1003 int
1004 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1005                         struct switch_port_link *link)
1006 {
1007         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1008
1009         ar8216_read_port_link(priv, port, link);
1010         return 0;
1011 }
1012
1013 static int
1014 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1015 {
1016         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1017         u8 ports;
1018         int i;
1019
1020         if (val->port_vlan >= AR8X16_MAX_VLANS)
1021                 return -EINVAL;
1022
1023         ports = priv->vlan_table[val->port_vlan];
1024         val->len = 0;
1025         for (i = 0; i < dev->ports; i++) {
1026                 struct switch_port *p;
1027
1028                 if (!(ports & (1 << i)))
1029                         continue;
1030
1031                 p = &val->value.ports[val->len++];
1032                 p->id = i;
1033                 if (priv->vlan_tagged & (1 << i))
1034                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1035                 else
1036                         p->flags = 0;
1037         }
1038         return 0;
1039 }
1040
1041 static int
1042 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1043 {
1044         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1045         u8 *vt = &priv->vlan_table[val->port_vlan];
1046         int i, j;
1047
1048         *vt = 0;
1049         for (i = 0; i < val->len; i++) {
1050                 struct switch_port *p = &val->value.ports[i];
1051
1052                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1053                         priv->vlan_tagged |= (1 << p->id);
1054                 } else {
1055                         priv->vlan_tagged &= ~(1 << p->id);
1056                         priv->pvid[p->id] = val->port_vlan;
1057
1058                         /* make sure that an untagged port does not
1059                          * appear in other vlans */
1060                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1061                                 if (j == val->port_vlan)
1062                                         continue;
1063                                 priv->vlan_table[j] &= ~(1 << p->id);
1064                         }
1065                 }
1066
1067                 *vt |= 1 << p->id;
1068         }
1069         return 0;
1070 }
1071
1072 static void
1073 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1074 {
1075         int port;
1076
1077         /* reset all mirror registers */
1078         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1079                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1080                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1081         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1082                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1083                            AR8216_PORT_CTRL_MIRROR_RX);
1084
1085                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1086                            AR8216_PORT_CTRL_MIRROR_TX);
1087         }
1088
1089         /* now enable mirroring if necessary */
1090         if (priv->source_port >= AR8216_NUM_PORTS ||
1091             priv->monitor_port >= AR8216_NUM_PORTS ||
1092             priv->source_port == priv->monitor_port) {
1093                 return;
1094         }
1095
1096         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1097                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1098                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1099
1100         if (priv->mirror_rx)
1101                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1102                            AR8216_PORT_CTRL_MIRROR_RX);
1103
1104         if (priv->mirror_tx)
1105                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1106                            AR8216_PORT_CTRL_MIRROR_TX);
1107 }
1108
1109 static inline u32
1110 ar8xxx_age_time_val(int age_time)
1111 {
1112         return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1113                AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1114 }
1115
1116 static inline void
1117 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1118 {
1119         u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1120         ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1121 }
1122
1123 int
1124 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1125 {
1126         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1127         const struct ar8xxx_chip *chip = priv->chip;
1128         u8 portmask[AR8X16_MAX_PORTS];
1129         int i, j;
1130
1131         mutex_lock(&priv->reg_mutex);
1132         /* flush all vlan translation unit entries */
1133         priv->chip->vtu_flush(priv);
1134
1135         memset(portmask, 0, sizeof(portmask));
1136         if (!priv->init) {
1137                 /* calculate the port destination masks and load vlans
1138                  * into the vlan translation unit */
1139                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1140                         u8 vp = priv->vlan_table[j];
1141
1142                         if (!vp)
1143                                 continue;
1144
1145                         for (i = 0; i < dev->ports; i++) {
1146                                 u8 mask = (1 << i);
1147                                 if (vp & mask)
1148                                         portmask[i] |= vp & ~mask;
1149                         }
1150
1151                         chip->vtu_load_vlan(priv, priv->vlan_id[j],
1152                                             priv->vlan_table[j]);
1153                 }
1154         } else {
1155                 /* vlan disabled:
1156                  * isolate all ports, but connect them to the cpu port */
1157                 for (i = 0; i < dev->ports; i++) {
1158                         if (i == AR8216_PORT_CPU)
1159                                 continue;
1160
1161                         portmask[i] = 1 << AR8216_PORT_CPU;
1162                         portmask[AR8216_PORT_CPU] |= (1 << i);
1163                 }
1164         }
1165
1166         /* update the port destination mask registers and tag settings */
1167         for (i = 0; i < dev->ports; i++) {
1168                 chip->setup_port(priv, i, portmask[i]);
1169         }
1170
1171         chip->set_mirror_regs(priv);
1172
1173         /* set age time */
1174         if (chip->reg_arl_ctrl)
1175                 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1176
1177         mutex_unlock(&priv->reg_mutex);
1178         return 0;
1179 }
1180
1181 int
1182 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1183 {
1184         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1185         const struct ar8xxx_chip *chip = priv->chip;
1186         int i;
1187
1188         mutex_lock(&priv->reg_mutex);
1189         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1190                 offsetof(struct ar8xxx_priv, vlan));
1191
1192         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1193                 priv->vlan_id[i] = i;
1194
1195         /* Configure all ports */
1196         for (i = 0; i < dev->ports; i++)
1197                 chip->init_port(priv, i);
1198
1199         priv->mirror_rx = false;
1200         priv->mirror_tx = false;
1201         priv->source_port = 0;
1202         priv->monitor_port = 0;
1203         priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1204
1205         chip->init_globals(priv);
1206         chip->atu_flush(priv);
1207
1208         mutex_unlock(&priv->reg_mutex);
1209
1210         return chip->sw_hw_apply(dev);
1211 }
1212
1213 int
1214 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1215                          const struct switch_attr *attr,
1216                          struct switch_val *val)
1217 {
1218         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1219         unsigned int len;
1220         int ret;
1221
1222         if (!ar8xxx_has_mib_counters(priv))
1223                 return -EOPNOTSUPP;
1224
1225         mutex_lock(&priv->mib_lock);
1226
1227         len = priv->dev.ports * priv->chip->num_mibs *
1228               sizeof(*priv->mib_stats);
1229         memset(priv->mib_stats, '\0', len);
1230         ret = ar8xxx_mib_flush(priv);
1231         if (ret)
1232                 goto unlock;
1233
1234         ret = 0;
1235
1236 unlock:
1237         mutex_unlock(&priv->mib_lock);
1238         return ret;
1239 }
1240
1241 int
1242 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1243                                const struct switch_attr *attr,
1244                                struct switch_val *val)
1245 {
1246         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1247
1248         mutex_lock(&priv->reg_mutex);
1249         priv->mirror_rx = !!val->value.i;
1250         priv->chip->set_mirror_regs(priv);
1251         mutex_unlock(&priv->reg_mutex);
1252
1253         return 0;
1254 }
1255
1256 int
1257 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1258                                const struct switch_attr *attr,
1259                                struct switch_val *val)
1260 {
1261         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1262         val->value.i = priv->mirror_rx;
1263         return 0;
1264 }
1265
1266 int
1267 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1268                                const struct switch_attr *attr,
1269                                struct switch_val *val)
1270 {
1271         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1272
1273         mutex_lock(&priv->reg_mutex);
1274         priv->mirror_tx = !!val->value.i;
1275         priv->chip->set_mirror_regs(priv);
1276         mutex_unlock(&priv->reg_mutex);
1277
1278         return 0;
1279 }
1280
1281 int
1282 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1283                                const struct switch_attr *attr,
1284                                struct switch_val *val)
1285 {
1286         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1287         val->value.i = priv->mirror_tx;
1288         return 0;
1289 }
1290
1291 int
1292 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1293                                   const struct switch_attr *attr,
1294                                   struct switch_val *val)
1295 {
1296         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1297
1298         mutex_lock(&priv->reg_mutex);
1299         priv->monitor_port = val->value.i;
1300         priv->chip->set_mirror_regs(priv);
1301         mutex_unlock(&priv->reg_mutex);
1302
1303         return 0;
1304 }
1305
1306 int
1307 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1308                                   const struct switch_attr *attr,
1309                                   struct switch_val *val)
1310 {
1311         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1312         val->value.i = priv->monitor_port;
1313         return 0;
1314 }
1315
1316 int
1317 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1318                                  const struct switch_attr *attr,
1319                                  struct switch_val *val)
1320 {
1321         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1322
1323         mutex_lock(&priv->reg_mutex);
1324         priv->source_port = val->value.i;
1325         priv->chip->set_mirror_regs(priv);
1326         mutex_unlock(&priv->reg_mutex);
1327
1328         return 0;
1329 }
1330
1331 int
1332 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1333                                  const struct switch_attr *attr,
1334                                  struct switch_val *val)
1335 {
1336         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1337         val->value.i = priv->source_port;
1338         return 0;
1339 }
1340
1341 int
1342 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1343                              const struct switch_attr *attr,
1344                              struct switch_val *val)
1345 {
1346         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1347         int port;
1348         int ret;
1349
1350         if (!ar8xxx_has_mib_counters(priv))
1351                 return -EOPNOTSUPP;
1352
1353         port = val->port_vlan;
1354         if (port >= dev->ports)
1355                 return -EINVAL;
1356
1357         mutex_lock(&priv->mib_lock);
1358         ret = ar8xxx_mib_capture(priv);
1359         if (ret)
1360                 goto unlock;
1361
1362         ar8xxx_mib_fetch_port_stat(priv, port, true);
1363
1364         ret = 0;
1365
1366 unlock:
1367         mutex_unlock(&priv->mib_lock);
1368         return ret;
1369 }
1370
1371 static void
1372 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1373 {
1374         unsigned long b;
1375         const char *unit;
1376
1377         if (byte >= 0x40000000) { /* 1 GiB */
1378                 b = byte * 10 / 0x40000000;
1379                 unit = "GiB";
1380         } else if (byte >= 0x100000) { /* 1 MiB */
1381                 b = byte * 10 / 0x100000;
1382                 unit = "MiB";
1383         } else if (byte >= 0x400) { /* 1 KiB */
1384                 b = byte * 10 / 0x400;
1385                 unit = "KiB";
1386         } else {
1387                 b = byte;
1388                 unit = "Byte";
1389         }
1390         if (strcmp(unit, "Byte"))
1391                 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1392         else
1393                 snprintf(buf, len, "%lu %s", b, unit);
1394 }
1395
1396 int
1397 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1398                        const struct switch_attr *attr,
1399                        struct switch_val *val)
1400 {
1401         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1402         const struct ar8xxx_chip *chip = priv->chip;
1403         u64 *mib_stats, mib_data;
1404         unsigned int port;
1405         int ret;
1406         char *buf = priv->buf;
1407         char buf1[64];
1408         const char *mib_name;
1409         int i, len = 0;
1410         bool mib_stats_empty = true;
1411
1412         if (!ar8xxx_has_mib_counters(priv))
1413                 return -EOPNOTSUPP;
1414
1415         port = val->port_vlan;
1416         if (port >= dev->ports)
1417                 return -EINVAL;
1418
1419         mutex_lock(&priv->mib_lock);
1420         ret = ar8xxx_mib_capture(priv);
1421         if (ret)
1422                 goto unlock;
1423
1424         ar8xxx_mib_fetch_port_stat(priv, port, false);
1425
1426         len += snprintf(buf + len, sizeof(priv->buf) - len,
1427                         "MIB counters\n");
1428
1429         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1430         for (i = 0; i < chip->num_mibs; i++) {
1431                 mib_name = chip->mib_decs[i].name;
1432                 mib_data = mib_stats[i];
1433                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1434                                 "%-12s: %llu\n", mib_name, mib_data);
1435                 if ((!strcmp(mib_name, "TxByte") ||
1436                     !strcmp(mib_name, "RxGoodByte")) &&
1437                     mib_data >= 1024) {
1438                         ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1439                         --len; /* discard newline at the end of buf */
1440                         len += snprintf(buf + len, sizeof(priv->buf) - len,
1441                                         " (%s)\n", buf1);
1442                 }
1443                 if (mib_stats_empty && mib_data)
1444                         mib_stats_empty = false;
1445         }
1446
1447         if (mib_stats_empty)
1448                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1449
1450         val->value.s = buf;
1451         val->len = len;
1452
1453         ret = 0;
1454
1455 unlock:
1456         mutex_unlock(&priv->mib_lock);
1457         return ret;
1458 }
1459
1460 int
1461 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1462                            struct switch_val *val)
1463 {
1464         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1465         int age_time = val->value.i;
1466         u32 age_time_val;
1467
1468         if (age_time < 0)
1469                 return -EINVAL;
1470
1471         age_time_val = ar8xxx_age_time_val(age_time);
1472         if (age_time_val == 0 || age_time_val > 0xffff)
1473                 return -EINVAL;
1474
1475         priv->arl_age_time = age_time;
1476         return 0;
1477 }
1478
1479 int
1480 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1481                    struct switch_val *val)
1482 {
1483         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1484         val->value.i = priv->arl_age_time;
1485         return 0;
1486 }
1487
1488 int
1489 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1490                         const struct switch_attr *attr,
1491                         struct switch_val *val)
1492 {
1493         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1494         struct mii_bus *bus = priv->mii_bus;
1495         const struct ar8xxx_chip *chip = priv->chip;
1496         char *buf = priv->arl_buf;
1497         int i, j, k, len = 0;
1498         struct arl_entry *a, *a1;
1499         u32 status;
1500
1501         if (!chip->get_arl_entry)
1502                 return -EOPNOTSUPP;
1503
1504         mutex_lock(&priv->reg_mutex);
1505         mutex_lock(&bus->mdio_lock);
1506
1507         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1508
1509         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1510                 a = &priv->arl_table[i];
1511                 duplicate:
1512                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1513
1514                 if (!status)
1515                         break;
1516
1517                 /* avoid duplicates
1518                  * ARL table can include multiple valid entries
1519                  * per MAC, just with differing status codes
1520                  */
1521                 for (j = 0; j < i; ++j) {
1522                         a1 = &priv->arl_table[j];
1523                         if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1524                                 /* ignore ports already seen in former entry */
1525                                 a->portmap &= ~a1->portmap;
1526                                 if (!a->portmap)
1527                                         goto duplicate;
1528                         }
1529                 }
1530         }
1531
1532         mutex_unlock(&bus->mdio_lock);
1533
1534         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1535                         "address resolution table\n");
1536
1537         if (i == AR8XXX_NUM_ARL_RECORDS)
1538                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1539                                 "Too many entries found, displaying the first %d only!\n",
1540                                 AR8XXX_NUM_ARL_RECORDS);
1541
1542         for (j = 0; j < priv->dev.ports; ++j) {
1543                 for (k = 0; k < i; ++k) {
1544                         a = &priv->arl_table[k];
1545                         if (!(a->portmap & BIT(j)))
1546                                 continue;
1547                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1548                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1549                                         j,
1550                                         a->mac[5], a->mac[4], a->mac[3],
1551                                         a->mac[2], a->mac[1], a->mac[0]);
1552                 }
1553         }
1554
1555         val->value.s = buf;
1556         val->len = len;
1557
1558         mutex_unlock(&priv->reg_mutex);
1559
1560         return 0;
1561 }
1562
1563 int
1564 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1565                               const struct switch_attr *attr,
1566                               struct switch_val *val)
1567 {
1568         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1569         int ret;
1570
1571         mutex_lock(&priv->reg_mutex);
1572         ret = priv->chip->atu_flush(priv);
1573         mutex_unlock(&priv->reg_mutex);
1574
1575         return ret;
1576 }
1577
1578 int
1579 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1580                                    const struct switch_attr *attr,
1581                                    struct switch_val *val)
1582 {
1583         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1584         int port, ret;
1585
1586         port = val->port_vlan;
1587         if (port >= dev->ports)
1588                 return -EINVAL;
1589
1590         mutex_lock(&priv->reg_mutex);
1591         ret = priv->chip->atu_flush_port(priv, port);
1592         mutex_unlock(&priv->reg_mutex);
1593
1594         return ret;
1595 }
1596
1597 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1598         {
1599                 .type = SWITCH_TYPE_INT,
1600                 .name = "enable_vlan",
1601                 .description = "Enable VLAN mode",
1602                 .set = ar8xxx_sw_set_vlan,
1603                 .get = ar8xxx_sw_get_vlan,
1604                 .max = 1
1605         },
1606         {
1607                 .type = SWITCH_TYPE_NOVAL,
1608                 .name = "reset_mibs",
1609                 .description = "Reset all MIB counters",
1610                 .set = ar8xxx_sw_set_reset_mibs,
1611         },
1612         {
1613                 .type = SWITCH_TYPE_INT,
1614                 .name = "enable_mirror_rx",
1615                 .description = "Enable mirroring of RX packets",
1616                 .set = ar8xxx_sw_set_mirror_rx_enable,
1617                 .get = ar8xxx_sw_get_mirror_rx_enable,
1618                 .max = 1
1619         },
1620         {
1621                 .type = SWITCH_TYPE_INT,
1622                 .name = "enable_mirror_tx",
1623                 .description = "Enable mirroring of TX packets",
1624                 .set = ar8xxx_sw_set_mirror_tx_enable,
1625                 .get = ar8xxx_sw_get_mirror_tx_enable,
1626                 .max = 1
1627         },
1628         {
1629                 .type = SWITCH_TYPE_INT,
1630                 .name = "mirror_monitor_port",
1631                 .description = "Mirror monitor port",
1632                 .set = ar8xxx_sw_set_mirror_monitor_port,
1633                 .get = ar8xxx_sw_get_mirror_monitor_port,
1634                 .max = AR8216_NUM_PORTS - 1
1635         },
1636         {
1637                 .type = SWITCH_TYPE_INT,
1638                 .name = "mirror_source_port",
1639                 .description = "Mirror source port",
1640                 .set = ar8xxx_sw_set_mirror_source_port,
1641                 .get = ar8xxx_sw_get_mirror_source_port,
1642                 .max = AR8216_NUM_PORTS - 1
1643         },
1644         {
1645                 .type = SWITCH_TYPE_STRING,
1646                 .name = "arl_table",
1647                 .description = "Get ARL table",
1648                 .set = NULL,
1649                 .get = ar8xxx_sw_get_arl_table,
1650         },
1651         {
1652                 .type = SWITCH_TYPE_NOVAL,
1653                 .name = "flush_arl_table",
1654                 .description = "Flush ARL table",
1655                 .set = ar8xxx_sw_set_flush_arl_table,
1656         },
1657 };
1658
1659 const struct switch_attr ar8xxx_sw_attr_port[] = {
1660         {
1661                 .type = SWITCH_TYPE_NOVAL,
1662                 .name = "reset_mib",
1663                 .description = "Reset single port MIB counters",
1664                 .set = ar8xxx_sw_set_port_reset_mib,
1665         },
1666         {
1667                 .type = SWITCH_TYPE_STRING,
1668                 .name = "mib",
1669                 .description = "Get port's MIB counters",
1670                 .set = NULL,
1671                 .get = ar8xxx_sw_get_port_mib,
1672         },
1673         {
1674                 .type = SWITCH_TYPE_NOVAL,
1675                 .name = "flush_arl_table",
1676                 .description = "Flush port's ARL table entries",
1677                 .set = ar8xxx_sw_set_flush_port_arl_table,
1678         },
1679 };
1680
1681 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1682         {
1683                 .type = SWITCH_TYPE_INT,
1684                 .name = "vid",
1685                 .description = "VLAN ID (0-4094)",
1686                 .set = ar8xxx_sw_set_vid,
1687                 .get = ar8xxx_sw_get_vid,
1688                 .max = 4094,
1689         },
1690 };
1691
1692 static const struct switch_dev_ops ar8xxx_sw_ops = {
1693         .attr_global = {
1694                 .attr = ar8xxx_sw_attr_globals,
1695                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1696         },
1697         .attr_port = {
1698                 .attr = ar8xxx_sw_attr_port,
1699                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1700         },
1701         .attr_vlan = {
1702                 .attr = ar8xxx_sw_attr_vlan,
1703                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1704         },
1705         .get_port_pvid = ar8xxx_sw_get_pvid,
1706         .set_port_pvid = ar8xxx_sw_set_pvid,
1707         .get_vlan_ports = ar8xxx_sw_get_ports,
1708         .set_vlan_ports = ar8xxx_sw_set_ports,
1709         .apply_config = ar8xxx_sw_hw_apply,
1710         .reset_switch = ar8xxx_sw_reset_switch,
1711         .get_port_link = ar8xxx_sw_get_port_link,
1712 /* The following op is disabled as it hogs the CPU and degrades performance.
1713    An implementation has been attempted in 4d8a66d but reading MIB data is slow
1714    on ar8xxx switches.
1715
1716    The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1717    ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1718    the request to update the MIB counter is cleared. */
1719 #if 0
1720         .get_port_stats = ar8xxx_sw_get_port_stats,
1721 #endif
1722 };
1723
1724 static const struct ar8xxx_chip ar8216_chip = {
1725         .caps = AR8XXX_CAP_MIB_COUNTERS,
1726
1727         .reg_port_stats_start = 0x19000,
1728         .reg_port_stats_length = 0xa0,
1729         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1730
1731         .name = "Atheros AR8216",
1732         .ports = AR8216_NUM_PORTS,
1733         .vlans = AR8216_NUM_VLANS,
1734         .swops = &ar8xxx_sw_ops,
1735
1736         .hw_init = ar8216_hw_init,
1737         .init_globals = ar8216_init_globals,
1738         .init_port = ar8216_init_port,
1739         .setup_port = ar8216_setup_port,
1740         .read_port_status = ar8216_read_port_status,
1741         .atu_flush = ar8216_atu_flush,
1742         .atu_flush_port = ar8216_atu_flush_port,
1743         .vtu_flush = ar8216_vtu_flush,
1744         .vtu_load_vlan = ar8216_vtu_load_vlan,
1745         .set_mirror_regs = ar8216_set_mirror_regs,
1746         .get_arl_entry = ar8216_get_arl_entry,
1747         .sw_hw_apply = ar8xxx_sw_hw_apply,
1748
1749         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1750         .mib_decs = ar8216_mibs,
1751         .mib_func = AR8216_REG_MIB_FUNC
1752 };
1753
1754 static const struct ar8xxx_chip ar8236_chip = {
1755         .caps = AR8XXX_CAP_MIB_COUNTERS,
1756
1757         .reg_port_stats_start = 0x20000,
1758         .reg_port_stats_length = 0x100,
1759         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1760
1761         .name = "Atheros AR8236",
1762         .ports = AR8216_NUM_PORTS,
1763         .vlans = AR8216_NUM_VLANS,
1764         .swops = &ar8xxx_sw_ops,
1765
1766         .hw_init = ar8216_hw_init,
1767         .init_globals = ar8236_init_globals,
1768         .init_port = ar8216_init_port,
1769         .setup_port = ar8236_setup_port,
1770         .read_port_status = ar8216_read_port_status,
1771         .atu_flush = ar8216_atu_flush,
1772         .atu_flush_port = ar8216_atu_flush_port,
1773         .vtu_flush = ar8216_vtu_flush,
1774         .vtu_load_vlan = ar8216_vtu_load_vlan,
1775         .set_mirror_regs = ar8216_set_mirror_regs,
1776         .get_arl_entry = ar8216_get_arl_entry,
1777         .sw_hw_apply = ar8xxx_sw_hw_apply,
1778
1779         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1780         .mib_decs = ar8236_mibs,
1781         .mib_func = AR8216_REG_MIB_FUNC
1782 };
1783
1784 static const struct ar8xxx_chip ar8316_chip = {
1785         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1786
1787         .reg_port_stats_start = 0x20000,
1788         .reg_port_stats_length = 0x100,
1789         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1790
1791         .name = "Atheros AR8316",
1792         .ports = AR8216_NUM_PORTS,
1793         .vlans = AR8X16_MAX_VLANS,
1794         .swops = &ar8xxx_sw_ops,
1795
1796         .hw_init = ar8316_hw_init,
1797         .init_globals = ar8316_init_globals,
1798         .init_port = ar8216_init_port,
1799         .setup_port = ar8216_setup_port,
1800         .read_port_status = ar8216_read_port_status,
1801         .atu_flush = ar8216_atu_flush,
1802         .atu_flush_port = ar8216_atu_flush_port,
1803         .vtu_flush = ar8216_vtu_flush,
1804         .vtu_load_vlan = ar8216_vtu_load_vlan,
1805         .set_mirror_regs = ar8216_set_mirror_regs,
1806         .get_arl_entry = ar8216_get_arl_entry,
1807         .sw_hw_apply = ar8xxx_sw_hw_apply,
1808
1809         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1810         .mib_decs = ar8236_mibs,
1811         .mib_func = AR8216_REG_MIB_FUNC
1812 };
1813
1814 static int
1815 ar8xxx_read_id(struct ar8xxx_priv *priv)
1816 {
1817         u32 val;
1818         u16 id;
1819         int i;
1820
1821         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1822         if (val == ~0)
1823                 return -ENODEV;
1824
1825         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1826         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1827                 u16 t;
1828
1829                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1830                 if (val == ~0)
1831                         return -ENODEV;
1832
1833                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1834                 if (t != id)
1835                         return -ENODEV;
1836         }
1837
1838         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1839         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1840         return 0;
1841 }
1842
1843 static int
1844 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1845 {
1846         int ret;
1847
1848         ret = ar8xxx_read_id(priv);
1849         if(ret)
1850                 return ret;
1851
1852         switch (priv->chip_ver) {
1853         case AR8XXX_VER_AR8216:
1854                 priv->chip = &ar8216_chip;
1855                 break;
1856         case AR8XXX_VER_AR8236:
1857                 priv->chip = &ar8236_chip;
1858                 break;
1859         case AR8XXX_VER_AR8316:
1860                 priv->chip = &ar8316_chip;
1861                 break;
1862         case AR8XXX_VER_AR8327:
1863                 priv->chip = &ar8327_chip;
1864                 break;
1865         case AR8XXX_VER_AR8337:
1866                 priv->chip = &ar8337_chip;
1867                 break;
1868         default:
1869                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1870                        priv->chip_ver, priv->chip_rev);
1871
1872                 return -ENODEV;
1873         }
1874
1875         return 0;
1876 }
1877
1878 static void
1879 ar8xxx_mib_work_func(struct work_struct *work)
1880 {
1881         struct ar8xxx_priv *priv;
1882         int err;
1883
1884         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1885
1886         mutex_lock(&priv->mib_lock);
1887
1888         err = ar8xxx_mib_capture(priv);
1889         if (err)
1890                 goto next_port;
1891
1892         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1893
1894 next_port:
1895         priv->mib_next_port++;
1896         if (priv->mib_next_port >= priv->dev.ports)
1897                 priv->mib_next_port = 0;
1898
1899         mutex_unlock(&priv->mib_lock);
1900         schedule_delayed_work(&priv->mib_work,
1901                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1902 }
1903
1904 static int
1905 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1906 {
1907         unsigned int len;
1908
1909         if (!ar8xxx_has_mib_counters(priv))
1910                 return 0;
1911
1912         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1913
1914         len = priv->dev.ports * priv->chip->num_mibs *
1915               sizeof(*priv->mib_stats);
1916         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1917
1918         if (!priv->mib_stats)
1919                 return -ENOMEM;
1920
1921         return 0;
1922 }
1923
1924 static void
1925 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1926 {
1927         if (!ar8xxx_has_mib_counters(priv))
1928                 return;
1929
1930         schedule_delayed_work(&priv->mib_work,
1931                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1932 }
1933
1934 static void
1935 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1936 {
1937         if (!ar8xxx_has_mib_counters(priv))
1938                 return;
1939
1940         cancel_delayed_work_sync(&priv->mib_work);
1941 }
1942
1943 static struct ar8xxx_priv *
1944 ar8xxx_create(void)
1945 {
1946         struct ar8xxx_priv *priv;
1947
1948         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1949         if (priv == NULL)
1950                 return NULL;
1951
1952         mutex_init(&priv->reg_mutex);
1953         mutex_init(&priv->mib_lock);
1954         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1955
1956         return priv;
1957 }
1958
1959 static void
1960 ar8xxx_free(struct ar8xxx_priv *priv)
1961 {
1962         if (priv->chip && priv->chip->cleanup)
1963                 priv->chip->cleanup(priv);
1964
1965         kfree(priv->chip_data);
1966         kfree(priv->mib_stats);
1967         kfree(priv);
1968 }
1969
1970 static int
1971 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1972 {
1973         const struct ar8xxx_chip *chip;
1974         struct switch_dev *swdev;
1975         int ret;
1976
1977         ret = ar8xxx_id_chip(priv);
1978         if (ret)
1979                 return ret;
1980
1981         chip = priv->chip;
1982
1983         swdev = &priv->dev;
1984         swdev->cpu_port = AR8216_PORT_CPU;
1985         swdev->name = chip->name;
1986         swdev->vlans = chip->vlans;
1987         swdev->ports = chip->ports;
1988         swdev->ops = chip->swops;
1989
1990         ret = ar8xxx_mib_init(priv);
1991         if (ret)
1992                 return ret;
1993
1994         return 0;
1995 }
1996
1997 static int
1998 ar8xxx_start(struct ar8xxx_priv *priv)
1999 {
2000         int ret;
2001
2002         priv->init = true;
2003
2004         ret = priv->chip->hw_init(priv);
2005         if (ret)
2006                 return ret;
2007
2008         ret = ar8xxx_sw_reset_switch(&priv->dev);
2009         if (ret)
2010                 return ret;
2011
2012         priv->init = false;
2013
2014         ar8xxx_mib_start(priv);
2015
2016         return 0;
2017 }
2018
2019 static int
2020 ar8xxx_phy_config_init(struct phy_device *phydev)
2021 {
2022         struct ar8xxx_priv *priv = phydev->priv;
2023         struct net_device *dev = phydev->attached_dev;
2024         int ret;
2025
2026         if (WARN_ON(!priv))
2027                 return -ENODEV;
2028
2029         if (priv->chip->config_at_probe)
2030                 return ar8xxx_phy_check_aneg(phydev);
2031
2032         priv->phy = phydev;
2033
2034         if (phydev->mdio.addr != 0) {
2035                 if (chip_is_ar8316(priv)) {
2036                         /* switch device has been initialized, reinit */
2037                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2038                         priv->initialized = false;
2039                         priv->port4_phy = true;
2040                         ar8316_hw_init(priv);
2041                         return 0;
2042                 }
2043
2044                 return 0;
2045         }
2046
2047         ret = ar8xxx_start(priv);
2048         if (ret)
2049                 return ret;
2050
2051         /* VID fixup only needed on ar8216 */
2052         if (chip_is_ar8216(priv)) {
2053                 dev->phy_ptr = priv;
2054                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2055                 dev->eth_mangle_rx = ar8216_mangle_rx;
2056                 dev->eth_mangle_tx = ar8216_mangle_tx;
2057         }
2058
2059         return 0;
2060 }
2061
2062 static bool
2063 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2064 {
2065         bool link_new, changed = false;
2066         u32 status;
2067         int i;
2068
2069         mutex_lock(&priv->reg_mutex);
2070
2071         for (i = 0; i < priv->dev.ports; i++) {
2072                 status = priv->chip->read_port_status(priv, i);
2073                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2074                 if (link_new == priv->link_up[i])
2075                         continue;
2076
2077                 priv->link_up[i] = link_new;
2078                 changed = true;
2079                 /* flush ARL entries for this port if it went down*/
2080                 if (!link_new)
2081                         priv->chip->atu_flush_port(priv, i);
2082                 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2083                          i, link_new ? "up" : "down");
2084         }
2085
2086         mutex_unlock(&priv->reg_mutex);
2087
2088         return changed;
2089 }
2090
2091 static int
2092 ar8xxx_phy_read_status(struct phy_device *phydev)
2093 {
2094         struct ar8xxx_priv *priv = phydev->priv;
2095         struct switch_port_link link;
2096
2097         /* check for switch port link changes */
2098         if (phydev->state == PHY_CHANGELINK)
2099                 ar8xxx_check_link_states(priv);
2100
2101         if (phydev->mdio.addr != 0)
2102                 return genphy_read_status(phydev);
2103
2104         ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2105         phydev->link = !!link.link;
2106         if (!phydev->link)
2107                 return 0;
2108
2109         switch (link.speed) {
2110         case SWITCH_PORT_SPEED_10:
2111                 phydev->speed = SPEED_10;
2112                 break;
2113         case SWITCH_PORT_SPEED_100:
2114                 phydev->speed = SPEED_100;
2115                 break;
2116         case SWITCH_PORT_SPEED_1000:
2117                 phydev->speed = SPEED_1000;
2118                 break;
2119         default:
2120                 phydev->speed = 0;
2121         }
2122         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2123
2124         phydev->state = PHY_RUNNING;
2125         netif_carrier_on(phydev->attached_dev);
2126         if (phydev->adjust_link)
2127                 phydev->adjust_link(phydev->attached_dev);
2128
2129         return 0;
2130 }
2131
2132 static int
2133 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2134 {
2135         if (phydev->mdio.addr == 0)
2136                 return 0;
2137
2138         return genphy_config_aneg(phydev);
2139 }
2140
2141 static const u32 ar8xxx_phy_ids[] = {
2142         0x004dd033,
2143         0x004dd034, /* AR8327 */
2144         0x004dd036, /* AR8337 */
2145         0x004dd041,
2146         0x004dd042,
2147         0x004dd043, /* AR8236 */
2148 };
2149
2150 static bool
2151 ar8xxx_phy_match(u32 phy_id)
2152 {
2153         int i;
2154
2155         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2156                 if (phy_id == ar8xxx_phy_ids[i])
2157                         return true;
2158
2159         return false;
2160 }
2161
2162 static bool
2163 ar8xxx_is_possible(struct mii_bus *bus)
2164 {
2165         unsigned int i, found_phys = 0;
2166
2167         for (i = 0; i < 5; i++) {
2168                 u32 phy_id;
2169
2170                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2171                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2172                 if (ar8xxx_phy_match(phy_id)) {
2173                         found_phys++;
2174                 } else if (phy_id) {
2175                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2176                                  dev_name(&bus->dev), i, phy_id);
2177                 }
2178         }
2179         return !!found_phys;
2180 }
2181
2182 static int
2183 ar8xxx_phy_probe(struct phy_device *phydev)
2184 {
2185         struct ar8xxx_priv *priv;
2186         struct switch_dev *swdev;
2187         int ret;
2188
2189         /* skip PHYs at unused adresses */
2190         if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2191                 return -ENODEV;
2192
2193         if (!ar8xxx_is_possible(phydev->mdio.bus))
2194                 return -ENODEV;
2195
2196         mutex_lock(&ar8xxx_dev_list_lock);
2197         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2198                 if (priv->mii_bus == phydev->mdio.bus)
2199                         goto found;
2200
2201         priv = ar8xxx_create();
2202         if (priv == NULL) {
2203                 ret = -ENOMEM;
2204                 goto unlock;
2205         }
2206
2207         priv->mii_bus = phydev->mdio.bus;
2208
2209         ret = ar8xxx_probe_switch(priv);
2210         if (ret)
2211                 goto free_priv;
2212
2213         swdev = &priv->dev;
2214         swdev->alias = dev_name(&priv->mii_bus->dev);
2215         ret = register_switch(swdev, NULL);
2216         if (ret)
2217                 goto free_priv;
2218
2219         pr_info("%s: %s rev. %u switch registered on %s\n",
2220                 swdev->devname, swdev->name, priv->chip_rev,
2221                 dev_name(&priv->mii_bus->dev));
2222
2223         list_add(&priv->list, &ar8xxx_dev_list);
2224
2225 found:
2226         priv->use_count++;
2227
2228         if (phydev->mdio.addr == 0) {
2229                 if (ar8xxx_has_gige(priv)) {
2230                         phydev->supported = SUPPORTED_1000baseT_Full;
2231                         phydev->advertising = ADVERTISED_1000baseT_Full;
2232                 } else {
2233                         phydev->supported = SUPPORTED_100baseT_Full;
2234                         phydev->advertising = ADVERTISED_100baseT_Full;
2235                 }
2236
2237                 if (priv->chip->config_at_probe) {
2238                         priv->phy = phydev;
2239
2240                         ret = ar8xxx_start(priv);
2241                         if (ret)
2242                                 goto err_unregister_switch;
2243                 }
2244         } else {
2245                 if (ar8xxx_has_gige(priv)) {
2246                         phydev->supported |= SUPPORTED_1000baseT_Full;
2247                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2248                 }
2249                 if (priv->chip->phy_rgmii_set)
2250                         priv->chip->phy_rgmii_set(priv, phydev);
2251         }
2252
2253         phydev->priv = priv;
2254
2255         mutex_unlock(&ar8xxx_dev_list_lock);
2256
2257         return 0;
2258
2259 err_unregister_switch:
2260         if (--priv->use_count)
2261                 goto unlock;
2262
2263         unregister_switch(&priv->dev);
2264
2265 free_priv:
2266         ar8xxx_free(priv);
2267 unlock:
2268         mutex_unlock(&ar8xxx_dev_list_lock);
2269         return ret;
2270 }
2271
2272 static void
2273 ar8xxx_phy_detach(struct phy_device *phydev)
2274 {
2275         struct net_device *dev = phydev->attached_dev;
2276
2277         if (!dev)
2278                 return;
2279
2280         dev->phy_ptr = NULL;
2281         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2282         dev->eth_mangle_rx = NULL;
2283         dev->eth_mangle_tx = NULL;
2284 }
2285
2286 static void
2287 ar8xxx_phy_remove(struct phy_device *phydev)
2288 {
2289         struct ar8xxx_priv *priv = phydev->priv;
2290
2291         if (WARN_ON(!priv))
2292                 return;
2293
2294         phydev->priv = NULL;
2295
2296         mutex_lock(&ar8xxx_dev_list_lock);
2297
2298         if (--priv->use_count > 0) {
2299                 mutex_unlock(&ar8xxx_dev_list_lock);
2300                 return;
2301         }
2302
2303         list_del(&priv->list);
2304         mutex_unlock(&ar8xxx_dev_list_lock);
2305
2306         unregister_switch(&priv->dev);
2307         ar8xxx_mib_stop(priv);
2308         ar8xxx_free(priv);
2309 }
2310
2311 static int
2312 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2313 {
2314         /* we don't need an extra reset */
2315         return 0;
2316 }
2317
2318 static struct phy_driver ar8xxx_phy_driver[] = {
2319         {
2320                 .phy_id         = 0x004d0000,
2321                 .name           = "Atheros AR8216/AR8236/AR8316",
2322                 .phy_id_mask    = 0xffff0000,
2323                 .features       = PHY_BASIC_FEATURES,
2324                 .probe          = ar8xxx_phy_probe,
2325                 .remove         = ar8xxx_phy_remove,
2326                 .detach         = ar8xxx_phy_detach,
2327                 .config_init    = ar8xxx_phy_config_init,
2328                 .config_aneg    = ar8xxx_phy_config_aneg,
2329                 .read_status    = ar8xxx_phy_read_status,
2330                 .soft_reset     = ar8xxx_phy_soft_reset,
2331         }
2332 };
2333
2334 module_phy_driver(ar8xxx_phy_driver);
2335 MODULE_LICENSE("GPL");