2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54 #define AR8XXX_NUM_PHYS 5
57 AR8XXX_VER_AR8216 = 0x01,
58 AR8XXX_VER_AR8236 = 0x03,
59 AR8XXX_VER_AR8316 = 0x10,
60 AR8XXX_VER_AR8327 = 0x12,
61 AR8XXX_VER_AR8337 = 0x13,
64 struct ar8xxx_mib_desc {
73 int (*hw_init)(struct ar8xxx_priv *priv);
74 void (*cleanup)(struct ar8xxx_priv *priv);
76 void (*init_globals)(struct ar8xxx_priv *priv);
77 void (*init_port)(struct ar8xxx_priv *priv, int port);
78 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
79 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
80 int (*atu_flush)(struct ar8xxx_priv *priv);
81 void (*vtu_flush)(struct ar8xxx_priv *priv);
82 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
83 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
85 const struct ar8xxx_mib_desc *mib_decs;
89 enum ar8327_led_pattern {
90 AR8327_LED_PATTERN_OFF = 0,
91 AR8327_LED_PATTERN_BLINK,
92 AR8327_LED_PATTERN_ON,
93 AR8327_LED_PATTERN_RULE,
96 struct ar8327_led_entry {
102 struct led_classdev cdev;
103 struct ar8xxx_priv *sw_priv;
108 enum ar8327_led_mode mode;
112 struct work_struct led_work;
114 enum ar8327_led_pattern pattern;
121 struct ar8327_led **leds;
122 unsigned int num_leds;
126 struct switch_dev dev;
127 struct mii_bus *mii_bus;
128 struct phy_device *phy;
130 u32 (*read)(struct ar8xxx_priv *priv, int reg);
131 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
132 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
134 int (*get_port_link)(unsigned port);
136 const struct net_device_ops *ndo_old;
137 struct net_device_ops ndo;
138 struct mutex reg_mutex;
141 const struct ar8xxx_chip *chip;
143 struct ar8327_data ar8327;
152 struct mutex mib_lock;
153 struct delayed_work mib_work;
157 struct list_head list;
158 unsigned int use_count;
160 /* all fields below are cleared on reset */
162 u16 vlan_id[AR8X16_MAX_VLANS];
163 u8 vlan_table[AR8X16_MAX_VLANS];
165 u16 pvid[AR8X16_MAX_PORTS];
174 #define MIB_DESC(_s , _o, _n) \
181 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
182 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
183 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
184 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
185 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
186 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
187 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
188 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
189 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
190 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
191 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
192 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
193 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
194 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
195 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
196 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
197 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
198 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
199 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
200 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
201 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
202 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
203 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
204 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
205 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
206 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
207 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
208 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
209 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
210 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
211 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
212 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
213 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
214 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
215 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
216 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
217 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
218 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
221 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
222 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
223 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
224 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
225 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
226 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
227 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
228 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
229 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
230 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
231 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
232 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
235 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
236 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
237 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
238 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
239 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
240 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
241 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
242 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
243 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
244 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
245 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
246 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
247 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
248 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
251 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
252 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
253 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
254 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
255 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
256 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
257 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
258 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
259 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
260 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
263 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
264 static LIST_HEAD(ar8xxx_dev_list);
266 static inline struct ar8xxx_priv *
267 swdev_to_ar8xxx(struct switch_dev *swdev)
269 return container_of(swdev, struct ar8xxx_priv, dev);
272 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
274 return priv->chip->caps & AR8XXX_CAP_GIGE;
277 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
279 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
282 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
284 return priv->chip_ver == AR8XXX_VER_AR8216;
287 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
289 return priv->chip_ver == AR8XXX_VER_AR8236;
292 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
294 return priv->chip_ver == AR8XXX_VER_AR8316;
297 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
299 return priv->chip_ver == AR8XXX_VER_AR8327;
302 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
304 return priv->chip_ver == AR8XXX_VER_AR8337;
308 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
311 *r1 = regaddr & 0x1e;
317 *page = regaddr & 0x1ff;
320 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
322 ar8xxx_phy_poll_reset(struct mii_bus *bus)
324 unsigned int sleep_msecs = 20;
327 for (elapsed = sleep_msecs; elapsed <= 600;
328 elapsed += sleep_msecs) {
330 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
331 ret = mdiobus_read(bus, i, MII_BMCR);
334 if (ret & BMCR_RESET)
336 if (i == AR8XXX_NUM_PHYS - 1) {
337 usleep_range(1000, 2000);
346 ar8xxx_phy_init(struct ar8xxx_priv *priv)
352 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
353 if (priv->chip->phy_fixup)
354 priv->chip->phy_fixup(priv, i);
356 /* initialize the port itself */
357 mdiobus_write(bus, i, MII_ADVERTISE,
358 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
359 if (ar8xxx_has_gige(priv))
360 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
361 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
364 ar8xxx_phy_poll_reset(bus);
368 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
370 struct mii_bus *bus = priv->mii_bus;
374 split_addr((u32) reg, &r1, &r2, &page);
376 mutex_lock(&bus->mdio_lock);
378 bus->write(bus, 0x18, 0, page);
379 usleep_range(1000, 2000); /* wait for the page switch to propagate */
380 lo = bus->read(bus, 0x10 | r2, r1);
381 hi = bus->read(bus, 0x10 | r2, r1 + 1);
383 mutex_unlock(&bus->mdio_lock);
385 return (hi << 16) | lo;
389 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
391 struct mii_bus *bus = priv->mii_bus;
395 split_addr((u32) reg, &r1, &r2, &r3);
397 hi = (u16) (val >> 16);
399 mutex_lock(&bus->mdio_lock);
401 bus->write(bus, 0x18, 0, r3);
402 usleep_range(1000, 2000); /* wait for the page switch to propagate */
403 if (priv->mii_lo_first) {
404 bus->write(bus, 0x10 | r2, r1, lo);
405 bus->write(bus, 0x10 | r2, r1 + 1, hi);
407 bus->write(bus, 0x10 | r2, r1 + 1, hi);
408 bus->write(bus, 0x10 | r2, r1, lo);
411 mutex_unlock(&bus->mdio_lock);
415 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
417 struct mii_bus *bus = priv->mii_bus;
422 split_addr((u32) reg, &r1, &r2, &page);
424 mutex_lock(&bus->mdio_lock);
426 bus->write(bus, 0x18, 0, page);
427 usleep_range(1000, 2000); /* wait for the page switch to propagate */
429 lo = bus->read(bus, 0x10 | r2, r1);
430 hi = bus->read(bus, 0x10 | r2, r1 + 1);
437 hi = (u16) (ret >> 16);
439 if (priv->mii_lo_first) {
440 bus->write(bus, 0x10 | r2, r1, lo);
441 bus->write(bus, 0x10 | r2, r1 + 1, hi);
443 bus->write(bus, 0x10 | r2, r1 + 1, hi);
444 bus->write(bus, 0x10 | r2, r1, lo);
447 mutex_unlock(&bus->mdio_lock);
454 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
455 u16 dbg_addr, u16 dbg_data)
457 struct mii_bus *bus = priv->mii_bus;
459 mutex_lock(&bus->mdio_lock);
460 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
461 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
462 mutex_unlock(&bus->mdio_lock);
466 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
468 struct mii_bus *bus = priv->mii_bus;
470 mutex_lock(&bus->mdio_lock);
471 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
472 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
473 mutex_unlock(&bus->mdio_lock);
477 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
479 return priv->rmw(priv, reg, mask, val);
483 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
485 priv->rmw(priv, reg, 0, val);
489 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
494 for (i = 0; i < timeout; i++) {
497 t = priv->read(priv, reg);
498 if ((t & mask) == val)
501 usleep_range(1000, 2000);
508 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
513 lockdep_assert_held(&priv->mib_lock);
515 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
516 mib_func = AR8327_REG_MIB_FUNC;
518 mib_func = AR8216_REG_MIB_FUNC;
520 /* Capture the hardware statistics for all ports */
521 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
523 /* Wait for the capturing to complete. */
524 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
535 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
537 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
541 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
543 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
547 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
553 WARN_ON(port >= priv->dev.ports);
555 lockdep_assert_held(&priv->mib_lock);
557 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
558 base = AR8327_REG_PORT_STATS_BASE(port);
559 else if (chip_is_ar8236(priv) ||
560 chip_is_ar8316(priv))
561 base = AR8236_REG_PORT_STATS_BASE(port);
563 base = AR8216_REG_PORT_STATS_BASE(port);
565 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
566 for (i = 0; i < priv->chip->num_mibs; i++) {
567 const struct ar8xxx_mib_desc *mib;
570 mib = &priv->chip->mib_decs[i];
571 t = priv->read(priv, base + mib->offset);
572 if (mib->size == 2) {
575 hi = priv->read(priv, base + mib->offset + 4);
587 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
588 struct switch_port_link *link)
593 memset(link, '\0', sizeof(*link));
595 status = priv->chip->read_port_status(priv, port);
597 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
599 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
603 if (priv->get_port_link) {
606 err = priv->get_port_link(port);
615 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
616 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
617 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
619 speed = (status & AR8216_PORT_STATUS_SPEED) >>
620 AR8216_PORT_STATUS_SPEED_S;
623 case AR8216_PORT_SPEED_10M:
624 link->speed = SWITCH_PORT_SPEED_10;
626 case AR8216_PORT_SPEED_100M:
627 link->speed = SWITCH_PORT_SPEED_100;
629 case AR8216_PORT_SPEED_1000M:
630 link->speed = SWITCH_PORT_SPEED_1000;
633 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
638 static struct sk_buff *
639 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
641 struct ar8xxx_priv *priv = dev->phy_ptr;
650 if (unlikely(skb_headroom(skb) < 2)) {
651 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
655 buf = skb_push(skb, 2);
663 dev_kfree_skb_any(skb);
668 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
670 struct ar8xxx_priv *priv;
678 /* don't strip the header if vlan mode is disabled */
682 /* strip header, get vlan id */
686 /* check for vlan header presence */
687 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
692 /* no need to fix up packets coming from a tagged source */
693 if (priv->vlan_tagged & (1 << port))
696 /* lookup port vid from local table, the switch passes an invalid vlan id */
697 vlan = priv->vlan_id[priv->pvid[port]];
700 buf[14 + 2] |= vlan >> 8;
701 buf[15 + 2] = vlan & 0xff;
705 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
711 t = priv->read(priv, reg);
712 if ((t & mask) == val)
721 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
722 (unsigned int) reg, t, mask, val);
727 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
729 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
731 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
732 val &= AR8216_VTUDATA_MEMBER;
733 val |= AR8216_VTUDATA_VALID;
734 priv->write(priv, AR8216_REG_VTU_DATA, val);
736 op |= AR8216_VTU_ACTIVE;
737 priv->write(priv, AR8216_REG_VTU, op);
741 ar8216_vtu_flush(struct ar8xxx_priv *priv)
743 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
747 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
751 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
752 ar8216_vtu_op(priv, op, port_mask);
756 ar8216_atu_flush(struct ar8xxx_priv *priv)
760 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
762 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
768 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
770 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
774 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
781 pvid = priv->vlan_id[priv->pvid[port]];
782 if (priv->vlan_tagged & (1 << port))
783 egress = AR8216_OUT_ADD_VLAN;
785 egress = AR8216_OUT_STRIP_VLAN;
786 ingress = AR8216_IN_SECURE;
789 egress = AR8216_OUT_KEEP;
790 ingress = AR8216_IN_PORT_ONLY;
793 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
794 header = AR8216_PORT_CTRL_HEADER;
798 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
799 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
800 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
801 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
802 AR8216_PORT_CTRL_LEARN | header |
803 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
804 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
806 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
807 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
808 AR8216_PORT_VLAN_DEFAULT_ID,
809 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
810 (ingress << AR8216_PORT_VLAN_MODE_S) |
811 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
815 ar8216_hw_init(struct ar8xxx_priv *priv)
821 ar8216_init_globals(struct ar8xxx_priv *priv)
823 /* standard atheros magic */
824 priv->write(priv, 0x38, 0xc000050e);
826 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
827 AR8216_GCTRL_MTU, 1518 + 8 + 2);
831 ar8216_init_port(struct ar8xxx_priv *priv, int port)
833 /* Enable port learning and tx */
834 priv->write(priv, AR8216_REG_PORT_CTRL(port),
835 AR8216_PORT_CTRL_LEARN |
836 (4 << AR8216_PORT_CTRL_STATE_S));
838 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
840 if (port == AR8216_PORT_CPU) {
841 priv->write(priv, AR8216_REG_PORT_STATUS(port),
842 AR8216_PORT_STATUS_LINK_UP |
843 (ar8xxx_has_gige(priv) ?
844 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
845 AR8216_PORT_STATUS_TXMAC |
846 AR8216_PORT_STATUS_RXMAC |
847 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
848 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
849 AR8216_PORT_STATUS_DUPLEX);
851 priv->write(priv, AR8216_REG_PORT_STATUS(port),
852 AR8216_PORT_STATUS_LINK_AUTO);
856 static const struct ar8xxx_chip ar8216_chip = {
857 .caps = AR8XXX_CAP_MIB_COUNTERS,
859 .hw_init = ar8216_hw_init,
860 .init_globals = ar8216_init_globals,
861 .init_port = ar8216_init_port,
862 .setup_port = ar8216_setup_port,
863 .read_port_status = ar8216_read_port_status,
864 .atu_flush = ar8216_atu_flush,
865 .vtu_flush = ar8216_vtu_flush,
866 .vtu_load_vlan = ar8216_vtu_load_vlan,
868 .num_mibs = ARRAY_SIZE(ar8216_mibs),
869 .mib_decs = ar8216_mibs,
873 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
879 pvid = priv->vlan_id[priv->pvid[port]];
880 if (priv->vlan_tagged & (1 << port))
881 egress = AR8216_OUT_ADD_VLAN;
883 egress = AR8216_OUT_STRIP_VLAN;
884 ingress = AR8216_IN_SECURE;
887 egress = AR8216_OUT_KEEP;
888 ingress = AR8216_IN_PORT_ONLY;
891 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
892 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
893 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
894 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
895 AR8216_PORT_CTRL_LEARN |
896 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
897 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
899 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
900 AR8236_PORT_VLAN_DEFAULT_ID,
901 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
903 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
904 AR8236_PORT_VLAN2_VLAN_MODE |
905 AR8236_PORT_VLAN2_MEMBER,
906 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
907 (members << AR8236_PORT_VLAN2_MEMBER_S));
911 ar8236_hw_init(struct ar8xxx_priv *priv)
913 if (priv->initialized)
916 ar8xxx_phy_init(priv);
918 priv->initialized = true;
923 ar8236_init_globals(struct ar8xxx_priv *priv)
925 /* enable jumbo frames */
926 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
927 AR8316_GCTRL_MTU, 9018 + 8 + 2);
929 /* Enable MIB counters */
930 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
931 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
935 static const struct ar8xxx_chip ar8236_chip = {
936 .caps = AR8XXX_CAP_MIB_COUNTERS,
937 .hw_init = ar8236_hw_init,
938 .init_globals = ar8236_init_globals,
939 .init_port = ar8216_init_port,
940 .setup_port = ar8236_setup_port,
941 .read_port_status = ar8216_read_port_status,
942 .atu_flush = ar8216_atu_flush,
943 .vtu_flush = ar8216_vtu_flush,
944 .vtu_load_vlan = ar8216_vtu_load_vlan,
946 .num_mibs = ARRAY_SIZE(ar8236_mibs),
947 .mib_decs = ar8236_mibs,
951 ar8316_hw_init(struct ar8xxx_priv *priv)
955 val = priv->read(priv, AR8316_REG_POSTRIP);
957 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
958 if (priv->port4_phy) {
959 /* value taken from Ubiquiti RouterStation Pro */
961 pr_info("ar8316: Using port 4 as PHY\n");
964 pr_info("ar8316: Using port 4 as switch port\n");
966 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
967 /* value taken from AVM Fritz!Box 7390 sources */
970 /* no known value for phy interface */
971 pr_err("ar8316: unsupported mii mode: %d.\n",
972 priv->phy->interface);
979 priv->write(priv, AR8316_REG_POSTRIP, newval);
981 if (priv->port4_phy &&
982 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
983 /* work around for phy4 rgmii mode */
984 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
986 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
988 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
992 ar8xxx_phy_init(priv);
995 priv->initialized = true;
1000 ar8316_init_globals(struct ar8xxx_priv *priv)
1002 /* standard atheros magic */
1003 priv->write(priv, 0x38, 0xc000050e);
1005 /* enable cpu port to receive multicast and broadcast frames */
1006 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1008 /* enable jumbo frames */
1009 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1010 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1012 /* Enable MIB counters */
1013 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1014 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1018 static const struct ar8xxx_chip ar8316_chip = {
1019 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1020 .hw_init = ar8316_hw_init,
1021 .init_globals = ar8316_init_globals,
1022 .init_port = ar8216_init_port,
1023 .setup_port = ar8216_setup_port,
1024 .read_port_status = ar8216_read_port_status,
1025 .atu_flush = ar8216_atu_flush,
1026 .vtu_flush = ar8216_vtu_flush,
1027 .vtu_load_vlan = ar8216_vtu_load_vlan,
1029 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1030 .mib_decs = ar8236_mibs,
1034 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1042 switch (cfg->mode) {
1046 case AR8327_PAD_MAC2MAC_MII:
1047 t = AR8327_PAD_MAC_MII_EN;
1049 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1051 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1054 case AR8327_PAD_MAC2MAC_GMII:
1055 t = AR8327_PAD_MAC_GMII_EN;
1057 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1059 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1062 case AR8327_PAD_MAC_SGMII:
1063 t = AR8327_PAD_SGMII_EN;
1066 * WAR for the QUalcomm Atheros AP136 board.
1067 * It seems that RGMII TX/RX delay settings needs to be
1068 * applied for SGMII mode as well, The ethernet is not
1069 * reliable without this.
1071 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1072 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1073 if (cfg->rxclk_delay_en)
1074 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1075 if (cfg->txclk_delay_en)
1076 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1078 if (cfg->sgmii_delay_en)
1079 t |= AR8327_PAD_SGMII_DELAY_EN;
1083 case AR8327_PAD_MAC2PHY_MII:
1084 t = AR8327_PAD_PHY_MII_EN;
1086 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1088 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1091 case AR8327_PAD_MAC2PHY_GMII:
1092 t = AR8327_PAD_PHY_GMII_EN;
1093 if (cfg->pipe_rxclk_sel)
1094 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1096 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1098 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1101 case AR8327_PAD_MAC_RGMII:
1102 t = AR8327_PAD_RGMII_EN;
1103 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1104 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1105 if (cfg->rxclk_delay_en)
1106 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1107 if (cfg->txclk_delay_en)
1108 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1111 case AR8327_PAD_PHY_GMII:
1112 t = AR8327_PAD_PHYX_GMII_EN;
1115 case AR8327_PAD_PHY_RGMII:
1116 t = AR8327_PAD_PHYX_RGMII_EN;
1119 case AR8327_PAD_PHY_MII:
1120 t = AR8327_PAD_PHYX_MII_EN;
1128 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1130 switch (priv->chip_rev) {
1132 /* For 100M waveform */
1133 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1134 /* Turn on Gigabit clock */
1135 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1139 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1140 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1143 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1144 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1158 if (!cfg->force_link)
1159 return AR8216_PORT_STATUS_LINK_AUTO;
1161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1166 switch (cfg->speed) {
1167 case AR8327_PORT_SPEED_10:
1168 t |= AR8216_PORT_SPEED_10M;
1170 case AR8327_PORT_SPEED_100:
1171 t |= AR8216_PORT_SPEED_100M;
1173 case AR8327_PORT_SPEED_1000:
1174 t |= AR8216_PORT_SPEED_1000M;
1181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1182 [_num] = { .reg = (_reg), .shift = (_shift) }
1184 static const struct ar8327_led_entry
1185 ar8327_led_map[AR8327_NUM_LEDS] = {
1186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1209 enum ar8327_led_pattern pattern)
1211 const struct ar8327_led_entry *entry;
1213 entry = &ar8327_led_map[led_num];
1214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1215 (3 << entry->shift), pattern << entry->shift);
1219 ar8327_led_work_func(struct work_struct *work)
1221 struct ar8327_led *aled;
1224 aled = container_of(work, struct ar8327_led, led_work);
1226 spin_lock(&aled->lock);
1227 pattern = aled->pattern;
1228 spin_unlock(&aled->lock);
1230 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1235 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1237 if (aled->pattern == pattern)
1240 aled->pattern = pattern;
1241 schedule_work(&aled->led_work);
1244 static inline struct ar8327_led *
1245 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1247 return container_of(led_cdev, struct ar8327_led, cdev);
1251 ar8327_led_blink_set(struct led_classdev *led_cdev,
1252 unsigned long *delay_on,
1253 unsigned long *delay_off)
1255 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1257 if (*delay_on == 0 && *delay_off == 0) {
1262 if (*delay_on != 125 || *delay_off != 125) {
1264 * The hardware only supports blinking at 4Hz. Fall back
1265 * to software implementation in other cases.
1270 spin_lock(&aled->lock);
1272 aled->enable_hw_mode = false;
1273 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1275 spin_unlock(&aled->lock);
1281 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1282 enum led_brightness brightness)
1284 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1288 active = (brightness != LED_OFF);
1289 active ^= aled->active_low;
1291 pattern = (active) ? AR8327_LED_PATTERN_ON :
1292 AR8327_LED_PATTERN_OFF;
1294 spin_lock(&aled->lock);
1296 aled->enable_hw_mode = false;
1297 ar8327_led_schedule_change(aled, pattern);
1299 spin_unlock(&aled->lock);
1303 ar8327_led_enable_hw_mode_show(struct device *dev,
1304 struct device_attribute *attr,
1307 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1308 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1311 spin_lock(&aled->lock);
1312 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1313 spin_unlock(&aled->lock);
1319 ar8327_led_enable_hw_mode_store(struct device *dev,
1320 struct device_attribute *attr,
1324 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1325 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1330 ret = kstrtou8(buf, 10, &value);
1334 spin_lock(&aled->lock);
1336 aled->enable_hw_mode = !!value;
1337 if (aled->enable_hw_mode)
1338 pattern = AR8327_LED_PATTERN_RULE;
1340 pattern = AR8327_LED_PATTERN_OFF;
1342 ar8327_led_schedule_change(aled, pattern);
1344 spin_unlock(&aled->lock);
1349 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1350 ar8327_led_enable_hw_mode_show,
1351 ar8327_led_enable_hw_mode_store);
1354 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1358 ret = led_classdev_register(NULL, &aled->cdev);
1362 if (aled->mode == AR8327_LED_MODE_HW) {
1363 ret = device_create_file(aled->cdev.dev,
1364 &dev_attr_enable_hw_mode);
1366 goto err_unregister;
1372 led_classdev_unregister(&aled->cdev);
1377 ar8327_led_unregister(struct ar8327_led *aled)
1379 if (aled->mode == AR8327_LED_MODE_HW)
1380 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1382 led_classdev_unregister(&aled->cdev);
1383 cancel_work_sync(&aled->led_work);
1387 ar8327_led_create(struct ar8xxx_priv *priv,
1388 const struct ar8327_led_info *led_info)
1390 struct ar8327_data *data = &priv->chip_data.ar8327;
1391 struct ar8327_led *aled;
1394 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1397 if (!led_info->name)
1400 if (led_info->led_num >= AR8327_NUM_LEDS)
1403 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1408 aled->sw_priv = priv;
1409 aled->led_num = led_info->led_num;
1410 aled->active_low = led_info->active_low;
1411 aled->mode = led_info->mode;
1413 if (aled->mode == AR8327_LED_MODE_HW)
1414 aled->enable_hw_mode = true;
1416 aled->name = (char *)(aled + 1);
1417 strcpy(aled->name, led_info->name);
1419 aled->cdev.name = aled->name;
1420 aled->cdev.brightness_set = ar8327_led_set_brightness;
1421 aled->cdev.blink_set = ar8327_led_blink_set;
1422 aled->cdev.default_trigger = led_info->default_trigger;
1424 spin_lock_init(&aled->lock);
1425 mutex_init(&aled->mutex);
1426 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1428 ret = ar8327_led_register(priv, aled);
1432 data->leds[data->num_leds++] = aled;
1442 ar8327_led_destroy(struct ar8327_led *aled)
1444 ar8327_led_unregister(aled);
1449 ar8327_leds_init(struct ar8xxx_priv *priv)
1451 struct ar8327_data *data;
1454 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1457 data = &priv->chip_data.ar8327;
1459 for (i = 0; i < data->num_leds; i++) {
1460 struct ar8327_led *aled;
1462 aled = data->leds[i];
1464 if (aled->enable_hw_mode)
1465 aled->pattern = AR8327_LED_PATTERN_RULE;
1467 aled->pattern = AR8327_LED_PATTERN_OFF;
1469 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1474 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1476 struct ar8327_data *data = &priv->chip_data.ar8327;
1479 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1482 for (i = 0; i < data->num_leds; i++) {
1483 struct ar8327_led *aled;
1485 aled = data->leds[i];
1486 ar8327_led_destroy(aled);
1493 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1494 struct ar8327_platform_data *pdata)
1496 struct ar8327_led_cfg *led_cfg;
1497 struct ar8327_data *data;
1504 priv->get_port_link = pdata->get_port_link;
1506 data = &priv->chip_data.ar8327;
1508 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1509 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1511 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1512 if (chip_is_ar8337(priv))
1513 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1515 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1516 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1517 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1518 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1519 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1521 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1524 led_cfg = pdata->led_cfg;
1526 if (led_cfg->open_drain)
1527 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1529 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1531 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1532 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1533 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1534 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1537 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1540 if (pdata->sgmii_cfg) {
1541 t = pdata->sgmii_cfg->sgmii_ctrl;
1542 if (priv->chip_rev == 1)
1543 t |= AR8327_SGMII_CTRL_EN_PLL |
1544 AR8327_SGMII_CTRL_EN_RX |
1545 AR8327_SGMII_CTRL_EN_TX;
1547 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1548 AR8327_SGMII_CTRL_EN_RX |
1549 AR8327_SGMII_CTRL_EN_TX);
1551 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1553 if (pdata->sgmii_cfg->serdes_aen)
1554 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1556 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1559 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1561 if (pdata->leds && pdata->num_leds) {
1564 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1569 for (i = 0; i < pdata->num_leds; i++)
1570 ar8327_led_create(priv, &pdata->leds[i]);
1578 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1580 const __be32 *paddr;
1584 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1585 if (!paddr || len < (2 * sizeof(*paddr)))
1588 len /= sizeof(*paddr);
1590 for (i = 0; i < len - 1; i += 2) {
1594 reg = be32_to_cpup(paddr + i);
1595 val = be32_to_cpup(paddr + i + 1);
1598 case AR8327_REG_PORT_STATUS(0):
1599 priv->chip_data.ar8327.port0_status = val;
1601 case AR8327_REG_PORT_STATUS(6):
1602 priv->chip_data.ar8327.port6_status = val;
1605 priv->write(priv, reg, val);
1614 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1621 ar8327_hw_init(struct ar8xxx_priv *priv)
1625 if (priv->phy->dev.of_node)
1626 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1628 ret = ar8327_hw_config_pdata(priv,
1629 priv->phy->dev.platform_data);
1634 ar8327_leds_init(priv);
1636 ar8xxx_phy_init(priv);
1642 ar8327_cleanup(struct ar8xxx_priv *priv)
1644 ar8327_leds_cleanup(priv);
1648 ar8327_init_globals(struct ar8xxx_priv *priv)
1652 /* enable CPU port and disable mirror port */
1653 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1654 AR8327_FWD_CTRL0_MIRROR_PORT;
1655 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1657 /* forward multicast and broadcast frames to CPU */
1658 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1659 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1660 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1661 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1663 /* enable jumbo frames */
1664 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1665 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1667 /* Enable MIB counters */
1668 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1669 AR8327_MODULE_EN_MIB);
1671 /* Disable EEE on all ports due to stability issues */
1672 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1673 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1674 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1675 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1676 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1677 AR8327_EEE_CTRL_DISABLE_PHY(4);
1678 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1682 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1686 if (port == AR8216_PORT_CPU)
1687 t = priv->chip_data.ar8327.port0_status;
1689 t = priv->chip_data.ar8327.port6_status;
1691 t = AR8216_PORT_STATUS_LINK_AUTO;
1693 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1694 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1696 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1697 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1698 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1700 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1701 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1703 t = AR8327_PORT_LOOKUP_LEARN;
1704 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1705 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1709 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1711 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1715 ar8327_atu_flush(struct ar8xxx_priv *priv)
1719 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1720 AR8327_ATU_FUNC_BUSY, 0);
1722 priv->write(priv, AR8327_REG_ATU_FUNC,
1723 AR8327_ATU_FUNC_OP_FLUSH);
1729 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1731 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1732 AR8327_VTU_FUNC1_BUSY, 0))
1735 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1736 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1738 op |= AR8327_VTU_FUNC1_BUSY;
1739 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1743 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1745 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1749 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1755 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1756 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1757 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1760 if ((port_mask & BIT(i)) == 0)
1761 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1762 else if (priv->vlan == 0)
1763 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1764 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1765 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1767 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1769 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1771 ar8327_vtu_op(priv, op, val);
1775 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1778 u32 egress, ingress;
1779 u32 pvid = priv->vlan_id[priv->pvid[port]];
1782 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1783 ingress = AR8216_IN_SECURE;
1785 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1786 ingress = AR8216_IN_PORT_ONLY;
1789 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1790 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1791 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1793 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1794 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1795 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1798 t |= AR8327_PORT_LOOKUP_LEARN;
1799 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1800 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1801 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1804 static const struct ar8xxx_chip ar8327_chip = {
1805 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1806 .hw_init = ar8327_hw_init,
1807 .cleanup = ar8327_cleanup,
1808 .init_globals = ar8327_init_globals,
1809 .init_port = ar8327_init_port,
1810 .setup_port = ar8327_setup_port,
1811 .read_port_status = ar8327_read_port_status,
1812 .atu_flush = ar8327_atu_flush,
1813 .vtu_flush = ar8327_vtu_flush,
1814 .vtu_load_vlan = ar8327_vtu_load_vlan,
1815 .phy_fixup = ar8327_phy_fixup,
1817 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1818 .mib_decs = ar8236_mibs,
1822 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1823 struct switch_val *val)
1825 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1826 priv->vlan = !!val->value.i;
1831 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1832 struct switch_val *val)
1834 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1835 val->value.i = priv->vlan;
1841 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1843 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1845 /* make sure no invalid PVIDs get set */
1847 if (vlan >= dev->vlans)
1850 priv->pvid[port] = vlan;
1855 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1857 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1858 *vlan = priv->pvid[port];
1863 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1864 struct switch_val *val)
1866 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1867 priv->vlan_id[val->port_vlan] = val->value.i;
1872 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1873 struct switch_val *val)
1875 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1876 val->value.i = priv->vlan_id[val->port_vlan];
1881 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1882 struct switch_port_link *link)
1884 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1886 ar8216_read_port_link(priv, port, link);
1891 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1893 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1894 u8 ports = priv->vlan_table[val->port_vlan];
1898 for (i = 0; i < dev->ports; i++) {
1899 struct switch_port *p;
1901 if (!(ports & (1 << i)))
1904 p = &val->value.ports[val->len++];
1906 if (priv->vlan_tagged & (1 << i))
1907 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1915 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1917 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1918 u8 ports = priv->vlan_table[val->port_vlan];
1922 for (i = 0; i < dev->ports; i++) {
1923 struct switch_port *p;
1925 if (!(ports & (1 << i)))
1928 p = &val->value.ports[val->len++];
1930 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1931 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1939 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1941 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1942 u8 *vt = &priv->vlan_table[val->port_vlan];
1946 for (i = 0; i < val->len; i++) {
1947 struct switch_port *p = &val->value.ports[i];
1949 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1950 priv->vlan_tagged |= (1 << p->id);
1952 priv->vlan_tagged &= ~(1 << p->id);
1953 priv->pvid[p->id] = val->port_vlan;
1955 /* make sure that an untagged port does not
1956 * appear in other vlans */
1957 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1958 if (j == val->port_vlan)
1960 priv->vlan_table[j] &= ~(1 << p->id);
1970 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1972 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1973 u8 *vt = &priv->vlan_table[val->port_vlan];
1977 for (i = 0; i < val->len; i++) {
1978 struct switch_port *p = &val->value.ports[i];
1980 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1981 if (val->port_vlan == priv->pvid[p->id]) {
1982 priv->vlan_tagged |= (1 << p->id);
1985 priv->vlan_tagged &= ~(1 << p->id);
1986 priv->pvid[p->id] = val->port_vlan;
1995 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1999 /* reset all mirror registers */
2000 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2001 AR8327_FWD_CTRL0_MIRROR_PORT,
2002 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2003 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2004 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2005 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2008 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2009 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2013 /* now enable mirroring if necessary */
2014 if (priv->source_port >= AR8327_NUM_PORTS ||
2015 priv->monitor_port >= AR8327_NUM_PORTS ||
2016 priv->source_port == priv->monitor_port) {
2020 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2021 AR8327_FWD_CTRL0_MIRROR_PORT,
2022 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2024 if (priv->mirror_rx)
2025 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2026 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2027 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2029 if (priv->mirror_tx)
2030 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2031 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2032 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2036 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2040 /* reset all mirror registers */
2041 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2042 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2043 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2044 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2045 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2046 AR8216_PORT_CTRL_MIRROR_RX,
2049 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2050 AR8216_PORT_CTRL_MIRROR_TX,
2054 /* now enable mirroring if necessary */
2055 if (priv->source_port >= AR8216_NUM_PORTS ||
2056 priv->monitor_port >= AR8216_NUM_PORTS ||
2057 priv->source_port == priv->monitor_port) {
2061 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2062 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2063 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2065 if (priv->mirror_rx)
2066 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2067 AR8216_PORT_CTRL_MIRROR_RX,
2068 AR8216_PORT_CTRL_MIRROR_RX);
2070 if (priv->mirror_tx)
2071 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2072 AR8216_PORT_CTRL_MIRROR_TX,
2073 AR8216_PORT_CTRL_MIRROR_TX);
2077 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2079 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2080 ar8327_set_mirror_regs(priv);
2082 ar8216_set_mirror_regs(priv);
2087 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2089 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2090 u8 portmask[AR8X16_MAX_PORTS];
2093 mutex_lock(&priv->reg_mutex);
2094 /* flush all vlan translation unit entries */
2095 priv->chip->vtu_flush(priv);
2097 memset(portmask, 0, sizeof(portmask));
2099 /* calculate the port destination masks and load vlans
2100 * into the vlan translation unit */
2101 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2102 u8 vp = priv->vlan_table[j];
2107 for (i = 0; i < dev->ports; i++) {
2110 portmask[i] |= vp & ~mask;
2113 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2114 priv->vlan_table[j]);
2118 * isolate all ports, but connect them to the cpu port */
2119 for (i = 0; i < dev->ports; i++) {
2120 if (i == AR8216_PORT_CPU)
2123 portmask[i] = 1 << AR8216_PORT_CPU;
2124 portmask[AR8216_PORT_CPU] |= (1 << i);
2128 /* update the port destination mask registers and tag settings */
2129 for (i = 0; i < dev->ports; i++) {
2130 priv->chip->setup_port(priv, i, portmask[i]);
2133 ar8xxx_set_mirror_regs(priv);
2135 mutex_unlock(&priv->reg_mutex);
2140 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2142 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2145 mutex_lock(&priv->reg_mutex);
2146 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2147 offsetof(struct ar8xxx_priv, vlan));
2149 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2150 priv->vlan_id[i] = i;
2152 /* Configure all ports */
2153 for (i = 0; i < dev->ports; i++)
2154 priv->chip->init_port(priv, i);
2156 priv->mirror_rx = false;
2157 priv->mirror_tx = false;
2158 priv->source_port = 0;
2159 priv->monitor_port = 0;
2161 priv->chip->init_globals(priv);
2163 mutex_unlock(&priv->reg_mutex);
2165 return ar8xxx_sw_hw_apply(dev);
2169 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2170 const struct switch_attr *attr,
2171 struct switch_val *val)
2173 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2177 if (!ar8xxx_has_mib_counters(priv))
2180 mutex_lock(&priv->mib_lock);
2182 len = priv->dev.ports * priv->chip->num_mibs *
2183 sizeof(*priv->mib_stats);
2184 memset(priv->mib_stats, '\0', len);
2185 ret = ar8xxx_mib_flush(priv);
2192 mutex_unlock(&priv->mib_lock);
2197 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2198 const struct switch_attr *attr,
2199 struct switch_val *val)
2201 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2203 mutex_lock(&priv->reg_mutex);
2204 priv->mirror_rx = !!val->value.i;
2205 ar8xxx_set_mirror_regs(priv);
2206 mutex_unlock(&priv->reg_mutex);
2212 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2213 const struct switch_attr *attr,
2214 struct switch_val *val)
2216 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2217 val->value.i = priv->mirror_rx;
2222 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2223 const struct switch_attr *attr,
2224 struct switch_val *val)
2226 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2228 mutex_lock(&priv->reg_mutex);
2229 priv->mirror_tx = !!val->value.i;
2230 ar8xxx_set_mirror_regs(priv);
2231 mutex_unlock(&priv->reg_mutex);
2237 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2238 const struct switch_attr *attr,
2239 struct switch_val *val)
2241 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2242 val->value.i = priv->mirror_tx;
2247 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2248 const struct switch_attr *attr,
2249 struct switch_val *val)
2251 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2253 mutex_lock(&priv->reg_mutex);
2254 priv->monitor_port = val->value.i;
2255 ar8xxx_set_mirror_regs(priv);
2256 mutex_unlock(&priv->reg_mutex);
2262 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2263 const struct switch_attr *attr,
2264 struct switch_val *val)
2266 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2267 val->value.i = priv->monitor_port;
2272 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2273 const struct switch_attr *attr,
2274 struct switch_val *val)
2276 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2278 mutex_lock(&priv->reg_mutex);
2279 priv->source_port = val->value.i;
2280 ar8xxx_set_mirror_regs(priv);
2281 mutex_unlock(&priv->reg_mutex);
2287 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2288 const struct switch_attr *attr,
2289 struct switch_val *val)
2291 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2292 val->value.i = priv->source_port;
2297 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2298 const struct switch_attr *attr,
2299 struct switch_val *val)
2301 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2305 if (!ar8xxx_has_mib_counters(priv))
2308 port = val->port_vlan;
2309 if (port >= dev->ports)
2312 mutex_lock(&priv->mib_lock);
2313 ret = ar8xxx_mib_capture(priv);
2317 ar8xxx_mib_fetch_port_stat(priv, port, true);
2322 mutex_unlock(&priv->mib_lock);
2327 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2328 const struct switch_attr *attr,
2329 struct switch_val *val)
2331 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2332 const struct ar8xxx_chip *chip = priv->chip;
2336 char *buf = priv->buf;
2339 if (!ar8xxx_has_mib_counters(priv))
2342 port = val->port_vlan;
2343 if (port >= dev->ports)
2346 mutex_lock(&priv->mib_lock);
2347 ret = ar8xxx_mib_capture(priv);
2351 ar8xxx_mib_fetch_port_stat(priv, port, false);
2353 len += snprintf(buf + len, sizeof(priv->buf) - len,
2354 "Port %d MIB counters\n",
2357 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2358 for (i = 0; i < chip->num_mibs; i++)
2359 len += snprintf(buf + len, sizeof(priv->buf) - len,
2361 chip->mib_decs[i].name,
2370 mutex_unlock(&priv->mib_lock);
2374 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2376 .type = SWITCH_TYPE_INT,
2377 .name = "enable_vlan",
2378 .description = "Enable VLAN mode",
2379 .set = ar8xxx_sw_set_vlan,
2380 .get = ar8xxx_sw_get_vlan,
2384 .type = SWITCH_TYPE_NOVAL,
2385 .name = "reset_mibs",
2386 .description = "Reset all MIB counters",
2387 .set = ar8xxx_sw_set_reset_mibs,
2390 .type = SWITCH_TYPE_INT,
2391 .name = "enable_mirror_rx",
2392 .description = "Enable mirroring of RX packets",
2393 .set = ar8xxx_sw_set_mirror_rx_enable,
2394 .get = ar8xxx_sw_get_mirror_rx_enable,
2398 .type = SWITCH_TYPE_INT,
2399 .name = "enable_mirror_tx",
2400 .description = "Enable mirroring of TX packets",
2401 .set = ar8xxx_sw_set_mirror_tx_enable,
2402 .get = ar8xxx_sw_get_mirror_tx_enable,
2406 .type = SWITCH_TYPE_INT,
2407 .name = "mirror_monitor_port",
2408 .description = "Mirror monitor port",
2409 .set = ar8xxx_sw_set_mirror_monitor_port,
2410 .get = ar8xxx_sw_get_mirror_monitor_port,
2411 .max = AR8216_NUM_PORTS - 1
2414 .type = SWITCH_TYPE_INT,
2415 .name = "mirror_source_port",
2416 .description = "Mirror source port",
2417 .set = ar8xxx_sw_set_mirror_source_port,
2418 .get = ar8xxx_sw_get_mirror_source_port,
2419 .max = AR8216_NUM_PORTS - 1
2423 static struct switch_attr ar8327_sw_attr_globals[] = {
2425 .type = SWITCH_TYPE_INT,
2426 .name = "enable_vlan",
2427 .description = "Enable VLAN mode",
2428 .set = ar8xxx_sw_set_vlan,
2429 .get = ar8xxx_sw_get_vlan,
2433 .type = SWITCH_TYPE_NOVAL,
2434 .name = "reset_mibs",
2435 .description = "Reset all MIB counters",
2436 .set = ar8xxx_sw_set_reset_mibs,
2439 .type = SWITCH_TYPE_INT,
2440 .name = "enable_mirror_rx",
2441 .description = "Enable mirroring of RX packets",
2442 .set = ar8xxx_sw_set_mirror_rx_enable,
2443 .get = ar8xxx_sw_get_mirror_rx_enable,
2447 .type = SWITCH_TYPE_INT,
2448 .name = "enable_mirror_tx",
2449 .description = "Enable mirroring of TX packets",
2450 .set = ar8xxx_sw_set_mirror_tx_enable,
2451 .get = ar8xxx_sw_get_mirror_tx_enable,
2455 .type = SWITCH_TYPE_INT,
2456 .name = "mirror_monitor_port",
2457 .description = "Mirror monitor port",
2458 .set = ar8xxx_sw_set_mirror_monitor_port,
2459 .get = ar8xxx_sw_get_mirror_monitor_port,
2460 .max = AR8327_NUM_PORTS - 1
2463 .type = SWITCH_TYPE_INT,
2464 .name = "mirror_source_port",
2465 .description = "Mirror source port",
2466 .set = ar8xxx_sw_set_mirror_source_port,
2467 .get = ar8xxx_sw_get_mirror_source_port,
2468 .max = AR8327_NUM_PORTS - 1
2472 static struct switch_attr ar8xxx_sw_attr_port[] = {
2474 .type = SWITCH_TYPE_NOVAL,
2475 .name = "reset_mib",
2476 .description = "Reset single port MIB counters",
2477 .set = ar8xxx_sw_set_port_reset_mib,
2480 .type = SWITCH_TYPE_STRING,
2482 .description = "Get port's MIB counters",
2484 .get = ar8xxx_sw_get_port_mib,
2488 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2490 .type = SWITCH_TYPE_INT,
2492 .description = "VLAN ID (0-4094)",
2493 .set = ar8xxx_sw_set_vid,
2494 .get = ar8xxx_sw_get_vid,
2499 static const struct switch_dev_ops ar8xxx_sw_ops = {
2501 .attr = ar8xxx_sw_attr_globals,
2502 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2505 .attr = ar8xxx_sw_attr_port,
2506 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2509 .attr = ar8xxx_sw_attr_vlan,
2510 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2512 .get_port_pvid = ar8xxx_sw_get_pvid,
2513 .set_port_pvid = ar8xxx_sw_set_pvid,
2514 .get_vlan_ports = ar8xxx_sw_get_ports,
2515 .set_vlan_ports = ar8xxx_sw_set_ports,
2516 .apply_config = ar8xxx_sw_hw_apply,
2517 .reset_switch = ar8xxx_sw_reset_switch,
2518 .get_port_link = ar8xxx_sw_get_port_link,
2521 static const struct switch_dev_ops ar8327_sw_ops = {
2523 .attr = ar8327_sw_attr_globals,
2524 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2527 .attr = ar8xxx_sw_attr_port,
2528 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2531 .attr = ar8xxx_sw_attr_vlan,
2532 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2534 .get_port_pvid = ar8xxx_sw_get_pvid,
2535 .set_port_pvid = ar8xxx_sw_set_pvid,
2536 .get_vlan_ports = ar8327_sw_get_ports,
2537 .set_vlan_ports = ar8327_sw_set_ports,
2538 .apply_config = ar8xxx_sw_hw_apply,
2539 .reset_switch = ar8xxx_sw_reset_switch,
2540 .get_port_link = ar8xxx_sw_get_port_link,
2544 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2550 val = priv->read(priv, AR8216_REG_CTRL);
2554 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2555 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2558 val = priv->read(priv, AR8216_REG_CTRL);
2562 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2567 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2568 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2570 switch (priv->chip_ver) {
2571 case AR8XXX_VER_AR8216:
2572 priv->chip = &ar8216_chip;
2574 case AR8XXX_VER_AR8236:
2575 priv->chip = &ar8236_chip;
2577 case AR8XXX_VER_AR8316:
2578 priv->chip = &ar8316_chip;
2580 case AR8XXX_VER_AR8327:
2581 priv->mii_lo_first = true;
2582 priv->chip = &ar8327_chip;
2584 case AR8XXX_VER_AR8337:
2585 priv->mii_lo_first = true;
2586 priv->chip = &ar8327_chip;
2589 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2590 priv->chip_ver, priv->chip_rev);
2599 ar8xxx_mib_work_func(struct work_struct *work)
2601 struct ar8xxx_priv *priv;
2604 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2606 mutex_lock(&priv->mib_lock);
2608 err = ar8xxx_mib_capture(priv);
2612 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2615 priv->mib_next_port++;
2616 if (priv->mib_next_port >= priv->dev.ports)
2617 priv->mib_next_port = 0;
2619 mutex_unlock(&priv->mib_lock);
2620 schedule_delayed_work(&priv->mib_work,
2621 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2625 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2629 if (!ar8xxx_has_mib_counters(priv))
2632 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2634 len = priv->dev.ports * priv->chip->num_mibs *
2635 sizeof(*priv->mib_stats);
2636 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2638 if (!priv->mib_stats)
2645 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2647 if (!ar8xxx_has_mib_counters(priv))
2650 schedule_delayed_work(&priv->mib_work,
2651 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2655 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2657 if (!ar8xxx_has_mib_counters(priv))
2660 cancel_delayed_work(&priv->mib_work);
2663 static struct ar8xxx_priv *
2666 struct ar8xxx_priv *priv;
2668 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2672 mutex_init(&priv->reg_mutex);
2673 mutex_init(&priv->mib_lock);
2674 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2680 ar8xxx_free(struct ar8xxx_priv *priv)
2682 if (priv->chip && priv->chip->cleanup)
2683 priv->chip->cleanup(priv);
2685 kfree(priv->mib_stats);
2689 static struct ar8xxx_priv *
2690 ar8xxx_create_mii(struct mii_bus *bus)
2692 struct ar8xxx_priv *priv;
2694 priv = ar8xxx_create();
2696 priv->mii_bus = bus;
2697 priv->read = ar8xxx_mii_read;
2698 priv->write = ar8xxx_mii_write;
2699 priv->rmw = ar8xxx_mii_rmw;
2706 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2708 struct switch_dev *swdev;
2711 ret = ar8xxx_id_chip(priv);
2716 swdev->cpu_port = AR8216_PORT_CPU;
2717 swdev->ops = &ar8xxx_sw_ops;
2719 if (chip_is_ar8316(priv)) {
2720 swdev->name = "Atheros AR8316";
2721 swdev->vlans = AR8X16_MAX_VLANS;
2722 swdev->ports = AR8216_NUM_PORTS;
2723 } else if (chip_is_ar8236(priv)) {
2724 swdev->name = "Atheros AR8236";
2725 swdev->vlans = AR8216_NUM_VLANS;
2726 swdev->ports = AR8216_NUM_PORTS;
2727 } else if (chip_is_ar8327(priv)) {
2728 swdev->name = "Atheros AR8327";
2729 swdev->vlans = AR8X16_MAX_VLANS;
2730 swdev->ports = AR8327_NUM_PORTS;
2731 swdev->ops = &ar8327_sw_ops;
2732 } else if (chip_is_ar8337(priv)) {
2733 swdev->name = "Atheros AR8337";
2734 swdev->vlans = AR8X16_MAX_VLANS;
2735 swdev->ports = AR8327_NUM_PORTS;
2736 swdev->ops = &ar8327_sw_ops;
2738 swdev->name = "Atheros AR8216";
2739 swdev->vlans = AR8216_NUM_VLANS;
2740 swdev->ports = AR8216_NUM_PORTS;
2743 ret = ar8xxx_mib_init(priv);
2751 ar8xxx_start(struct ar8xxx_priv *priv)
2757 ret = priv->chip->hw_init(priv);
2761 ret = ar8xxx_sw_reset_switch(&priv->dev);
2767 ar8xxx_mib_start(priv);
2773 ar8xxx_phy_config_init(struct phy_device *phydev)
2775 struct ar8xxx_priv *priv = phydev->priv;
2776 struct net_device *dev = phydev->attached_dev;
2782 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2787 if (phydev->addr != 0) {
2788 if (chip_is_ar8316(priv)) {
2789 /* switch device has been initialized, reinit */
2790 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2791 priv->initialized = false;
2792 priv->port4_phy = true;
2793 ar8316_hw_init(priv);
2800 ret = ar8xxx_start(priv);
2804 /* VID fixup only needed on ar8216 */
2805 if (chip_is_ar8216(priv)) {
2806 dev->phy_ptr = priv;
2807 dev->priv_flags |= IFF_NO_IP_ALIGN;
2808 dev->eth_mangle_rx = ar8216_mangle_rx;
2809 dev->eth_mangle_tx = ar8216_mangle_tx;
2816 ar8xxx_phy_read_status(struct phy_device *phydev)
2818 struct ar8xxx_priv *priv = phydev->priv;
2819 struct switch_port_link link;
2822 if (phydev->addr != 0)
2823 return genphy_read_status(phydev);
2825 ar8216_read_port_link(priv, phydev->addr, &link);
2826 phydev->link = !!link.link;
2830 switch (link.speed) {
2831 case SWITCH_PORT_SPEED_10:
2832 phydev->speed = SPEED_10;
2834 case SWITCH_PORT_SPEED_100:
2835 phydev->speed = SPEED_100;
2837 case SWITCH_PORT_SPEED_1000:
2838 phydev->speed = SPEED_1000;
2843 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2845 /* flush the address translation unit */
2846 mutex_lock(&priv->reg_mutex);
2847 ret = priv->chip->atu_flush(priv);
2848 mutex_unlock(&priv->reg_mutex);
2850 phydev->state = PHY_RUNNING;
2851 netif_carrier_on(phydev->attached_dev);
2852 phydev->adjust_link(phydev->attached_dev);
2857 static const u32 ar8xxx_phy_ids[] = {
2859 0x004dd034, /* AR8327 */
2860 0x004dd036, /* AR8337 */
2863 0x004dd043, /* AR8236 */
2867 ar8xxx_phy_match(u32 phy_id)
2871 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2872 if (phy_id == ar8xxx_phy_ids[i])
2879 ar8xxx_is_possible(struct mii_bus *bus)
2883 for (i = 0; i < 4; i++) {
2886 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2887 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2888 if (!ar8xxx_phy_match(phy_id)) {
2889 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2890 dev_name(&bus->dev), i, phy_id);
2899 ar8xxx_phy_probe(struct phy_device *phydev)
2901 struct ar8xxx_priv *priv;
2902 struct switch_dev *swdev;
2905 /* skip PHYs at unused adresses */
2906 if (phydev->addr != 0 && phydev->addr != 4)
2909 if (!ar8xxx_is_possible(phydev->bus))
2912 mutex_lock(&ar8xxx_dev_list_lock);
2913 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2914 if (priv->mii_bus == phydev->bus)
2917 priv = ar8xxx_create_mii(phydev->bus);
2923 ret = ar8xxx_probe_switch(priv);
2928 swdev->alias = dev_name(&priv->mii_bus->dev);
2929 ret = register_switch(swdev, NULL);
2933 pr_info("%s: %s rev. %u switch registered on %s\n",
2934 swdev->devname, swdev->name, priv->chip_rev,
2935 dev_name(&priv->mii_bus->dev));
2940 if (phydev->addr == 0) {
2941 if (ar8xxx_has_gige(priv)) {
2942 phydev->supported = SUPPORTED_1000baseT_Full;
2943 phydev->advertising = ADVERTISED_1000baseT_Full;
2945 phydev->supported = SUPPORTED_100baseT_Full;
2946 phydev->advertising = ADVERTISED_100baseT_Full;
2949 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2952 ret = ar8xxx_start(priv);
2954 goto err_unregister_switch;
2957 if (ar8xxx_has_gige(priv)) {
2958 phydev->supported |= SUPPORTED_1000baseT_Full;
2959 phydev->advertising |= ADVERTISED_1000baseT_Full;
2963 phydev->priv = priv;
2965 list_add(&priv->list, &ar8xxx_dev_list);
2967 mutex_unlock(&ar8xxx_dev_list_lock);
2971 err_unregister_switch:
2972 if (--priv->use_count)
2975 unregister_switch(&priv->dev);
2980 mutex_unlock(&ar8xxx_dev_list_lock);
2985 ar8xxx_phy_detach(struct phy_device *phydev)
2987 struct net_device *dev = phydev->attached_dev;
2992 dev->phy_ptr = NULL;
2993 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2994 dev->eth_mangle_rx = NULL;
2995 dev->eth_mangle_tx = NULL;
2999 ar8xxx_phy_remove(struct phy_device *phydev)
3001 struct ar8xxx_priv *priv = phydev->priv;
3006 phydev->priv = NULL;
3007 if (--priv->use_count > 0)
3010 mutex_lock(&ar8xxx_dev_list_lock);
3011 list_del(&priv->list);
3012 mutex_unlock(&ar8xxx_dev_list_lock);
3014 unregister_switch(&priv->dev);
3015 ar8xxx_mib_stop(priv);
3019 static struct phy_driver ar8xxx_phy_driver = {
3020 .phy_id = 0x004d0000,
3021 .name = "Atheros AR8216/AR8236/AR8316",
3022 .phy_id_mask = 0xffff0000,
3023 .features = PHY_BASIC_FEATURES,
3024 .probe = ar8xxx_phy_probe,
3025 .remove = ar8xxx_phy_remove,
3026 .detach = ar8xxx_phy_detach,
3027 .config_init = ar8xxx_phy_config_init,
3028 .config_aneg = genphy_config_aneg,
3029 .read_status = ar8xxx_phy_read_status,
3030 .driver = { .owner = THIS_MODULE },
3036 return phy_driver_register(&ar8xxx_phy_driver);
3042 phy_driver_unregister(&ar8xxx_phy_driver);
3045 module_init(ar8xxx_init);
3046 module_exit(ar8xxx_exit);
3047 MODULE_LICENSE("GPL");