2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/list.h>
21 #include <linux/if_ether.h>
22 #include <linux/skbuff.h>
23 #include <linux/netdevice.h>
24 #include <linux/netlink.h>
25 #include <linux/bitops.h>
26 #include <net/genetlink.h>
27 #include <linux/switch.h>
28 #include <linux/delay.h>
29 #include <linux/phy.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/lockdep.h>
35 /* size of the vlan table */
36 #define AR8X16_MAX_VLANS 128
37 #define AR8X16_PROBE_RETRIES 10
38 #define AR8X16_MAX_PORTS 8
42 #define AR8XXX_CAP_GIGE BIT(0)
47 int (*hw_init)(struct ar8216_priv *priv);
48 void (*init_globals)(struct ar8216_priv *priv);
49 void (*init_port)(struct ar8216_priv *priv, int port);
50 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
51 u32 ingress, u32 members, u32 pvid);
52 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
53 int (*atu_flush)(struct ar8216_priv *priv);
54 void (*vtu_flush)(struct ar8216_priv *priv);
55 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
59 struct switch_dev dev;
60 struct phy_device *phy;
61 u32 (*read)(struct ar8216_priv *priv, int reg);
62 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
63 const struct net_device_ops *ndo_old;
64 struct net_device_ops ndo;
65 struct mutex reg_mutex;
67 const struct ar8xxx_chip *chip;
74 /* all fields below are cleared on reset */
76 u16 vlan_id[AR8X16_MAX_VLANS];
77 u8 vlan_table[AR8X16_MAX_VLANS];
79 u16 pvid[AR8X16_MAX_PORTS];
82 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
84 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
86 return priv->chip->caps & AR8XXX_CAP_GIGE;
90 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
99 *page = regaddr & 0x1ff;
103 ar8216_mii_read(struct ar8216_priv *priv, int reg)
105 struct phy_device *phy = priv->phy;
106 struct mii_bus *bus = phy->bus;
110 split_addr((u32) reg, &r1, &r2, &page);
112 mutex_lock(&bus->mdio_lock);
114 bus->write(bus, 0x18, 0, page);
115 usleep_range(1000, 2000); /* wait for the page switch to propagate */
116 lo = bus->read(bus, 0x10 | r2, r1);
117 hi = bus->read(bus, 0x10 | r2, r1 + 1);
119 mutex_unlock(&bus->mdio_lock);
121 return (hi << 16) | lo;
125 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
127 struct phy_device *phy = priv->phy;
128 struct mii_bus *bus = phy->bus;
132 split_addr((u32) reg, &r1, &r2, &r3);
134 hi = (u16) (val >> 16);
136 mutex_lock(&bus->mdio_lock);
138 bus->write(bus, 0x18, 0, r3);
139 usleep_range(1000, 2000); /* wait for the page switch to propagate */
140 bus->write(bus, 0x10 | r2, r1 + 1, hi);
141 bus->write(bus, 0x10 | r2, r1, lo);
143 mutex_unlock(&bus->mdio_lock);
147 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
148 u16 dbg_addr, u16 dbg_data)
150 struct mii_bus *bus = priv->phy->bus;
152 mutex_lock(&bus->mdio_lock);
153 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
154 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
155 mutex_unlock(&bus->mdio_lock);
159 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
163 lockdep_assert_held(&priv->reg_mutex);
165 v = priv->read(priv, reg);
168 priv->write(priv, reg, v);
174 ar8216_read_port_link(struct ar8216_priv *priv, int port,
175 struct switch_port_link *link)
180 memset(link, '\0', sizeof(*link));
182 status = priv->chip->read_port_status(priv, port);
184 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
186 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
193 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
194 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
195 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
197 speed = (status & AR8216_PORT_STATUS_SPEED) >>
198 AR8216_PORT_STATUS_SPEED_S;
201 case AR8216_PORT_SPEED_10M:
202 link->speed = SWITCH_PORT_SPEED_10;
204 case AR8216_PORT_SPEED_100M:
205 link->speed = SWITCH_PORT_SPEED_100;
207 case AR8216_PORT_SPEED_1000M:
208 link->speed = SWITCH_PORT_SPEED_1000;
211 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
217 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
219 struct ar8216_priv *priv = dev->phy_ptr;
228 if (unlikely(skb_headroom(skb) < 2)) {
229 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
233 buf = skb_push(skb, 2);
238 return priv->ndo_old->ndo_start_xmit(skb, dev);
241 dev_kfree_skb_any(skb);
246 ar8216_mangle_rx(struct sk_buff *skb, int napi)
248 struct ar8216_priv *priv;
249 struct net_device *dev;
261 /* don't strip the header if vlan mode is disabled */
265 /* strip header, get vlan id */
269 /* check for vlan header presence */
270 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
275 /* no need to fix up packets coming from a tagged source */
276 if (priv->vlan_tagged & (1 << port))
279 /* lookup port vid from local table, the switch passes an invalid vlan id */
280 vlan = priv->vlan_id[priv->pvid[port]];
283 buf[14 + 2] |= vlan >> 8;
284 buf[15 + 2] = vlan & 0xff;
287 skb->protocol = eth_type_trans(skb, skb->dev);
290 return netif_receive_skb(skb);
292 return netif_rx(skb);
295 /* no vlan? eat the packet! */
296 dev_kfree_skb_any(skb);
301 ar8216_netif_rx(struct sk_buff *skb)
303 return ar8216_mangle_rx(skb, 0);
307 ar8216_netif_receive_skb(struct sk_buff *skb)
309 return ar8216_mangle_rx(skb, 1);
313 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
319 t = priv->read(priv, reg);
320 if ((t & mask) == val)
329 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
330 (unsigned int) reg, t, mask, val);
335 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
337 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
339 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
340 val &= AR8216_VTUDATA_MEMBER;
341 val |= AR8216_VTUDATA_VALID;
342 priv->write(priv, AR8216_REG_VTU_DATA, val);
344 op |= AR8216_VTU_ACTIVE;
345 priv->write(priv, AR8216_REG_VTU, op);
349 ar8216_vtu_flush(struct ar8216_priv *priv)
351 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
355 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
359 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
360 ar8216_vtu_op(priv, op, port_mask);
364 ar8216_atu_flush(struct ar8216_priv *priv)
368 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
370 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
376 ar8216_read_port_status(struct ar8216_priv *priv, int port)
378 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
382 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
383 u32 members, u32 pvid)
387 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
388 header = AR8216_PORT_CTRL_HEADER;
392 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
393 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
394 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
395 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
396 AR8216_PORT_CTRL_LEARN | header |
397 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
398 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
400 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
401 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
402 AR8216_PORT_VLAN_DEFAULT_ID,
403 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
404 (ingress << AR8216_PORT_VLAN_MODE_S) |
405 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
409 ar8216_hw_init(struct ar8216_priv *priv)
415 ar8216_init_globals(struct ar8216_priv *priv)
417 /* standard atheros magic */
418 priv->write(priv, 0x38, 0xc000050e);
420 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
421 AR8216_GCTRL_MTU, 1518 + 8 + 2);
425 ar8216_init_port(struct ar8216_priv *priv, int port)
427 /* Enable port learning and tx */
428 priv->write(priv, AR8216_REG_PORT_CTRL(port),
429 AR8216_PORT_CTRL_LEARN |
430 (4 << AR8216_PORT_CTRL_STATE_S));
432 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
434 if (port == AR8216_PORT_CPU) {
435 priv->write(priv, AR8216_REG_PORT_STATUS(port),
436 AR8216_PORT_STATUS_LINK_UP |
437 ar8xxx_has_gige(priv) ? AR8216_PORT_SPEED_1000M :
438 AR8216_PORT_SPEED_100M |
439 AR8216_PORT_STATUS_TXMAC |
440 AR8216_PORT_STATUS_RXMAC |
441 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
442 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
443 AR8216_PORT_STATUS_DUPLEX);
445 priv->write(priv, AR8216_REG_PORT_STATUS(port),
446 AR8216_PORT_STATUS_LINK_AUTO);
450 static const struct ar8xxx_chip ar8216_chip = {
451 .hw_init = ar8216_hw_init,
452 .init_globals = ar8216_init_globals,
453 .init_port = ar8216_init_port,
454 .setup_port = ar8216_setup_port,
455 .read_port_status = ar8216_read_port_status,
456 .atu_flush = ar8216_atu_flush,
457 .vtu_flush = ar8216_vtu_flush,
458 .vtu_load_vlan = ar8216_vtu_load_vlan,
462 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
463 u32 members, u32 pvid)
465 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
466 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
467 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
468 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
469 AR8216_PORT_CTRL_LEARN |
470 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
471 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
473 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
474 AR8236_PORT_VLAN_DEFAULT_ID,
475 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
477 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
478 AR8236_PORT_VLAN2_VLAN_MODE |
479 AR8236_PORT_VLAN2_MEMBER,
480 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
481 (members << AR8236_PORT_VLAN2_MEMBER_S));
485 ar8236_hw_init(struct ar8216_priv *priv)
490 if (priv->initialized)
493 /* Initialize the PHYs */
494 bus = priv->phy->bus;
495 for (i = 0; i < 5; i++) {
496 mdiobus_write(bus, i, MII_ADVERTISE,
497 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
498 ADVERTISE_PAUSE_ASYM);
499 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
503 priv->initialized = true;
508 ar8236_init_globals(struct ar8216_priv *priv)
510 /* enable jumbo frames */
511 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
512 AR8316_GCTRL_MTU, 9018 + 8 + 2);
515 static const struct ar8xxx_chip ar8236_chip = {
516 .hw_init = ar8236_hw_init,
517 .init_globals = ar8236_init_globals,
518 .init_port = ar8216_init_port,
519 .setup_port = ar8236_setup_port,
520 .read_port_status = ar8216_read_port_status,
521 .atu_flush = ar8216_atu_flush,
522 .vtu_flush = ar8216_vtu_flush,
523 .vtu_load_vlan = ar8216_vtu_load_vlan,
527 ar8316_hw_init(struct ar8216_priv *priv)
533 val = priv->read(priv, 0x8);
535 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
536 if (priv->port4_phy) {
537 /* value taken from Ubiquiti RouterStation Pro */
539 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
542 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
544 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
545 /* value taken from AVM Fritz!Box 7390 sources */
548 /* no known value for phy interface */
549 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
550 priv->phy->interface);
557 priv->write(priv, 0x8, newval);
559 /* Initialize the ports */
560 bus = priv->phy->bus;
561 for (i = 0; i < 5; i++) {
562 if ((i == 4) && priv->port4_phy &&
563 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
564 /* work around for phy4 rgmii mode */
565 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
567 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
569 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
573 /* initialize the port itself */
574 mdiobus_write(bus, i, MII_ADVERTISE,
575 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
576 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
577 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
582 priv->initialized = true;
587 ar8316_init_globals(struct ar8216_priv *priv)
589 /* standard atheros magic */
590 priv->write(priv, 0x38, 0xc000050e);
592 /* enable cpu port to receive multicast and broadcast frames */
593 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
595 /* enable jumbo frames */
596 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
597 AR8316_GCTRL_MTU, 9018 + 8 + 2);
600 static const struct ar8xxx_chip ar8316_chip = {
601 .caps = AR8XXX_CAP_GIGE,
602 .hw_init = ar8316_hw_init,
603 .init_globals = ar8316_init_globals,
604 .init_port = ar8216_init_port,
605 .setup_port = ar8216_setup_port,
606 .read_port_status = ar8216_read_port_status,
607 .atu_flush = ar8216_atu_flush,
608 .vtu_flush = ar8216_vtu_flush,
609 .vtu_load_vlan = ar8216_vtu_load_vlan,
613 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
614 struct switch_val *val)
616 struct ar8216_priv *priv = to_ar8216(dev);
617 priv->vlan = !!val->value.i;
622 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
623 struct switch_val *val)
625 struct ar8216_priv *priv = to_ar8216(dev);
626 val->value.i = priv->vlan;
632 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
634 struct ar8216_priv *priv = to_ar8216(dev);
636 /* make sure no invalid PVIDs get set */
638 if (vlan >= dev->vlans)
641 priv->pvid[port] = vlan;
646 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
648 struct ar8216_priv *priv = to_ar8216(dev);
649 *vlan = priv->pvid[port];
654 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
655 struct switch_val *val)
657 struct ar8216_priv *priv = to_ar8216(dev);
658 priv->vlan_id[val->port_vlan] = val->value.i;
663 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
664 struct switch_val *val)
666 struct ar8216_priv *priv = to_ar8216(dev);
667 val->value.i = priv->vlan_id[val->port_vlan];
672 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
673 struct switch_port_link *link)
675 struct ar8216_priv *priv = to_ar8216(dev);
677 ar8216_read_port_link(priv, port, link);
682 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
684 struct ar8216_priv *priv = to_ar8216(dev);
685 u8 ports = priv->vlan_table[val->port_vlan];
689 for (i = 0; i < dev->ports; i++) {
690 struct switch_port *p;
692 if (!(ports & (1 << i)))
695 p = &val->value.ports[val->len++];
697 if (priv->vlan_tagged & (1 << i))
698 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
706 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
708 struct ar8216_priv *priv = to_ar8216(dev);
709 u8 *vt = &priv->vlan_table[val->port_vlan];
713 for (i = 0; i < val->len; i++) {
714 struct switch_port *p = &val->value.ports[i];
716 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
717 priv->vlan_tagged |= (1 << p->id);
719 priv->vlan_tagged &= ~(1 << p->id);
720 priv->pvid[p->id] = val->port_vlan;
722 /* make sure that an untagged port does not
723 * appear in other vlans */
724 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
725 if (j == val->port_vlan)
727 priv->vlan_table[j] &= ~(1 << p->id);
737 ar8216_sw_hw_apply(struct switch_dev *dev)
739 struct ar8216_priv *priv = to_ar8216(dev);
740 u8 portmask[AR8X16_MAX_PORTS];
743 mutex_lock(&priv->reg_mutex);
744 /* flush all vlan translation unit entries */
745 priv->chip->vtu_flush(priv);
747 memset(portmask, 0, sizeof(portmask));
749 /* calculate the port destination masks and load vlans
750 * into the vlan translation unit */
751 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
752 u8 vp = priv->vlan_table[j];
757 for (i = 0; i < dev->ports; i++) {
760 portmask[i] |= vp & ~mask;
763 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
764 priv->vlan_table[j]);
768 * isolate all ports, but connect them to the cpu port */
769 for (i = 0; i < dev->ports; i++) {
770 if (i == AR8216_PORT_CPU)
773 portmask[i] = 1 << AR8216_PORT_CPU;
774 portmask[AR8216_PORT_CPU] |= (1 << i);
778 /* update the port destination mask registers and tag settings */
779 for (i = 0; i < dev->ports; i++) {
784 pvid = priv->vlan_id[priv->pvid[i]];
785 if (priv->vlan_tagged & (1 << i))
786 egress = AR8216_OUT_ADD_VLAN;
788 egress = AR8216_OUT_STRIP_VLAN;
789 ingress = AR8216_IN_SECURE;
792 egress = AR8216_OUT_KEEP;
793 ingress = AR8216_IN_PORT_ONLY;
796 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
799 mutex_unlock(&priv->reg_mutex);
804 ar8216_sw_reset_switch(struct switch_dev *dev)
806 struct ar8216_priv *priv = to_ar8216(dev);
809 mutex_lock(&priv->reg_mutex);
810 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
811 offsetof(struct ar8216_priv, vlan));
813 for (i = 0; i < AR8X16_MAX_VLANS; i++)
814 priv->vlan_id[i] = i;
816 /* Configure all ports */
817 for (i = 0; i < dev->ports; i++)
818 priv->chip->init_port(priv, i);
820 priv->chip->init_globals(priv);
821 mutex_unlock(&priv->reg_mutex);
823 return ar8216_sw_hw_apply(dev);
826 static struct switch_attr ar8216_globals[] = {
828 .type = SWITCH_TYPE_INT,
829 .name = "enable_vlan",
830 .description = "Enable VLAN mode",
831 .set = ar8216_sw_set_vlan,
832 .get = ar8216_sw_get_vlan,
837 static struct switch_attr ar8216_port[] = {
840 static struct switch_attr ar8216_vlan[] = {
842 .type = SWITCH_TYPE_INT,
844 .description = "VLAN ID (0-4094)",
845 .set = ar8216_sw_set_vid,
846 .get = ar8216_sw_get_vid,
851 static const struct switch_dev_ops ar8216_sw_ops = {
853 .attr = ar8216_globals,
854 .n_attr = ARRAY_SIZE(ar8216_globals),
858 .n_attr = ARRAY_SIZE(ar8216_port),
862 .n_attr = ARRAY_SIZE(ar8216_vlan),
864 .get_port_pvid = ar8216_sw_get_pvid,
865 .set_port_pvid = ar8216_sw_set_pvid,
866 .get_vlan_ports = ar8216_sw_get_ports,
867 .set_vlan_ports = ar8216_sw_set_ports,
868 .apply_config = ar8216_sw_hw_apply,
869 .reset_switch = ar8216_sw_reset_switch,
870 .get_port_link = ar8216_sw_get_port_link,
874 ar8216_id_chip(struct ar8216_priv *priv)
880 priv->chip_type = UNKNOWN;
882 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
886 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
887 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
890 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
894 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
901 priv->chip_type = AR8216;
902 priv->chip = &ar8216_chip;
905 priv->chip_type = AR8236;
906 priv->chip = &ar8236_chip;
910 priv->chip_type = AR8316;
911 priv->chip = &ar8316_chip;
915 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
916 (int)(id >> AR8216_CTRL_VERSION_S),
917 (int)(id & AR8216_CTRL_REVISION),
918 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
919 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
928 ar8216_config_init(struct phy_device *pdev)
930 struct ar8216_priv *priv = pdev->priv;
931 struct net_device *dev = pdev->attached_dev;
932 struct switch_dev *swdev;
936 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
943 ret = ar8216_id_chip(priv);
947 if (pdev->addr != 0) {
948 if (ar8xxx_has_gige(priv)) {
949 pdev->supported |= SUPPORTED_1000baseT_Full;
950 pdev->advertising |= ADVERTISED_1000baseT_Full;
953 if (priv->chip_type == AR8316) {
954 /* check if we're attaching to the switch twice */
955 pdev = pdev->bus->phy_map[0];
961 /* switch device has not been initialized, reuse priv */
963 priv->port4_phy = true;
970 /* switch device has been initialized, reinit */
972 priv->dev.ports = (AR8216_NUM_PORTS - 1);
973 priv->initialized = false;
974 priv->port4_phy = true;
975 ar8316_hw_init(priv);
983 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
984 pdev->attached_dev->name, priv->chip_type);
986 if (ar8xxx_has_gige(priv))
987 pdev->supported = SUPPORTED_1000baseT_Full;
989 pdev->supported = SUPPORTED_100baseT_Full;
990 pdev->advertising = pdev->supported;
992 mutex_init(&priv->reg_mutex);
993 priv->read = ar8216_mii_read;
994 priv->write = ar8216_mii_write;
999 swdev->cpu_port = AR8216_PORT_CPU;
1000 swdev->ops = &ar8216_sw_ops;
1001 swdev->ports = AR8216_NUM_PORTS;
1003 if (priv->chip_type == AR8316) {
1004 swdev->name = "Atheros AR8316";
1005 swdev->vlans = AR8X16_MAX_VLANS;
1007 if (priv->port4_phy) {
1008 /* port 5 connected to the other mac, therefore unusable */
1009 swdev->ports = (AR8216_NUM_PORTS - 1);
1011 } else if (priv->chip_type == AR8236) {
1012 swdev->name = "Atheros AR8236";
1013 swdev->vlans = AR8216_NUM_VLANS;
1014 swdev->ports = AR8216_NUM_PORTS;
1016 swdev->name = "Atheros AR8216";
1017 swdev->vlans = AR8216_NUM_VLANS;
1020 ret = register_switch(&priv->dev, pdev->attached_dev);
1026 ret = priv->chip->hw_init(priv);
1030 ret = ar8216_sw_reset_switch(&priv->dev);
1034 dev->phy_ptr = priv;
1036 /* VID fixup only needed on ar8216 */
1037 if (pdev->addr == 0 && priv->chip_type == AR8216) {
1038 pdev->pkt_align = 2;
1039 pdev->netif_receive_skb = ar8216_netif_receive_skb;
1040 pdev->netif_rx = ar8216_netif_rx;
1041 priv->ndo_old = dev->netdev_ops;
1042 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
1043 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
1044 dev->netdev_ops = &priv->ndo;
1057 ar8216_read_status(struct phy_device *phydev)
1059 struct ar8216_priv *priv = phydev->priv;
1060 struct switch_port_link link;
1063 if (phydev->addr != 0)
1064 return genphy_read_status(phydev);
1066 ar8216_read_port_link(priv, phydev->addr, &link);
1067 phydev->link = !!link.link;
1071 switch (link.speed) {
1072 case SWITCH_PORT_SPEED_10:
1073 phydev->speed = SPEED_10;
1075 case SWITCH_PORT_SPEED_100:
1076 phydev->speed = SPEED_100;
1078 case SWITCH_PORT_SPEED_1000:
1079 phydev->speed = SPEED_1000;
1084 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1086 /* flush the address translation unit */
1087 mutex_lock(&priv->reg_mutex);
1088 ret = priv->chip->atu_flush(priv);
1089 mutex_unlock(&priv->reg_mutex);
1091 phydev->state = PHY_RUNNING;
1092 netif_carrier_on(phydev->attached_dev);
1093 phydev->adjust_link(phydev->attached_dev);
1099 ar8216_config_aneg(struct phy_device *phydev)
1101 if (phydev->addr == 0)
1104 return genphy_config_aneg(phydev);
1108 ar8216_probe(struct phy_device *pdev)
1110 struct ar8216_priv priv;
1113 return ar8216_id_chip(&priv);
1117 ar8216_remove(struct phy_device *pdev)
1119 struct ar8216_priv *priv = pdev->priv;
1120 struct net_device *dev = pdev->attached_dev;
1125 if (priv->ndo_old && dev)
1126 dev->netdev_ops = priv->ndo_old;
1127 if (pdev->addr == 0)
1128 unregister_switch(&priv->dev);
1132 static struct phy_driver ar8216_driver = {
1133 .phy_id = 0x004d0000,
1134 .name = "Atheros AR8216/AR8236/AR8316",
1135 .phy_id_mask = 0xffff0000,
1136 .features = PHY_BASIC_FEATURES,
1137 .probe = ar8216_probe,
1138 .remove = ar8216_remove,
1139 .config_init = &ar8216_config_init,
1140 .config_aneg = &ar8216_config_aneg,
1141 .read_status = &ar8216_read_status,
1142 .driver = { .owner = THIS_MODULE },
1148 return phy_driver_register(&ar8216_driver);
1154 phy_driver_unregister(&ar8216_driver);
1157 module_init(ar8216_init);
1158 module_exit(ar8216_exit);
1159 MODULE_LICENSE("GPL");