2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216 = 0x01,
52 AR8XXX_VER_AR8236 = 0x03,
53 AR8XXX_VER_AR8316 = 0x10,
54 AR8XXX_VER_AR8327 = 0x12,
57 struct ar8xxx_mib_desc {
66 int (*hw_init)(struct ar8216_priv *priv);
67 void (*init_globals)(struct ar8216_priv *priv);
68 void (*init_port)(struct ar8216_priv *priv, int port);
69 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
70 u32 ingress, u32 members, u32 pvid);
71 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
72 int (*atu_flush)(struct ar8216_priv *priv);
73 void (*vtu_flush)(struct ar8216_priv *priv);
74 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
76 const struct ar8xxx_mib_desc *mib_decs;
81 struct switch_dev dev;
82 struct phy_device *phy;
83 u32 (*read)(struct ar8216_priv *priv, int reg);
84 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
85 const struct net_device_ops *ndo_old;
86 struct net_device_ops ndo;
87 struct mutex reg_mutex;
90 const struct ar8xxx_chip *chip;
98 struct mutex mib_lock;
99 struct delayed_work mib_work;
103 /* all fields below are cleared on reset */
105 u16 vlan_id[AR8X16_MAX_VLANS];
106 u8 vlan_table[AR8X16_MAX_VLANS];
108 u16 pvid[AR8X16_MAX_PORTS];
111 #define MIB_DESC(_s , _o, _n) \
118 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
119 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
120 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
121 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
122 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
123 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
124 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
125 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
126 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
127 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
128 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
129 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
130 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
131 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
132 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
133 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
134 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
135 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
136 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
137 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
138 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
139 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
140 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
141 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
142 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
143 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
144 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
145 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
146 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
147 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
148 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
149 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
150 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
151 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
152 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
153 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
154 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
155 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
158 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
159 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
160 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
161 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
162 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
163 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
164 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
165 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
166 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
167 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
168 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
169 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
170 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
172 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
173 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
174 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
175 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
176 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
177 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
178 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
179 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
180 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
181 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
182 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
183 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
184 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
185 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
186 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
188 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
189 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
190 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
191 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
192 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
193 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
194 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
195 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
196 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
197 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
200 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
202 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
204 return priv->chip->caps & AR8XXX_CAP_GIGE;
207 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
209 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
212 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
214 return priv->chip_ver == AR8XXX_VER_AR8216;
217 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
219 return priv->chip_ver == AR8XXX_VER_AR8236;
222 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
224 return priv->chip_ver == AR8XXX_VER_AR8316;
227 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
229 return priv->chip_ver == AR8XXX_VER_AR8327;
233 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
236 *r1 = regaddr & 0x1e;
242 *page = regaddr & 0x1ff;
246 ar8216_mii_read(struct ar8216_priv *priv, int reg)
248 struct phy_device *phy = priv->phy;
249 struct mii_bus *bus = phy->bus;
253 split_addr((u32) reg, &r1, &r2, &page);
255 mutex_lock(&bus->mdio_lock);
257 bus->write(bus, 0x18, 0, page);
258 usleep_range(1000, 2000); /* wait for the page switch to propagate */
259 lo = bus->read(bus, 0x10 | r2, r1);
260 hi = bus->read(bus, 0x10 | r2, r1 + 1);
262 mutex_unlock(&bus->mdio_lock);
264 return (hi << 16) | lo;
268 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
270 struct phy_device *phy = priv->phy;
271 struct mii_bus *bus = phy->bus;
275 split_addr((u32) reg, &r1, &r2, &r3);
277 hi = (u16) (val >> 16);
279 mutex_lock(&bus->mdio_lock);
281 bus->write(bus, 0x18, 0, r3);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 if (priv->mii_lo_first) {
284 bus->write(bus, 0x10 | r2, r1, lo);
285 bus->write(bus, 0x10 | r2, r1 + 1, hi);
287 bus->write(bus, 0x10 | r2, r1 + 1, hi);
288 bus->write(bus, 0x10 | r2, r1, lo);
291 mutex_unlock(&bus->mdio_lock);
295 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
296 u16 dbg_addr, u16 dbg_data)
298 struct mii_bus *bus = priv->phy->bus;
300 mutex_lock(&bus->mdio_lock);
301 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
302 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
303 mutex_unlock(&bus->mdio_lock);
307 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
309 struct mii_bus *bus = priv->phy->bus;
311 mutex_lock(&bus->mdio_lock);
312 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
313 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
314 mutex_unlock(&bus->mdio_lock);
318 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
322 lockdep_assert_held(&priv->reg_mutex);
324 v = priv->read(priv, reg);
327 priv->write(priv, reg, v);
333 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
337 lockdep_assert_held(&priv->reg_mutex);
339 v = priv->read(priv, reg);
341 priv->write(priv, reg, v);
345 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
350 for (i = 0; i < timeout; i++) {
353 t = priv->read(priv, reg);
354 if ((t & mask) == val)
357 usleep_range(1000, 2000);
364 ar8216_mib_capture(struct ar8216_priv *priv)
369 lockdep_assert_held(&priv->mib_lock);
371 if (chip_is_ar8327(priv))
372 mib_func = AR8327_REG_MIB_FUNC;
374 mib_func = AR8216_REG_MIB_FUNC;
376 /* Capture the hardware statistics for all ports */
377 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
378 (AR8216_MIB_FUNC_CAPTURE << AR8216_MIB_FUNC_S));
380 /* Wait for the capturing to complete. */
381 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
392 ar8216_mib_flush(struct ar8216_priv *priv)
397 lockdep_assert_held(&priv->mib_lock);
399 if (chip_is_ar8327(priv))
400 mib_func = AR8327_REG_MIB_FUNC;
402 mib_func = AR8216_REG_MIB_FUNC;
404 /* Flush hardware statistics for all ports */
405 ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
406 (AR8216_MIB_FUNC_FLUSH << AR8216_MIB_FUNC_S));
408 /* Wait for the capturing to complete. */
409 ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
420 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
426 lockdep_assert_held(&priv->mib_lock);
428 if (chip_is_ar8327(priv))
429 base = AR8327_REG_PORT_STATS_BASE(port);
430 else if (chip_is_ar8236(priv) ||
431 chip_is_ar8316(priv))
432 base = AR8236_REG_PORT_STATS_BASE(port);
434 base = AR8216_REG_PORT_STATS_BASE(port);
436 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
437 for (i = 0; i < priv->chip->num_mibs; i++) {
438 const struct ar8xxx_mib_desc *mib;
441 mib = &priv->chip->mib_decs[i];
442 t = priv->read(priv, base + mib->offset);
443 if (mib->size == 2) {
446 hi = priv->read(priv, base + mib->offset + 4);
458 ar8216_read_port_link(struct ar8216_priv *priv, int port,
459 struct switch_port_link *link)
464 memset(link, '\0', sizeof(*link));
466 status = priv->chip->read_port_status(priv, port);
468 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
470 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
477 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
478 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
479 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
481 speed = (status & AR8216_PORT_STATUS_SPEED) >>
482 AR8216_PORT_STATUS_SPEED_S;
485 case AR8216_PORT_SPEED_10M:
486 link->speed = SWITCH_PORT_SPEED_10;
488 case AR8216_PORT_SPEED_100M:
489 link->speed = SWITCH_PORT_SPEED_100;
491 case AR8216_PORT_SPEED_1000M:
492 link->speed = SWITCH_PORT_SPEED_1000;
495 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
500 static struct sk_buff *
501 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
503 struct ar8216_priv *priv = dev->phy_ptr;
512 if (unlikely(skb_headroom(skb) < 2)) {
513 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
517 buf = skb_push(skb, 2);
525 dev_kfree_skb_any(skb);
530 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
532 struct ar8216_priv *priv;
540 /* don't strip the header if vlan mode is disabled */
544 /* strip header, get vlan id */
548 /* check for vlan header presence */
549 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
554 /* no need to fix up packets coming from a tagged source */
555 if (priv->vlan_tagged & (1 << port))
558 /* lookup port vid from local table, the switch passes an invalid vlan id */
559 vlan = priv->vlan_id[priv->pvid[port]];
562 buf[14 + 2] |= vlan >> 8;
563 buf[15 + 2] = vlan & 0xff;
567 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
573 t = priv->read(priv, reg);
574 if ((t & mask) == val)
583 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
584 (unsigned int) reg, t, mask, val);
589 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
591 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
593 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
594 val &= AR8216_VTUDATA_MEMBER;
595 val |= AR8216_VTUDATA_VALID;
596 priv->write(priv, AR8216_REG_VTU_DATA, val);
598 op |= AR8216_VTU_ACTIVE;
599 priv->write(priv, AR8216_REG_VTU, op);
603 ar8216_vtu_flush(struct ar8216_priv *priv)
605 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
609 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
613 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
614 ar8216_vtu_op(priv, op, port_mask);
618 ar8216_atu_flush(struct ar8216_priv *priv)
622 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
624 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
630 ar8216_read_port_status(struct ar8216_priv *priv, int port)
632 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
636 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
637 u32 members, u32 pvid)
641 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
642 header = AR8216_PORT_CTRL_HEADER;
646 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
647 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
648 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
649 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
650 AR8216_PORT_CTRL_LEARN | header |
651 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
652 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
654 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
655 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
656 AR8216_PORT_VLAN_DEFAULT_ID,
657 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
658 (ingress << AR8216_PORT_VLAN_MODE_S) |
659 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
663 ar8216_hw_init(struct ar8216_priv *priv)
669 ar8216_init_globals(struct ar8216_priv *priv)
671 /* standard atheros magic */
672 priv->write(priv, 0x38, 0xc000050e);
674 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
675 AR8216_GCTRL_MTU, 1518 + 8 + 2);
679 ar8216_init_port(struct ar8216_priv *priv, int port)
681 /* Enable port learning and tx */
682 priv->write(priv, AR8216_REG_PORT_CTRL(port),
683 AR8216_PORT_CTRL_LEARN |
684 (4 << AR8216_PORT_CTRL_STATE_S));
686 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
688 if (port == AR8216_PORT_CPU) {
689 priv->write(priv, AR8216_REG_PORT_STATUS(port),
690 AR8216_PORT_STATUS_LINK_UP |
691 (ar8xxx_has_gige(priv) ?
692 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
693 AR8216_PORT_STATUS_TXMAC |
694 AR8216_PORT_STATUS_RXMAC |
695 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
696 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
697 AR8216_PORT_STATUS_DUPLEX);
699 priv->write(priv, AR8216_REG_PORT_STATUS(port),
700 AR8216_PORT_STATUS_LINK_AUTO);
704 static const struct ar8xxx_chip ar8216_chip = {
705 .caps = AR8XXX_CAP_MIB_COUNTERS,
707 .hw_init = ar8216_hw_init,
708 .init_globals = ar8216_init_globals,
709 .init_port = ar8216_init_port,
710 .setup_port = ar8216_setup_port,
711 .read_port_status = ar8216_read_port_status,
712 .atu_flush = ar8216_atu_flush,
713 .vtu_flush = ar8216_vtu_flush,
714 .vtu_load_vlan = ar8216_vtu_load_vlan,
716 .num_mibs = ARRAY_SIZE(ar8216_mibs),
717 .mib_decs = ar8216_mibs,
721 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
722 u32 members, u32 pvid)
724 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
725 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
726 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
727 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
728 AR8216_PORT_CTRL_LEARN |
729 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
730 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
732 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
733 AR8236_PORT_VLAN_DEFAULT_ID,
734 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
736 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
737 AR8236_PORT_VLAN2_VLAN_MODE |
738 AR8236_PORT_VLAN2_MEMBER,
739 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
740 (members << AR8236_PORT_VLAN2_MEMBER_S));
744 ar8236_hw_init(struct ar8216_priv *priv)
749 if (priv->initialized)
752 /* Initialize the PHYs */
753 bus = priv->phy->bus;
754 for (i = 0; i < 5; i++) {
755 mdiobus_write(bus, i, MII_ADVERTISE,
756 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
757 ADVERTISE_PAUSE_ASYM);
758 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
762 priv->initialized = true;
767 ar8236_init_globals(struct ar8216_priv *priv)
769 /* enable jumbo frames */
770 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
771 AR8316_GCTRL_MTU, 9018 + 8 + 2);
773 /* Enable MIB counters */
774 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
775 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
779 static const struct ar8xxx_chip ar8236_chip = {
780 .caps = AR8XXX_CAP_MIB_COUNTERS,
781 .hw_init = ar8236_hw_init,
782 .init_globals = ar8236_init_globals,
783 .init_port = ar8216_init_port,
784 .setup_port = ar8236_setup_port,
785 .read_port_status = ar8216_read_port_status,
786 .atu_flush = ar8216_atu_flush,
787 .vtu_flush = ar8216_vtu_flush,
788 .vtu_load_vlan = ar8216_vtu_load_vlan,
790 .num_mibs = ARRAY_SIZE(ar8236_mibs),
791 .mib_decs = ar8236_mibs,
795 ar8316_hw_init(struct ar8216_priv *priv)
801 val = priv->read(priv, 0x8);
803 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
804 if (priv->port4_phy) {
805 /* value taken from Ubiquiti RouterStation Pro */
807 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
810 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
812 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
813 /* value taken from AVM Fritz!Box 7390 sources */
816 /* no known value for phy interface */
817 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
818 priv->phy->interface);
825 priv->write(priv, 0x8, newval);
827 /* Initialize the ports */
828 bus = priv->phy->bus;
829 for (i = 0; i < 5; i++) {
830 if ((i == 4) && priv->port4_phy &&
831 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
832 /* work around for phy4 rgmii mode */
833 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
835 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
837 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
841 /* initialize the port itself */
842 mdiobus_write(bus, i, MII_ADVERTISE,
843 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
844 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
845 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
850 priv->initialized = true;
855 ar8316_init_globals(struct ar8216_priv *priv)
857 /* standard atheros magic */
858 priv->write(priv, 0x38, 0xc000050e);
860 /* enable cpu port to receive multicast and broadcast frames */
861 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
863 /* enable jumbo frames */
864 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
865 AR8316_GCTRL_MTU, 9018 + 8 + 2);
867 /* Enable MIB counters */
868 ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
869 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
873 static const struct ar8xxx_chip ar8316_chip = {
874 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
875 .hw_init = ar8316_hw_init,
876 .init_globals = ar8316_init_globals,
877 .init_port = ar8216_init_port,
878 .setup_port = ar8216_setup_port,
879 .read_port_status = ar8216_read_port_status,
880 .atu_flush = ar8216_atu_flush,
881 .vtu_flush = ar8216_vtu_flush,
882 .vtu_load_vlan = ar8216_vtu_load_vlan,
884 .num_mibs = ARRAY_SIZE(ar8236_mibs),
885 .mib_decs = ar8236_mibs,
889 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
901 case AR8327_PAD_MAC2MAC_MII:
902 t = AR8327_PAD_MAC_MII_EN;
904 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
906 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
909 case AR8327_PAD_MAC2MAC_GMII:
910 t = AR8327_PAD_MAC_GMII_EN;
912 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
914 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
917 case AR8327_PAD_MAC_SGMII:
918 t = AR8327_PAD_SGMII_EN;
921 case AR8327_PAD_MAC2PHY_MII:
922 t = AR8327_PAD_PHY_MII_EN;
924 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
926 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
929 case AR8327_PAD_MAC2PHY_GMII:
930 t = AR8327_PAD_PHY_GMII_EN;
931 if (cfg->pipe_rxclk_sel)
932 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
934 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
936 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
939 case AR8327_PAD_MAC_RGMII:
940 t = AR8327_PAD_RGMII_EN;
941 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
942 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
943 if (cfg->rxclk_delay_en)
944 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
945 if (cfg->txclk_delay_en)
946 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
949 case AR8327_PAD_PHY_GMII:
950 t = AR8327_PAD_PHYX_GMII_EN;
953 case AR8327_PAD_PHY_RGMII:
954 t = AR8327_PAD_PHYX_RGMII_EN;
957 case AR8327_PAD_PHY_MII:
958 t = AR8327_PAD_PHYX_MII_EN;
966 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
968 switch (priv->chip_rev) {
970 /* For 100M waveform */
971 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
972 /* Turn on Gigabit clock */
973 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
977 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
978 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
981 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
982 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
984 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
985 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
986 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
992 ar8327_hw_init(struct ar8216_priv *priv)
994 struct ar8327_platform_data *pdata;
995 struct ar8327_led_cfg *led_cfg;
1001 pdata = priv->phy->dev.platform_data;
1005 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1006 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1007 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1008 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1009 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1010 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1012 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1015 led_cfg = pdata->led_cfg;
1017 if (led_cfg->open_drain)
1018 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1020 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1022 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1023 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1024 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1025 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1028 if (new_pos != pos) {
1029 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1030 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1033 bus = priv->phy->bus;
1034 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1035 ar8327_phy_fixup(priv, i);
1037 /* start aneg on the PHY */
1038 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1039 ADVERTISE_PAUSE_CAP |
1040 ADVERTISE_PAUSE_ASYM);
1041 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1042 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1051 ar8327_init_globals(struct ar8216_priv *priv)
1055 /* enable CPU port and disable mirror port */
1056 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1057 AR8327_FWD_CTRL0_MIRROR_PORT;
1058 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1060 /* forward multicast and broadcast frames to CPU */
1061 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1062 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1063 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1064 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1067 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1068 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1070 /* Enable MIB counters */
1071 ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1072 AR8327_MODULE_EN_MIB);
1076 ar8327_init_cpuport(struct ar8216_priv *priv)
1078 struct ar8327_platform_data *pdata;
1079 struct ar8327_port_cfg *cfg;
1082 pdata = priv->phy->dev.platform_data;
1086 cfg = &pdata->cpuport_cfg;
1087 if (!cfg->force_link) {
1088 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
1089 AR8216_PORT_STATUS_LINK_AUTO);
1093 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1094 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1095 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1096 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1097 switch (cfg->speed) {
1098 case AR8327_PORT_SPEED_10:
1099 t |= AR8216_PORT_SPEED_10M;
1101 case AR8327_PORT_SPEED_100:
1102 t |= AR8216_PORT_SPEED_100M;
1104 case AR8327_PORT_SPEED_1000:
1105 t |= AR8216_PORT_SPEED_1000M;
1109 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
1113 ar8327_init_port(struct ar8216_priv *priv, int port)
1117 if (port == AR8216_PORT_CPU) {
1118 ar8327_init_cpuport(priv);
1120 t = AR8216_PORT_STATUS_LINK_AUTO;
1121 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1124 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1126 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
1128 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1129 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1131 t = AR8327_PORT_LOOKUP_LEARN;
1132 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1133 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1137 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1139 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1143 ar8327_atu_flush(struct ar8216_priv *priv)
1147 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1148 AR8327_ATU_FUNC_BUSY, 0);
1150 priv->write(priv, AR8327_REG_ATU_FUNC,
1151 AR8327_ATU_FUNC_OP_FLUSH);
1157 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1159 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1160 AR8327_VTU_FUNC1_BUSY, 0))
1163 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1164 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1166 op |= AR8327_VTU_FUNC1_BUSY;
1167 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1171 ar8327_vtu_flush(struct ar8216_priv *priv)
1173 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1177 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1183 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1184 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1185 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1188 if ((port_mask & BIT(i)) == 0)
1189 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1190 else if (priv->vlan == 0)
1191 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1192 else if (priv->vlan_tagged & BIT(i))
1193 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1195 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1197 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1199 ar8327_vtu_op(priv, op, val);
1203 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1204 u32 members, u32 pvid)
1209 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1210 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1211 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1213 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1215 case AR8216_OUT_KEEP:
1216 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1218 case AR8216_OUT_STRIP_VLAN:
1219 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1221 case AR8216_OUT_ADD_VLAN:
1222 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1226 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1227 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1228 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1231 t |= AR8327_PORT_LOOKUP_LEARN;
1232 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1233 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1234 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1237 static const struct ar8xxx_chip ar8327_chip = {
1238 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1239 .hw_init = ar8327_hw_init,
1240 .init_globals = ar8327_init_globals,
1241 .init_port = ar8327_init_port,
1242 .setup_port = ar8327_setup_port,
1243 .read_port_status = ar8327_read_port_status,
1244 .atu_flush = ar8327_atu_flush,
1245 .vtu_flush = ar8327_vtu_flush,
1246 .vtu_load_vlan = ar8327_vtu_load_vlan,
1248 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1249 .mib_decs = ar8236_mibs,
1253 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1254 struct switch_val *val)
1256 struct ar8216_priv *priv = to_ar8216(dev);
1257 priv->vlan = !!val->value.i;
1262 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1263 struct switch_val *val)
1265 struct ar8216_priv *priv = to_ar8216(dev);
1266 val->value.i = priv->vlan;
1272 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1274 struct ar8216_priv *priv = to_ar8216(dev);
1276 /* make sure no invalid PVIDs get set */
1278 if (vlan >= dev->vlans)
1281 priv->pvid[port] = vlan;
1286 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1288 struct ar8216_priv *priv = to_ar8216(dev);
1289 *vlan = priv->pvid[port];
1294 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1295 struct switch_val *val)
1297 struct ar8216_priv *priv = to_ar8216(dev);
1298 priv->vlan_id[val->port_vlan] = val->value.i;
1303 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1304 struct switch_val *val)
1306 struct ar8216_priv *priv = to_ar8216(dev);
1307 val->value.i = priv->vlan_id[val->port_vlan];
1312 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1313 struct switch_port_link *link)
1315 struct ar8216_priv *priv = to_ar8216(dev);
1317 ar8216_read_port_link(priv, port, link);
1322 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1324 struct ar8216_priv *priv = to_ar8216(dev);
1325 u8 ports = priv->vlan_table[val->port_vlan];
1329 for (i = 0; i < dev->ports; i++) {
1330 struct switch_port *p;
1332 if (!(ports & (1 << i)))
1335 p = &val->value.ports[val->len++];
1337 if (priv->vlan_tagged & (1 << i))
1338 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1346 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1348 struct ar8216_priv *priv = to_ar8216(dev);
1349 u8 *vt = &priv->vlan_table[val->port_vlan];
1353 for (i = 0; i < val->len; i++) {
1354 struct switch_port *p = &val->value.ports[i];
1356 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1357 priv->vlan_tagged |= (1 << p->id);
1359 priv->vlan_tagged &= ~(1 << p->id);
1360 priv->pvid[p->id] = val->port_vlan;
1362 /* make sure that an untagged port does not
1363 * appear in other vlans */
1364 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1365 if (j == val->port_vlan)
1367 priv->vlan_table[j] &= ~(1 << p->id);
1377 ar8216_sw_hw_apply(struct switch_dev *dev)
1379 struct ar8216_priv *priv = to_ar8216(dev);
1380 u8 portmask[AR8X16_MAX_PORTS];
1383 mutex_lock(&priv->reg_mutex);
1384 /* flush all vlan translation unit entries */
1385 priv->chip->vtu_flush(priv);
1387 memset(portmask, 0, sizeof(portmask));
1389 /* calculate the port destination masks and load vlans
1390 * into the vlan translation unit */
1391 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1392 u8 vp = priv->vlan_table[j];
1397 for (i = 0; i < dev->ports; i++) {
1400 portmask[i] |= vp & ~mask;
1403 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1404 priv->vlan_table[j]);
1408 * isolate all ports, but connect them to the cpu port */
1409 for (i = 0; i < dev->ports; i++) {
1410 if (i == AR8216_PORT_CPU)
1413 portmask[i] = 1 << AR8216_PORT_CPU;
1414 portmask[AR8216_PORT_CPU] |= (1 << i);
1418 /* update the port destination mask registers and tag settings */
1419 for (i = 0; i < dev->ports; i++) {
1420 int egress, ingress;
1424 pvid = priv->vlan_id[priv->pvid[i]];
1425 if (priv->vlan_tagged & (1 << i))
1426 egress = AR8216_OUT_ADD_VLAN;
1428 egress = AR8216_OUT_STRIP_VLAN;
1429 ingress = AR8216_IN_SECURE;
1432 egress = AR8216_OUT_KEEP;
1433 ingress = AR8216_IN_PORT_ONLY;
1436 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1439 mutex_unlock(&priv->reg_mutex);
1444 ar8216_sw_reset_switch(struct switch_dev *dev)
1446 struct ar8216_priv *priv = to_ar8216(dev);
1449 mutex_lock(&priv->reg_mutex);
1450 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1451 offsetof(struct ar8216_priv, vlan));
1453 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1454 priv->vlan_id[i] = i;
1456 /* Configure all ports */
1457 for (i = 0; i < dev->ports; i++)
1458 priv->chip->init_port(priv, i);
1460 priv->chip->init_globals(priv);
1461 mutex_unlock(&priv->reg_mutex);
1463 return ar8216_sw_hw_apply(dev);
1467 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1468 const struct switch_attr *attr,
1469 struct switch_val *val)
1471 struct ar8216_priv *priv = to_ar8216(dev);
1475 if (!ar8xxx_has_mib_counters(priv))
1478 mutex_lock(&priv->mib_lock);
1480 len = priv->dev.ports * priv->chip->num_mibs *
1481 sizeof(*priv->mib_stats);
1482 memset(priv->mib_stats, '\0', len);
1483 ret = ar8216_mib_flush(priv);
1490 mutex_unlock(&priv->mib_lock);
1495 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1496 const struct switch_attr *attr,
1497 struct switch_val *val)
1499 struct ar8216_priv *priv = to_ar8216(dev);
1503 if (!ar8xxx_has_mib_counters(priv))
1506 port = val->port_vlan;
1507 if (port >= dev->ports)
1510 mutex_lock(&priv->mib_lock);
1511 ret = ar8216_mib_capture(priv);
1515 ar8216_mib_fetch_port_stat(priv, port, true);
1520 mutex_unlock(&priv->mib_lock);
1525 ar8216_sw_get_port_mib(struct switch_dev *dev,
1526 const struct switch_attr *attr,
1527 struct switch_val *val)
1529 struct ar8216_priv *priv = to_ar8216(dev);
1530 const struct ar8xxx_chip *chip = priv->chip;
1534 char *buf = priv->buf;
1537 if (!ar8xxx_has_mib_counters(priv))
1540 port = val->port_vlan;
1541 if (port >= dev->ports)
1544 mutex_lock(&priv->mib_lock);
1545 ret = ar8216_mib_capture(priv);
1549 ar8216_mib_fetch_port_stat(priv, port, false);
1550 mutex_unlock(&priv->mib_lock);
1552 len += snprintf(buf + len, sizeof(priv->buf) - len,
1553 "Port %d MIB counters\n",
1556 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1557 for (i = 0; i < chip->num_mibs; i++)
1558 len += snprintf(buf + len, sizeof(priv->buf) - len,
1560 chip->mib_decs[i].name,
1569 mutex_unlock(&priv->mib_lock);
1573 static struct switch_attr ar8216_globals[] = {
1575 .type = SWITCH_TYPE_INT,
1576 .name = "enable_vlan",
1577 .description = "Enable VLAN mode",
1578 .set = ar8216_sw_set_vlan,
1579 .get = ar8216_sw_get_vlan,
1583 .type = SWITCH_TYPE_NOVAL,
1584 .name = "reset_mibs",
1585 .description = "Reset all MIB counters",
1586 .set = ar8216_sw_set_reset_mibs,
1591 static struct switch_attr ar8216_port[] = {
1593 .type = SWITCH_TYPE_NOVAL,
1594 .name = "reset_mib",
1595 .description = "Reset single port MIB counters",
1596 .set = ar8216_sw_set_port_reset_mib,
1599 .type = SWITCH_TYPE_STRING,
1601 .description = "Get port's MIB counters",
1603 .get = ar8216_sw_get_port_mib,
1607 static struct switch_attr ar8216_vlan[] = {
1609 .type = SWITCH_TYPE_INT,
1611 .description = "VLAN ID (0-4094)",
1612 .set = ar8216_sw_set_vid,
1613 .get = ar8216_sw_get_vid,
1618 static const struct switch_dev_ops ar8216_sw_ops = {
1620 .attr = ar8216_globals,
1621 .n_attr = ARRAY_SIZE(ar8216_globals),
1624 .attr = ar8216_port,
1625 .n_attr = ARRAY_SIZE(ar8216_port),
1628 .attr = ar8216_vlan,
1629 .n_attr = ARRAY_SIZE(ar8216_vlan),
1631 .get_port_pvid = ar8216_sw_get_pvid,
1632 .set_port_pvid = ar8216_sw_set_pvid,
1633 .get_vlan_ports = ar8216_sw_get_ports,
1634 .set_vlan_ports = ar8216_sw_set_ports,
1635 .apply_config = ar8216_sw_hw_apply,
1636 .reset_switch = ar8216_sw_reset_switch,
1637 .get_port_link = ar8216_sw_get_port_link,
1641 ar8216_id_chip(struct ar8216_priv *priv)
1647 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1651 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1652 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1655 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1659 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1664 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1665 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1667 switch (priv->chip_ver) {
1668 case AR8XXX_VER_AR8216:
1669 priv->chip = &ar8216_chip;
1671 case AR8XXX_VER_AR8236:
1672 priv->chip = &ar8236_chip;
1674 case AR8XXX_VER_AR8316:
1675 priv->chip = &ar8316_chip;
1677 case AR8XXX_VER_AR8327:
1678 priv->mii_lo_first = true;
1679 priv->chip = &ar8327_chip;
1683 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1684 priv->chip_ver, priv->chip_rev,
1685 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1686 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1695 ar8xxx_mib_work_func(struct work_struct *work)
1697 struct ar8216_priv *priv;
1700 priv = container_of(work, struct ar8216_priv, mib_work.work);
1702 mutex_lock(&priv->mib_lock);
1704 err = ar8216_mib_capture(priv);
1708 ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1711 priv->mib_next_port++;
1712 if (priv->mib_next_port > priv->dev.ports)
1713 priv->mib_next_port = 0;
1715 mutex_unlock(&priv->mib_lock);
1716 schedule_delayed_work(&priv->mib_work,
1717 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1721 ar8xxx_mib_init(struct ar8216_priv *priv)
1725 if (!ar8xxx_has_mib_counters(priv))
1728 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1730 len = priv->dev.ports * priv->chip->num_mibs *
1731 sizeof(*priv->mib_stats);
1732 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1734 if (!priv->mib_stats)
1737 mutex_init(&priv->mib_lock);
1738 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1744 ar8xxx_mib_start(struct ar8216_priv *priv)
1746 if (!ar8xxx_has_mib_counters(priv))
1749 schedule_delayed_work(&priv->mib_work,
1750 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1754 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1756 if (!ar8xxx_has_mib_counters(priv))
1759 cancel_delayed_work(&priv->mib_work);
1760 kfree(priv->mib_stats);
1764 ar8216_config_init(struct phy_device *pdev)
1766 struct ar8216_priv *priv = pdev->priv;
1767 struct net_device *dev = pdev->attached_dev;
1768 struct switch_dev *swdev;
1772 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1779 ret = ar8216_id_chip(priv);
1783 if (pdev->addr != 0) {
1784 if (ar8xxx_has_gige(priv)) {
1785 pdev->supported |= SUPPORTED_1000baseT_Full;
1786 pdev->advertising |= ADVERTISED_1000baseT_Full;
1789 if (chip_is_ar8316(priv)) {
1790 /* check if we're attaching to the switch twice */
1791 pdev = pdev->bus->phy_map[0];
1797 /* switch device has not been initialized, reuse priv */
1799 priv->port4_phy = true;
1806 /* switch device has been initialized, reinit */
1808 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1809 priv->initialized = false;
1810 priv->port4_phy = true;
1811 ar8316_hw_init(priv);
1819 if (ar8xxx_has_gige(priv))
1820 pdev->supported = SUPPORTED_1000baseT_Full;
1822 pdev->supported = SUPPORTED_100baseT_Full;
1823 pdev->advertising = pdev->supported;
1825 mutex_init(&priv->reg_mutex);
1826 priv->read = ar8216_mii_read;
1827 priv->write = ar8216_mii_write;
1832 swdev->cpu_port = AR8216_PORT_CPU;
1833 swdev->ops = &ar8216_sw_ops;
1834 swdev->ports = AR8216_NUM_PORTS;
1836 if (chip_is_ar8316(priv)) {
1837 swdev->name = "Atheros AR8316";
1838 swdev->vlans = AR8X16_MAX_VLANS;
1840 if (priv->port4_phy) {
1841 /* port 5 connected to the other mac, therefore unusable */
1842 swdev->ports = (AR8216_NUM_PORTS - 1);
1844 } else if (chip_is_ar8236(priv)) {
1845 swdev->name = "Atheros AR8236";
1846 swdev->vlans = AR8216_NUM_VLANS;
1847 swdev->ports = AR8216_NUM_PORTS;
1848 } else if (chip_is_ar8327(priv)) {
1849 swdev->name = "Atheros AR8327";
1850 swdev->vlans = AR8X16_MAX_VLANS;
1851 swdev->ports = AR8327_NUM_PORTS;
1853 swdev->name = "Atheros AR8216";
1854 swdev->vlans = AR8216_NUM_VLANS;
1857 ret = ar8xxx_mib_init(priv);
1861 ret = register_switch(&priv->dev, pdev->attached_dev);
1863 goto err_cleanup_mib;
1865 printk(KERN_INFO "%s: %s switch driver attached.\n",
1866 pdev->attached_dev->name, swdev->name);
1870 ret = priv->chip->hw_init(priv);
1872 goto err_cleanup_mib;
1874 ret = ar8216_sw_reset_switch(&priv->dev);
1876 goto err_cleanup_mib;
1878 dev->phy_ptr = priv;
1880 /* VID fixup only needed on ar8216 */
1881 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1882 dev->priv_flags |= IFF_NO_IP_ALIGN;
1883 dev->eth_mangle_rx = ar8216_mangle_rx;
1884 dev->eth_mangle_tx = ar8216_mangle_tx;
1889 ar8xxx_mib_start(priv);
1894 ar8xxx_mib_cleanup(priv);
1901 ar8216_read_status(struct phy_device *phydev)
1903 struct ar8216_priv *priv = phydev->priv;
1904 struct switch_port_link link;
1907 if (phydev->addr != 0)
1908 return genphy_read_status(phydev);
1910 ar8216_read_port_link(priv, phydev->addr, &link);
1911 phydev->link = !!link.link;
1915 switch (link.speed) {
1916 case SWITCH_PORT_SPEED_10:
1917 phydev->speed = SPEED_10;
1919 case SWITCH_PORT_SPEED_100:
1920 phydev->speed = SPEED_100;
1922 case SWITCH_PORT_SPEED_1000:
1923 phydev->speed = SPEED_1000;
1928 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1930 /* flush the address translation unit */
1931 mutex_lock(&priv->reg_mutex);
1932 ret = priv->chip->atu_flush(priv);
1933 mutex_unlock(&priv->reg_mutex);
1935 phydev->state = PHY_RUNNING;
1936 netif_carrier_on(phydev->attached_dev);
1937 phydev->adjust_link(phydev->attached_dev);
1943 ar8216_config_aneg(struct phy_device *phydev)
1945 if (phydev->addr == 0)
1948 return genphy_config_aneg(phydev);
1952 ar8216_probe(struct phy_device *pdev)
1954 struct ar8216_priv *priv;
1957 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1963 ret = ar8216_id_chip(priv);
1970 ar8216_remove(struct phy_device *pdev)
1972 struct ar8216_priv *priv = pdev->priv;
1973 struct net_device *dev = pdev->attached_dev;
1978 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1979 dev->eth_mangle_rx = NULL;
1980 dev->eth_mangle_tx = NULL;
1982 if (pdev->addr == 0)
1983 unregister_switch(&priv->dev);
1985 ar8xxx_mib_cleanup(priv);
1989 static struct phy_driver ar8216_driver = {
1990 .phy_id = 0x004d0000,
1991 .name = "Atheros AR8216/AR8236/AR8316",
1992 .phy_id_mask = 0xffff0000,
1993 .features = PHY_BASIC_FEATURES,
1994 .probe = ar8216_probe,
1995 .remove = ar8216_remove,
1996 .config_init = &ar8216_config_init,
1997 .config_aneg = &ar8216_config_aneg,
1998 .read_status = &ar8216_read_status,
1999 .driver = { .owner = THIS_MODULE },
2005 return phy_driver_register(&ar8216_driver);
2011 phy_driver_unregister(&ar8216_driver);
2014 module_init(ar8216_init);
2015 module_exit(ar8216_exit);
2016 MODULE_LICENSE("GPL");