target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 #define AR8216_MIB_RXB_ID       14      /* RxGoodByte */
  53 #define AR8216_MIB_TXB_ID       29      /* TxByte */
  54
  55 #define AR8236_MIB_RXB_ID       15      /* RxGoodByte */
  56 #define AR8236_MIB_TXB_ID       31      /* TxByte */
  57
  58 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  59         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  60         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  61         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  62         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  63         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  64         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  65         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  66         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  67         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  68         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  69         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  70         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  71         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  72         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  73         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  74         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  75         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  76         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  77         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  78         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  79         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  80         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  81         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  82         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  83         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  84         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  85         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  86         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  87         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  88         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  89         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  90         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  91         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  92         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  93         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  94         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  95         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  96 };
  97
  98 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  99         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 100         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 101         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 102         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 103         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 104         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 105         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 106         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 107         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 108         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 109         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 110         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 111         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 112         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 113         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 114         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 115         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 116         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 117         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 118         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 119         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 120         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 121         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 122         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 123         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 124         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 125         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 126         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 127         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 128         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 129         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 130         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 131         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 132         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 133         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 134         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 135         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 136         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 137         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 138 };
 139
 140 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 141 static LIST_HEAD(ar8xxx_dev_list);
 142
 143 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 144 static int
 145 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 146 {
 147         unsigned int sleep_msecs = 20;
 148         int ret, elapsed, i;
 149
 150         for (elapsed = sleep_msecs; elapsed <= 600;
 151              elapsed += sleep_msecs) {
 152                 msleep(sleep_msecs);
 153                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 154                         ret = mdiobus_read(bus, i, MII_BMCR);
 155                         if (ret < 0)
 156                                 return ret;
 157                         if (ret & BMCR_RESET)
 158                                 break;
 159                         if (i == AR8XXX_NUM_PHYS - 1) {
 160                                 usleep_range(1000, 2000);
 161                                 return 0;
 162                         }
 163                 }
 164         }
 165         return -ETIMEDOUT;
 166 }
 167
 168 static int
 169 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 170 {
 171         int ret;
 172
 173         if (phydev->autoneg != AUTONEG_ENABLE)
 174                 return 0;
 175         /*
 176          * BMCR_ANENABLE might have been cleared
 177          * by phy_init_hw in certain kernel versions
 178          * therefore check for it
 179          */
 180         ret = phy_read(phydev, MII_BMCR);
 181         if (ret < 0)
 182                 return ret;
 183         if (ret & BMCR_ANENABLE)
 184                 return 0;
 185
 186         dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
 187         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 188         return phy_write(phydev, MII_BMCR, ret);
 189 }
 190
 191 void
 192 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 193 {
 194         int i;
 195         struct mii_bus *bus;
 196
 197         bus = priv->mii_bus;
 198         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 199                 if (priv->chip->phy_fixup)
 200                         priv->chip->phy_fixup(priv, i);
 201
 202                 /* initialize the port itself */
 203                 mdiobus_write(bus, i, MII_ADVERTISE,
 204                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 205                 if (ar8xxx_has_gige(priv))
 206                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 207                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 208         }
 209
 210         ar8xxx_phy_poll_reset(bus);
 211 }
 212
 213 u32
 214 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 215 {
 216         struct mii_bus *bus = priv->mii_bus;
 217         u16 lo, hi;
 218
 219         lo = bus->read(bus, phy_id, regnum);
 220         hi = bus->read(bus, phy_id, regnum + 1);
 221
 222         return (hi << 16) | lo;
 223 }
 224
 225 void
 226 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 227 {
 228         struct mii_bus *bus = priv->mii_bus;
 229         u16 lo, hi;
 230
 231         lo = val & 0xffff;
 232         hi = (u16) (val >> 16);
 233
 234         if (priv->chip->mii_lo_first)
 235         {
 236                 bus->write(bus, phy_id, regnum, lo);
 237                 bus->write(bus, phy_id, regnum + 1, hi);
 238         } else {
 239                 bus->write(bus, phy_id, regnum + 1, hi);
 240                 bus->write(bus, phy_id, regnum, lo);
 241         }
 242 }
 243
 244 u32
 245 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 246 {
 247         struct mii_bus *bus = priv->mii_bus;
 248         u16 r1, r2, page;
 249         u32 val;
 250
 251         split_addr((u32) reg, &r1, &r2, &page);
 252
 253         mutex_lock(&bus->mdio_lock);
 254
 255         bus->write(bus, 0x18, 0, page);
 256         wait_for_page_switch();
 257         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 258
 259         mutex_unlock(&bus->mdio_lock);
 260
 261         return val;
 262 }
 263
 264 void
 265 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 266 {
 267         struct mii_bus *bus = priv->mii_bus;
 268         u16 r1, r2, page;
 269
 270         split_addr((u32) reg, &r1, &r2, &page);
 271
 272         mutex_lock(&bus->mdio_lock);
 273
 274         bus->write(bus, 0x18, 0, page);
 275         wait_for_page_switch();
 276         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 277
 278         mutex_unlock(&bus->mdio_lock);
 279 }
 280
 281 u32
 282 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 283 {
 284         struct mii_bus *bus = priv->mii_bus;
 285         u16 r1, r2, page;
 286         u32 ret;
 287
 288         split_addr((u32) reg, &r1, &r2, &page);
 289
 290         mutex_lock(&bus->mdio_lock);
 291
 292         bus->write(bus, 0x18, 0, page);
 293         wait_for_page_switch();
 294
 295         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 296         ret &= ~mask;
 297         ret |= val;
 298         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 299
 300         mutex_unlock(&bus->mdio_lock);
 301
 302         return ret;
 303 }
 304
 305 void
 306 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 307                      u16 dbg_addr, u16 dbg_data)
 308 {
 309         struct mii_bus *bus = priv->mii_bus;
 310
 311         mutex_lock(&bus->mdio_lock);
 312         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 313         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 314         mutex_unlock(&bus->mdio_lock);
 315 }
 316
 317 static inline void
 318 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
 319 {
 320         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 321         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
 322         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
 323 }
 324
 325 void
 326 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
 327 {
 328         struct mii_bus *bus = priv->mii_bus;
 329
 330         mutex_lock(&bus->mdio_lock);
 331         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 332         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 333         mutex_unlock(&bus->mdio_lock);
 334 }
 335
 336 u16
 337 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
 338 {
 339         struct mii_bus *bus = priv->mii_bus;
 340         u16 data;
 341
 342         mutex_lock(&bus->mdio_lock);
 343         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 344         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 345         mutex_unlock(&bus->mdio_lock);
 346
 347         return data;
 348 }
 349
 350 static int
 351 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 352                 unsigned timeout)
 353 {
 354         int i;
 355
 356         for (i = 0; i < timeout; i++) {
 357                 u32 t;
 358
 359                 t = ar8xxx_read(priv, reg);
 360                 if ((t & mask) == val)
 361                         return 0;
 362
 363                 usleep_range(1000, 2000);
 364         }
 365
 366         return -ETIMEDOUT;
 367 }
 368
 369 static int
 370 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 371 {
 372         unsigned mib_func = priv->chip->mib_func;
 373         int ret;
 374
 375         lockdep_assert_held(&priv->mib_lock);
 376
 377         /* Capture the hardware statistics for all ports */
 378         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 379
 380         /* Wait for the capturing to complete. */
 381         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 382         if (ret)
 383                 goto out;
 384
 385         ret = 0;
 386
 387 out:
 388         return ret;
 389 }
 390
 391 static int
 392 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 393 {
 394         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 395 }
 396
 397 static int
 398 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 399 {
 400         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 401 }
 402
 403 static void
 404 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 405 {
 406         unsigned int base;
 407         u64 *mib_stats;
 408         int i;
 409
 410         WARN_ON(port >= priv->dev.ports);
 411
 412         lockdep_assert_held(&priv->mib_lock);
 413
 414         base = priv->chip->reg_port_stats_start +
 415                priv->chip->reg_port_stats_length * port;
 416
 417         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 418         for (i = 0; i < priv->chip->num_mibs; i++) {
 419                 const struct ar8xxx_mib_desc *mib;
 420                 u64 t;
 421
 422                 mib = &priv->chip->mib_decs[i];
 423                 t = ar8xxx_read(priv, base + mib->offset);
 424                 if (mib->size == 2) {
 425                         u64 hi;
 426
 427                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 428                         t |= hi << 32;
 429                 }
 430
 431                 if (flush)
 432                         mib_stats[i] = 0;
 433                 else
 434                         mib_stats[i] += t;
 435         }
 436 }
 437
 438 static void
 439 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 440                       struct switch_port_link *link)
 441 {
 442         u32 status;
 443         u32 speed;
 444
 445         memset(link, '\0', sizeof(*link));
 446
 447         status = priv->chip->read_port_status(priv, port);
 448
 449         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 450         if (link->aneg) {
 451                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 452         } else {
 453                 link->link = true;
 454
 455                 if (priv->get_port_link) {
 456                         int err;
 457
 458                         err = priv->get_port_link(port);
 459                         if (err >= 0)
 460                                 link->link = !!err;
 461                 }
 462         }
 463
 464         if (!link->link)
 465                 return;
 466
 467         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 468         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 469         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 470
 471         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 472                 link->eee = priv->chip->read_port_eee_status(priv, port);
 473
 474         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 475                  AR8216_PORT_STATUS_SPEED_S;
 476
 477         switch (speed) {
 478         case AR8216_PORT_SPEED_10M:
 479                 link->speed = SWITCH_PORT_SPEED_10;
 480                 break;
 481         case AR8216_PORT_SPEED_100M:
 482                 link->speed = SWITCH_PORT_SPEED_100;
 483                 break;
 484         case AR8216_PORT_SPEED_1000M:
 485                 link->speed = SWITCH_PORT_SPEED_1000;
 486                 break;
 487         default:
 488                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 489                 break;
 490         }
 491 }
 492
 493 static struct sk_buff *
 494 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 495 {
 496         struct ar8xxx_priv *priv = dev->phy_ptr;
 497         unsigned char *buf;
 498
 499         if (unlikely(!priv))
 500                 goto error;
 501
 502         if (!priv->vlan)
 503                 goto send;
 504
 505         if (unlikely(skb_headroom(skb) < 2)) {
 506                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 507                         goto error;
 508         }
 509
 510         buf = skb_push(skb, 2);
 511         buf[0] = 0x10;
 512         buf[1] = 0x80;
 513
 514 send:
 515         return skb;
 516
 517 error:
 518         dev_kfree_skb_any(skb);
 519         return NULL;
 520 }
 521
 522 static void
 523 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 524 {
 525         struct ar8xxx_priv *priv;
 526         unsigned char *buf;
 527         int port, vlan;
 528
 529         priv = dev->phy_ptr;
 530         if (!priv)
 531                 return;
 532
 533         /* don't strip the header if vlan mode is disabled */
 534         if (!priv->vlan)
 535                 return;
 536
 537         /* strip header, get vlan id */
 538         buf = skb->data;
 539         skb_pull(skb, 2);
 540
 541         /* check for vlan header presence */
 542         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 543                 return;
 544
 545         port = buf[0] & 0x7;
 546
 547         /* no need to fix up packets coming from a tagged source */
 548         if (priv->vlan_tagged & (1 << port))
 549                 return;
 550
 551         /* lookup port vid from local table, the switch passes an invalid vlan id */
 552         vlan = priv->vlan_id[priv->pvid[port]];
 553
 554         buf[14 + 2] &= 0xf0;
 555         buf[14 + 2] |= vlan >> 8;
 556         buf[15 + 2] = vlan & 0xff;
 557 }
 558
 559 int
 560 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 561 {
 562         int timeout = 20;
 563         u32 t = 0;
 564
 565         while (1) {
 566                 t = ar8xxx_read(priv, reg);
 567                 if ((t & mask) == val)
 568                         return 0;
 569
 570                 if (timeout-- <= 0)
 571                         break;
 572
 573                 udelay(10);
 574         }
 575
 576         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 577                (unsigned int) reg, t, mask, val);
 578         return -ETIMEDOUT;
 579 }
 580
 581 static void
 582 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 583 {
 584         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 585                 return;
 586         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 587                 val &= AR8216_VTUDATA_MEMBER;
 588                 val |= AR8216_VTUDATA_VALID;
 589                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 590         }
 591         op |= AR8216_VTU_ACTIVE;
 592         ar8xxx_write(priv, AR8216_REG_VTU, op);
 593 }
 594
 595 static void
 596 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 597 {
 598         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 599 }
 600
 601 static void
 602 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 603 {
 604         u32 op;
 605
 606         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 607         ar8216_vtu_op(priv, op, port_mask);
 608 }
 609
 610 static int
 611 ar8216_atu_flush(struct ar8xxx_priv *priv)
 612 {
 613         int ret;
 614
 615         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 616         if (!ret)
 617                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 618                                                          AR8216_ATU_ACTIVE);
 619
 620         return ret;
 621 }
 622
 623 static int
 624 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 625 {
 626         u32 t;
 627         int ret;
 628
 629         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 630         if (!ret) {
 631                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 632                 t |= AR8216_ATU_ACTIVE;
 633                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 634         }
 635
 636         return ret;
 637 }
 638
 639 static u32
 640 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 641 {
 642         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 643 }
 644
 645 static void
 646 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 647 {
 648         u32 header;
 649         u32 egress, ingress;
 650         u32 pvid;
 651
 652         if (priv->vlan) {
 653                 pvid = priv->vlan_id[priv->pvid[port]];
 654                 if (priv->vlan_tagged & (1 << port))
 655                         egress = AR8216_OUT_ADD_VLAN;
 656                 else
 657                         egress = AR8216_OUT_STRIP_VLAN;
 658                 ingress = AR8216_IN_SECURE;
 659         } else {
 660                 pvid = port;
 661                 egress = AR8216_OUT_KEEP;
 662                 ingress = AR8216_IN_PORT_ONLY;
 663         }
 664
 665         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 666                 header = AR8216_PORT_CTRL_HEADER;
 667         else
 668                 header = 0;
 669
 670         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 671                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 672                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 673                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 674                    AR8216_PORT_CTRL_LEARN | header |
 675                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 676                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 677
 678         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 679                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 680                    AR8216_PORT_VLAN_DEFAULT_ID,
 681                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 682                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 683                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 684 }
 685
 686 static int
 687 ar8216_hw_init(struct ar8xxx_priv *priv)
 688 {
 689         if (priv->initialized)
 690                 return 0;
 691
 692         ar8xxx_phy_init(priv);
 693
 694         priv->initialized = true;
 695         return 0;
 696 }
 697
 698 static void
 699 ar8216_init_globals(struct ar8xxx_priv *priv)
 700 {
 701         /* standard atheros magic */
 702         ar8xxx_write(priv, 0x38, 0xc000050e);
 703
 704         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 705                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 706 }
 707
 708 static void
 709 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 710 {
 711         /* Enable port learning and tx */
 712         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 713                 AR8216_PORT_CTRL_LEARN |
 714                 (4 << AR8216_PORT_CTRL_STATE_S));
 715
 716         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 717
 718         if (port == AR8216_PORT_CPU) {
 719                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 720                         AR8216_PORT_STATUS_LINK_UP |
 721                         (ar8xxx_has_gige(priv) ?
 722                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 723                         AR8216_PORT_STATUS_TXMAC |
 724                         AR8216_PORT_STATUS_RXMAC |
 725                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 726                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 727                         AR8216_PORT_STATUS_DUPLEX);
 728         } else {
 729                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 730                         AR8216_PORT_STATUS_LINK_AUTO);
 731         }
 732 }
 733
 734 static void
 735 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 736 {
 737         int timeout = 20;
 738
 739         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
 740                 udelay(10);
 741
 742         if (!timeout)
 743                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 744 }
 745
 746 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 747                                  struct arl_entry *a, u32 *status, enum arl_op op)
 748 {
 749         struct mii_bus *bus = priv->mii_bus;
 750         u16 r2, page;
 751         u16 r1_func0, r1_func1, r1_func2;
 752         u32 t, val0, val1, val2;
 753         int i;
 754
 755         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 756         r2 |= 0x10;
 757
 758         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 759         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 760
 761         switch (op) {
 762         case AR8XXX_ARL_INITIALIZE:
 763                 /* all ATU registers are on the same page
 764                 * therefore set page only once
 765                 */
 766                 bus->write(bus, 0x18, 0, page);
 767                 wait_for_page_switch();
 768
 769                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 770
 771                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 772                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 773                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 774                 break;
 775         case AR8XXX_ARL_GET_NEXT:
 776                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 777                 t |= AR8216_ATU_ACTIVE;
 778                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 779                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 780
 781                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 782                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 783                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 784
 785                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 786                 if (!*status)
 787                         break;
 788
 789                 i = 0;
 790                 t = AR8216_ATU_PORT0;
 791                 while (!(val2 & t) && ++i < priv->dev.ports)
 792                         t <<= 1;
 793
 794                 a->port = i;
 795                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 796                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 797                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 798                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 799                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 800                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 801                 break;
 802         }
 803 }
 804
 805 static void
 806 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 807 {
 808         u32 egress, ingress;
 809         u32 pvid;
 810
 811         if (priv->vlan) {
 812                 pvid = priv->vlan_id[priv->pvid[port]];
 813                 if (priv->vlan_tagged & (1 << port))
 814                         egress = AR8216_OUT_ADD_VLAN;
 815                 else
 816                         egress = AR8216_OUT_STRIP_VLAN;
 817                 ingress = AR8216_IN_SECURE;
 818         } else {
 819                 pvid = port;
 820                 egress = AR8216_OUT_KEEP;
 821                 ingress = AR8216_IN_PORT_ONLY;
 822         }
 823
 824         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 825                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 826                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 827                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 828                    AR8216_PORT_CTRL_LEARN |
 829                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 830                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 831
 832         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 833                    AR8236_PORT_VLAN_DEFAULT_ID,
 834                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 835
 836         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 837                    AR8236_PORT_VLAN2_VLAN_MODE |
 838                    AR8236_PORT_VLAN2_MEMBER,
 839                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 840                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 841 }
 842
 843 static void
 844 ar8236_init_globals(struct ar8xxx_priv *priv)
 845 {
 846         /* enable jumbo frames */
 847         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 848                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 849
 850         /* enable cpu port to receive arp frames */
 851         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 852                    AR8236_ATU_CTRL_RES);
 853
 854         /* enable cpu port to receive multicast and broadcast frames */
 855         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 856                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 857
 858         /* Enable MIB counters */
 859         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 860                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 861                    AR8236_MIB_EN);
 862 }
 863
 864 static int
 865 ar8316_hw_init(struct ar8xxx_priv *priv)
 866 {
 867         u32 val, newval;
 868
 869         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 870
 871         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 872                 if (priv->port4_phy) {
 873                         /* value taken from Ubiquiti RouterStation Pro */
 874                         newval = 0x81461bea;
 875                         pr_info("ar8316: Using port 4 as PHY\n");
 876                 } else {
 877                         newval = 0x01261be2;
 878                         pr_info("ar8316: Using port 4 as switch port\n");
 879                 }
 880         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 881                 /* value taken from AVM Fritz!Box 7390 sources */
 882                 newval = 0x010e5b71;
 883         } else {
 884                 /* no known value for phy interface */
 885                 pr_err("ar8316: unsupported mii mode: %d.\n",
 886                        priv->phy->interface);
 887                 return -EINVAL;
 888         }
 889
 890         if (val == newval)
 891                 goto out;
 892
 893         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 894
 895         if (priv->port4_phy &&
 896             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 897                 /* work around for phy4 rgmii mode */
 898                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 899                 /* rx delay */
 900                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 901                 /* tx delay */
 902                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 903                 msleep(1000);
 904         }
 905
 906         ar8xxx_phy_init(priv);
 907
 908 out:
 909         priv->initialized = true;
 910         return 0;
 911 }
 912
 913 static void
 914 ar8316_init_globals(struct ar8xxx_priv *priv)
 915 {
 916         /* standard atheros magic */
 917         ar8xxx_write(priv, 0x38, 0xc000050e);
 918
 919         /* enable cpu port to receive multicast and broadcast frames */
 920         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 921
 922         /* enable jumbo frames */
 923         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 924                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 925
 926         /* Enable MIB counters */
 927         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 928                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 929                    AR8236_MIB_EN);
 930 }
 931
 932 int
 933 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 934                    struct switch_val *val)
 935 {
 936         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 937         priv->vlan = !!val->value.i;
 938         return 0;
 939 }
 940
 941 int
 942 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 943                    struct switch_val *val)
 944 {
 945         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 946         val->value.i = priv->vlan;
 947         return 0;
 948 }
 949
 950
 951 int
 952 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 953 {
 954         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 955
 956         /* make sure no invalid PVIDs get set */
 957
 958         if (vlan < 0 || vlan >= dev->vlans ||
 959             port < 0 || port >= AR8X16_MAX_PORTS)
 960                 return -EINVAL;
 961
 962         priv->pvid[port] = vlan;
 963         return 0;
 964 }
 965
 966 int
 967 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 968 {
 969         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 970
 971         if (port < 0 || port >= AR8X16_MAX_PORTS)
 972                 return -EINVAL;
 973
 974         *vlan = priv->pvid[port];
 975         return 0;
 976 }
 977
 978 static int
 979 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 980                   struct switch_val *val)
 981 {
 982         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 983
 984         if (val->port_vlan >= AR8X16_MAX_VLANS)
 985                 return -EINVAL;
 986
 987         priv->vlan_id[val->port_vlan] = val->value.i;
 988         return 0;
 989 }
 990
 991 static int
 992 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 993                   struct switch_val *val)
 994 {
 995         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 996         val->value.i = priv->vlan_id[val->port_vlan];
 997         return 0;
 998 }
 999
1000 int
1001 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1002                         struct switch_port_link *link)
1003 {
1004         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1005
1006         ar8216_read_port_link(priv, port, link);
1007         return 0;
1008 }
1009
1010 static int
1011 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1012 {
1013         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1014         u8 ports;
1015         int i;
1016
1017         if (val->port_vlan >= AR8X16_MAX_VLANS)
1018                 return -EINVAL;
1019
1020         ports = priv->vlan_table[val->port_vlan];
1021         val->len = 0;
1022         for (i = 0; i < dev->ports; i++) {
1023                 struct switch_port *p;
1024
1025                 if (!(ports & (1 << i)))
1026                         continue;
1027
1028                 p = &val->value.ports[val->len++];
1029                 p->id = i;
1030                 if (priv->vlan_tagged & (1 << i))
1031                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1032                 else
1033                         p->flags = 0;
1034         }
1035         return 0;
1036 }
1037
1038 static int
1039 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1040 {
1041         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1042         u8 *vt = &priv->vlan_table[val->port_vlan];
1043         int i, j;
1044
1045         *vt = 0;
1046         for (i = 0; i < val->len; i++) {
1047                 struct switch_port *p = &val->value.ports[i];
1048
1049                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1050                         priv->vlan_tagged |= (1 << p->id);
1051                 } else {
1052                         priv->vlan_tagged &= ~(1 << p->id);
1053                         priv->pvid[p->id] = val->port_vlan;
1054
1055                         /* make sure that an untagged port does not
1056                          * appear in other vlans */
1057                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1058                                 if (j == val->port_vlan)
1059                                         continue;
1060                                 priv->vlan_table[j] &= ~(1 << p->id);
1061                         }
1062                 }
1063
1064                 *vt |= 1 << p->id;
1065         }
1066         return 0;
1067 }
1068
1069 static void
1070 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1071 {
1072         int port;
1073
1074         /* reset all mirror registers */
1075         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1076                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1077                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1078         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1079                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1080                            AR8216_PORT_CTRL_MIRROR_RX);
1081
1082                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1083                            AR8216_PORT_CTRL_MIRROR_TX);
1084         }
1085
1086         /* now enable mirroring if necessary */
1087         if (priv->source_port >= AR8216_NUM_PORTS ||
1088             priv->monitor_port >= AR8216_NUM_PORTS ||
1089             priv->source_port == priv->monitor_port) {
1090                 return;
1091         }
1092
1093         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1094                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1095                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1096
1097         if (priv->mirror_rx)
1098                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1099                            AR8216_PORT_CTRL_MIRROR_RX);
1100
1101         if (priv->mirror_tx)
1102                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1103                            AR8216_PORT_CTRL_MIRROR_TX);
1104 }
1105
1106 static inline u32
1107 ar8xxx_age_time_val(int age_time)
1108 {
1109         return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1110                AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1111 }
1112
1113 static inline void
1114 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1115 {
1116         u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1117         ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1118 }
1119
1120 int
1121 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1122 {
1123         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1124         const struct ar8xxx_chip *chip = priv->chip;
1125         u8 portmask[AR8X16_MAX_PORTS];
1126         int i, j;
1127
1128         mutex_lock(&priv->reg_mutex);
1129         /* flush all vlan translation unit entries */
1130         priv->chip->vtu_flush(priv);
1131
1132         memset(portmask, 0, sizeof(portmask));
1133         if (!priv->init) {
1134                 /* calculate the port destination masks and load vlans
1135                  * into the vlan translation unit */
1136                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1137                         u8 vp = priv->vlan_table[j];
1138
1139                         if (!vp)
1140                                 continue;
1141
1142                         for (i = 0; i < dev->ports; i++) {
1143                                 u8 mask = (1 << i);
1144                                 if (vp & mask)
1145                                         portmask[i] |= vp & ~mask;
1146                         }
1147
1148                         chip->vtu_load_vlan(priv, priv->vlan_id[j],
1149                                             priv->vlan_table[j]);
1150                 }
1151         } else {
1152                 /* vlan disabled:
1153                  * isolate all ports, but connect them to the cpu port */
1154                 for (i = 0; i < dev->ports; i++) {
1155                         if (i == AR8216_PORT_CPU)
1156                                 continue;
1157
1158                         portmask[i] = 1 << AR8216_PORT_CPU;
1159                         portmask[AR8216_PORT_CPU] |= (1 << i);
1160                 }
1161         }
1162
1163         /* update the port destination mask registers and tag settings */
1164         for (i = 0; i < dev->ports; i++) {
1165                 chip->setup_port(priv, i, portmask[i]);
1166         }
1167
1168         chip->set_mirror_regs(priv);
1169
1170         /* set age time */
1171         if (chip->reg_arl_ctrl)
1172                 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1173
1174         mutex_unlock(&priv->reg_mutex);
1175         return 0;
1176 }
1177
1178 int
1179 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1180 {
1181         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1182         const struct ar8xxx_chip *chip = priv->chip;
1183         int i;
1184
1185         mutex_lock(&priv->reg_mutex);
1186         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1187                 offsetof(struct ar8xxx_priv, vlan));
1188
1189         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1190                 priv->vlan_id[i] = i;
1191
1192         /* Configure all ports */
1193         for (i = 0; i < dev->ports; i++)
1194                 chip->init_port(priv, i);
1195
1196         priv->mirror_rx = false;
1197         priv->mirror_tx = false;
1198         priv->source_port = 0;
1199         priv->monitor_port = 0;
1200         priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1201
1202         chip->init_globals(priv);
1203         chip->atu_flush(priv);
1204
1205         mutex_unlock(&priv->reg_mutex);
1206
1207         return chip->sw_hw_apply(dev);
1208 }
1209
1210 int
1211 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1212                          const struct switch_attr *attr,
1213                          struct switch_val *val)
1214 {
1215         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1216         unsigned int len;
1217         int ret;
1218
1219         if (!ar8xxx_has_mib_counters(priv))
1220                 return -EOPNOTSUPP;
1221
1222         mutex_lock(&priv->mib_lock);
1223
1224         len = priv->dev.ports * priv->chip->num_mibs *
1225               sizeof(*priv->mib_stats);
1226         memset(priv->mib_stats, '\0', len);
1227         ret = ar8xxx_mib_flush(priv);
1228         if (ret)
1229                 goto unlock;
1230
1231         ret = 0;
1232
1233 unlock:
1234         mutex_unlock(&priv->mib_lock);
1235         return ret;
1236 }
1237
1238 int
1239 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1240                                const struct switch_attr *attr,
1241                                struct switch_val *val)
1242 {
1243         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1244
1245         mutex_lock(&priv->reg_mutex);
1246         priv->mirror_rx = !!val->value.i;
1247         priv->chip->set_mirror_regs(priv);
1248         mutex_unlock(&priv->reg_mutex);
1249
1250         return 0;
1251 }
1252
1253 int
1254 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1255                                const struct switch_attr *attr,
1256                                struct switch_val *val)
1257 {
1258         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1259         val->value.i = priv->mirror_rx;
1260         return 0;
1261 }
1262
1263 int
1264 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1265                                const struct switch_attr *attr,
1266                                struct switch_val *val)
1267 {
1268         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1269
1270         mutex_lock(&priv->reg_mutex);
1271         priv->mirror_tx = !!val->value.i;
1272         priv->chip->set_mirror_regs(priv);
1273         mutex_unlock(&priv->reg_mutex);
1274
1275         return 0;
1276 }
1277
1278 int
1279 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1280                                const struct switch_attr *attr,
1281                                struct switch_val *val)
1282 {
1283         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1284         val->value.i = priv->mirror_tx;
1285         return 0;
1286 }
1287
1288 int
1289 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1290                                   const struct switch_attr *attr,
1291                                   struct switch_val *val)
1292 {
1293         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1294
1295         mutex_lock(&priv->reg_mutex);
1296         priv->monitor_port = val->value.i;
1297         priv->chip->set_mirror_regs(priv);
1298         mutex_unlock(&priv->reg_mutex);
1299
1300         return 0;
1301 }
1302
1303 int
1304 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1305                                   const struct switch_attr *attr,
1306                                   struct switch_val *val)
1307 {
1308         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1309         val->value.i = priv->monitor_port;
1310         return 0;
1311 }
1312
1313 int
1314 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1315                                  const struct switch_attr *attr,
1316                                  struct switch_val *val)
1317 {
1318         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1319
1320         mutex_lock(&priv->reg_mutex);
1321         priv->source_port = val->value.i;
1322         priv->chip->set_mirror_regs(priv);
1323         mutex_unlock(&priv->reg_mutex);
1324
1325         return 0;
1326 }
1327
1328 int
1329 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1330                                  const struct switch_attr *attr,
1331                                  struct switch_val *val)
1332 {
1333         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1334         val->value.i = priv->source_port;
1335         return 0;
1336 }
1337
1338 int
1339 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1340                              const struct switch_attr *attr,
1341                              struct switch_val *val)
1342 {
1343         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1344         int port;
1345         int ret;
1346
1347         if (!ar8xxx_has_mib_counters(priv))
1348                 return -EOPNOTSUPP;
1349
1350         port = val->port_vlan;
1351         if (port >= dev->ports)
1352                 return -EINVAL;
1353
1354         mutex_lock(&priv->mib_lock);
1355         ret = ar8xxx_mib_capture(priv);
1356         if (ret)
1357                 goto unlock;
1358
1359         ar8xxx_mib_fetch_port_stat(priv, port, true);
1360
1361         ret = 0;
1362
1363 unlock:
1364         mutex_unlock(&priv->mib_lock);
1365         return ret;
1366 }
1367
1368 static void
1369 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1370 {
1371         unsigned long b;
1372         const char *unit;
1373
1374         if (byte >= 0x40000000) { /* 1 GiB */
1375                 b = byte * 10 / 0x40000000;
1376                 unit = "GiB";
1377         } else if (byte >= 0x100000) { /* 1 MiB */
1378                 b = byte * 10 / 0x100000;
1379                 unit = "MiB";
1380         } else if (byte >= 0x400) { /* 1 KiB */
1381                 b = byte * 10 / 0x400;
1382                 unit = "KiB";
1383         } else {
1384                 b = byte;
1385                 unit = "Byte";
1386         }
1387         if (strcmp(unit, "Byte"))
1388                 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1389         else
1390                 snprintf(buf, len, "%lu %s", b, unit);
1391 }
1392
1393 int
1394 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1395                        const struct switch_attr *attr,
1396                        struct switch_val *val)
1397 {
1398         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1399         const struct ar8xxx_chip *chip = priv->chip;
1400         u64 *mib_stats, mib_data;
1401         unsigned int port;
1402         int ret;
1403         char *buf = priv->buf;
1404         char buf1[64];
1405         const char *mib_name;
1406         int i, len = 0;
1407         bool mib_stats_empty = true;
1408
1409         if (!ar8xxx_has_mib_counters(priv))
1410                 return -EOPNOTSUPP;
1411
1412         port = val->port_vlan;
1413         if (port >= dev->ports)
1414                 return -EINVAL;
1415
1416         mutex_lock(&priv->mib_lock);
1417         ret = ar8xxx_mib_capture(priv);
1418         if (ret)
1419                 goto unlock;
1420
1421         ar8xxx_mib_fetch_port_stat(priv, port, false);
1422
1423         len += snprintf(buf + len, sizeof(priv->buf) - len,
1424                         "MIB counters\n");
1425
1426         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1427         for (i = 0; i < chip->num_mibs; i++) {
1428                 mib_name = chip->mib_decs[i].name;
1429                 mib_data = mib_stats[i];
1430                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1431                                 "%-12s: %llu\n", mib_name, mib_data);
1432                 if ((!strcmp(mib_name, "TxByte") ||
1433                     !strcmp(mib_name, "RxGoodByte")) &&
1434                     mib_data >= 1024) {
1435                         ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1436                         --len; /* discard newline at the end of buf */
1437                         len += snprintf(buf + len, sizeof(priv->buf) - len,
1438                                         " (%s)\n", buf1);
1439                 }
1440                 if (mib_stats_empty && mib_data)
1441                         mib_stats_empty = false;
1442         }
1443
1444         if (mib_stats_empty)
1445                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1446
1447         val->value.s = buf;
1448         val->len = len;
1449
1450         ret = 0;
1451
1452 unlock:
1453         mutex_unlock(&priv->mib_lock);
1454         return ret;
1455 }
1456
1457 int
1458 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1459                            struct switch_val *val)
1460 {
1461         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1462         int age_time = val->value.i;
1463         u32 age_time_val;
1464
1465         if (age_time < 0)
1466                 return -EINVAL;
1467
1468         age_time_val = ar8xxx_age_time_val(age_time);
1469         if (age_time_val == 0 || age_time_val > 0xffff)
1470                 return -EINVAL;
1471
1472         priv->arl_age_time = age_time;
1473         return 0;
1474 }
1475
1476 int
1477 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1478                    struct switch_val *val)
1479 {
1480         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1481         val->value.i = priv->arl_age_time;
1482         return 0;
1483 }
1484
1485 int
1486 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1487                         const struct switch_attr *attr,
1488                         struct switch_val *val)
1489 {
1490         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1491         struct mii_bus *bus = priv->mii_bus;
1492         const struct ar8xxx_chip *chip = priv->chip;
1493         char *buf = priv->arl_buf;
1494         int i, j, k, len = 0;
1495         struct arl_entry *a, *a1;
1496         u32 status;
1497
1498         if (!chip->get_arl_entry)
1499                 return -EOPNOTSUPP;
1500
1501         mutex_lock(&priv->reg_mutex);
1502         mutex_lock(&bus->mdio_lock);
1503
1504         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1505
1506         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1507                 a = &priv->arl_table[i];
1508                 duplicate:
1509                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1510
1511                 if (!status)
1512                         break;
1513
1514                 /* avoid duplicates
1515                  * ARL table can include multiple valid entries
1516                  * per MAC, just with differing status codes
1517                  */
1518                 for (j = 0; j < i; ++j) {
1519                         a1 = &priv->arl_table[j];
1520                         if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1521                                 goto duplicate;
1522                 }
1523         }
1524
1525         mutex_unlock(&bus->mdio_lock);
1526
1527         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1528                         "address resolution table\n");
1529
1530         if (i == AR8XXX_NUM_ARL_RECORDS)
1531                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1532                                 "Too many entries found, displaying the first %d only!\n",
1533                                 AR8XXX_NUM_ARL_RECORDS);
1534
1535         for (j = 0; j < priv->dev.ports; ++j) {
1536                 for (k = 0; k < i; ++k) {
1537                         a = &priv->arl_table[k];
1538                         if (a->port != j)
1539                                 continue;
1540                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1541                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1542                                         j,
1543                                         a->mac[5], a->mac[4], a->mac[3],
1544                                         a->mac[2], a->mac[1], a->mac[0]);
1545                 }
1546         }
1547
1548         val->value.s = buf;
1549         val->len = len;
1550
1551         mutex_unlock(&priv->reg_mutex);
1552
1553         return 0;
1554 }
1555
1556 int
1557 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1558                               const struct switch_attr *attr,
1559                               struct switch_val *val)
1560 {
1561         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1562         int ret;
1563
1564         mutex_lock(&priv->reg_mutex);
1565         ret = priv->chip->atu_flush(priv);
1566         mutex_unlock(&priv->reg_mutex);
1567
1568         return ret;
1569 }
1570
1571 int
1572 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1573                                    const struct switch_attr *attr,
1574                                    struct switch_val *val)
1575 {
1576         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1577         int port, ret;
1578
1579         port = val->port_vlan;
1580         if (port >= dev->ports)
1581                 return -EINVAL;
1582
1583         mutex_lock(&priv->reg_mutex);
1584         ret = priv->chip->atu_flush_port(priv, port);
1585         mutex_unlock(&priv->reg_mutex);
1586
1587         return ret;
1588 }
1589
1590 int
1591 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1592                         struct switch_port_stats *stats)
1593 {
1594         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1595         u64 *mib_stats;
1596         int ret;
1597         int mib_txb_id, mib_rxb_id;
1598
1599         if (!ar8xxx_has_mib_counters(priv))
1600                 return -EOPNOTSUPP;
1601
1602         if (port >= dev->ports)
1603                 return -EINVAL;
1604
1605         switch (priv->chip_ver) {
1606                 case AR8XXX_VER_AR8216:
1607                         mib_txb_id = AR8216_MIB_TXB_ID;
1608                         mib_rxb_id = AR8216_MIB_RXB_ID;
1609                         break;
1610                 case AR8XXX_VER_AR8236:
1611                 case AR8XXX_VER_AR8316:
1612                 case AR8XXX_VER_AR8327:
1613                 case AR8XXX_VER_AR8337:
1614                         mib_txb_id = AR8236_MIB_TXB_ID;
1615                         mib_rxb_id = AR8236_MIB_RXB_ID;
1616                         break;
1617                 default:
1618                         return -EOPNOTSUPP;
1619         }
1620
1621         mutex_lock(&priv->mib_lock);
1622         ret = ar8xxx_mib_capture(priv);
1623         if (ret)
1624                 goto unlock;
1625
1626         ar8xxx_mib_fetch_port_stat(priv, port, false);
1627
1628         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1629
1630         stats->tx_bytes = mib_stats[mib_txb_id];
1631         stats->rx_bytes = mib_stats[mib_rxb_id];
1632
1633         ret = 0;
1634
1635 unlock:
1636         mutex_unlock(&priv->mib_lock);
1637         return ret;
1638 }
1639
1640 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1641         {
1642                 .type = SWITCH_TYPE_INT,
1643                 .name = "enable_vlan",
1644                 .description = "Enable VLAN mode",
1645                 .set = ar8xxx_sw_set_vlan,
1646                 .get = ar8xxx_sw_get_vlan,
1647                 .max = 1
1648         },
1649         {
1650                 .type = SWITCH_TYPE_NOVAL,
1651                 .name = "reset_mibs",
1652                 .description = "Reset all MIB counters",
1653                 .set = ar8xxx_sw_set_reset_mibs,
1654         },
1655         {
1656                 .type = SWITCH_TYPE_INT,
1657                 .name = "enable_mirror_rx",
1658                 .description = "Enable mirroring of RX packets",
1659                 .set = ar8xxx_sw_set_mirror_rx_enable,
1660                 .get = ar8xxx_sw_get_mirror_rx_enable,
1661                 .max = 1
1662         },
1663         {
1664                 .type = SWITCH_TYPE_INT,
1665                 .name = "enable_mirror_tx",
1666                 .description = "Enable mirroring of TX packets",
1667                 .set = ar8xxx_sw_set_mirror_tx_enable,
1668                 .get = ar8xxx_sw_get_mirror_tx_enable,
1669                 .max = 1
1670         },
1671         {
1672                 .type = SWITCH_TYPE_INT,
1673                 .name = "mirror_monitor_port",
1674                 .description = "Mirror monitor port",
1675                 .set = ar8xxx_sw_set_mirror_monitor_port,
1676                 .get = ar8xxx_sw_get_mirror_monitor_port,
1677                 .max = AR8216_NUM_PORTS - 1
1678         },
1679         {
1680                 .type = SWITCH_TYPE_INT,
1681                 .name = "mirror_source_port",
1682                 .description = "Mirror source port",
1683                 .set = ar8xxx_sw_set_mirror_source_port,
1684                 .get = ar8xxx_sw_get_mirror_source_port,
1685                 .max = AR8216_NUM_PORTS - 1
1686         },
1687         {
1688                 .type = SWITCH_TYPE_STRING,
1689                 .name = "arl_table",
1690                 .description = "Get ARL table",
1691                 .set = NULL,
1692                 .get = ar8xxx_sw_get_arl_table,
1693         },
1694         {
1695                 .type = SWITCH_TYPE_NOVAL,
1696                 .name = "flush_arl_table",
1697                 .description = "Flush ARL table",
1698                 .set = ar8xxx_sw_set_flush_arl_table,
1699         },
1700 };
1701
1702 const struct switch_attr ar8xxx_sw_attr_port[] = {
1703         {
1704                 .type = SWITCH_TYPE_NOVAL,
1705                 .name = "reset_mib",
1706                 .description = "Reset single port MIB counters",
1707                 .set = ar8xxx_sw_set_port_reset_mib,
1708         },
1709         {
1710                 .type = SWITCH_TYPE_STRING,
1711                 .name = "mib",
1712                 .description = "Get port's MIB counters",
1713                 .set = NULL,
1714                 .get = ar8xxx_sw_get_port_mib,
1715         },
1716         {
1717                 .type = SWITCH_TYPE_NOVAL,
1718                 .name = "flush_arl_table",
1719                 .description = "Flush port's ARL table entries",
1720                 .set = ar8xxx_sw_set_flush_port_arl_table,
1721         },
1722 };
1723
1724 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1725         {
1726                 .type = SWITCH_TYPE_INT,
1727                 .name = "vid",
1728                 .description = "VLAN ID (0-4094)",
1729                 .set = ar8xxx_sw_set_vid,
1730                 .get = ar8xxx_sw_get_vid,
1731                 .max = 4094,
1732         },
1733 };
1734
1735 static const struct switch_dev_ops ar8xxx_sw_ops = {
1736         .attr_global = {
1737                 .attr = ar8xxx_sw_attr_globals,
1738                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1739         },
1740         .attr_port = {
1741                 .attr = ar8xxx_sw_attr_port,
1742                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1743         },
1744         .attr_vlan = {
1745                 .attr = ar8xxx_sw_attr_vlan,
1746                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1747         },
1748         .get_port_pvid = ar8xxx_sw_get_pvid,
1749         .set_port_pvid = ar8xxx_sw_set_pvid,
1750         .get_vlan_ports = ar8xxx_sw_get_ports,
1751         .set_vlan_ports = ar8xxx_sw_set_ports,
1752         .apply_config = ar8xxx_sw_hw_apply,
1753         .reset_switch = ar8xxx_sw_reset_switch,
1754         .get_port_link = ar8xxx_sw_get_port_link,
1755         .get_port_stats = ar8xxx_sw_get_port_stats,
1756 };
1757
1758 static const struct ar8xxx_chip ar8216_chip = {
1759         .caps = AR8XXX_CAP_MIB_COUNTERS,
1760
1761         .reg_port_stats_start = 0x19000,
1762         .reg_port_stats_length = 0xa0,
1763         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1764
1765         .name = "Atheros AR8216",
1766         .ports = AR8216_NUM_PORTS,
1767         .vlans = AR8216_NUM_VLANS,
1768         .swops = &ar8xxx_sw_ops,
1769
1770         .hw_init = ar8216_hw_init,
1771         .init_globals = ar8216_init_globals,
1772         .init_port = ar8216_init_port,
1773         .setup_port = ar8216_setup_port,
1774         .read_port_status = ar8216_read_port_status,
1775         .atu_flush = ar8216_atu_flush,
1776         .atu_flush_port = ar8216_atu_flush_port,
1777         .vtu_flush = ar8216_vtu_flush,
1778         .vtu_load_vlan = ar8216_vtu_load_vlan,
1779         .set_mirror_regs = ar8216_set_mirror_regs,
1780         .get_arl_entry = ar8216_get_arl_entry,
1781         .sw_hw_apply = ar8xxx_sw_hw_apply,
1782
1783         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1784         .mib_decs = ar8216_mibs,
1785         .mib_func = AR8216_REG_MIB_FUNC
1786 };
1787
1788 static const struct ar8xxx_chip ar8236_chip = {
1789         .caps = AR8XXX_CAP_MIB_COUNTERS,
1790
1791         .reg_port_stats_start = 0x20000,
1792         .reg_port_stats_length = 0x100,
1793         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1794
1795         .name = "Atheros AR8236",
1796         .ports = AR8216_NUM_PORTS,
1797         .vlans = AR8216_NUM_VLANS,
1798         .swops = &ar8xxx_sw_ops,
1799
1800         .hw_init = ar8216_hw_init,
1801         .init_globals = ar8236_init_globals,
1802         .init_port = ar8216_init_port,
1803         .setup_port = ar8236_setup_port,
1804         .read_port_status = ar8216_read_port_status,
1805         .atu_flush = ar8216_atu_flush,
1806         .atu_flush_port = ar8216_atu_flush_port,
1807         .vtu_flush = ar8216_vtu_flush,
1808         .vtu_load_vlan = ar8216_vtu_load_vlan,
1809         .set_mirror_regs = ar8216_set_mirror_regs,
1810         .get_arl_entry = ar8216_get_arl_entry,
1811         .sw_hw_apply = ar8xxx_sw_hw_apply,
1812
1813         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1814         .mib_decs = ar8236_mibs,
1815         .mib_func = AR8216_REG_MIB_FUNC
1816 };
1817
1818 static const struct ar8xxx_chip ar8316_chip = {
1819         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1820
1821         .reg_port_stats_start = 0x20000,
1822         .reg_port_stats_length = 0x100,
1823         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1824
1825         .name = "Atheros AR8316",
1826         .ports = AR8216_NUM_PORTS,
1827         .vlans = AR8X16_MAX_VLANS,
1828         .swops = &ar8xxx_sw_ops,
1829
1830         .hw_init = ar8316_hw_init,
1831         .init_globals = ar8316_init_globals,
1832         .init_port = ar8216_init_port,
1833         .setup_port = ar8216_setup_port,
1834         .read_port_status = ar8216_read_port_status,
1835         .atu_flush = ar8216_atu_flush,
1836         .atu_flush_port = ar8216_atu_flush_port,
1837         .vtu_flush = ar8216_vtu_flush,
1838         .vtu_load_vlan = ar8216_vtu_load_vlan,
1839         .set_mirror_regs = ar8216_set_mirror_regs,
1840         .get_arl_entry = ar8216_get_arl_entry,
1841         .sw_hw_apply = ar8xxx_sw_hw_apply,
1842
1843         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1844         .mib_decs = ar8236_mibs,
1845         .mib_func = AR8216_REG_MIB_FUNC
1846 };
1847
1848 static int
1849 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1850 {
1851         u32 val;
1852         u16 id;
1853         int i;
1854
1855         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1856         if (val == ~0)
1857                 return -ENODEV;
1858
1859         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1860         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1861                 u16 t;
1862
1863                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1864                 if (val == ~0)
1865                         return -ENODEV;
1866
1867                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1868                 if (t != id)
1869                         return -ENODEV;
1870         }
1871
1872         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1873         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1874
1875         switch (priv->chip_ver) {
1876         case AR8XXX_VER_AR8216:
1877                 priv->chip = &ar8216_chip;
1878                 break;
1879         case AR8XXX_VER_AR8236:
1880                 priv->chip = &ar8236_chip;
1881                 break;
1882         case AR8XXX_VER_AR8316:
1883                 priv->chip = &ar8316_chip;
1884                 break;
1885         case AR8XXX_VER_AR8327:
1886                 priv->chip = &ar8327_chip;
1887                 break;
1888         case AR8XXX_VER_AR8337:
1889                 priv->chip = &ar8337_chip;
1890                 break;
1891         default:
1892                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1893                        priv->chip_ver, priv->chip_rev);
1894
1895                 return -ENODEV;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static void
1902 ar8xxx_mib_work_func(struct work_struct *work)
1903 {
1904         struct ar8xxx_priv *priv;
1905         int err;
1906
1907         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1908
1909         mutex_lock(&priv->mib_lock);
1910
1911         err = ar8xxx_mib_capture(priv);
1912         if (err)
1913                 goto next_port;
1914
1915         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1916
1917 next_port:
1918         priv->mib_next_port++;
1919         if (priv->mib_next_port >= priv->dev.ports)
1920                 priv->mib_next_port = 0;
1921
1922         mutex_unlock(&priv->mib_lock);
1923         schedule_delayed_work(&priv->mib_work,
1924                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1925 }
1926
1927 static int
1928 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1929 {
1930         unsigned int len;
1931
1932         if (!ar8xxx_has_mib_counters(priv))
1933                 return 0;
1934
1935         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1936
1937         len = priv->dev.ports * priv->chip->num_mibs *
1938               sizeof(*priv->mib_stats);
1939         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1940
1941         if (!priv->mib_stats)
1942                 return -ENOMEM;
1943
1944         return 0;
1945 }
1946
1947 static void
1948 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1949 {
1950         if (!ar8xxx_has_mib_counters(priv))
1951                 return;
1952
1953         schedule_delayed_work(&priv->mib_work,
1954                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1955 }
1956
1957 static void
1958 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1959 {
1960         if (!ar8xxx_has_mib_counters(priv))
1961                 return;
1962
1963         cancel_delayed_work_sync(&priv->mib_work);
1964 }
1965
1966 static struct ar8xxx_priv *
1967 ar8xxx_create(void)
1968 {
1969         struct ar8xxx_priv *priv;
1970
1971         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1972         if (priv == NULL)
1973                 return NULL;
1974
1975         mutex_init(&priv->reg_mutex);
1976         mutex_init(&priv->mib_lock);
1977         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1978
1979         return priv;
1980 }
1981
1982 static void
1983 ar8xxx_free(struct ar8xxx_priv *priv)
1984 {
1985         if (priv->chip && priv->chip->cleanup)
1986                 priv->chip->cleanup(priv);
1987
1988         kfree(priv->chip_data);
1989         kfree(priv->mib_stats);
1990         kfree(priv);
1991 }
1992
1993 static int
1994 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1995 {
1996         const struct ar8xxx_chip *chip;
1997         struct switch_dev *swdev;
1998         int ret;
1999
2000         ret = ar8xxx_id_chip(priv);
2001         if (ret)
2002                 return ret;
2003
2004         chip = priv->chip;
2005
2006         swdev = &priv->dev;
2007         swdev->cpu_port = AR8216_PORT_CPU;
2008         swdev->name = chip->name;
2009         swdev->vlans = chip->vlans;
2010         swdev->ports = chip->ports;
2011         swdev->ops = chip->swops;
2012
2013         ret = ar8xxx_mib_init(priv);
2014         if (ret)
2015                 return ret;
2016
2017         return 0;
2018 }
2019
2020 static int
2021 ar8xxx_start(struct ar8xxx_priv *priv)
2022 {
2023         int ret;
2024
2025         priv->init = true;
2026
2027         ret = priv->chip->hw_init(priv);
2028         if (ret)
2029                 return ret;
2030
2031         ret = ar8xxx_sw_reset_switch(&priv->dev);
2032         if (ret)
2033                 return ret;
2034
2035         priv->init = false;
2036
2037         ar8xxx_mib_start(priv);
2038
2039         return 0;
2040 }
2041
2042 static int
2043 ar8xxx_phy_config_init(struct phy_device *phydev)
2044 {
2045         struct ar8xxx_priv *priv = phydev->priv;
2046         struct net_device *dev = phydev->attached_dev;
2047         int ret;
2048
2049         if (WARN_ON(!priv))
2050                 return -ENODEV;
2051
2052         if (priv->chip->config_at_probe)
2053                 return ar8xxx_phy_check_aneg(phydev);
2054
2055         priv->phy = phydev;
2056
2057         if (phydev->mdio.addr != 0) {
2058                 if (chip_is_ar8316(priv)) {
2059                         /* switch device has been initialized, reinit */
2060                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2061                         priv->initialized = false;
2062                         priv->port4_phy = true;
2063                         ar8316_hw_init(priv);
2064                         return 0;
2065                 }
2066
2067                 return 0;
2068         }
2069
2070         ret = ar8xxx_start(priv);
2071         if (ret)
2072                 return ret;
2073
2074         /* VID fixup only needed on ar8216 */
2075         if (chip_is_ar8216(priv)) {
2076                 dev->phy_ptr = priv;
2077                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2078                 dev->eth_mangle_rx = ar8216_mangle_rx;
2079                 dev->eth_mangle_tx = ar8216_mangle_tx;
2080         }
2081
2082         return 0;
2083 }
2084
2085 static bool
2086 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2087 {
2088         bool link_new, changed = false;
2089         u32 status;
2090         int i;
2091
2092         mutex_lock(&priv->reg_mutex);
2093
2094         for (i = 0; i < priv->dev.ports; i++) {
2095                 status = priv->chip->read_port_status(priv, i);
2096                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2097                 if (link_new == priv->link_up[i])
2098                         continue;
2099
2100                 priv->link_up[i] = link_new;
2101                 changed = true;
2102                 /* flush ARL entries for this port if it went down*/
2103                 if (!link_new)
2104                         priv->chip->atu_flush_port(priv, i);
2105                 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2106                          i, link_new ? "up" : "down");
2107         }
2108
2109         mutex_unlock(&priv->reg_mutex);
2110
2111         return changed;
2112 }
2113
2114 static int
2115 ar8xxx_phy_read_status(struct phy_device *phydev)
2116 {
2117         struct ar8xxx_priv *priv = phydev->priv;
2118         struct switch_port_link link;
2119
2120         /* check for switch port link changes */
2121         if (phydev->state == PHY_CHANGELINK)
2122                 ar8xxx_check_link_states(priv);
2123
2124         if (phydev->mdio.addr != 0)
2125                 return genphy_read_status(phydev);
2126
2127         ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2128         phydev->link = !!link.link;
2129         if (!phydev->link)
2130                 return 0;
2131
2132         switch (link.speed) {
2133         case SWITCH_PORT_SPEED_10:
2134                 phydev->speed = SPEED_10;
2135                 break;
2136         case SWITCH_PORT_SPEED_100:
2137                 phydev->speed = SPEED_100;
2138                 break;
2139         case SWITCH_PORT_SPEED_1000:
2140                 phydev->speed = SPEED_1000;
2141                 break;
2142         default:
2143                 phydev->speed = 0;
2144         }
2145         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2146
2147         phydev->state = PHY_RUNNING;
2148         netif_carrier_on(phydev->attached_dev);
2149         phydev->adjust_link(phydev->attached_dev);
2150
2151         return 0;
2152 }
2153
2154 static int
2155 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2156 {
2157         if (phydev->mdio.addr == 0)
2158                 return 0;
2159
2160         return genphy_config_aneg(phydev);
2161 }
2162
2163 static const u32 ar8xxx_phy_ids[] = {
2164         0x004dd033,
2165         0x004dd034, /* AR8327 */
2166         0x004dd036, /* AR8337 */
2167         0x004dd041,
2168         0x004dd042,
2169         0x004dd043, /* AR8236 */
2170 };
2171
2172 static bool
2173 ar8xxx_phy_match(u32 phy_id)
2174 {
2175         int i;
2176
2177         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2178                 if (phy_id == ar8xxx_phy_ids[i])
2179                         return true;
2180
2181         return false;
2182 }
2183
2184 static bool
2185 ar8xxx_is_possible(struct mii_bus *bus)
2186 {
2187         unsigned int i, found_phys = 0;
2188
2189         for (i = 0; i < 5; i++) {
2190                 u32 phy_id;
2191
2192                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2193                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2194                 if (ar8xxx_phy_match(phy_id)) {
2195                         found_phys++;
2196                 } else if (phy_id) {
2197                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2198                                  dev_name(&bus->dev), i, phy_id);
2199                 }
2200         }
2201         return !!found_phys;
2202 }
2203
2204 static int
2205 ar8xxx_phy_probe(struct phy_device *phydev)
2206 {
2207         struct ar8xxx_priv *priv;
2208         struct switch_dev *swdev;
2209         int ret;
2210
2211         /* skip PHYs at unused adresses */
2212         if (phydev->mdio.addr != 0 && phydev->mdio.addr != 4)
2213                 return -ENODEV;
2214
2215         if (!ar8xxx_is_possible(phydev->mdio.bus))
2216                 return -ENODEV;
2217
2218         mutex_lock(&ar8xxx_dev_list_lock);
2219         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2220                 if (priv->mii_bus == phydev->mdio.bus)
2221                         goto found;
2222
2223         priv = ar8xxx_create();
2224         if (priv == NULL) {
2225                 ret = -ENOMEM;
2226                 goto unlock;
2227         }
2228
2229         priv->mii_bus = phydev->mdio.bus;
2230
2231         ret = ar8xxx_probe_switch(priv);
2232         if (ret)
2233                 goto free_priv;
2234
2235         swdev = &priv->dev;
2236         swdev->alias = dev_name(&priv->mii_bus->dev);
2237         ret = register_switch(swdev, NULL);
2238         if (ret)
2239                 goto free_priv;
2240
2241         pr_info("%s: %s rev. %u switch registered on %s\n",
2242                 swdev->devname, swdev->name, priv->chip_rev,
2243                 dev_name(&priv->mii_bus->dev));
2244
2245         list_add(&priv->list, &ar8xxx_dev_list);
2246
2247 found:
2248         priv->use_count++;
2249
2250         if (phydev->mdio.addr == 0) {
2251                 if (ar8xxx_has_gige(priv)) {
2252                         phydev->supported = SUPPORTED_1000baseT_Full;
2253                         phydev->advertising = ADVERTISED_1000baseT_Full;
2254                 } else {
2255                         phydev->supported = SUPPORTED_100baseT_Full;
2256                         phydev->advertising = ADVERTISED_100baseT_Full;
2257                 }
2258
2259                 if (priv->chip->config_at_probe) {
2260                         priv->phy = phydev;
2261
2262                         ret = ar8xxx_start(priv);
2263                         if (ret)
2264                                 goto err_unregister_switch;
2265                 }
2266         } else {
2267                 if (ar8xxx_has_gige(priv)) {
2268                         phydev->supported |= SUPPORTED_1000baseT_Full;
2269                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2270                 }
2271         }
2272
2273         phydev->priv = priv;
2274
2275         mutex_unlock(&ar8xxx_dev_list_lock);
2276
2277         return 0;
2278
2279 err_unregister_switch:
2280         if (--priv->use_count)
2281                 goto unlock;
2282
2283         unregister_switch(&priv->dev);
2284
2285 free_priv:
2286         ar8xxx_free(priv);
2287 unlock:
2288         mutex_unlock(&ar8xxx_dev_list_lock);
2289         return ret;
2290 }
2291
2292 static void
2293 ar8xxx_phy_detach(struct phy_device *phydev)
2294 {
2295         struct net_device *dev = phydev->attached_dev;
2296
2297         if (!dev)
2298                 return;
2299
2300         dev->phy_ptr = NULL;
2301         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2302         dev->eth_mangle_rx = NULL;
2303         dev->eth_mangle_tx = NULL;
2304 }
2305
2306 static void
2307 ar8xxx_phy_remove(struct phy_device *phydev)
2308 {
2309         struct ar8xxx_priv *priv = phydev->priv;
2310
2311         if (WARN_ON(!priv))
2312                 return;
2313
2314         phydev->priv = NULL;
2315
2316         mutex_lock(&ar8xxx_dev_list_lock);
2317
2318         if (--priv->use_count > 0) {
2319                 mutex_unlock(&ar8xxx_dev_list_lock);
2320                 return;
2321         }
2322
2323         list_del(&priv->list);
2324         mutex_unlock(&ar8xxx_dev_list_lock);
2325
2326         unregister_switch(&priv->dev);
2327         ar8xxx_mib_stop(priv);
2328         ar8xxx_free(priv);
2329 }
2330
2331 static int
2332 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2333 {
2334         /* we don't need an extra reset */
2335         return 0;
2336 }
2337
2338 static struct phy_driver ar8xxx_phy_driver[] = {
2339         {
2340                 .phy_id         = 0x004d0000,
2341                 .name           = "Atheros AR8216/AR8236/AR8316",
2342                 .phy_id_mask    = 0xffff0000,
2343                 .features       = PHY_BASIC_FEATURES,
2344                 .probe          = ar8xxx_phy_probe,
2345                 .remove         = ar8xxx_phy_remove,
2346                 .detach         = ar8xxx_phy_detach,
2347                 .config_init    = ar8xxx_phy_config_init,
2348                 .config_aneg    = ar8xxx_phy_config_aneg,
2349                 .read_status    = ar8xxx_phy_read_status,
2350                 .soft_reset     = ar8xxx_phy_soft_reset,
2351         }
2352 };
2353
2354 module_phy_driver(ar8xxx_phy_driver);
2355 MODULE_LICENSE("GPL");