2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
141 unsigned int sleep_msecs = 20;
144 for (elapsed = sleep_msecs; elapsed <= 600;
145 elapsed += sleep_msecs) {
147 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
148 ret = mdiobus_read(bus, i, MII_BMCR);
151 if (ret & BMCR_RESET)
153 if (i == AR8XXX_NUM_PHYS - 1) {
154 usleep_range(1000, 2000);
163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
167 if (phydev->autoneg != AUTONEG_ENABLE)
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
174 ret = phy_read(phydev, MII_BMCR);
177 if (ret & BMCR_ANENABLE)
180 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
181 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
182 return phy_write(phydev, MII_BMCR, ret);
186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
192 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
193 if (priv->chip->phy_fixup)
194 priv->chip->phy_fixup(priv, i);
196 /* initialize the port itself */
197 mdiobus_write(bus, i, MII_ADVERTISE,
198 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
199 if (ar8xxx_has_gige(priv))
200 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
201 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
204 ar8xxx_phy_poll_reset(bus);
208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
210 struct mii_bus *bus = priv->mii_bus;
213 lo = bus->read(bus, phy_id, regnum);
214 hi = bus->read(bus, phy_id, regnum + 1);
216 return (hi << 16) | lo;
220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
222 struct mii_bus *bus = priv->mii_bus;
226 hi = (u16) (val >> 16);
228 if (priv->chip->mii_lo_first)
230 bus->write(bus, phy_id, regnum, lo);
231 bus->write(bus, phy_id, regnum + 1, hi);
233 bus->write(bus, phy_id, regnum + 1, hi);
234 bus->write(bus, phy_id, regnum, lo);
239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
241 struct mii_bus *bus = priv->mii_bus;
245 split_addr((u32) reg, &r1, &r2, &page);
247 mutex_lock(&bus->mdio_lock);
249 bus->write(bus, 0x18, 0, page);
250 wait_for_page_switch();
251 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
253 mutex_unlock(&bus->mdio_lock);
259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
261 struct mii_bus *bus = priv->mii_bus;
264 split_addr((u32) reg, &r1, &r2, &page);
266 mutex_lock(&bus->mdio_lock);
268 bus->write(bus, 0x18, 0, page);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
272 mutex_unlock(&bus->mdio_lock);
276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
278 struct mii_bus *bus = priv->mii_bus;
282 split_addr((u32) reg, &r1, &r2, &page);
284 mutex_lock(&bus->mdio_lock);
286 bus->write(bus, 0x18, 0, page);
287 wait_for_page_switch();
289 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
292 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
294 mutex_unlock(&bus->mdio_lock);
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
301 u16 dbg_addr, u16 dbg_data)
303 struct mii_bus *bus = priv->mii_bus;
305 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
307 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
308 mutex_unlock(&bus->mdio_lock);
312 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
314 struct mii_bus *bus = priv->mii_bus;
316 mutex_lock(&bus->mdio_lock);
317 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
318 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
319 mutex_unlock(&bus->mdio_lock);
323 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
325 struct mii_bus *bus = priv->mii_bus;
328 mutex_lock(&bus->mdio_lock);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
330 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
331 mutex_unlock(&bus->mdio_lock);
337 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
342 for (i = 0; i < timeout; i++) {
345 t = ar8xxx_read(priv, reg);
346 if ((t & mask) == val)
349 usleep_range(1000, 2000);
356 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
358 unsigned mib_func = priv->chip->mib_func;
361 lockdep_assert_held(&priv->mib_lock);
363 /* Capture the hardware statistics for all ports */
364 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
366 /* Wait for the capturing to complete. */
367 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
378 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
380 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
384 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
386 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
390 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
396 WARN_ON(port >= priv->dev.ports);
398 lockdep_assert_held(&priv->mib_lock);
400 base = priv->chip->reg_port_stats_start +
401 priv->chip->reg_port_stats_length * port;
403 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
404 for (i = 0; i < priv->chip->num_mibs; i++) {
405 const struct ar8xxx_mib_desc *mib;
408 mib = &priv->chip->mib_decs[i];
409 t = ar8xxx_read(priv, base + mib->offset);
410 if (mib->size == 2) {
413 hi = ar8xxx_read(priv, base + mib->offset + 4);
425 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
426 struct switch_port_link *link)
431 memset(link, '\0', sizeof(*link));
433 status = priv->chip->read_port_status(priv, port);
435 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
437 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
441 if (priv->get_port_link) {
444 err = priv->get_port_link(port);
453 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
454 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
455 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
457 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
458 link->eee = priv->chip->read_port_eee_status(priv, port);
460 speed = (status & AR8216_PORT_STATUS_SPEED) >>
461 AR8216_PORT_STATUS_SPEED_S;
464 case AR8216_PORT_SPEED_10M:
465 link->speed = SWITCH_PORT_SPEED_10;
467 case AR8216_PORT_SPEED_100M:
468 link->speed = SWITCH_PORT_SPEED_100;
470 case AR8216_PORT_SPEED_1000M:
471 link->speed = SWITCH_PORT_SPEED_1000;
474 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
479 static struct sk_buff *
480 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
482 struct ar8xxx_priv *priv = dev->phy_ptr;
491 if (unlikely(skb_headroom(skb) < 2)) {
492 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
496 buf = skb_push(skb, 2);
504 dev_kfree_skb_any(skb);
509 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
511 struct ar8xxx_priv *priv;
519 /* don't strip the header if vlan mode is disabled */
523 /* strip header, get vlan id */
527 /* check for vlan header presence */
528 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
533 /* no need to fix up packets coming from a tagged source */
534 if (priv->vlan_tagged & (1 << port))
537 /* lookup port vid from local table, the switch passes an invalid vlan id */
538 vlan = priv->vlan_id[priv->pvid[port]];
541 buf[14 + 2] |= vlan >> 8;
542 buf[15 + 2] = vlan & 0xff;
546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
552 t = ar8xxx_read(priv, reg);
553 if ((t & mask) == val)
562 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
563 (unsigned int) reg, t, mask, val);
568 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
570 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
572 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
573 val &= AR8216_VTUDATA_MEMBER;
574 val |= AR8216_VTUDATA_VALID;
575 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
577 op |= AR8216_VTU_ACTIVE;
578 ar8xxx_write(priv, AR8216_REG_VTU, op);
582 ar8216_vtu_flush(struct ar8xxx_priv *priv)
584 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
588 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
592 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
593 ar8216_vtu_op(priv, op, port_mask);
597 ar8216_atu_flush(struct ar8xxx_priv *priv)
601 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
603 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
610 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
615 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
617 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
618 t |= AR8216_ATU_ACTIVE;
619 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
626 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
628 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
632 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
639 pvid = priv->vlan_id[priv->pvid[port]];
640 if (priv->vlan_tagged & (1 << port))
641 egress = AR8216_OUT_ADD_VLAN;
643 egress = AR8216_OUT_STRIP_VLAN;
644 ingress = AR8216_IN_SECURE;
647 egress = AR8216_OUT_KEEP;
648 ingress = AR8216_IN_PORT_ONLY;
651 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
652 header = AR8216_PORT_CTRL_HEADER;
656 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
657 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
658 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
659 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
660 AR8216_PORT_CTRL_LEARN | header |
661 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
662 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
664 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
665 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
666 AR8216_PORT_VLAN_DEFAULT_ID,
667 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
668 (ingress << AR8216_PORT_VLAN_MODE_S) |
669 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
673 ar8216_hw_init(struct ar8xxx_priv *priv)
675 if (priv->initialized)
678 ar8xxx_phy_init(priv);
680 priv->initialized = true;
685 ar8216_init_globals(struct ar8xxx_priv *priv)
687 /* standard atheros magic */
688 ar8xxx_write(priv, 0x38, 0xc000050e);
690 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
691 AR8216_GCTRL_MTU, 1518 + 8 + 2);
695 ar8216_init_port(struct ar8xxx_priv *priv, int port)
697 /* Enable port learning and tx */
698 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
699 AR8216_PORT_CTRL_LEARN |
700 (4 << AR8216_PORT_CTRL_STATE_S));
702 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
704 if (port == AR8216_PORT_CPU) {
705 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
706 AR8216_PORT_STATUS_LINK_UP |
707 (ar8xxx_has_gige(priv) ?
708 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
709 AR8216_PORT_STATUS_TXMAC |
710 AR8216_PORT_STATUS_RXMAC |
711 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
712 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
713 AR8216_PORT_STATUS_DUPLEX);
715 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
716 AR8216_PORT_STATUS_LINK_AUTO);
721 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
725 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
729 pr_err("ar8216: timeout waiting for atu to become ready\n");
732 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
733 struct arl_entry *a, u32 *status, enum arl_op op)
735 struct mii_bus *bus = priv->mii_bus;
737 u16 r1_func0, r1_func1, r1_func2;
738 u32 t, val0, val1, val2;
741 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
744 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
745 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
748 case AR8XXX_ARL_INITIALIZE:
749 /* all ATU registers are on the same page
750 * therefore set page only once
752 bus->write(bus, 0x18, 0, page);
753 wait_for_page_switch();
755 ar8216_wait_atu_ready(priv, r2, r1_func0);
757 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
758 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
759 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
761 case AR8XXX_ARL_GET_NEXT:
762 t = ar8xxx_mii_read32(priv, r2, r1_func0);
763 t |= AR8216_ATU_ACTIVE;
764 ar8xxx_mii_write32(priv, r2, r1_func0, t);
765 ar8216_wait_atu_ready(priv, r2, r1_func0);
767 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
768 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
769 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
771 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
776 t = AR8216_ATU_PORT0;
777 while (!(val2 & t) && ++i < priv->dev.ports)
781 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
782 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
783 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
784 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
785 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
786 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
792 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
798 pvid = priv->vlan_id[priv->pvid[port]];
799 if (priv->vlan_tagged & (1 << port))
800 egress = AR8216_OUT_ADD_VLAN;
802 egress = AR8216_OUT_STRIP_VLAN;
803 ingress = AR8216_IN_SECURE;
806 egress = AR8216_OUT_KEEP;
807 ingress = AR8216_IN_PORT_ONLY;
810 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
811 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
812 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
813 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
814 AR8216_PORT_CTRL_LEARN |
815 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
816 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
818 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
819 AR8236_PORT_VLAN_DEFAULT_ID,
820 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
822 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
823 AR8236_PORT_VLAN2_VLAN_MODE |
824 AR8236_PORT_VLAN2_MEMBER,
825 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
826 (members << AR8236_PORT_VLAN2_MEMBER_S));
830 ar8236_init_globals(struct ar8xxx_priv *priv)
832 /* enable jumbo frames */
833 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
834 AR8316_GCTRL_MTU, 9018 + 8 + 2);
836 /* enable cpu port to receive arp frames */
837 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
838 AR8236_ATU_CTRL_RES);
840 /* enable cpu port to receive multicast and broadcast frames */
841 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
842 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
844 /* Enable MIB counters */
845 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
846 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
851 ar8316_hw_init(struct ar8xxx_priv *priv)
855 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
857 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
858 if (priv->port4_phy) {
859 /* value taken from Ubiquiti RouterStation Pro */
861 pr_info("ar8316: Using port 4 as PHY\n");
864 pr_info("ar8316: Using port 4 as switch port\n");
866 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
867 /* value taken from AVM Fritz!Box 7390 sources */
870 /* no known value for phy interface */
871 pr_err("ar8316: unsupported mii mode: %d.\n",
872 priv->phy->interface);
879 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
881 if (priv->port4_phy &&
882 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
883 /* work around for phy4 rgmii mode */
884 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
886 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
888 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
892 ar8xxx_phy_init(priv);
895 priv->initialized = true;
900 ar8316_init_globals(struct ar8xxx_priv *priv)
902 /* standard atheros magic */
903 ar8xxx_write(priv, 0x38, 0xc000050e);
905 /* enable cpu port to receive multicast and broadcast frames */
906 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
908 /* enable jumbo frames */
909 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
910 AR8316_GCTRL_MTU, 9018 + 8 + 2);
912 /* Enable MIB counters */
913 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
914 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
919 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
920 struct switch_val *val)
922 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
923 priv->vlan = !!val->value.i;
928 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
929 struct switch_val *val)
931 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
932 val->value.i = priv->vlan;
938 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
940 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
942 /* make sure no invalid PVIDs get set */
944 if (vlan >= dev->vlans)
947 priv->pvid[port] = vlan;
952 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
954 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
955 *vlan = priv->pvid[port];
960 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
961 struct switch_val *val)
963 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
964 priv->vlan_id[val->port_vlan] = val->value.i;
969 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
970 struct switch_val *val)
972 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
973 val->value.i = priv->vlan_id[val->port_vlan];
978 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
979 struct switch_port_link *link)
981 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
983 ar8216_read_port_link(priv, port, link);
988 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
990 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
991 u8 ports = priv->vlan_table[val->port_vlan];
995 for (i = 0; i < dev->ports; i++) {
996 struct switch_port *p;
998 if (!(ports & (1 << i)))
1001 p = &val->value.ports[val->len++];
1003 if (priv->vlan_tagged & (1 << i))
1004 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1012 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1014 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1015 u8 *vt = &priv->vlan_table[val->port_vlan];
1019 for (i = 0; i < val->len; i++) {
1020 struct switch_port *p = &val->value.ports[i];
1022 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1023 priv->vlan_tagged |= (1 << p->id);
1025 priv->vlan_tagged &= ~(1 << p->id);
1026 priv->pvid[p->id] = val->port_vlan;
1028 /* make sure that an untagged port does not
1029 * appear in other vlans */
1030 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1031 if (j == val->port_vlan)
1033 priv->vlan_table[j] &= ~(1 << p->id);
1043 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1047 /* reset all mirror registers */
1048 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1049 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1050 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1051 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1052 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1053 AR8216_PORT_CTRL_MIRROR_RX);
1055 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1056 AR8216_PORT_CTRL_MIRROR_TX);
1059 /* now enable mirroring if necessary */
1060 if (priv->source_port >= AR8216_NUM_PORTS ||
1061 priv->monitor_port >= AR8216_NUM_PORTS ||
1062 priv->source_port == priv->monitor_port) {
1066 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1067 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1068 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1070 if (priv->mirror_rx)
1071 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1072 AR8216_PORT_CTRL_MIRROR_RX);
1074 if (priv->mirror_tx)
1075 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1076 AR8216_PORT_CTRL_MIRROR_TX);
1080 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1082 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1083 u8 portmask[AR8X16_MAX_PORTS];
1086 mutex_lock(&priv->reg_mutex);
1087 /* flush all vlan translation unit entries */
1088 priv->chip->vtu_flush(priv);
1090 memset(portmask, 0, sizeof(portmask));
1092 /* calculate the port destination masks and load vlans
1093 * into the vlan translation unit */
1094 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1095 u8 vp = priv->vlan_table[j];
1100 for (i = 0; i < dev->ports; i++) {
1103 portmask[i] |= vp & ~mask;
1106 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1107 priv->vlan_table[j]);
1111 * isolate all ports, but connect them to the cpu port */
1112 for (i = 0; i < dev->ports; i++) {
1113 if (i == AR8216_PORT_CPU)
1116 portmask[i] = 1 << AR8216_PORT_CPU;
1117 portmask[AR8216_PORT_CPU] |= (1 << i);
1121 /* update the port destination mask registers and tag settings */
1122 for (i = 0; i < dev->ports; i++) {
1123 priv->chip->setup_port(priv, i, portmask[i]);
1126 priv->chip->set_mirror_regs(priv);
1128 mutex_unlock(&priv->reg_mutex);
1133 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1135 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1136 const struct ar8xxx_chip *chip = priv->chip;
1139 mutex_lock(&priv->reg_mutex);
1140 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1141 offsetof(struct ar8xxx_priv, vlan));
1143 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1144 priv->vlan_id[i] = i;
1146 /* Configure all ports */
1147 for (i = 0; i < dev->ports; i++)
1148 chip->init_port(priv, i);
1150 priv->mirror_rx = false;
1151 priv->mirror_tx = false;
1152 priv->source_port = 0;
1153 priv->monitor_port = 0;
1155 chip->init_globals(priv);
1157 mutex_unlock(&priv->reg_mutex);
1159 return chip->sw_hw_apply(dev);
1163 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1164 const struct switch_attr *attr,
1165 struct switch_val *val)
1167 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1171 if (!ar8xxx_has_mib_counters(priv))
1174 mutex_lock(&priv->mib_lock);
1176 len = priv->dev.ports * priv->chip->num_mibs *
1177 sizeof(*priv->mib_stats);
1178 memset(priv->mib_stats, '\0', len);
1179 ret = ar8xxx_mib_flush(priv);
1186 mutex_unlock(&priv->mib_lock);
1191 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1192 const struct switch_attr *attr,
1193 struct switch_val *val)
1195 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1197 mutex_lock(&priv->reg_mutex);
1198 priv->mirror_rx = !!val->value.i;
1199 priv->chip->set_mirror_regs(priv);
1200 mutex_unlock(&priv->reg_mutex);
1206 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1207 const struct switch_attr *attr,
1208 struct switch_val *val)
1210 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1211 val->value.i = priv->mirror_rx;
1216 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1220 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1222 mutex_lock(&priv->reg_mutex);
1223 priv->mirror_tx = !!val->value.i;
1224 priv->chip->set_mirror_regs(priv);
1225 mutex_unlock(&priv->reg_mutex);
1231 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1232 const struct switch_attr *attr,
1233 struct switch_val *val)
1235 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1236 val->value.i = priv->mirror_tx;
1241 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1242 const struct switch_attr *attr,
1243 struct switch_val *val)
1245 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1247 mutex_lock(&priv->reg_mutex);
1248 priv->monitor_port = val->value.i;
1249 priv->chip->set_mirror_regs(priv);
1250 mutex_unlock(&priv->reg_mutex);
1256 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1257 const struct switch_attr *attr,
1258 struct switch_val *val)
1260 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1261 val->value.i = priv->monitor_port;
1266 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1267 const struct switch_attr *attr,
1268 struct switch_val *val)
1270 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1272 mutex_lock(&priv->reg_mutex);
1273 priv->source_port = val->value.i;
1274 priv->chip->set_mirror_regs(priv);
1275 mutex_unlock(&priv->reg_mutex);
1281 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1282 const struct switch_attr *attr,
1283 struct switch_val *val)
1285 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1286 val->value.i = priv->source_port;
1291 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1292 const struct switch_attr *attr,
1293 struct switch_val *val)
1295 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1299 if (!ar8xxx_has_mib_counters(priv))
1302 port = val->port_vlan;
1303 if (port >= dev->ports)
1306 mutex_lock(&priv->mib_lock);
1307 ret = ar8xxx_mib_capture(priv);
1311 ar8xxx_mib_fetch_port_stat(priv, port, true);
1316 mutex_unlock(&priv->mib_lock);
1321 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1322 const struct switch_attr *attr,
1323 struct switch_val *val)
1325 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1326 const struct ar8xxx_chip *chip = priv->chip;
1330 char *buf = priv->buf;
1333 if (!ar8xxx_has_mib_counters(priv))
1336 port = val->port_vlan;
1337 if (port >= dev->ports)
1340 mutex_lock(&priv->mib_lock);
1341 ret = ar8xxx_mib_capture(priv);
1345 ar8xxx_mib_fetch_port_stat(priv, port, false);
1347 len += snprintf(buf + len, sizeof(priv->buf) - len,
1348 "Port %d MIB counters\n",
1351 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1352 for (i = 0; i < chip->num_mibs; i++)
1353 len += snprintf(buf + len, sizeof(priv->buf) - len,
1355 chip->mib_decs[i].name,
1364 mutex_unlock(&priv->mib_lock);
1369 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1370 const struct switch_attr *attr,
1371 struct switch_val *val)
1373 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1374 struct mii_bus *bus = priv->mii_bus;
1375 const struct ar8xxx_chip *chip = priv->chip;
1376 char *buf = priv->arl_buf;
1377 int i, j, k, len = 0;
1378 struct arl_entry *a, *a1;
1381 if (!chip->get_arl_entry)
1384 mutex_lock(&priv->reg_mutex);
1385 mutex_lock(&bus->mdio_lock);
1387 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1389 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1390 a = &priv->arl_table[i];
1392 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1398 * ARL table can include multiple valid entries
1399 * per MAC, just with differing status codes
1401 for (j = 0; j < i; ++j) {
1402 a1 = &priv->arl_table[j];
1403 if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1408 mutex_unlock(&bus->mdio_lock);
1410 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1411 "address resolution table\n");
1413 if (i == AR8XXX_NUM_ARL_RECORDS)
1414 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1415 "Too many entries found, displaying the first %d only!\n",
1416 AR8XXX_NUM_ARL_RECORDS);
1418 for (j = 0; j < priv->dev.ports; ++j) {
1419 for (k = 0; k < i; ++k) {
1420 a = &priv->arl_table[k];
1423 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1424 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1426 a->mac[5], a->mac[4], a->mac[3],
1427 a->mac[2], a->mac[1], a->mac[0]);
1434 mutex_unlock(&priv->reg_mutex);
1440 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1441 const struct switch_attr *attr,
1442 struct switch_val *val)
1444 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1447 mutex_lock(&priv->reg_mutex);
1448 ret = priv->chip->atu_flush(priv);
1449 mutex_unlock(&priv->reg_mutex);
1455 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1456 const struct switch_attr *attr,
1457 struct switch_val *val)
1459 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1462 port = val->port_vlan;
1463 if (port >= dev->ports)
1466 mutex_lock(&priv->reg_mutex);
1467 ret = priv->chip->atu_flush_port(priv, port);
1468 mutex_unlock(&priv->reg_mutex);
1473 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1475 .type = SWITCH_TYPE_INT,
1476 .name = "enable_vlan",
1477 .description = "Enable VLAN mode",
1478 .set = ar8xxx_sw_set_vlan,
1479 .get = ar8xxx_sw_get_vlan,
1483 .type = SWITCH_TYPE_NOVAL,
1484 .name = "reset_mibs",
1485 .description = "Reset all MIB counters",
1486 .set = ar8xxx_sw_set_reset_mibs,
1489 .type = SWITCH_TYPE_INT,
1490 .name = "enable_mirror_rx",
1491 .description = "Enable mirroring of RX packets",
1492 .set = ar8xxx_sw_set_mirror_rx_enable,
1493 .get = ar8xxx_sw_get_mirror_rx_enable,
1497 .type = SWITCH_TYPE_INT,
1498 .name = "enable_mirror_tx",
1499 .description = "Enable mirroring of TX packets",
1500 .set = ar8xxx_sw_set_mirror_tx_enable,
1501 .get = ar8xxx_sw_get_mirror_tx_enable,
1505 .type = SWITCH_TYPE_INT,
1506 .name = "mirror_monitor_port",
1507 .description = "Mirror monitor port",
1508 .set = ar8xxx_sw_set_mirror_monitor_port,
1509 .get = ar8xxx_sw_get_mirror_monitor_port,
1510 .max = AR8216_NUM_PORTS - 1
1513 .type = SWITCH_TYPE_INT,
1514 .name = "mirror_source_port",
1515 .description = "Mirror source port",
1516 .set = ar8xxx_sw_set_mirror_source_port,
1517 .get = ar8xxx_sw_get_mirror_source_port,
1518 .max = AR8216_NUM_PORTS - 1
1521 .type = SWITCH_TYPE_STRING,
1522 .name = "arl_table",
1523 .description = "Get ARL table",
1525 .get = ar8xxx_sw_get_arl_table,
1528 .type = SWITCH_TYPE_NOVAL,
1529 .name = "flush_arl_table",
1530 .description = "Flush ARL table",
1531 .set = ar8xxx_sw_set_flush_arl_table,
1535 const struct switch_attr ar8xxx_sw_attr_port[] = {
1537 .type = SWITCH_TYPE_NOVAL,
1538 .name = "reset_mib",
1539 .description = "Reset single port MIB counters",
1540 .set = ar8xxx_sw_set_port_reset_mib,
1543 .type = SWITCH_TYPE_STRING,
1545 .description = "Get port's MIB counters",
1547 .get = ar8xxx_sw_get_port_mib,
1550 .type = SWITCH_TYPE_NOVAL,
1551 .name = "flush_arl_table",
1552 .description = "Flush port's ARL table entries",
1553 .set = ar8xxx_sw_set_flush_port_arl_table,
1557 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1559 .type = SWITCH_TYPE_INT,
1561 .description = "VLAN ID (0-4094)",
1562 .set = ar8xxx_sw_set_vid,
1563 .get = ar8xxx_sw_get_vid,
1568 static const struct switch_dev_ops ar8xxx_sw_ops = {
1570 .attr = ar8xxx_sw_attr_globals,
1571 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1574 .attr = ar8xxx_sw_attr_port,
1575 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1578 .attr = ar8xxx_sw_attr_vlan,
1579 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1581 .get_port_pvid = ar8xxx_sw_get_pvid,
1582 .set_port_pvid = ar8xxx_sw_set_pvid,
1583 .get_vlan_ports = ar8xxx_sw_get_ports,
1584 .set_vlan_ports = ar8xxx_sw_set_ports,
1585 .apply_config = ar8xxx_sw_hw_apply,
1586 .reset_switch = ar8xxx_sw_reset_switch,
1587 .get_port_link = ar8xxx_sw_get_port_link,
1590 static const struct ar8xxx_chip ar8216_chip = {
1591 .caps = AR8XXX_CAP_MIB_COUNTERS,
1593 .reg_port_stats_start = 0x19000,
1594 .reg_port_stats_length = 0xa0,
1596 .name = "Atheros AR8216",
1597 .ports = AR8216_NUM_PORTS,
1598 .vlans = AR8216_NUM_VLANS,
1599 .swops = &ar8xxx_sw_ops,
1601 .hw_init = ar8216_hw_init,
1602 .init_globals = ar8216_init_globals,
1603 .init_port = ar8216_init_port,
1604 .setup_port = ar8216_setup_port,
1605 .read_port_status = ar8216_read_port_status,
1606 .atu_flush = ar8216_atu_flush,
1607 .atu_flush_port = ar8216_atu_flush_port,
1608 .vtu_flush = ar8216_vtu_flush,
1609 .vtu_load_vlan = ar8216_vtu_load_vlan,
1610 .set_mirror_regs = ar8216_set_mirror_regs,
1611 .get_arl_entry = ar8216_get_arl_entry,
1612 .sw_hw_apply = ar8xxx_sw_hw_apply,
1614 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1615 .mib_decs = ar8216_mibs,
1616 .mib_func = AR8216_REG_MIB_FUNC
1619 static const struct ar8xxx_chip ar8236_chip = {
1620 .caps = AR8XXX_CAP_MIB_COUNTERS,
1622 .reg_port_stats_start = 0x20000,
1623 .reg_port_stats_length = 0x100,
1625 .name = "Atheros AR8236",
1626 .ports = AR8216_NUM_PORTS,
1627 .vlans = AR8216_NUM_VLANS,
1628 .swops = &ar8xxx_sw_ops,
1630 .hw_init = ar8216_hw_init,
1631 .init_globals = ar8236_init_globals,
1632 .init_port = ar8216_init_port,
1633 .setup_port = ar8236_setup_port,
1634 .read_port_status = ar8216_read_port_status,
1635 .atu_flush = ar8216_atu_flush,
1636 .atu_flush_port = ar8216_atu_flush_port,
1637 .vtu_flush = ar8216_vtu_flush,
1638 .vtu_load_vlan = ar8216_vtu_load_vlan,
1639 .set_mirror_regs = ar8216_set_mirror_regs,
1640 .get_arl_entry = ar8216_get_arl_entry,
1641 .sw_hw_apply = ar8xxx_sw_hw_apply,
1643 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1644 .mib_decs = ar8236_mibs,
1645 .mib_func = AR8216_REG_MIB_FUNC
1648 static const struct ar8xxx_chip ar8316_chip = {
1649 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1651 .reg_port_stats_start = 0x20000,
1652 .reg_port_stats_length = 0x100,
1654 .name = "Atheros AR8316",
1655 .ports = AR8216_NUM_PORTS,
1656 .vlans = AR8X16_MAX_VLANS,
1657 .swops = &ar8xxx_sw_ops,
1659 .hw_init = ar8316_hw_init,
1660 .init_globals = ar8316_init_globals,
1661 .init_port = ar8216_init_port,
1662 .setup_port = ar8216_setup_port,
1663 .read_port_status = ar8216_read_port_status,
1664 .atu_flush = ar8216_atu_flush,
1665 .atu_flush_port = ar8216_atu_flush_port,
1666 .vtu_flush = ar8216_vtu_flush,
1667 .vtu_load_vlan = ar8216_vtu_load_vlan,
1668 .set_mirror_regs = ar8216_set_mirror_regs,
1669 .get_arl_entry = ar8216_get_arl_entry,
1670 .sw_hw_apply = ar8xxx_sw_hw_apply,
1672 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1673 .mib_decs = ar8236_mibs,
1674 .mib_func = AR8216_REG_MIB_FUNC
1678 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1684 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1688 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1689 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1692 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1696 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1701 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1702 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1704 switch (priv->chip_ver) {
1705 case AR8XXX_VER_AR8216:
1706 priv->chip = &ar8216_chip;
1708 case AR8XXX_VER_AR8236:
1709 priv->chip = &ar8236_chip;
1711 case AR8XXX_VER_AR8316:
1712 priv->chip = &ar8316_chip;
1714 case AR8XXX_VER_AR8327:
1715 priv->chip = &ar8327_chip;
1717 case AR8XXX_VER_AR8337:
1718 priv->chip = &ar8337_chip;
1721 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1722 priv->chip_ver, priv->chip_rev);
1731 ar8xxx_mib_work_func(struct work_struct *work)
1733 struct ar8xxx_priv *priv;
1736 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1738 mutex_lock(&priv->mib_lock);
1740 err = ar8xxx_mib_capture(priv);
1744 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1747 priv->mib_next_port++;
1748 if (priv->mib_next_port >= priv->dev.ports)
1749 priv->mib_next_port = 0;
1751 mutex_unlock(&priv->mib_lock);
1752 schedule_delayed_work(&priv->mib_work,
1753 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1757 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1761 if (!ar8xxx_has_mib_counters(priv))
1764 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1766 len = priv->dev.ports * priv->chip->num_mibs *
1767 sizeof(*priv->mib_stats);
1768 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1770 if (!priv->mib_stats)
1777 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1779 if (!ar8xxx_has_mib_counters(priv))
1782 schedule_delayed_work(&priv->mib_work,
1783 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1787 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1789 if (!ar8xxx_has_mib_counters(priv))
1792 cancel_delayed_work(&priv->mib_work);
1795 static struct ar8xxx_priv *
1798 struct ar8xxx_priv *priv;
1800 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1804 mutex_init(&priv->reg_mutex);
1805 mutex_init(&priv->mib_lock);
1806 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1812 ar8xxx_free(struct ar8xxx_priv *priv)
1814 if (priv->chip && priv->chip->cleanup)
1815 priv->chip->cleanup(priv);
1817 kfree(priv->chip_data);
1818 kfree(priv->mib_stats);
1823 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1825 const struct ar8xxx_chip *chip;
1826 struct switch_dev *swdev;
1829 ret = ar8xxx_id_chip(priv);
1836 swdev->cpu_port = AR8216_PORT_CPU;
1837 swdev->name = chip->name;
1838 swdev->vlans = chip->vlans;
1839 swdev->ports = chip->ports;
1840 swdev->ops = chip->swops;
1842 ret = ar8xxx_mib_init(priv);
1850 ar8xxx_start(struct ar8xxx_priv *priv)
1856 ret = priv->chip->hw_init(priv);
1860 ret = ar8xxx_sw_reset_switch(&priv->dev);
1866 ar8xxx_mib_start(priv);
1872 ar8xxx_phy_config_init(struct phy_device *phydev)
1874 struct ar8xxx_priv *priv = phydev->priv;
1875 struct net_device *dev = phydev->attached_dev;
1881 if (priv->chip->config_at_probe)
1882 return ar8xxx_phy_check_aneg(phydev);
1886 if (phydev->addr != 0) {
1887 if (chip_is_ar8316(priv)) {
1888 /* switch device has been initialized, reinit */
1889 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1890 priv->initialized = false;
1891 priv->port4_phy = true;
1892 ar8316_hw_init(priv);
1899 ret = ar8xxx_start(priv);
1903 /* VID fixup only needed on ar8216 */
1904 if (chip_is_ar8216(priv)) {
1905 dev->phy_ptr = priv;
1906 dev->priv_flags |= IFF_NO_IP_ALIGN;
1907 dev->eth_mangle_rx = ar8216_mangle_rx;
1908 dev->eth_mangle_tx = ar8216_mangle_tx;
1915 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
1917 bool link_new, changed = false;
1921 mutex_lock(&priv->reg_mutex);
1923 for (i = 0; i < priv->dev.ports; i++) {
1924 status = priv->chip->read_port_status(priv, i);
1925 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
1926 if (link_new == priv->link_up[i])
1929 priv->link_up[i] = link_new;
1931 /* flush ARL entries for this port if it went down*/
1933 priv->chip->atu_flush_port(priv, i);
1934 dev_info(&priv->phy->dev, "Port %d is %s\n",
1935 i, link_new ? "up" : "down");
1938 mutex_unlock(&priv->reg_mutex);
1944 ar8xxx_phy_read_status(struct phy_device *phydev)
1946 struct ar8xxx_priv *priv = phydev->priv;
1947 struct switch_port_link link;
1949 /* check for switch port link changes */
1950 if (phydev->state == PHY_CHANGELINK)
1951 ar8xxx_check_link_states(priv);
1953 if (phydev->addr != 0)
1954 return genphy_read_status(phydev);
1956 ar8216_read_port_link(priv, phydev->addr, &link);
1957 phydev->link = !!link.link;
1961 switch (link.speed) {
1962 case SWITCH_PORT_SPEED_10:
1963 phydev->speed = SPEED_10;
1965 case SWITCH_PORT_SPEED_100:
1966 phydev->speed = SPEED_100;
1968 case SWITCH_PORT_SPEED_1000:
1969 phydev->speed = SPEED_1000;
1974 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1976 phydev->state = PHY_RUNNING;
1977 netif_carrier_on(phydev->attached_dev);
1978 phydev->adjust_link(phydev->attached_dev);
1984 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1986 if (phydev->addr == 0)
1989 return genphy_config_aneg(phydev);
1992 static const u32 ar8xxx_phy_ids[] = {
1994 0x004dd034, /* AR8327 */
1995 0x004dd036, /* AR8337 */
1998 0x004dd043, /* AR8236 */
2002 ar8xxx_phy_match(u32 phy_id)
2006 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2007 if (phy_id == ar8xxx_phy_ids[i])
2014 ar8xxx_is_possible(struct mii_bus *bus)
2018 for (i = 0; i < 4; i++) {
2021 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2022 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2023 if (!ar8xxx_phy_match(phy_id)) {
2024 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2025 dev_name(&bus->dev), i, phy_id);
2034 ar8xxx_phy_probe(struct phy_device *phydev)
2036 struct ar8xxx_priv *priv;
2037 struct switch_dev *swdev;
2040 /* skip PHYs at unused adresses */
2041 if (phydev->addr != 0 && phydev->addr != 4)
2044 if (!ar8xxx_is_possible(phydev->bus))
2047 mutex_lock(&ar8xxx_dev_list_lock);
2048 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2049 if (priv->mii_bus == phydev->bus)
2052 priv = ar8xxx_create();
2058 priv->mii_bus = phydev->bus;
2060 ret = ar8xxx_probe_switch(priv);
2065 swdev->alias = dev_name(&priv->mii_bus->dev);
2066 ret = register_switch(swdev, NULL);
2070 pr_info("%s: %s rev. %u switch registered on %s\n",
2071 swdev->devname, swdev->name, priv->chip_rev,
2072 dev_name(&priv->mii_bus->dev));
2077 if (phydev->addr == 0) {
2078 if (ar8xxx_has_gige(priv)) {
2079 phydev->supported = SUPPORTED_1000baseT_Full;
2080 phydev->advertising = ADVERTISED_1000baseT_Full;
2082 phydev->supported = SUPPORTED_100baseT_Full;
2083 phydev->advertising = ADVERTISED_100baseT_Full;
2086 if (priv->chip->config_at_probe) {
2089 ret = ar8xxx_start(priv);
2091 goto err_unregister_switch;
2094 if (ar8xxx_has_gige(priv)) {
2095 phydev->supported |= SUPPORTED_1000baseT_Full;
2096 phydev->advertising |= ADVERTISED_1000baseT_Full;
2100 phydev->priv = priv;
2102 list_add(&priv->list, &ar8xxx_dev_list);
2104 mutex_unlock(&ar8xxx_dev_list_lock);
2108 err_unregister_switch:
2109 if (--priv->use_count)
2112 unregister_switch(&priv->dev);
2117 mutex_unlock(&ar8xxx_dev_list_lock);
2122 ar8xxx_phy_detach(struct phy_device *phydev)
2124 struct net_device *dev = phydev->attached_dev;
2129 dev->phy_ptr = NULL;
2130 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2131 dev->eth_mangle_rx = NULL;
2132 dev->eth_mangle_tx = NULL;
2136 ar8xxx_phy_remove(struct phy_device *phydev)
2138 struct ar8xxx_priv *priv = phydev->priv;
2143 phydev->priv = NULL;
2144 if (--priv->use_count > 0)
2147 mutex_lock(&ar8xxx_dev_list_lock);
2148 list_del(&priv->list);
2149 mutex_unlock(&ar8xxx_dev_list_lock);
2151 unregister_switch(&priv->dev);
2152 ar8xxx_mib_stop(priv);
2156 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2158 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2160 /* we don't need an extra reset */
2165 static struct phy_driver ar8xxx_phy_driver = {
2166 .phy_id = 0x004d0000,
2167 .name = "Atheros AR8216/AR8236/AR8316",
2168 .phy_id_mask = 0xffff0000,
2169 .features = PHY_BASIC_FEATURES,
2170 .probe = ar8xxx_phy_probe,
2171 .remove = ar8xxx_phy_remove,
2172 .detach = ar8xxx_phy_detach,
2173 .config_init = ar8xxx_phy_config_init,
2174 .config_aneg = ar8xxx_phy_config_aneg,
2175 .read_status = ar8xxx_phy_read_status,
2176 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2177 .soft_reset = ar8xxx_phy_soft_reset,
2179 .driver = { .owner = THIS_MODULE },
2185 return phy_driver_register(&ar8xxx_phy_driver);
2191 phy_driver_unregister(&ar8xxx_phy_driver);
2194 module_init(ar8xxx_init);
2195 module_exit(ar8xxx_exit);
2196 MODULE_LICENSE("GPL");