2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
53 AR8XXX_VER_AR8216 = 0x01,
54 AR8XXX_VER_AR8236 = 0x03,
55 AR8XXX_VER_AR8316 = 0x10,
56 AR8XXX_VER_AR8327 = 0x12,
59 struct ar8xxx_mib_desc {
68 int (*hw_init)(struct ar8xxx_priv *priv);
69 void (*init_globals)(struct ar8xxx_priv *priv);
70 void (*init_port)(struct ar8xxx_priv *priv, int port);
71 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
72 u32 ingress, u32 members, u32 pvid);
73 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
74 int (*atu_flush)(struct ar8xxx_priv *priv);
75 void (*vtu_flush)(struct ar8xxx_priv *priv);
76 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
78 const struct ar8xxx_mib_desc *mib_decs;
88 struct switch_dev dev;
89 struct mii_bus *mii_bus;
90 struct phy_device *phy;
91 u32 (*read)(struct ar8xxx_priv *priv, int reg);
92 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
93 const struct net_device_ops *ndo_old;
94 struct net_device_ops ndo;
95 struct mutex reg_mutex;
98 const struct ar8xxx_chip *chip;
100 struct ar8327_data ar8327;
109 struct mutex mib_lock;
110 struct delayed_work mib_work;
114 struct list_head list;
115 unsigned int use_count;
117 /* all fields below are cleared on reset */
119 u16 vlan_id[AR8X16_MAX_VLANS];
120 u8 vlan_table[AR8X16_MAX_VLANS];
122 u16 pvid[AR8X16_MAX_PORTS];
131 #define MIB_DESC(_s , _o, _n) \
138 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
139 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
140 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
141 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
142 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
143 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
144 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
145 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
146 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
147 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
148 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
149 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
150 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
151 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
152 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
153 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
154 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
155 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
156 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
157 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
158 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
159 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
160 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
161 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
162 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
163 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
164 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
165 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
166 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
167 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
168 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
169 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
170 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
171 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
172 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
173 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
174 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
175 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
178 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
179 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
180 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
181 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
182 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
183 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
184 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
185 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
186 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
187 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
188 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
189 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
190 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
191 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
192 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
193 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
194 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
195 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
196 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
197 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
198 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
199 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
200 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
201 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
202 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
203 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
204 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
205 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
206 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
207 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
208 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
209 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
210 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
211 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
212 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
213 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
214 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
215 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
216 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
217 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
220 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
221 static LIST_HEAD(ar8xxx_dev_list);
223 static inline struct ar8xxx_priv *
224 swdev_to_ar8xxx(struct switch_dev *swdev)
226 return container_of(swdev, struct ar8xxx_priv, dev);
229 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
231 return priv->chip->caps & AR8XXX_CAP_GIGE;
234 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
236 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
239 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
241 return priv->chip_ver == AR8XXX_VER_AR8216;
244 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
246 return priv->chip_ver == AR8XXX_VER_AR8236;
249 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
251 return priv->chip_ver == AR8XXX_VER_AR8316;
254 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
256 return priv->chip_ver == AR8XXX_VER_AR8327;
260 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
263 *r1 = regaddr & 0x1e;
269 *page = regaddr & 0x1ff;
273 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
275 struct mii_bus *bus = priv->mii_bus;
279 split_addr((u32) reg, &r1, &r2, &page);
281 mutex_lock(&bus->mdio_lock);
283 bus->write(bus, 0x18, 0, page);
284 usleep_range(1000, 2000); /* wait for the page switch to propagate */
285 lo = bus->read(bus, 0x10 | r2, r1);
286 hi = bus->read(bus, 0x10 | r2, r1 + 1);
288 mutex_unlock(&bus->mdio_lock);
290 return (hi << 16) | lo;
294 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
296 struct mii_bus *bus = priv->mii_bus;
300 split_addr((u32) reg, &r1, &r2, &r3);
302 hi = (u16) (val >> 16);
304 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, 0x18, 0, r3);
307 usleep_range(1000, 2000); /* wait for the page switch to propagate */
308 if (priv->mii_lo_first) {
309 bus->write(bus, 0x10 | r2, r1, lo);
310 bus->write(bus, 0x10 | r2, r1 + 1, hi);
312 bus->write(bus, 0x10 | r2, r1 + 1, hi);
313 bus->write(bus, 0x10 | r2, r1, lo);
316 mutex_unlock(&bus->mdio_lock);
320 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
321 u16 dbg_addr, u16 dbg_data)
323 struct mii_bus *bus = priv->mii_bus;
325 mutex_lock(&bus->mdio_lock);
326 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
327 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
328 mutex_unlock(&bus->mdio_lock);
332 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
334 struct mii_bus *bus = priv->mii_bus;
336 mutex_lock(&bus->mdio_lock);
337 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
338 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
339 mutex_unlock(&bus->mdio_lock);
343 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
347 lockdep_assert_held(&priv->reg_mutex);
349 v = priv->read(priv, reg);
352 priv->write(priv, reg, v);
358 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
362 lockdep_assert_held(&priv->reg_mutex);
364 v = priv->read(priv, reg);
366 priv->write(priv, reg, v);
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
375 for (i = 0; i < timeout; i++) {
378 t = priv->read(priv, reg);
379 if ((t & mask) == val)
382 usleep_range(1000, 2000);
389 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
394 lockdep_assert_held(&priv->mib_lock);
396 if (chip_is_ar8327(priv))
397 mib_func = AR8327_REG_MIB_FUNC;
399 mib_func = AR8216_REG_MIB_FUNC;
401 mutex_lock(&priv->reg_mutex);
402 /* Capture the hardware statistics for all ports */
403 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
404 mutex_unlock(&priv->reg_mutex);
406 /* Wait for the capturing to complete. */
407 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
418 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
424 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
426 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
430 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
436 WARN_ON(port >= priv->dev.ports);
438 lockdep_assert_held(&priv->mib_lock);
440 if (chip_is_ar8327(priv))
441 base = AR8327_REG_PORT_STATS_BASE(port);
442 else if (chip_is_ar8236(priv) ||
443 chip_is_ar8316(priv))
444 base = AR8236_REG_PORT_STATS_BASE(port);
446 base = AR8216_REG_PORT_STATS_BASE(port);
448 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
449 for (i = 0; i < priv->chip->num_mibs; i++) {
450 const struct ar8xxx_mib_desc *mib;
453 mib = &priv->chip->mib_decs[i];
454 t = priv->read(priv, base + mib->offset);
455 if (mib->size == 2) {
458 hi = priv->read(priv, base + mib->offset + 4);
470 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
471 struct switch_port_link *link)
476 memset(link, '\0', sizeof(*link));
478 status = priv->chip->read_port_status(priv, port);
480 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
482 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
489 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
490 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
491 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
493 speed = (status & AR8216_PORT_STATUS_SPEED) >>
494 AR8216_PORT_STATUS_SPEED_S;
497 case AR8216_PORT_SPEED_10M:
498 link->speed = SWITCH_PORT_SPEED_10;
500 case AR8216_PORT_SPEED_100M:
501 link->speed = SWITCH_PORT_SPEED_100;
503 case AR8216_PORT_SPEED_1000M:
504 link->speed = SWITCH_PORT_SPEED_1000;
507 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
512 static struct sk_buff *
513 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
515 struct ar8xxx_priv *priv = dev->phy_ptr;
524 if (unlikely(skb_headroom(skb) < 2)) {
525 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
529 buf = skb_push(skb, 2);
537 dev_kfree_skb_any(skb);
542 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
544 struct ar8xxx_priv *priv;
552 /* don't strip the header if vlan mode is disabled */
556 /* strip header, get vlan id */
560 /* check for vlan header presence */
561 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
566 /* no need to fix up packets coming from a tagged source */
567 if (priv->vlan_tagged & (1 << port))
570 /* lookup port vid from local table, the switch passes an invalid vlan id */
571 vlan = priv->vlan_id[priv->pvid[port]];
574 buf[14 + 2] |= vlan >> 8;
575 buf[15 + 2] = vlan & 0xff;
579 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
585 t = priv->read(priv, reg);
586 if ((t & mask) == val)
595 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
596 (unsigned int) reg, t, mask, val);
601 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
603 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
605 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
606 val &= AR8216_VTUDATA_MEMBER;
607 val |= AR8216_VTUDATA_VALID;
608 priv->write(priv, AR8216_REG_VTU_DATA, val);
610 op |= AR8216_VTU_ACTIVE;
611 priv->write(priv, AR8216_REG_VTU, op);
615 ar8216_vtu_flush(struct ar8xxx_priv *priv)
617 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
621 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
625 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
626 ar8216_vtu_op(priv, op, port_mask);
630 ar8216_atu_flush(struct ar8xxx_priv *priv)
634 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
636 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
642 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
644 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
648 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
649 u32 members, u32 pvid)
653 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
654 header = AR8216_PORT_CTRL_HEADER;
658 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
659 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
660 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
661 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
662 AR8216_PORT_CTRL_LEARN | header |
663 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
664 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
666 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
667 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
668 AR8216_PORT_VLAN_DEFAULT_ID,
669 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
670 (ingress << AR8216_PORT_VLAN_MODE_S) |
671 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
675 ar8216_hw_init(struct ar8xxx_priv *priv)
681 ar8216_init_globals(struct ar8xxx_priv *priv)
683 /* standard atheros magic */
684 priv->write(priv, 0x38, 0xc000050e);
686 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
687 AR8216_GCTRL_MTU, 1518 + 8 + 2);
691 ar8216_init_port(struct ar8xxx_priv *priv, int port)
693 /* Enable port learning and tx */
694 priv->write(priv, AR8216_REG_PORT_CTRL(port),
695 AR8216_PORT_CTRL_LEARN |
696 (4 << AR8216_PORT_CTRL_STATE_S));
698 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
700 if (port == AR8216_PORT_CPU) {
701 priv->write(priv, AR8216_REG_PORT_STATUS(port),
702 AR8216_PORT_STATUS_LINK_UP |
703 (ar8xxx_has_gige(priv) ?
704 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
705 AR8216_PORT_STATUS_TXMAC |
706 AR8216_PORT_STATUS_RXMAC |
707 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
708 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
709 AR8216_PORT_STATUS_DUPLEX);
711 priv->write(priv, AR8216_REG_PORT_STATUS(port),
712 AR8216_PORT_STATUS_LINK_AUTO);
716 static const struct ar8xxx_chip ar8216_chip = {
717 .caps = AR8XXX_CAP_MIB_COUNTERS,
719 .hw_init = ar8216_hw_init,
720 .init_globals = ar8216_init_globals,
721 .init_port = ar8216_init_port,
722 .setup_port = ar8216_setup_port,
723 .read_port_status = ar8216_read_port_status,
724 .atu_flush = ar8216_atu_flush,
725 .vtu_flush = ar8216_vtu_flush,
726 .vtu_load_vlan = ar8216_vtu_load_vlan,
728 .num_mibs = ARRAY_SIZE(ar8216_mibs),
729 .mib_decs = ar8216_mibs,
733 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
734 u32 members, u32 pvid)
736 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
737 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
738 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
739 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
740 AR8216_PORT_CTRL_LEARN |
741 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
742 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
744 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
745 AR8236_PORT_VLAN_DEFAULT_ID,
746 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
748 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
749 AR8236_PORT_VLAN2_VLAN_MODE |
750 AR8236_PORT_VLAN2_MEMBER,
751 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
752 (members << AR8236_PORT_VLAN2_MEMBER_S));
756 ar8236_hw_init(struct ar8xxx_priv *priv)
761 if (priv->initialized)
764 /* Initialize the PHYs */
766 for (i = 0; i < 5; i++) {
767 mdiobus_write(bus, i, MII_ADVERTISE,
768 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
769 ADVERTISE_PAUSE_ASYM);
770 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
774 priv->initialized = true;
779 ar8236_init_globals(struct ar8xxx_priv *priv)
781 /* enable jumbo frames */
782 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
783 AR8316_GCTRL_MTU, 9018 + 8 + 2);
785 /* Enable MIB counters */
786 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
787 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
791 static const struct ar8xxx_chip ar8236_chip = {
792 .caps = AR8XXX_CAP_MIB_COUNTERS,
793 .hw_init = ar8236_hw_init,
794 .init_globals = ar8236_init_globals,
795 .init_port = ar8216_init_port,
796 .setup_port = ar8236_setup_port,
797 .read_port_status = ar8216_read_port_status,
798 .atu_flush = ar8216_atu_flush,
799 .vtu_flush = ar8216_vtu_flush,
800 .vtu_load_vlan = ar8216_vtu_load_vlan,
802 .num_mibs = ARRAY_SIZE(ar8236_mibs),
803 .mib_decs = ar8236_mibs,
807 ar8316_hw_init(struct ar8xxx_priv *priv)
813 val = priv->read(priv, AR8316_REG_POSTRIP);
815 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
816 if (priv->port4_phy) {
817 /* value taken from Ubiquiti RouterStation Pro */
819 pr_info("ar8316: Using port 4 as PHY\n");
822 pr_info("ar8316: Using port 4 as switch port\n");
824 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
825 /* value taken from AVM Fritz!Box 7390 sources */
828 /* no known value for phy interface */
829 pr_err("ar8316: unsupported mii mode: %d.\n",
830 priv->phy->interface);
837 priv->write(priv, AR8316_REG_POSTRIP, newval);
839 if (priv->port4_phy &&
840 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
841 /* work around for phy4 rgmii mode */
842 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
844 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
846 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
850 /* Initialize the ports */
852 for (i = 0; i < 5; i++) {
853 /* initialize the port itself */
854 mdiobus_write(bus, i, MII_ADVERTISE,
855 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
856 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
857 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
863 priv->initialized = true;
868 ar8316_init_globals(struct ar8xxx_priv *priv)
870 /* standard atheros magic */
871 priv->write(priv, 0x38, 0xc000050e);
873 /* enable cpu port to receive multicast and broadcast frames */
874 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
876 /* enable jumbo frames */
877 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
878 AR8316_GCTRL_MTU, 9018 + 8 + 2);
880 /* Enable MIB counters */
881 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
882 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
886 static const struct ar8xxx_chip ar8316_chip = {
887 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
888 .hw_init = ar8316_hw_init,
889 .init_globals = ar8316_init_globals,
890 .init_port = ar8216_init_port,
891 .setup_port = ar8216_setup_port,
892 .read_port_status = ar8216_read_port_status,
893 .atu_flush = ar8216_atu_flush,
894 .vtu_flush = ar8216_vtu_flush,
895 .vtu_load_vlan = ar8216_vtu_load_vlan,
897 .num_mibs = ARRAY_SIZE(ar8236_mibs),
898 .mib_decs = ar8236_mibs,
902 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
914 case AR8327_PAD_MAC2MAC_MII:
915 t = AR8327_PAD_MAC_MII_EN;
917 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
919 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
922 case AR8327_PAD_MAC2MAC_GMII:
923 t = AR8327_PAD_MAC_GMII_EN;
925 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
927 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
930 case AR8327_PAD_MAC_SGMII:
931 t = AR8327_PAD_SGMII_EN;
934 * WAR for the QUalcomm Atheros AP136 board.
935 * It seems that RGMII TX/RX delay settings needs to be
936 * applied for SGMII mode as well, The ethernet is not
937 * reliable without this.
939 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
940 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
941 if (cfg->rxclk_delay_en)
942 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
943 if (cfg->txclk_delay_en)
944 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
946 if (cfg->sgmii_delay_en)
947 t |= AR8327_PAD_SGMII_DELAY_EN;
951 case AR8327_PAD_MAC2PHY_MII:
952 t = AR8327_PAD_PHY_MII_EN;
954 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
956 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
959 case AR8327_PAD_MAC2PHY_GMII:
960 t = AR8327_PAD_PHY_GMII_EN;
961 if (cfg->pipe_rxclk_sel)
962 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
964 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
966 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
969 case AR8327_PAD_MAC_RGMII:
970 t = AR8327_PAD_RGMII_EN;
971 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
972 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
973 if (cfg->rxclk_delay_en)
974 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
975 if (cfg->txclk_delay_en)
976 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
979 case AR8327_PAD_PHY_GMII:
980 t = AR8327_PAD_PHYX_GMII_EN;
983 case AR8327_PAD_PHY_RGMII:
984 t = AR8327_PAD_PHYX_RGMII_EN;
987 case AR8327_PAD_PHY_MII:
988 t = AR8327_PAD_PHYX_MII_EN;
996 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
998 switch (priv->chip_rev) {
1000 /* For 100M waveform */
1001 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1002 /* Turn on Gigabit clock */
1003 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1007 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1008 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1011 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1012 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1014 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1015 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1016 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1022 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1026 if (!cfg->force_link)
1027 return AR8216_PORT_STATUS_LINK_AUTO;
1029 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1030 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1031 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1032 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1034 switch (cfg->speed) {
1035 case AR8327_PORT_SPEED_10:
1036 t |= AR8216_PORT_SPEED_10M;
1038 case AR8327_PORT_SPEED_100:
1039 t |= AR8216_PORT_SPEED_100M;
1041 case AR8327_PORT_SPEED_1000:
1042 t |= AR8216_PORT_SPEED_1000M;
1050 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1051 struct ar8327_platform_data *pdata)
1053 struct ar8327_led_cfg *led_cfg;
1054 struct ar8327_data *data;
1061 data = &priv->chip_data.ar8327;
1063 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1064 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1066 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1067 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1068 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1069 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1070 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1071 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1073 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1076 led_cfg = pdata->led_cfg;
1078 if (led_cfg->open_drain)
1079 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1081 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1083 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1084 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1085 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1086 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1089 if (new_pos != pos) {
1090 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1091 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1099 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1101 const __be32 *paddr;
1105 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1106 if (!paddr || len < (2 * sizeof(*paddr)))
1109 len /= sizeof(*paddr);
1111 for (i = 0; i < len - 1; i += 2) {
1115 reg = be32_to_cpup(paddr + i);
1116 val = be32_to_cpup(paddr + i + 1);
1119 case AR8327_REG_PORT_STATUS(0):
1120 priv->chip_data.ar8327.port0_status = val;
1122 case AR8327_REG_PORT_STATUS(6):
1123 priv->chip_data.ar8327.port6_status = val;
1126 priv->write(priv, reg, val);
1135 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1142 ar8327_hw_init(struct ar8xxx_priv *priv)
1144 struct mii_bus *bus;
1148 if (priv->phy->dev.of_node)
1149 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1151 ret = ar8327_hw_config_pdata(priv,
1152 priv->phy->dev.platform_data);
1157 bus = priv->mii_bus;
1158 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1159 ar8327_phy_fixup(priv, i);
1161 /* start aneg on the PHY */
1162 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1163 ADVERTISE_PAUSE_CAP |
1164 ADVERTISE_PAUSE_ASYM);
1165 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1166 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1175 ar8327_init_globals(struct ar8xxx_priv *priv)
1179 /* enable CPU port and disable mirror port */
1180 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1181 AR8327_FWD_CTRL0_MIRROR_PORT;
1182 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1184 /* forward multicast and broadcast frames to CPU */
1185 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1186 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1187 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1188 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1191 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1192 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1194 /* Enable MIB counters */
1195 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1196 AR8327_MODULE_EN_MIB);
1200 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1204 if (port == AR8216_PORT_CPU)
1205 t = priv->chip_data.ar8327.port0_status;
1207 t = priv->chip_data.ar8327.port6_status;
1209 t = AR8216_PORT_STATUS_LINK_AUTO;
1211 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1212 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1214 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1215 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1216 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1218 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1219 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1221 t = AR8327_PORT_LOOKUP_LEARN;
1222 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1223 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1227 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1229 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1233 ar8327_atu_flush(struct ar8xxx_priv *priv)
1237 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1238 AR8327_ATU_FUNC_BUSY, 0);
1240 priv->write(priv, AR8327_REG_ATU_FUNC,
1241 AR8327_ATU_FUNC_OP_FLUSH);
1247 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1249 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1250 AR8327_VTU_FUNC1_BUSY, 0))
1253 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1254 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1256 op |= AR8327_VTU_FUNC1_BUSY;
1257 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1261 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1263 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1267 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1273 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1274 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1275 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1278 if ((port_mask & BIT(i)) == 0)
1279 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1280 else if (priv->vlan == 0)
1281 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1282 else if (priv->vlan_tagged & BIT(i))
1283 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1285 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1287 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1289 ar8327_vtu_op(priv, op, val);
1293 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1294 u32 members, u32 pvid)
1299 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1300 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1301 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1303 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1305 case AR8216_OUT_KEEP:
1306 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1308 case AR8216_OUT_STRIP_VLAN:
1309 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1311 case AR8216_OUT_ADD_VLAN:
1312 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1316 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1317 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1318 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1321 t |= AR8327_PORT_LOOKUP_LEARN;
1322 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1323 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1324 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1327 static const struct ar8xxx_chip ar8327_chip = {
1328 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1329 .hw_init = ar8327_hw_init,
1330 .init_globals = ar8327_init_globals,
1331 .init_port = ar8327_init_port,
1332 .setup_port = ar8327_setup_port,
1333 .read_port_status = ar8327_read_port_status,
1334 .atu_flush = ar8327_atu_flush,
1335 .vtu_flush = ar8327_vtu_flush,
1336 .vtu_load_vlan = ar8327_vtu_load_vlan,
1338 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1339 .mib_decs = ar8236_mibs,
1343 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1344 struct switch_val *val)
1346 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1347 priv->vlan = !!val->value.i;
1352 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1353 struct switch_val *val)
1355 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1356 val->value.i = priv->vlan;
1362 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1364 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1366 /* make sure no invalid PVIDs get set */
1368 if (vlan >= dev->vlans)
1371 priv->pvid[port] = vlan;
1376 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1378 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1379 *vlan = priv->pvid[port];
1384 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1385 struct switch_val *val)
1387 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1388 priv->vlan_id[val->port_vlan] = val->value.i;
1393 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1394 struct switch_val *val)
1396 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1397 val->value.i = priv->vlan_id[val->port_vlan];
1402 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1403 struct switch_port_link *link)
1405 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1407 ar8216_read_port_link(priv, port, link);
1412 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1414 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1415 u8 ports = priv->vlan_table[val->port_vlan];
1419 for (i = 0; i < dev->ports; i++) {
1420 struct switch_port *p;
1422 if (!(ports & (1 << i)))
1425 p = &val->value.ports[val->len++];
1427 if (priv->vlan_tagged & (1 << i))
1428 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1436 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1438 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1439 u8 *vt = &priv->vlan_table[val->port_vlan];
1443 for (i = 0; i < val->len; i++) {
1444 struct switch_port *p = &val->value.ports[i];
1446 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1447 priv->vlan_tagged |= (1 << p->id);
1449 priv->vlan_tagged &= ~(1 << p->id);
1450 priv->pvid[p->id] = val->port_vlan;
1452 /* make sure that an untagged port does not
1453 * appear in other vlans */
1454 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1455 if (j == val->port_vlan)
1457 priv->vlan_table[j] &= ~(1 << p->id);
1467 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1471 /* reset all mirror registers */
1472 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1473 AR8327_FWD_CTRL0_MIRROR_PORT,
1474 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1475 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1476 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1477 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1480 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1481 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1485 /* now enable mirroring if necessary */
1486 if (priv->source_port >= AR8327_NUM_PORTS ||
1487 priv->monitor_port >= AR8327_NUM_PORTS ||
1488 priv->source_port == priv->monitor_port) {
1492 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1493 AR8327_FWD_CTRL0_MIRROR_PORT,
1494 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1496 if (priv->mirror_rx)
1497 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1498 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1499 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1501 if (priv->mirror_tx)
1502 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1503 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1504 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1508 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1512 /* reset all mirror registers */
1513 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1514 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1515 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1516 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1517 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1518 AR8216_PORT_CTRL_MIRROR_RX,
1521 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1522 AR8216_PORT_CTRL_MIRROR_TX,
1526 /* now enable mirroring if necessary */
1527 if (priv->source_port >= AR8216_NUM_PORTS ||
1528 priv->monitor_port >= AR8216_NUM_PORTS ||
1529 priv->source_port == priv->monitor_port) {
1533 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1534 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1535 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1537 if (priv->mirror_rx)
1538 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1539 AR8216_PORT_CTRL_MIRROR_RX,
1540 AR8216_PORT_CTRL_MIRROR_RX);
1542 if (priv->mirror_tx)
1543 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1544 AR8216_PORT_CTRL_MIRROR_TX,
1545 AR8216_PORT_CTRL_MIRROR_TX);
1549 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1551 if (chip_is_ar8327(priv)) {
1552 ar8327_set_mirror_regs(priv);
1554 ar8216_set_mirror_regs(priv);
1559 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1561 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1562 u8 portmask[AR8X16_MAX_PORTS];
1565 mutex_lock(&priv->reg_mutex);
1566 /* flush all vlan translation unit entries */
1567 priv->chip->vtu_flush(priv);
1569 memset(portmask, 0, sizeof(portmask));
1571 /* calculate the port destination masks and load vlans
1572 * into the vlan translation unit */
1573 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1574 u8 vp = priv->vlan_table[j];
1579 for (i = 0; i < dev->ports; i++) {
1582 portmask[i] |= vp & ~mask;
1585 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1586 priv->vlan_table[j]);
1590 * isolate all ports, but connect them to the cpu port */
1591 for (i = 0; i < dev->ports; i++) {
1592 if (i == AR8216_PORT_CPU)
1595 portmask[i] = 1 << AR8216_PORT_CPU;
1596 portmask[AR8216_PORT_CPU] |= (1 << i);
1600 /* update the port destination mask registers and tag settings */
1601 for (i = 0; i < dev->ports; i++) {
1602 int egress, ingress;
1606 pvid = priv->vlan_id[priv->pvid[i]];
1607 if (priv->vlan_tagged & (1 << i))
1608 egress = AR8216_OUT_ADD_VLAN;
1610 egress = AR8216_OUT_STRIP_VLAN;
1611 ingress = AR8216_IN_SECURE;
1614 egress = AR8216_OUT_KEEP;
1615 ingress = AR8216_IN_PORT_ONLY;
1618 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1622 ar8xxx_set_mirror_regs(priv);
1624 mutex_unlock(&priv->reg_mutex);
1629 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1631 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1634 mutex_lock(&priv->reg_mutex);
1635 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1636 offsetof(struct ar8xxx_priv, vlan));
1638 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1639 priv->vlan_id[i] = i;
1641 /* Configure all ports */
1642 for (i = 0; i < dev->ports; i++)
1643 priv->chip->init_port(priv, i);
1645 priv->mirror_rx = false;
1646 priv->mirror_tx = false;
1647 priv->source_port = 0;
1648 priv->monitor_port = 0;
1650 priv->chip->init_globals(priv);
1652 mutex_unlock(&priv->reg_mutex);
1654 return ar8xxx_sw_hw_apply(dev);
1658 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1659 const struct switch_attr *attr,
1660 struct switch_val *val)
1662 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1666 if (!ar8xxx_has_mib_counters(priv))
1669 mutex_lock(&priv->mib_lock);
1671 len = priv->dev.ports * priv->chip->num_mibs *
1672 sizeof(*priv->mib_stats);
1673 memset(priv->mib_stats, '\0', len);
1674 ret = ar8xxx_mib_flush(priv);
1681 mutex_unlock(&priv->mib_lock);
1686 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1687 const struct switch_attr *attr,
1688 struct switch_val *val)
1690 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1692 mutex_lock(&priv->reg_mutex);
1693 priv->mirror_rx = !!val->value.i;
1694 ar8xxx_set_mirror_regs(priv);
1695 mutex_unlock(&priv->reg_mutex);
1701 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1702 const struct switch_attr *attr,
1703 struct switch_val *val)
1705 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1706 val->value.i = priv->mirror_rx;
1711 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1712 const struct switch_attr *attr,
1713 struct switch_val *val)
1715 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1717 mutex_lock(&priv->reg_mutex);
1718 priv->mirror_tx = !!val->value.i;
1719 ar8xxx_set_mirror_regs(priv);
1720 mutex_unlock(&priv->reg_mutex);
1726 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1727 const struct switch_attr *attr,
1728 struct switch_val *val)
1730 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1731 val->value.i = priv->mirror_tx;
1736 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1737 const struct switch_attr *attr,
1738 struct switch_val *val)
1740 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1742 mutex_lock(&priv->reg_mutex);
1743 priv->monitor_port = val->value.i;
1744 ar8xxx_set_mirror_regs(priv);
1745 mutex_unlock(&priv->reg_mutex);
1751 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1752 const struct switch_attr *attr,
1753 struct switch_val *val)
1755 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1756 val->value.i = priv->monitor_port;
1761 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1762 const struct switch_attr *attr,
1763 struct switch_val *val)
1765 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1767 mutex_lock(&priv->reg_mutex);
1768 priv->source_port = val->value.i;
1769 ar8xxx_set_mirror_regs(priv);
1770 mutex_unlock(&priv->reg_mutex);
1776 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1777 const struct switch_attr *attr,
1778 struct switch_val *val)
1780 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1781 val->value.i = priv->source_port;
1786 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1787 const struct switch_attr *attr,
1788 struct switch_val *val)
1790 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1794 if (!ar8xxx_has_mib_counters(priv))
1797 port = val->port_vlan;
1798 if (port >= dev->ports)
1801 mutex_lock(&priv->mib_lock);
1802 ret = ar8xxx_mib_capture(priv);
1806 ar8xxx_mib_fetch_port_stat(priv, port, true);
1811 mutex_unlock(&priv->mib_lock);
1816 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1817 const struct switch_attr *attr,
1818 struct switch_val *val)
1820 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1821 const struct ar8xxx_chip *chip = priv->chip;
1825 char *buf = priv->buf;
1828 if (!ar8xxx_has_mib_counters(priv))
1831 port = val->port_vlan;
1832 if (port >= dev->ports)
1835 mutex_lock(&priv->mib_lock);
1836 ret = ar8xxx_mib_capture(priv);
1840 ar8xxx_mib_fetch_port_stat(priv, port, false);
1842 len += snprintf(buf + len, sizeof(priv->buf) - len,
1843 "Port %d MIB counters\n",
1846 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1847 for (i = 0; i < chip->num_mibs; i++)
1848 len += snprintf(buf + len, sizeof(priv->buf) - len,
1850 chip->mib_decs[i].name,
1859 mutex_unlock(&priv->mib_lock);
1863 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1865 .type = SWITCH_TYPE_INT,
1866 .name = "enable_vlan",
1867 .description = "Enable VLAN mode",
1868 .set = ar8xxx_sw_set_vlan,
1869 .get = ar8xxx_sw_get_vlan,
1873 .type = SWITCH_TYPE_NOVAL,
1874 .name = "reset_mibs",
1875 .description = "Reset all MIB counters",
1876 .set = ar8xxx_sw_set_reset_mibs,
1879 .type = SWITCH_TYPE_INT,
1880 .name = "enable_mirror_rx",
1881 .description = "Enable mirroring of RX packets",
1882 .set = ar8xxx_sw_set_mirror_rx_enable,
1883 .get = ar8xxx_sw_get_mirror_rx_enable,
1887 .type = SWITCH_TYPE_INT,
1888 .name = "enable_mirror_tx",
1889 .description = "Enable mirroring of TX packets",
1890 .set = ar8xxx_sw_set_mirror_tx_enable,
1891 .get = ar8xxx_sw_get_mirror_tx_enable,
1895 .type = SWITCH_TYPE_INT,
1896 .name = "mirror_monitor_port",
1897 .description = "Mirror monitor port",
1898 .set = ar8xxx_sw_set_mirror_monitor_port,
1899 .get = ar8xxx_sw_get_mirror_monitor_port,
1900 .max = AR8216_NUM_PORTS - 1
1903 .type = SWITCH_TYPE_INT,
1904 .name = "mirror_source_port",
1905 .description = "Mirror source port",
1906 .set = ar8xxx_sw_set_mirror_source_port,
1907 .get = ar8xxx_sw_get_mirror_source_port,
1908 .max = AR8216_NUM_PORTS - 1
1912 static struct switch_attr ar8327_sw_attr_globals[] = {
1914 .type = SWITCH_TYPE_INT,
1915 .name = "enable_vlan",
1916 .description = "Enable VLAN mode",
1917 .set = ar8xxx_sw_set_vlan,
1918 .get = ar8xxx_sw_get_vlan,
1922 .type = SWITCH_TYPE_NOVAL,
1923 .name = "reset_mibs",
1924 .description = "Reset all MIB counters",
1925 .set = ar8xxx_sw_set_reset_mibs,
1928 .type = SWITCH_TYPE_INT,
1929 .name = "enable_mirror_rx",
1930 .description = "Enable mirroring of RX packets",
1931 .set = ar8xxx_sw_set_mirror_rx_enable,
1932 .get = ar8xxx_sw_get_mirror_rx_enable,
1936 .type = SWITCH_TYPE_INT,
1937 .name = "enable_mirror_tx",
1938 .description = "Enable mirroring of TX packets",
1939 .set = ar8xxx_sw_set_mirror_tx_enable,
1940 .get = ar8xxx_sw_get_mirror_tx_enable,
1944 .type = SWITCH_TYPE_INT,
1945 .name = "mirror_monitor_port",
1946 .description = "Mirror monitor port",
1947 .set = ar8xxx_sw_set_mirror_monitor_port,
1948 .get = ar8xxx_sw_get_mirror_monitor_port,
1949 .max = AR8327_NUM_PORTS - 1
1952 .type = SWITCH_TYPE_INT,
1953 .name = "mirror_source_port",
1954 .description = "Mirror source port",
1955 .set = ar8xxx_sw_set_mirror_source_port,
1956 .get = ar8xxx_sw_get_mirror_source_port,
1957 .max = AR8327_NUM_PORTS - 1
1961 static struct switch_attr ar8xxx_sw_attr_port[] = {
1963 .type = SWITCH_TYPE_NOVAL,
1964 .name = "reset_mib",
1965 .description = "Reset single port MIB counters",
1966 .set = ar8xxx_sw_set_port_reset_mib,
1969 .type = SWITCH_TYPE_STRING,
1971 .description = "Get port's MIB counters",
1973 .get = ar8xxx_sw_get_port_mib,
1977 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1979 .type = SWITCH_TYPE_INT,
1981 .description = "VLAN ID (0-4094)",
1982 .set = ar8xxx_sw_set_vid,
1983 .get = ar8xxx_sw_get_vid,
1988 static const struct switch_dev_ops ar8xxx_sw_ops = {
1990 .attr = ar8xxx_sw_attr_globals,
1991 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1994 .attr = ar8xxx_sw_attr_port,
1995 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1998 .attr = ar8xxx_sw_attr_vlan,
1999 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2001 .get_port_pvid = ar8xxx_sw_get_pvid,
2002 .set_port_pvid = ar8xxx_sw_set_pvid,
2003 .get_vlan_ports = ar8xxx_sw_get_ports,
2004 .set_vlan_ports = ar8xxx_sw_set_ports,
2005 .apply_config = ar8xxx_sw_hw_apply,
2006 .reset_switch = ar8xxx_sw_reset_switch,
2007 .get_port_link = ar8xxx_sw_get_port_link,
2010 static const struct switch_dev_ops ar8327_sw_ops = {
2012 .attr = ar8327_sw_attr_globals,
2013 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2016 .attr = ar8xxx_sw_attr_port,
2017 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2020 .attr = ar8xxx_sw_attr_vlan,
2021 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2023 .get_port_pvid = ar8xxx_sw_get_pvid,
2024 .set_port_pvid = ar8xxx_sw_set_pvid,
2025 .get_vlan_ports = ar8xxx_sw_get_ports,
2026 .set_vlan_ports = ar8xxx_sw_set_ports,
2027 .apply_config = ar8xxx_sw_hw_apply,
2028 .reset_switch = ar8xxx_sw_reset_switch,
2029 .get_port_link = ar8xxx_sw_get_port_link,
2033 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2039 val = priv->read(priv, AR8216_REG_CTRL);
2043 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2044 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2047 val = priv->read(priv, AR8216_REG_CTRL);
2051 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2056 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2057 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2059 switch (priv->chip_ver) {
2060 case AR8XXX_VER_AR8216:
2061 priv->chip = &ar8216_chip;
2063 case AR8XXX_VER_AR8236:
2064 priv->chip = &ar8236_chip;
2066 case AR8XXX_VER_AR8316:
2067 priv->chip = &ar8316_chip;
2069 case AR8XXX_VER_AR8327:
2070 priv->mii_lo_first = true;
2071 priv->chip = &ar8327_chip;
2074 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2075 priv->chip_ver, priv->chip_rev);
2084 ar8xxx_mib_work_func(struct work_struct *work)
2086 struct ar8xxx_priv *priv;
2089 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2091 mutex_lock(&priv->mib_lock);
2093 err = ar8xxx_mib_capture(priv);
2097 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2100 priv->mib_next_port++;
2101 if (priv->mib_next_port >= priv->dev.ports)
2102 priv->mib_next_port = 0;
2104 mutex_unlock(&priv->mib_lock);
2105 schedule_delayed_work(&priv->mib_work,
2106 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2110 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2114 if (!ar8xxx_has_mib_counters(priv))
2117 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2119 len = priv->dev.ports * priv->chip->num_mibs *
2120 sizeof(*priv->mib_stats);
2121 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2123 if (!priv->mib_stats)
2130 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2132 if (!ar8xxx_has_mib_counters(priv))
2135 schedule_delayed_work(&priv->mib_work,
2136 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2140 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2142 if (!ar8xxx_has_mib_counters(priv))
2145 cancel_delayed_work(&priv->mib_work);
2148 static struct ar8xxx_priv *
2151 struct ar8xxx_priv *priv;
2153 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2157 mutex_init(&priv->reg_mutex);
2158 mutex_init(&priv->mib_lock);
2159 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2165 ar8xxx_free(struct ar8xxx_priv *priv)
2167 kfree(priv->mib_stats);
2171 static struct ar8xxx_priv *
2172 ar8xxx_create_mii(struct mii_bus *bus)
2174 struct ar8xxx_priv *priv;
2176 priv = ar8xxx_create();
2178 priv->mii_bus = bus;
2179 priv->read = ar8xxx_mii_read;
2180 priv->write = ar8xxx_mii_write;
2187 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2189 struct switch_dev *swdev;
2192 ret = ar8xxx_id_chip(priv);
2197 swdev->cpu_port = AR8216_PORT_CPU;
2198 swdev->ops = &ar8xxx_sw_ops;
2200 if (chip_is_ar8316(priv)) {
2201 swdev->name = "Atheros AR8316";
2202 swdev->vlans = AR8X16_MAX_VLANS;
2203 swdev->ports = AR8216_NUM_PORTS;
2204 } else if (chip_is_ar8236(priv)) {
2205 swdev->name = "Atheros AR8236";
2206 swdev->vlans = AR8216_NUM_VLANS;
2207 swdev->ports = AR8216_NUM_PORTS;
2208 } else if (chip_is_ar8327(priv)) {
2209 swdev->name = "Atheros AR8327";
2210 swdev->vlans = AR8X16_MAX_VLANS;
2211 swdev->ports = AR8327_NUM_PORTS;
2212 swdev->ops = &ar8327_sw_ops;
2214 swdev->name = "Atheros AR8216";
2215 swdev->vlans = AR8216_NUM_VLANS;
2216 swdev->ports = AR8216_NUM_PORTS;
2219 ret = ar8xxx_mib_init(priv);
2227 ar8xxx_start(struct ar8xxx_priv *priv)
2233 ret = priv->chip->hw_init(priv);
2237 ret = ar8xxx_sw_reset_switch(&priv->dev);
2243 ar8xxx_mib_start(priv);
2249 ar8xxx_phy_config_init(struct phy_device *phydev)
2251 struct ar8xxx_priv *priv = phydev->priv;
2252 struct net_device *dev = phydev->attached_dev;
2258 if (chip_is_ar8327(priv))
2263 if (phydev->addr != 0) {
2264 if (chip_is_ar8316(priv)) {
2265 /* switch device has been initialized, reinit */
2266 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2267 priv->initialized = false;
2268 priv->port4_phy = true;
2269 ar8316_hw_init(priv);
2276 ret = ar8xxx_start(priv);
2280 /* VID fixup only needed on ar8216 */
2281 if (chip_is_ar8216(priv)) {
2282 dev->phy_ptr = priv;
2283 dev->priv_flags |= IFF_NO_IP_ALIGN;
2284 dev->eth_mangle_rx = ar8216_mangle_rx;
2285 dev->eth_mangle_tx = ar8216_mangle_tx;
2292 ar8xxx_phy_read_status(struct phy_device *phydev)
2294 struct ar8xxx_priv *priv = phydev->priv;
2295 struct switch_port_link link;
2298 if (phydev->addr != 0)
2299 return genphy_read_status(phydev);
2301 ar8216_read_port_link(priv, phydev->addr, &link);
2302 phydev->link = !!link.link;
2306 switch (link.speed) {
2307 case SWITCH_PORT_SPEED_10:
2308 phydev->speed = SPEED_10;
2310 case SWITCH_PORT_SPEED_100:
2311 phydev->speed = SPEED_100;
2313 case SWITCH_PORT_SPEED_1000:
2314 phydev->speed = SPEED_1000;
2319 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2321 /* flush the address translation unit */
2322 mutex_lock(&priv->reg_mutex);
2323 ret = priv->chip->atu_flush(priv);
2324 mutex_unlock(&priv->reg_mutex);
2326 phydev->state = PHY_RUNNING;
2327 netif_carrier_on(phydev->attached_dev);
2328 phydev->adjust_link(phydev->attached_dev);
2334 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2336 if (phydev->addr == 0)
2339 return genphy_config_aneg(phydev);
2342 static const u32 ar8xxx_phy_ids[] = {
2350 ar8xxx_phy_match(u32 phy_id)
2354 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2355 if (phy_id == ar8xxx_phy_ids[i])
2362 ar8xxx_is_possible(struct mii_bus *bus)
2366 for (i = 0; i < 4; i++) {
2369 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2370 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2371 if (!ar8xxx_phy_match(phy_id)) {
2372 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2373 dev_name(&bus->dev), i, phy_id);
2382 ar8xxx_phy_probe(struct phy_device *phydev)
2384 struct ar8xxx_priv *priv;
2385 struct switch_dev *swdev;
2388 /* skip PHYs at unused adresses */
2389 if (phydev->addr != 0 && phydev->addr != 4)
2392 if (!ar8xxx_is_possible(phydev->bus))
2395 mutex_lock(&ar8xxx_dev_list_lock);
2396 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2397 if (priv->mii_bus == phydev->bus)
2400 priv = ar8xxx_create_mii(phydev->bus);
2406 ret = ar8xxx_probe_switch(priv);
2411 swdev->alias = dev_name(&priv->mii_bus->dev);
2412 ret = register_switch(swdev, NULL);
2416 pr_info("%s: %s rev. %u switch registered on %s\n",
2417 swdev->devname, swdev->name, priv->chip_rev,
2418 dev_name(&priv->mii_bus->dev));
2423 if (phydev->addr == 0) {
2424 if (ar8xxx_has_gige(priv)) {
2425 phydev->supported = SUPPORTED_1000baseT_Full;
2426 phydev->advertising = ADVERTISED_1000baseT_Full;
2428 phydev->supported = SUPPORTED_100baseT_Full;
2429 phydev->advertising = ADVERTISED_100baseT_Full;
2432 if (chip_is_ar8327(priv)) {
2435 ret = ar8xxx_start(priv);
2437 goto err_unregister_switch;
2440 if (ar8xxx_has_gige(priv)) {
2441 phydev->supported |= SUPPORTED_1000baseT_Full;
2442 phydev->advertising |= ADVERTISED_1000baseT_Full;
2446 phydev->priv = priv;
2448 list_add(&priv->list, &ar8xxx_dev_list);
2450 mutex_unlock(&ar8xxx_dev_list_lock);
2454 err_unregister_switch:
2455 if (--priv->use_count)
2458 unregister_switch(&priv->dev);
2463 mutex_unlock(&ar8xxx_dev_list_lock);
2468 ar8xxx_phy_detach(struct phy_device *phydev)
2470 struct net_device *dev = phydev->attached_dev;
2475 dev->phy_ptr = NULL;
2476 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2477 dev->eth_mangle_rx = NULL;
2478 dev->eth_mangle_tx = NULL;
2482 ar8xxx_phy_remove(struct phy_device *phydev)
2484 struct ar8xxx_priv *priv = phydev->priv;
2489 phydev->priv = NULL;
2490 if (--priv->use_count > 0)
2493 mutex_lock(&ar8xxx_dev_list_lock);
2494 list_del(&priv->list);
2495 mutex_unlock(&ar8xxx_dev_list_lock);
2497 unregister_switch(&priv->dev);
2498 ar8xxx_mib_stop(priv);
2502 static struct phy_driver ar8xxx_phy_driver = {
2503 .phy_id = 0x004d0000,
2504 .name = "Atheros AR8216/AR8236/AR8316",
2505 .phy_id_mask = 0xffff0000,
2506 .features = PHY_BASIC_FEATURES,
2507 .probe = ar8xxx_phy_probe,
2508 .remove = ar8xxx_phy_remove,
2509 .detach = ar8xxx_phy_detach,
2510 .config_init = ar8xxx_phy_config_init,
2511 .config_aneg = ar8xxx_phy_config_aneg,
2512 .read_status = ar8xxx_phy_read_status,
2513 .driver = { .owner = THIS_MODULE },
2519 return phy_driver_register(&ar8xxx_phy_driver);
2525 phy_driver_unregister(&ar8xxx_phy_driver);
2528 module_init(ar8xxx_init);
2529 module_exit(ar8xxx_exit);
2530 MODULE_LICENSE("GPL");