target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 138 static int
 139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 140 {
 141         unsigned int sleep_msecs = 20;
 142         int ret, elapsed, i;
 143
 144         for (elapsed = sleep_msecs; elapsed <= 600;
 145              elapsed += sleep_msecs) {
 146                 msleep(sleep_msecs);
 147                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 148                         ret = mdiobus_read(bus, i, MII_BMCR);
 149                         if (ret < 0)
 150                                 return ret;
 151                         if (ret & BMCR_RESET)
 152                                 break;
 153                         if (i == AR8XXX_NUM_PHYS - 1) {
 154                                 usleep_range(1000, 2000);
 155                                 return 0;
 156                         }
 157                 }
 158         }
 159         return -ETIMEDOUT;
 160 }
 161
 162 static int
 163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 164 {
 165         int ret;
 166
 167         if (phydev->autoneg != AUTONEG_ENABLE)
 168                 return 0;
 169         /*
 170          * BMCR_ANENABLE might have been cleared
 171          * by phy_init_hw in certain kernel versions
 172          * therefore check for it
 173          */
 174         ret = phy_read(phydev, MII_BMCR);
 175         if (ret < 0)
 176                 return ret;
 177         if (ret & BMCR_ANENABLE)
 178                 return 0;
 179
 180         dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
 181         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 182         return phy_write(phydev, MII_BMCR, ret);
 183 }
 184
 185 void
 186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 187 {
 188         int i;
 189         struct mii_bus *bus;
 190
 191         bus = priv->mii_bus;
 192         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 193                 if (priv->chip->phy_fixup)
 194                         priv->chip->phy_fixup(priv, i);
 195
 196                 /* initialize the port itself */
 197                 mdiobus_write(bus, i, MII_ADVERTISE,
 198                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 199                 if (ar8xxx_has_gige(priv))
 200                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 201                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 202         }
 203
 204         ar8xxx_phy_poll_reset(bus);
 205 }
 206
 207 u32
 208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 209 {
 210         struct mii_bus *bus = priv->mii_bus;
 211         u16 lo, hi;
 212
 213         lo = bus->read(bus, phy_id, regnum);
 214         hi = bus->read(bus, phy_id, regnum + 1);
 215
 216         return (hi << 16) | lo;
 217 }
 218
 219 void
 220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 221 {
 222         struct mii_bus *bus = priv->mii_bus;
 223         u16 lo, hi;
 224
 225         lo = val & 0xffff;
 226         hi = (u16) (val >> 16);
 227
 228         if (priv->chip->mii_lo_first)
 229         {
 230                 bus->write(bus, phy_id, regnum, lo);
 231                 bus->write(bus, phy_id, regnum + 1, hi);
 232         } else {
 233                 bus->write(bus, phy_id, regnum + 1, hi);
 234                 bus->write(bus, phy_id, regnum, lo);
 235         }
 236 }
 237
 238 u32
 239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 240 {
 241         struct mii_bus *bus = priv->mii_bus;
 242         u16 r1, r2, page;
 243         u32 val;
 244
 245         split_addr((u32) reg, &r1, &r2, &page);
 246
 247         mutex_lock(&bus->mdio_lock);
 248
 249         bus->write(bus, 0x18, 0, page);
 250         wait_for_page_switch();
 251         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 252
 253         mutex_unlock(&bus->mdio_lock);
 254
 255         return val;
 256 }
 257
 258 void
 259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 260 {
 261         struct mii_bus *bus = priv->mii_bus;
 262         u16 r1, r2, page;
 263
 264         split_addr((u32) reg, &r1, &r2, &page);
 265
 266         mutex_lock(&bus->mdio_lock);
 267
 268         bus->write(bus, 0x18, 0, page);
 269         wait_for_page_switch();
 270         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 271
 272         mutex_unlock(&bus->mdio_lock);
 273 }
 274
 275 u32
 276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 277 {
 278         struct mii_bus *bus = priv->mii_bus;
 279         u16 r1, r2, page;
 280         u32 ret;
 281
 282         split_addr((u32) reg, &r1, &r2, &page);
 283
 284         mutex_lock(&bus->mdio_lock);
 285
 286         bus->write(bus, 0x18, 0, page);
 287         wait_for_page_switch();
 288
 289         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 290         ret &= ~mask;
 291         ret |= val;
 292         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 293
 294         mutex_unlock(&bus->mdio_lock);
 295
 296         return ret;
 297 }
 298
 299 void
 300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 301                      u16 dbg_addr, u16 dbg_data)
 302 {
 303         struct mii_bus *bus = priv->mii_bus;
 304
 305         mutex_lock(&bus->mdio_lock);
 306         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 307         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 308         mutex_unlock(&bus->mdio_lock);
 309 }
 310
 311 static inline void
 312 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
 313 {
 314         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 315         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
 316         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
 317 }
 318
 319 void
 320 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
 321 {
 322         struct mii_bus *bus = priv->mii_bus;
 323
 324         mutex_lock(&bus->mdio_lock);
 325         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 326         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 327         mutex_unlock(&bus->mdio_lock);
 328 }
 329
 330 u16
 331 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
 332 {
 333         struct mii_bus *bus = priv->mii_bus;
 334         u16 data;
 335
 336         mutex_lock(&bus->mdio_lock);
 337         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 338         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 339         mutex_unlock(&bus->mdio_lock);
 340
 341         return data;
 342 }
 343
 344 static int
 345 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 346                 unsigned timeout)
 347 {
 348         int i;
 349
 350         for (i = 0; i < timeout; i++) {
 351                 u32 t;
 352
 353                 t = ar8xxx_read(priv, reg);
 354                 if ((t & mask) == val)
 355                         return 0;
 356
 357                 usleep_range(1000, 2000);
 358                 cond_resched();
 359         }
 360
 361         return -ETIMEDOUT;
 362 }
 363
 364 static int
 365 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 366 {
 367         unsigned mib_func = priv->chip->mib_func;
 368         int ret;
 369
 370         lockdep_assert_held(&priv->mib_lock);
 371
 372         /* Capture the hardware statistics for all ports */
 373         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 374
 375         /* Wait for the capturing to complete. */
 376         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 377         if (ret)
 378                 goto out;
 379
 380         ret = 0;
 381
 382 out:
 383         return ret;
 384 }
 385
 386 static int
 387 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 388 {
 389         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 390 }
 391
 392 static int
 393 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 394 {
 395         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 396 }
 397
 398 static void
 399 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 400 {
 401         unsigned int base;
 402         u64 *mib_stats;
 403         int i;
 404
 405         WARN_ON(port >= priv->dev.ports);
 406
 407         lockdep_assert_held(&priv->mib_lock);
 408
 409         base = priv->chip->reg_port_stats_start +
 410                priv->chip->reg_port_stats_length * port;
 411
 412         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 413         for (i = 0; i < priv->chip->num_mibs; i++) {
 414                 const struct ar8xxx_mib_desc *mib;
 415                 u64 t;
 416
 417                 mib = &priv->chip->mib_decs[i];
 418                 t = ar8xxx_read(priv, base + mib->offset);
 419                 if (mib->size == 2) {
 420                         u64 hi;
 421
 422                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 423                         t |= hi << 32;
 424                 }
 425
 426                 if (flush)
 427                         mib_stats[i] = 0;
 428                 else
 429                         mib_stats[i] += t;
 430                 cond_resched();
 431         }
 432 }
 433
 434 static void
 435 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 436                       struct switch_port_link *link)
 437 {
 438         u32 status;
 439         u32 speed;
 440
 441         memset(link, '\0', sizeof(*link));
 442
 443         status = priv->chip->read_port_status(priv, port);
 444
 445         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 446         if (link->aneg) {
 447                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 448         } else {
 449                 link->link = true;
 450
 451                 if (priv->get_port_link) {
 452                         int err;
 453
 454                         err = priv->get_port_link(port);
 455                         if (err >= 0)
 456                                 link->link = !!err;
 457                 }
 458         }
 459
 460         if (!link->link)
 461                 return;
 462
 463         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 464         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 465         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 466
 467         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 468                 link->eee = priv->chip->read_port_eee_status(priv, port);
 469
 470         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 471                  AR8216_PORT_STATUS_SPEED_S;
 472
 473         switch (speed) {
 474         case AR8216_PORT_SPEED_10M:
 475                 link->speed = SWITCH_PORT_SPEED_10;
 476                 break;
 477         case AR8216_PORT_SPEED_100M:
 478                 link->speed = SWITCH_PORT_SPEED_100;
 479                 break;
 480         case AR8216_PORT_SPEED_1000M:
 481                 link->speed = SWITCH_PORT_SPEED_1000;
 482                 break;
 483         default:
 484                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 485                 break;
 486         }
 487 }
 488
 489 static struct sk_buff *
 490 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 491 {
 492         struct ar8xxx_priv *priv = dev->phy_ptr;
 493         unsigned char *buf;
 494
 495         if (unlikely(!priv))
 496                 goto error;
 497
 498         if (!priv->vlan)
 499                 goto send;
 500
 501         if (unlikely(skb_headroom(skb) < 2)) {
 502                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 503                         goto error;
 504         }
 505
 506         buf = skb_push(skb, 2);
 507         buf[0] = 0x10;
 508         buf[1] = 0x80;
 509
 510 send:
 511         return skb;
 512
 513 error:
 514         dev_kfree_skb_any(skb);
 515         return NULL;
 516 }
 517
 518 static void
 519 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 520 {
 521         struct ar8xxx_priv *priv;
 522         unsigned char *buf;
 523         int port, vlan;
 524
 525         priv = dev->phy_ptr;
 526         if (!priv)
 527                 return;
 528
 529         /* don't strip the header if vlan mode is disabled */
 530         if (!priv->vlan)
 531                 return;
 532
 533         /* strip header, get vlan id */
 534         buf = skb->data;
 535         skb_pull(skb, 2);
 536
 537         /* check for vlan header presence */
 538         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 539                 return;
 540
 541         port = buf[0] & 0x7;
 542
 543         /* no need to fix up packets coming from a tagged source */
 544         if (priv->vlan_tagged & (1 << port))
 545                 return;
 546
 547         /* lookup port vid from local table, the switch passes an invalid vlan id */
 548         vlan = priv->vlan_id[priv->pvid[port]];
 549
 550         buf[14 + 2] &= 0xf0;
 551         buf[14 + 2] |= vlan >> 8;
 552         buf[15 + 2] = vlan & 0xff;
 553 }
 554
 555 int
 556 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 557 {
 558         int timeout = 20;
 559         u32 t = 0;
 560
 561         while (1) {
 562                 t = ar8xxx_read(priv, reg);
 563                 if ((t & mask) == val)
 564                         return 0;
 565
 566                 if (timeout-- <= 0)
 567                         break;
 568
 569                 udelay(10);
 570                 cond_resched();
 571         }
 572
 573         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 574                (unsigned int) reg, t, mask, val);
 575         return -ETIMEDOUT;
 576 }
 577
 578 static void
 579 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 580 {
 581         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 582                 return;
 583         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 584                 val &= AR8216_VTUDATA_MEMBER;
 585                 val |= AR8216_VTUDATA_VALID;
 586                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 587         }
 588         op |= AR8216_VTU_ACTIVE;
 589         ar8xxx_write(priv, AR8216_REG_VTU, op);
 590 }
 591
 592 static void
 593 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 594 {
 595         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 596 }
 597
 598 static void
 599 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 600 {
 601         u32 op;
 602
 603         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 604         ar8216_vtu_op(priv, op, port_mask);
 605 }
 606
 607 static int
 608 ar8216_atu_flush(struct ar8xxx_priv *priv)
 609 {
 610         int ret;
 611
 612         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 613         if (!ret)
 614                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 615                                                          AR8216_ATU_ACTIVE);
 616
 617         return ret;
 618 }
 619
 620 static int
 621 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 622 {
 623         u32 t;
 624         int ret;
 625
 626         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 627         if (!ret) {
 628                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 629                 t |= AR8216_ATU_ACTIVE;
 630                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 631         }
 632
 633         return ret;
 634 }
 635
 636 static u32
 637 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 638 {
 639         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 640 }
 641
 642 static void
 643 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 644 {
 645         u32 header;
 646         u32 egress, ingress;
 647         u32 pvid;
 648
 649         if (priv->vlan) {
 650                 pvid = priv->vlan_id[priv->pvid[port]];
 651                 if (priv->vlan_tagged & (1 << port))
 652                         egress = AR8216_OUT_ADD_VLAN;
 653                 else
 654                         egress = AR8216_OUT_STRIP_VLAN;
 655                 ingress = AR8216_IN_SECURE;
 656         } else {
 657                 pvid = port;
 658                 egress = AR8216_OUT_KEEP;
 659                 ingress = AR8216_IN_PORT_ONLY;
 660         }
 661
 662         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 663                 header = AR8216_PORT_CTRL_HEADER;
 664         else
 665                 header = 0;
 666
 667         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 668                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 669                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 670                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 671                    AR8216_PORT_CTRL_LEARN | header |
 672                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 673                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 674
 675         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 676                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 677                    AR8216_PORT_VLAN_DEFAULT_ID,
 678                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 679                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 680                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 681 }
 682
 683 static int
 684 ar8216_hw_init(struct ar8xxx_priv *priv)
 685 {
 686         if (priv->initialized)
 687                 return 0;
 688
 689         ar8xxx_phy_init(priv);
 690
 691         priv->initialized = true;
 692         return 0;
 693 }
 694
 695 static void
 696 ar8216_init_globals(struct ar8xxx_priv *priv)
 697 {
 698         /* standard atheros magic */
 699         ar8xxx_write(priv, 0x38, 0xc000050e);
 700
 701         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 702                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 703 }
 704
 705 static void
 706 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 707 {
 708         /* Enable port learning and tx */
 709         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 710                 AR8216_PORT_CTRL_LEARN |
 711                 (4 << AR8216_PORT_CTRL_STATE_S));
 712
 713         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 714
 715         if (port == AR8216_PORT_CPU) {
 716                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 717                         AR8216_PORT_STATUS_LINK_UP |
 718                         (ar8xxx_has_gige(priv) ?
 719                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 720                         AR8216_PORT_STATUS_TXMAC |
 721                         AR8216_PORT_STATUS_RXMAC |
 722                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 723                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 724                         AR8216_PORT_STATUS_DUPLEX);
 725         } else {
 726                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 727                         AR8216_PORT_STATUS_LINK_AUTO);
 728         }
 729 }
 730
 731 static void
 732 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 733 {
 734         int timeout = 20;
 735
 736         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
 737                 udelay(10);
 738                 cond_resched();
 739         }
 740
 741         if (!timeout)
 742                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 743 }
 744
 745 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 746                                  struct arl_entry *a, u32 *status, enum arl_op op)
 747 {
 748         struct mii_bus *bus = priv->mii_bus;
 749         u16 r2, page;
 750         u16 r1_func0, r1_func1, r1_func2;
 751         u32 t, val0, val1, val2;
 752
 753         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 754         r2 |= 0x10;
 755
 756         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 757         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 758
 759         switch (op) {
 760         case AR8XXX_ARL_INITIALIZE:
 761                 /* all ATU registers are on the same page
 762                 * therefore set page only once
 763                 */
 764                 bus->write(bus, 0x18, 0, page);
 765                 wait_for_page_switch();
 766
 767                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 768
 769                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 770                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 771                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 772                 break;
 773         case AR8XXX_ARL_GET_NEXT:
 774                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 775                 t |= AR8216_ATU_ACTIVE;
 776                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 777                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 778
 779                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 780                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 781                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 782
 783                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 784                 if (!*status)
 785                         break;
 786
 787                 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
 788                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 789                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 790                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 791                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 792                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 793                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 794                 break;
 795         }
 796 }
 797
 798 static void
 799 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 800 {
 801         u32 egress, ingress;
 802         u32 pvid;
 803
 804         if (priv->vlan) {
 805                 pvid = priv->vlan_id[priv->pvid[port]];
 806                 if (priv->vlan_tagged & (1 << port))
 807                         egress = AR8216_OUT_ADD_VLAN;
 808                 else
 809                         egress = AR8216_OUT_STRIP_VLAN;
 810                 ingress = AR8216_IN_SECURE;
 811         } else {
 812                 pvid = port;
 813                 egress = AR8216_OUT_KEEP;
 814                 ingress = AR8216_IN_PORT_ONLY;
 815         }
 816
 817         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 818                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 819                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 820                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 821                    AR8216_PORT_CTRL_LEARN |
 822                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 823                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 824
 825         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 826                    AR8236_PORT_VLAN_DEFAULT_ID,
 827                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 828
 829         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 830                    AR8236_PORT_VLAN2_VLAN_MODE |
 831                    AR8236_PORT_VLAN2_MEMBER,
 832                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 833                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 834 }
 835
 836 static void
 837 ar8236_init_globals(struct ar8xxx_priv *priv)
 838 {
 839         /* enable jumbo frames */
 840         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 841                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 842
 843         /* enable cpu port to receive arp frames */
 844         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 845                    AR8236_ATU_CTRL_RES);
 846
 847         /* enable cpu port to receive multicast and broadcast frames */
 848         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 849                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 850
 851         /* Enable MIB counters */
 852         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 853                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 854                    AR8236_MIB_EN);
 855 }
 856
 857 static int
 858 ar8316_hw_init(struct ar8xxx_priv *priv)
 859 {
 860         u32 val, newval;
 861
 862         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 863
 864         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 865                 if (priv->port4_phy) {
 866                         /* value taken from Ubiquiti RouterStation Pro */
 867                         newval = 0x81461bea;
 868                         pr_info("ar8316: Using port 4 as PHY\n");
 869                 } else {
 870                         newval = 0x01261be2;
 871                         pr_info("ar8316: Using port 4 as switch port\n");
 872                 }
 873         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 874                 /* value taken from AVM Fritz!Box 7390 sources */
 875                 newval = 0x010e5b71;
 876         } else {
 877                 /* no known value for phy interface */
 878                 pr_err("ar8316: unsupported mii mode: %d.\n",
 879                        priv->phy->interface);
 880                 return -EINVAL;
 881         }
 882
 883         if (val == newval)
 884                 goto out;
 885
 886         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 887
 888         if (priv->port4_phy &&
 889             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 890                 /* work around for phy4 rgmii mode */
 891                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 892                 /* rx delay */
 893                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 894                 /* tx delay */
 895                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 896                 msleep(1000);
 897         }
 898
 899         ar8xxx_phy_init(priv);
 900
 901 out:
 902         priv->initialized = true;
 903         return 0;
 904 }
 905
 906 static void
 907 ar8316_init_globals(struct ar8xxx_priv *priv)
 908 {
 909         /* standard atheros magic */
 910         ar8xxx_write(priv, 0x38, 0xc000050e);
 911
 912         /* enable cpu port to receive multicast and broadcast frames */
 913         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 914
 915         /* enable jumbo frames */
 916         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 917                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 918
 919         /* Enable MIB counters */
 920         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 921                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 922                    AR8236_MIB_EN);
 923 }
 924
 925 int
 926 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 927                    struct switch_val *val)
 928 {
 929         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 930         priv->vlan = !!val->value.i;
 931         return 0;
 932 }
 933
 934 int
 935 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 936                    struct switch_val *val)
 937 {
 938         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 939         val->value.i = priv->vlan;
 940         return 0;
 941 }
 942
 943
 944 int
 945 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 946 {
 947         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 948
 949         /* make sure no invalid PVIDs get set */
 950
 951         if (vlan < 0 || vlan >= dev->vlans ||
 952             port < 0 || port >= AR8X16_MAX_PORTS)
 953                 return -EINVAL;
 954
 955         priv->pvid[port] = vlan;
 956         return 0;
 957 }
 958
 959 int
 960 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 961 {
 962         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 963
 964         if (port < 0 || port >= AR8X16_MAX_PORTS)
 965                 return -EINVAL;
 966
 967         *vlan = priv->pvid[port];
 968         return 0;
 969 }
 970
 971 static int
 972 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 973                   struct switch_val *val)
 974 {
 975         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 976
 977         if (val->port_vlan >= AR8X16_MAX_VLANS)
 978                 return -EINVAL;
 979
 980         priv->vlan_id[val->port_vlan] = val->value.i;
 981         return 0;
 982 }
 983
 984 static int
 985 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 986                   struct switch_val *val)
 987 {
 988         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 989         val->value.i = priv->vlan_id[val->port_vlan];
 990         return 0;
 991 }
 992
 993 int
 994 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 995                         struct switch_port_link *link)
 996 {
 997         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 998
 999         ar8216_read_port_link(priv, port, link);
1000         return 0;
1001 }
1002
1003 static int
1004 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1005 {
1006         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1007         u8 ports;
1008         int i;
1009
1010         if (val->port_vlan >= AR8X16_MAX_VLANS)
1011                 return -EINVAL;
1012
1013         ports = priv->vlan_table[val->port_vlan];
1014         val->len = 0;
1015         for (i = 0; i < dev->ports; i++) {
1016                 struct switch_port *p;
1017
1018                 if (!(ports & (1 << i)))
1019                         continue;
1020
1021                 p = &val->value.ports[val->len++];
1022                 p->id = i;
1023                 if (priv->vlan_tagged & (1 << i))
1024                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1025                 else
1026                         p->flags = 0;
1027         }
1028         return 0;
1029 }
1030
1031 static int
1032 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1033 {
1034         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1035         u8 *vt = &priv->vlan_table[val->port_vlan];
1036         int i, j;
1037
1038         *vt = 0;
1039         for (i = 0; i < val->len; i++) {
1040                 struct switch_port *p = &val->value.ports[i];
1041
1042                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1043                         priv->vlan_tagged |= (1 << p->id);
1044                 } else {
1045                         priv->vlan_tagged &= ~(1 << p->id);
1046                         priv->pvid[p->id] = val->port_vlan;
1047
1048                         /* make sure that an untagged port does not
1049                          * appear in other vlans */
1050                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1051                                 if (j == val->port_vlan)
1052                                         continue;
1053                                 priv->vlan_table[j] &= ~(1 << p->id);
1054                         }
1055                 }
1056
1057                 *vt |= 1 << p->id;
1058         }
1059         return 0;
1060 }
1061
1062 static void
1063 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1064 {
1065         int port;
1066
1067         /* reset all mirror registers */
1068         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1069                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1070                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1071         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1072                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1073                            AR8216_PORT_CTRL_MIRROR_RX);
1074
1075                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1076                            AR8216_PORT_CTRL_MIRROR_TX);
1077         }
1078
1079         /* now enable mirroring if necessary */
1080         if (priv->source_port >= AR8216_NUM_PORTS ||
1081             priv->monitor_port >= AR8216_NUM_PORTS ||
1082             priv->source_port == priv->monitor_port) {
1083                 return;
1084         }
1085
1086         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1087                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1088                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1089
1090         if (priv->mirror_rx)
1091                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1092                            AR8216_PORT_CTRL_MIRROR_RX);
1093
1094         if (priv->mirror_tx)
1095                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1096                            AR8216_PORT_CTRL_MIRROR_TX);
1097 }
1098
1099 static inline u32
1100 ar8xxx_age_time_val(int age_time)
1101 {
1102         return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1103                AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1104 }
1105
1106 static inline void
1107 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1108 {
1109         u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1110         ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1111 }
1112
1113 int
1114 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1115 {
1116         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1117         const struct ar8xxx_chip *chip = priv->chip;
1118         u8 portmask[AR8X16_MAX_PORTS];
1119         int i, j;
1120
1121         mutex_lock(&priv->reg_mutex);
1122         /* flush all vlan translation unit entries */
1123         priv->chip->vtu_flush(priv);
1124
1125         memset(portmask, 0, sizeof(portmask));
1126         if (!priv->init) {
1127                 /* calculate the port destination masks and load vlans
1128                  * into the vlan translation unit */
1129                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1130                         u8 vp = priv->vlan_table[j];
1131
1132                         if (!vp)
1133                                 continue;
1134
1135                         for (i = 0; i < dev->ports; i++) {
1136                                 u8 mask = (1 << i);
1137                                 if (vp & mask)
1138                                         portmask[i] |= vp & ~mask;
1139                         }
1140
1141                         chip->vtu_load_vlan(priv, priv->vlan_id[j],
1142                                             priv->vlan_table[j]);
1143                 }
1144         } else {
1145                 /* vlan disabled:
1146                  * isolate all ports, but connect them to the cpu port */
1147                 for (i = 0; i < dev->ports; i++) {
1148                         if (i == AR8216_PORT_CPU)
1149                                 continue;
1150
1151                         portmask[i] = 1 << AR8216_PORT_CPU;
1152                         portmask[AR8216_PORT_CPU] |= (1 << i);
1153                 }
1154         }
1155
1156         /* update the port destination mask registers and tag settings */
1157         for (i = 0; i < dev->ports; i++) {
1158                 chip->setup_port(priv, i, portmask[i]);
1159         }
1160
1161         chip->set_mirror_regs(priv);
1162
1163         /* set age time */
1164         if (chip->reg_arl_ctrl)
1165                 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1166
1167         mutex_unlock(&priv->reg_mutex);
1168         return 0;
1169 }
1170
1171 int
1172 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1173 {
1174         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1175         const struct ar8xxx_chip *chip = priv->chip;
1176         int i;
1177
1178         mutex_lock(&priv->reg_mutex);
1179         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1180                 offsetof(struct ar8xxx_priv, vlan));
1181
1182         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1183                 priv->vlan_id[i] = i;
1184
1185         /* Configure all ports */
1186         for (i = 0; i < dev->ports; i++)
1187                 chip->init_port(priv, i);
1188
1189         priv->mirror_rx = false;
1190         priv->mirror_tx = false;
1191         priv->source_port = 0;
1192         priv->monitor_port = 0;
1193         priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1194
1195         chip->init_globals(priv);
1196         chip->atu_flush(priv);
1197
1198         mutex_unlock(&priv->reg_mutex);
1199
1200         return chip->sw_hw_apply(dev);
1201 }
1202
1203 int
1204 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1205                          const struct switch_attr *attr,
1206                          struct switch_val *val)
1207 {
1208         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1209         unsigned int len;
1210         int ret;
1211
1212         if (!ar8xxx_has_mib_counters(priv))
1213                 return -EOPNOTSUPP;
1214
1215         mutex_lock(&priv->mib_lock);
1216
1217         len = priv->dev.ports * priv->chip->num_mibs *
1218               sizeof(*priv->mib_stats);
1219         memset(priv->mib_stats, '\0', len);
1220         ret = ar8xxx_mib_flush(priv);
1221         if (ret)
1222                 goto unlock;
1223
1224         ret = 0;
1225
1226 unlock:
1227         mutex_unlock(&priv->mib_lock);
1228         return ret;
1229 }
1230
1231 int
1232 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1233                                const struct switch_attr *attr,
1234                                struct switch_val *val)
1235 {
1236         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1237
1238         mutex_lock(&priv->reg_mutex);
1239         priv->mirror_rx = !!val->value.i;
1240         priv->chip->set_mirror_regs(priv);
1241         mutex_unlock(&priv->reg_mutex);
1242
1243         return 0;
1244 }
1245
1246 int
1247 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1248                                const struct switch_attr *attr,
1249                                struct switch_val *val)
1250 {
1251         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1252         val->value.i = priv->mirror_rx;
1253         return 0;
1254 }
1255
1256 int
1257 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1258                                const struct switch_attr *attr,
1259                                struct switch_val *val)
1260 {
1261         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1262
1263         mutex_lock(&priv->reg_mutex);
1264         priv->mirror_tx = !!val->value.i;
1265         priv->chip->set_mirror_regs(priv);
1266         mutex_unlock(&priv->reg_mutex);
1267
1268         return 0;
1269 }
1270
1271 int
1272 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1273                                const struct switch_attr *attr,
1274                                struct switch_val *val)
1275 {
1276         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1277         val->value.i = priv->mirror_tx;
1278         return 0;
1279 }
1280
1281 int
1282 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1283                                   const struct switch_attr *attr,
1284                                   struct switch_val *val)
1285 {
1286         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1287
1288         mutex_lock(&priv->reg_mutex);
1289         priv->monitor_port = val->value.i;
1290         priv->chip->set_mirror_regs(priv);
1291         mutex_unlock(&priv->reg_mutex);
1292
1293         return 0;
1294 }
1295
1296 int
1297 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1298                                   const struct switch_attr *attr,
1299                                   struct switch_val *val)
1300 {
1301         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1302         val->value.i = priv->monitor_port;
1303         return 0;
1304 }
1305
1306 int
1307 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1308                                  const struct switch_attr *attr,
1309                                  struct switch_val *val)
1310 {
1311         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1312
1313         mutex_lock(&priv->reg_mutex);
1314         priv->source_port = val->value.i;
1315         priv->chip->set_mirror_regs(priv);
1316         mutex_unlock(&priv->reg_mutex);
1317
1318         return 0;
1319 }
1320
1321 int
1322 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1323                                  const struct switch_attr *attr,
1324                                  struct switch_val *val)
1325 {
1326         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1327         val->value.i = priv->source_port;
1328         return 0;
1329 }
1330
1331 int
1332 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1333                              const struct switch_attr *attr,
1334                              struct switch_val *val)
1335 {
1336         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1337         int port;
1338         int ret;
1339
1340         if (!ar8xxx_has_mib_counters(priv))
1341                 return -EOPNOTSUPP;
1342
1343         port = val->port_vlan;
1344         if (port >= dev->ports)
1345                 return -EINVAL;
1346
1347         mutex_lock(&priv->mib_lock);
1348         ret = ar8xxx_mib_capture(priv);
1349         if (ret)
1350                 goto unlock;
1351
1352         ar8xxx_mib_fetch_port_stat(priv, port, true);
1353
1354         ret = 0;
1355
1356 unlock:
1357         mutex_unlock(&priv->mib_lock);
1358         return ret;
1359 }
1360
1361 static void
1362 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1363 {
1364         unsigned long b;
1365         const char *unit;
1366
1367         if (byte >= 0x40000000) { /* 1 GiB */
1368                 b = byte * 10 / 0x40000000;
1369                 unit = "GiB";
1370         } else if (byte >= 0x100000) { /* 1 MiB */
1371                 b = byte * 10 / 0x100000;
1372                 unit = "MiB";
1373         } else if (byte >= 0x400) { /* 1 KiB */
1374                 b = byte * 10 / 0x400;
1375                 unit = "KiB";
1376         } else {
1377                 b = byte;
1378                 unit = "Byte";
1379         }
1380         if (strcmp(unit, "Byte"))
1381                 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1382         else
1383                 snprintf(buf, len, "%lu %s", b, unit);
1384 }
1385
1386 int
1387 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1388                        const struct switch_attr *attr,
1389                        struct switch_val *val)
1390 {
1391         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1392         const struct ar8xxx_chip *chip = priv->chip;
1393         u64 *mib_stats, mib_data;
1394         unsigned int port;
1395         int ret;
1396         char *buf = priv->buf;
1397         char buf1[64];
1398         const char *mib_name;
1399         int i, len = 0;
1400         bool mib_stats_empty = true;
1401
1402         if (!ar8xxx_has_mib_counters(priv))
1403                 return -EOPNOTSUPP;
1404
1405         port = val->port_vlan;
1406         if (port >= dev->ports)
1407                 return -EINVAL;
1408
1409         mutex_lock(&priv->mib_lock);
1410         ret = ar8xxx_mib_capture(priv);
1411         if (ret)
1412                 goto unlock;
1413
1414         ar8xxx_mib_fetch_port_stat(priv, port, false);
1415
1416         len += snprintf(buf + len, sizeof(priv->buf) - len,
1417                         "MIB counters\n");
1418
1419         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1420         for (i = 0; i < chip->num_mibs; i++) {
1421                 mib_name = chip->mib_decs[i].name;
1422                 mib_data = mib_stats[i];
1423                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1424                                 "%-12s: %llu\n", mib_name, mib_data);
1425                 if ((!strcmp(mib_name, "TxByte") ||
1426                     !strcmp(mib_name, "RxGoodByte")) &&
1427                     mib_data >= 1024) {
1428                         ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1429                         --len; /* discard newline at the end of buf */
1430                         len += snprintf(buf + len, sizeof(priv->buf) - len,
1431                                         " (%s)\n", buf1);
1432                 }
1433                 if (mib_stats_empty && mib_data)
1434                         mib_stats_empty = false;
1435         }
1436
1437         if (mib_stats_empty)
1438                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1439
1440         val->value.s = buf;
1441         val->len = len;
1442
1443         ret = 0;
1444
1445 unlock:
1446         mutex_unlock(&priv->mib_lock);
1447         return ret;
1448 }
1449
1450 int
1451 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1452                            struct switch_val *val)
1453 {
1454         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1455         int age_time = val->value.i;
1456         u32 age_time_val;
1457
1458         if (age_time < 0)
1459                 return -EINVAL;
1460
1461         age_time_val = ar8xxx_age_time_val(age_time);
1462         if (age_time_val == 0 || age_time_val > 0xffff)
1463                 return -EINVAL;
1464
1465         priv->arl_age_time = age_time;
1466         return 0;
1467 }
1468
1469 int
1470 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1471                    struct switch_val *val)
1472 {
1473         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1474         val->value.i = priv->arl_age_time;
1475         return 0;
1476 }
1477
1478 int
1479 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1480                         const struct switch_attr *attr,
1481                         struct switch_val *val)
1482 {
1483         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1484         struct mii_bus *bus = priv->mii_bus;
1485         const struct ar8xxx_chip *chip = priv->chip;
1486         char *buf = priv->arl_buf;
1487         int i, j, k, len = 0;
1488         struct arl_entry *a, *a1;
1489         u32 status;
1490
1491         if (!chip->get_arl_entry)
1492                 return -EOPNOTSUPP;
1493
1494         mutex_lock(&priv->reg_mutex);
1495         mutex_lock(&bus->mdio_lock);
1496
1497         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1498
1499         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1500                 a = &priv->arl_table[i];
1501                 duplicate:
1502                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1503
1504                 if (!status)
1505                         break;
1506
1507                 /* avoid duplicates
1508                  * ARL table can include multiple valid entries
1509                  * per MAC, just with differing status codes
1510                  */
1511                 for (j = 0; j < i; ++j) {
1512                         a1 = &priv->arl_table[j];
1513                         if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1514                                 /* ignore ports already seen in former entry */
1515                                 a->portmap &= ~a1->portmap;
1516                                 if (!a->portmap)
1517                                         goto duplicate;
1518                         }
1519                 }
1520         }
1521
1522         mutex_unlock(&bus->mdio_lock);
1523
1524         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1525                         "address resolution table\n");
1526
1527         if (i == AR8XXX_NUM_ARL_RECORDS)
1528                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1529                                 "Too many entries found, displaying the first %d only!\n",
1530                                 AR8XXX_NUM_ARL_RECORDS);
1531
1532         for (j = 0; j < priv->dev.ports; ++j) {
1533                 for (k = 0; k < i; ++k) {
1534                         a = &priv->arl_table[k];
1535                         if (!(a->portmap & BIT(j)))
1536                                 continue;
1537                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1538                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1539                                         j,
1540                                         a->mac[5], a->mac[4], a->mac[3],
1541                                         a->mac[2], a->mac[1], a->mac[0]);
1542                 }
1543         }
1544
1545         val->value.s = buf;
1546         val->len = len;
1547
1548         mutex_unlock(&priv->reg_mutex);
1549
1550         return 0;
1551 }
1552
1553 int
1554 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1555                               const struct switch_attr *attr,
1556                               struct switch_val *val)
1557 {
1558         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1559         int ret;
1560
1561         mutex_lock(&priv->reg_mutex);
1562         ret = priv->chip->atu_flush(priv);
1563         mutex_unlock(&priv->reg_mutex);
1564
1565         return ret;
1566 }
1567
1568 int
1569 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1570                                    const struct switch_attr *attr,
1571                                    struct switch_val *val)
1572 {
1573         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1574         int port, ret;
1575
1576         port = val->port_vlan;
1577         if (port >= dev->ports)
1578                 return -EINVAL;
1579
1580         mutex_lock(&priv->reg_mutex);
1581         ret = priv->chip->atu_flush_port(priv, port);
1582         mutex_unlock(&priv->reg_mutex);
1583
1584         return ret;
1585 }
1586
1587 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1588         {
1589                 .type = SWITCH_TYPE_INT,
1590                 .name = "enable_vlan",
1591                 .description = "Enable VLAN mode",
1592                 .set = ar8xxx_sw_set_vlan,
1593                 .get = ar8xxx_sw_get_vlan,
1594                 .max = 1
1595         },
1596         {
1597                 .type = SWITCH_TYPE_NOVAL,
1598                 .name = "reset_mibs",
1599                 .description = "Reset all MIB counters",
1600                 .set = ar8xxx_sw_set_reset_mibs,
1601         },
1602         {
1603                 .type = SWITCH_TYPE_INT,
1604                 .name = "enable_mirror_rx",
1605                 .description = "Enable mirroring of RX packets",
1606                 .set = ar8xxx_sw_set_mirror_rx_enable,
1607                 .get = ar8xxx_sw_get_mirror_rx_enable,
1608                 .max = 1
1609         },
1610         {
1611                 .type = SWITCH_TYPE_INT,
1612                 .name = "enable_mirror_tx",
1613                 .description = "Enable mirroring of TX packets",
1614                 .set = ar8xxx_sw_set_mirror_tx_enable,
1615                 .get = ar8xxx_sw_get_mirror_tx_enable,
1616                 .max = 1
1617         },
1618         {
1619                 .type = SWITCH_TYPE_INT,
1620                 .name = "mirror_monitor_port",
1621                 .description = "Mirror monitor port",
1622                 .set = ar8xxx_sw_set_mirror_monitor_port,
1623                 .get = ar8xxx_sw_get_mirror_monitor_port,
1624                 .max = AR8216_NUM_PORTS - 1
1625         },
1626         {
1627                 .type = SWITCH_TYPE_INT,
1628                 .name = "mirror_source_port",
1629                 .description = "Mirror source port",
1630                 .set = ar8xxx_sw_set_mirror_source_port,
1631                 .get = ar8xxx_sw_get_mirror_source_port,
1632                 .max = AR8216_NUM_PORTS - 1
1633         },
1634         {
1635                 .type = SWITCH_TYPE_STRING,
1636                 .name = "arl_table",
1637                 .description = "Get ARL table",
1638                 .set = NULL,
1639                 .get = ar8xxx_sw_get_arl_table,
1640         },
1641         {
1642                 .type = SWITCH_TYPE_NOVAL,
1643                 .name = "flush_arl_table",
1644                 .description = "Flush ARL table",
1645                 .set = ar8xxx_sw_set_flush_arl_table,
1646         },
1647 };
1648
1649 const struct switch_attr ar8xxx_sw_attr_port[] = {
1650         {
1651                 .type = SWITCH_TYPE_NOVAL,
1652                 .name = "reset_mib",
1653                 .description = "Reset single port MIB counters",
1654                 .set = ar8xxx_sw_set_port_reset_mib,
1655         },
1656         {
1657                 .type = SWITCH_TYPE_STRING,
1658                 .name = "mib",
1659                 .description = "Get port's MIB counters",
1660                 .set = NULL,
1661                 .get = ar8xxx_sw_get_port_mib,
1662         },
1663         {
1664                 .type = SWITCH_TYPE_NOVAL,
1665                 .name = "flush_arl_table",
1666                 .description = "Flush port's ARL table entries",
1667                 .set = ar8xxx_sw_set_flush_port_arl_table,
1668         },
1669 };
1670
1671 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1672         {
1673                 .type = SWITCH_TYPE_INT,
1674                 .name = "vid",
1675                 .description = "VLAN ID (0-4094)",
1676                 .set = ar8xxx_sw_set_vid,
1677                 .get = ar8xxx_sw_get_vid,
1678                 .max = 4094,
1679         },
1680 };
1681
1682 static const struct switch_dev_ops ar8xxx_sw_ops = {
1683         .attr_global = {
1684                 .attr = ar8xxx_sw_attr_globals,
1685                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1686         },
1687         .attr_port = {
1688                 .attr = ar8xxx_sw_attr_port,
1689                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1690         },
1691         .attr_vlan = {
1692                 .attr = ar8xxx_sw_attr_vlan,
1693                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1694         },
1695         .get_port_pvid = ar8xxx_sw_get_pvid,
1696         .set_port_pvid = ar8xxx_sw_set_pvid,
1697         .get_vlan_ports = ar8xxx_sw_get_ports,
1698         .set_vlan_ports = ar8xxx_sw_set_ports,
1699         .apply_config = ar8xxx_sw_hw_apply,
1700         .reset_switch = ar8xxx_sw_reset_switch,
1701         .get_port_link = ar8xxx_sw_get_port_link,
1702 /* The following op is disabled as it hogs the CPU and degrades performance.
1703    An implementation has been attempted in 4d8a66d but reading MIB data is slow
1704    on ar8xxx switches.
1705
1706    The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1707    ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1708    the request to update the MIB counter is cleared. */
1709 #if 0
1710         .get_port_stats = ar8xxx_sw_get_port_stats,
1711 #endif
1712 };
1713
1714 static const struct ar8xxx_chip ar8216_chip = {
1715         .caps = AR8XXX_CAP_MIB_COUNTERS,
1716
1717         .reg_port_stats_start = 0x19000,
1718         .reg_port_stats_length = 0xa0,
1719         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1720
1721         .name = "Atheros AR8216",
1722         .ports = AR8216_NUM_PORTS,
1723         .vlans = AR8216_NUM_VLANS,
1724         .swops = &ar8xxx_sw_ops,
1725
1726         .hw_init = ar8216_hw_init,
1727         .init_globals = ar8216_init_globals,
1728         .init_port = ar8216_init_port,
1729         .setup_port = ar8216_setup_port,
1730         .read_port_status = ar8216_read_port_status,
1731         .atu_flush = ar8216_atu_flush,
1732         .atu_flush_port = ar8216_atu_flush_port,
1733         .vtu_flush = ar8216_vtu_flush,
1734         .vtu_load_vlan = ar8216_vtu_load_vlan,
1735         .set_mirror_regs = ar8216_set_mirror_regs,
1736         .get_arl_entry = ar8216_get_arl_entry,
1737         .sw_hw_apply = ar8xxx_sw_hw_apply,
1738
1739         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1740         .mib_decs = ar8216_mibs,
1741         .mib_func = AR8216_REG_MIB_FUNC
1742 };
1743
1744 static const struct ar8xxx_chip ar8236_chip = {
1745         .caps = AR8XXX_CAP_MIB_COUNTERS,
1746
1747         .reg_port_stats_start = 0x20000,
1748         .reg_port_stats_length = 0x100,
1749         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1750
1751         .name = "Atheros AR8236",
1752         .ports = AR8216_NUM_PORTS,
1753         .vlans = AR8216_NUM_VLANS,
1754         .swops = &ar8xxx_sw_ops,
1755
1756         .hw_init = ar8216_hw_init,
1757         .init_globals = ar8236_init_globals,
1758         .init_port = ar8216_init_port,
1759         .setup_port = ar8236_setup_port,
1760         .read_port_status = ar8216_read_port_status,
1761         .atu_flush = ar8216_atu_flush,
1762         .atu_flush_port = ar8216_atu_flush_port,
1763         .vtu_flush = ar8216_vtu_flush,
1764         .vtu_load_vlan = ar8216_vtu_load_vlan,
1765         .set_mirror_regs = ar8216_set_mirror_regs,
1766         .get_arl_entry = ar8216_get_arl_entry,
1767         .sw_hw_apply = ar8xxx_sw_hw_apply,
1768
1769         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1770         .mib_decs = ar8236_mibs,
1771         .mib_func = AR8216_REG_MIB_FUNC
1772 };
1773
1774 static const struct ar8xxx_chip ar8316_chip = {
1775         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1776
1777         .reg_port_stats_start = 0x20000,
1778         .reg_port_stats_length = 0x100,
1779         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1780
1781         .name = "Atheros AR8316",
1782         .ports = AR8216_NUM_PORTS,
1783         .vlans = AR8X16_MAX_VLANS,
1784         .swops = &ar8xxx_sw_ops,
1785
1786         .hw_init = ar8316_hw_init,
1787         .init_globals = ar8316_init_globals,
1788         .init_port = ar8216_init_port,
1789         .setup_port = ar8216_setup_port,
1790         .read_port_status = ar8216_read_port_status,
1791         .atu_flush = ar8216_atu_flush,
1792         .atu_flush_port = ar8216_atu_flush_port,
1793         .vtu_flush = ar8216_vtu_flush,
1794         .vtu_load_vlan = ar8216_vtu_load_vlan,
1795         .set_mirror_regs = ar8216_set_mirror_regs,
1796         .get_arl_entry = ar8216_get_arl_entry,
1797         .sw_hw_apply = ar8xxx_sw_hw_apply,
1798
1799         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1800         .mib_decs = ar8236_mibs,
1801         .mib_func = AR8216_REG_MIB_FUNC
1802 };
1803
1804 static int
1805 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1806 {
1807         u32 val;
1808         u16 id;
1809         int i;
1810
1811         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1812         if (val == ~0)
1813                 return -ENODEV;
1814
1815         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1816         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1817                 u16 t;
1818
1819                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1820                 if (val == ~0)
1821                         return -ENODEV;
1822
1823                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1824                 if (t != id)
1825                         return -ENODEV;
1826         }
1827
1828         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1829         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1830
1831         switch (priv->chip_ver) {
1832         case AR8XXX_VER_AR8216:
1833                 priv->chip = &ar8216_chip;
1834                 break;
1835         case AR8XXX_VER_AR8236:
1836                 priv->chip = &ar8236_chip;
1837                 break;
1838         case AR8XXX_VER_AR8316:
1839                 priv->chip = &ar8316_chip;
1840                 break;
1841         case AR8XXX_VER_AR8327:
1842                 priv->chip = &ar8327_chip;
1843                 break;
1844         case AR8XXX_VER_AR8337:
1845                 priv->chip = &ar8337_chip;
1846                 break;
1847         default:
1848                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1849                        priv->chip_ver, priv->chip_rev);
1850
1851                 return -ENODEV;
1852         }
1853
1854         return 0;
1855 }
1856
1857 static void
1858 ar8xxx_mib_work_func(struct work_struct *work)
1859 {
1860         struct ar8xxx_priv *priv;
1861         int err;
1862
1863         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1864
1865         mutex_lock(&priv->mib_lock);
1866
1867         err = ar8xxx_mib_capture(priv);
1868         if (err)
1869                 goto next_port;
1870
1871         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1872
1873 next_port:
1874         priv->mib_next_port++;
1875         if (priv->mib_next_port >= priv->dev.ports)
1876                 priv->mib_next_port = 0;
1877
1878         mutex_unlock(&priv->mib_lock);
1879         schedule_delayed_work(&priv->mib_work,
1880                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1881 }
1882
1883 static int
1884 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1885 {
1886         unsigned int len;
1887
1888         if (!ar8xxx_has_mib_counters(priv))
1889                 return 0;
1890
1891         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1892
1893         len = priv->dev.ports * priv->chip->num_mibs *
1894               sizeof(*priv->mib_stats);
1895         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1896
1897         if (!priv->mib_stats)
1898                 return -ENOMEM;
1899
1900         return 0;
1901 }
1902
1903 static void
1904 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1905 {
1906         if (!ar8xxx_has_mib_counters(priv))
1907                 return;
1908
1909         schedule_delayed_work(&priv->mib_work,
1910                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1911 }
1912
1913 static void
1914 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1915 {
1916         if (!ar8xxx_has_mib_counters(priv))
1917                 return;
1918
1919         cancel_delayed_work_sync(&priv->mib_work);
1920 }
1921
1922 static struct ar8xxx_priv *
1923 ar8xxx_create(void)
1924 {
1925         struct ar8xxx_priv *priv;
1926
1927         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1928         if (priv == NULL)
1929                 return NULL;
1930
1931         mutex_init(&priv->reg_mutex);
1932         mutex_init(&priv->mib_lock);
1933         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1934
1935         return priv;
1936 }
1937
1938 static void
1939 ar8xxx_free(struct ar8xxx_priv *priv)
1940 {
1941         if (priv->chip && priv->chip->cleanup)
1942                 priv->chip->cleanup(priv);
1943
1944         kfree(priv->chip_data);
1945         kfree(priv->mib_stats);
1946         kfree(priv);
1947 }
1948
1949 static int
1950 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1951 {
1952         const struct ar8xxx_chip *chip;
1953         struct switch_dev *swdev;
1954         int ret;
1955
1956         ret = ar8xxx_id_chip(priv);
1957         if (ret)
1958                 return ret;
1959
1960         chip = priv->chip;
1961
1962         swdev = &priv->dev;
1963         swdev->cpu_port = AR8216_PORT_CPU;
1964         swdev->name = chip->name;
1965         swdev->vlans = chip->vlans;
1966         swdev->ports = chip->ports;
1967         swdev->ops = chip->swops;
1968
1969         ret = ar8xxx_mib_init(priv);
1970         if (ret)
1971                 return ret;
1972
1973         return 0;
1974 }
1975
1976 static int
1977 ar8xxx_start(struct ar8xxx_priv *priv)
1978 {
1979         int ret;
1980
1981         priv->init = true;
1982
1983         ret = priv->chip->hw_init(priv);
1984         if (ret)
1985                 return ret;
1986
1987         ret = ar8xxx_sw_reset_switch(&priv->dev);
1988         if (ret)
1989                 return ret;
1990
1991         priv->init = false;
1992
1993         ar8xxx_mib_start(priv);
1994
1995         return 0;
1996 }
1997
1998 static int
1999 ar8xxx_phy_config_init(struct phy_device *phydev)
2000 {
2001         struct ar8xxx_priv *priv = phydev->priv;
2002         struct net_device *dev = phydev->attached_dev;
2003         int ret;
2004
2005         if (WARN_ON(!priv))
2006                 return -ENODEV;
2007
2008         if (priv->chip->config_at_probe)
2009                 return ar8xxx_phy_check_aneg(phydev);
2010
2011         priv->phy = phydev;
2012
2013         if (phydev->mdio.addr != 0) {
2014                 if (chip_is_ar8316(priv)) {
2015                         /* switch device has been initialized, reinit */
2016                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2017                         priv->initialized = false;
2018                         priv->port4_phy = true;
2019                         ar8316_hw_init(priv);
2020                         return 0;
2021                 }
2022
2023                 return 0;
2024         }
2025
2026         ret = ar8xxx_start(priv);
2027         if (ret)
2028                 return ret;
2029
2030         /* VID fixup only needed on ar8216 */
2031         if (chip_is_ar8216(priv)) {
2032                 dev->phy_ptr = priv;
2033                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2034                 dev->eth_mangle_rx = ar8216_mangle_rx;
2035                 dev->eth_mangle_tx = ar8216_mangle_tx;
2036         }
2037
2038         return 0;
2039 }
2040
2041 static bool
2042 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2043 {
2044         bool link_new, changed = false;
2045         u32 status;
2046         int i;
2047
2048         mutex_lock(&priv->reg_mutex);
2049
2050         for (i = 0; i < priv->dev.ports; i++) {
2051                 status = priv->chip->read_port_status(priv, i);
2052                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2053                 if (link_new == priv->link_up[i])
2054                         continue;
2055
2056                 priv->link_up[i] = link_new;
2057                 changed = true;
2058                 /* flush ARL entries for this port if it went down*/
2059                 if (!link_new)
2060                         priv->chip->atu_flush_port(priv, i);
2061                 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2062                          i, link_new ? "up" : "down");
2063         }
2064
2065         mutex_unlock(&priv->reg_mutex);
2066
2067         return changed;
2068 }
2069
2070 static int
2071 ar8xxx_phy_read_status(struct phy_device *phydev)
2072 {
2073         struct ar8xxx_priv *priv = phydev->priv;
2074         struct switch_port_link link;
2075
2076         /* check for switch port link changes */
2077         if (phydev->state == PHY_CHANGELINK)
2078                 ar8xxx_check_link_states(priv);
2079
2080         if (phydev->mdio.addr != 0)
2081                 return genphy_read_status(phydev);
2082
2083         ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2084         phydev->link = !!link.link;
2085         if (!phydev->link)
2086                 return 0;
2087
2088         switch (link.speed) {
2089         case SWITCH_PORT_SPEED_10:
2090                 phydev->speed = SPEED_10;
2091                 break;
2092         case SWITCH_PORT_SPEED_100:
2093                 phydev->speed = SPEED_100;
2094                 break;
2095         case SWITCH_PORT_SPEED_1000:
2096                 phydev->speed = SPEED_1000;
2097                 break;
2098         default:
2099                 phydev->speed = 0;
2100         }
2101         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2102
2103         phydev->state = PHY_RUNNING;
2104         netif_carrier_on(phydev->attached_dev);
2105         if (phydev->adjust_link)
2106                 phydev->adjust_link(phydev->attached_dev);
2107
2108         return 0;
2109 }
2110
2111 static int
2112 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2113 {
2114         if (phydev->mdio.addr == 0)
2115                 return 0;
2116
2117         return genphy_config_aneg(phydev);
2118 }
2119
2120 static const u32 ar8xxx_phy_ids[] = {
2121         0x004dd033,
2122         0x004dd034, /* AR8327 */
2123         0x004dd036, /* AR8337 */
2124         0x004dd041,
2125         0x004dd042,
2126         0x004dd043, /* AR8236 */
2127 };
2128
2129 static bool
2130 ar8xxx_phy_match(u32 phy_id)
2131 {
2132         int i;
2133
2134         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2135                 if (phy_id == ar8xxx_phy_ids[i])
2136                         return true;
2137
2138         return false;
2139 }
2140
2141 static bool
2142 ar8xxx_is_possible(struct mii_bus *bus)
2143 {
2144         unsigned int i, found_phys = 0;
2145
2146         for (i = 0; i < 5; i++) {
2147                 u32 phy_id;
2148
2149                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2150                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2151                 if (ar8xxx_phy_match(phy_id)) {
2152                         found_phys++;
2153                 } else if (phy_id) {
2154                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2155                                  dev_name(&bus->dev), i, phy_id);
2156                 }
2157         }
2158         return !!found_phys;
2159 }
2160
2161 static int
2162 ar8xxx_phy_probe(struct phy_device *phydev)
2163 {
2164         struct ar8xxx_priv *priv;
2165         struct switch_dev *swdev;
2166         int ret;
2167
2168         /* skip PHYs at unused adresses */
2169         if (phydev->mdio.addr != 0 && phydev->mdio.addr != 4)
2170                 return -ENODEV;
2171
2172         if (!ar8xxx_is_possible(phydev->mdio.bus))
2173                 return -ENODEV;
2174
2175         mutex_lock(&ar8xxx_dev_list_lock);
2176         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2177                 if (priv->mii_bus == phydev->mdio.bus)
2178                         goto found;
2179
2180         priv = ar8xxx_create();
2181         if (priv == NULL) {
2182                 ret = -ENOMEM;
2183                 goto unlock;
2184         }
2185
2186         priv->mii_bus = phydev->mdio.bus;
2187
2188         ret = ar8xxx_probe_switch(priv);
2189         if (ret)
2190                 goto free_priv;
2191
2192         swdev = &priv->dev;
2193         swdev->alias = dev_name(&priv->mii_bus->dev);
2194         ret = register_switch(swdev, NULL);
2195         if (ret)
2196                 goto free_priv;
2197
2198         pr_info("%s: %s rev. %u switch registered on %s\n",
2199                 swdev->devname, swdev->name, priv->chip_rev,
2200                 dev_name(&priv->mii_bus->dev));
2201
2202         list_add(&priv->list, &ar8xxx_dev_list);
2203
2204 found:
2205         priv->use_count++;
2206
2207         if (phydev->mdio.addr == 0) {
2208                 if (ar8xxx_has_gige(priv)) {
2209                         phydev->supported = SUPPORTED_1000baseT_Full;
2210                         phydev->advertising = ADVERTISED_1000baseT_Full;
2211                 } else {
2212                         phydev->supported = SUPPORTED_100baseT_Full;
2213                         phydev->advertising = ADVERTISED_100baseT_Full;
2214                 }
2215
2216                 if (priv->chip->config_at_probe) {
2217                         priv->phy = phydev;
2218
2219                         ret = ar8xxx_start(priv);
2220                         if (ret)
2221                                 goto err_unregister_switch;
2222                 }
2223         } else {
2224                 if (ar8xxx_has_gige(priv)) {
2225                         phydev->supported |= SUPPORTED_1000baseT_Full;
2226                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2227                 }
2228         }
2229
2230         phydev->priv = priv;
2231
2232         mutex_unlock(&ar8xxx_dev_list_lock);
2233
2234         return 0;
2235
2236 err_unregister_switch:
2237         if (--priv->use_count)
2238                 goto unlock;
2239
2240         unregister_switch(&priv->dev);
2241
2242 free_priv:
2243         ar8xxx_free(priv);
2244 unlock:
2245         mutex_unlock(&ar8xxx_dev_list_lock);
2246         return ret;
2247 }
2248
2249 static void
2250 ar8xxx_phy_detach(struct phy_device *phydev)
2251 {
2252         struct net_device *dev = phydev->attached_dev;
2253
2254         if (!dev)
2255                 return;
2256
2257         dev->phy_ptr = NULL;
2258         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2259         dev->eth_mangle_rx = NULL;
2260         dev->eth_mangle_tx = NULL;
2261 }
2262
2263 static void
2264 ar8xxx_phy_remove(struct phy_device *phydev)
2265 {
2266         struct ar8xxx_priv *priv = phydev->priv;
2267
2268         if (WARN_ON(!priv))
2269                 return;
2270
2271         phydev->priv = NULL;
2272
2273         mutex_lock(&ar8xxx_dev_list_lock);
2274
2275         if (--priv->use_count > 0) {
2276                 mutex_unlock(&ar8xxx_dev_list_lock);
2277                 return;
2278         }
2279
2280         list_del(&priv->list);
2281         mutex_unlock(&ar8xxx_dev_list_lock);
2282
2283         unregister_switch(&priv->dev);
2284         ar8xxx_mib_stop(priv);
2285         ar8xxx_free(priv);
2286 }
2287
2288 static int
2289 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2290 {
2291         /* we don't need an extra reset */
2292         return 0;
2293 }
2294
2295 static struct phy_driver ar8xxx_phy_driver[] = {
2296         {
2297                 .phy_id         = 0x004d0000,
2298                 .name           = "Atheros AR8216/AR8236/AR8316",
2299                 .phy_id_mask    = 0xffff0000,
2300                 .features       = PHY_BASIC_FEATURES,
2301                 .probe          = ar8xxx_phy_probe,
2302                 .remove         = ar8xxx_phy_remove,
2303                 .detach         = ar8xxx_phy_detach,
2304                 .config_init    = ar8xxx_phy_config_init,
2305                 .config_aneg    = ar8xxx_phy_config_aneg,
2306                 .read_status    = ar8xxx_phy_read_status,
2307                 .soft_reset     = ar8xxx_phy_soft_reset,
2308         }
2309 };
2310
2311 module_phy_driver(ar8xxx_phy_driver);
2312 MODULE_LICENSE("GPL");