target/linux/generic/backport-4.19/452-v5.0-mtd-spinand-add-support-for-GigaDevice-GD5FxGQ4xA.patch

   1 From c93c613214ac70c87beab5422a60077bf126b855 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Wed, 28 Nov 2018 21:07:25 +0800
   4 Subject: [PATCH 3/8] mtd: spinand: add support for GigaDevice GD5FxGQ4xA
   5
   6 Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.
   7
   8 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
   9 Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
  10 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  11 ---
  12  drivers/mtd/nand/spi/Makefile     |   2 +-
  13  drivers/mtd/nand/spi/core.c       |   1 +
  14  drivers/mtd/nand/spi/gigadevice.c | 148 ++++++++++++++++++++++++++++++
  15  include/linux/mtd/spinand.h       |   1 +
  16  4 files changed, 151 insertions(+), 1 deletion(-)
  17  create mode 100644 drivers/mtd/nand/spi/gigadevice.c
  18
  19 --- a/drivers/mtd/nand/spi/Makefile
  20 +++ b/drivers/mtd/nand/spi/Makefile
  21 @@ -1,3 +1,3 @@
  22  # SPDX-License-Identifier: GPL-2.0
  23 -spinand-objs := core.o macronix.o micron.o toshiba.o winbond.o
  24 +spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
  25  obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
  26 --- a/drivers/mtd/nand/spi/core.c
  27 +++ b/drivers/mtd/nand/spi/core.c
  28 @@ -762,6 +762,7 @@ static const struct nand_ops spinand_ops
  29  };
  30
  31  static const struct spinand_manufacturer *spinand_manufacturers[] = {
  32 +       &gigadevice_spinand_manufacturer,
  33         &macronix_spinand_manufacturer,
  34         &micron_spinand_manufacturer,
  35         &toshiba_spinand_manufacturer,
  36 --- /dev/null
  37 +++ b/drivers/mtd/nand/spi/gigadevice.c
  38 @@ -0,0 +1,148 @@
  39 +// SPDX-License-Identifier: GPL-2.0
  40 +/*
  41 + * Author:
  42 + *     Chuanhong Guo <gch981213@gmail.com>
  43 + */
  44 +
  45 +#include <linux/device.h>
  46 +#include <linux/kernel.h>
  47 +#include <linux/mtd/spinand.h>
  48 +
  49 +#define SPINAND_MFR_GIGADEVICE                 0xC8
  50 +#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS     (1 << 4)
  51 +#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS       (3 << 4)
  52 +
  53 +static SPINAND_OP_VARIANTS(read_cache_variants,
  54 +               SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  55 +               SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
  56 +               SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
  57 +               SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
  58 +               SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
  59 +               SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
  60 +
  61 +static SPINAND_OP_VARIANTS(write_cache_variants,
  62 +               SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
  63 +               SPINAND_PROG_LOAD(true, 0, NULL, 0));
  64 +
  65 +static SPINAND_OP_VARIANTS(update_cache_variants,
  66 +               SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
  67 +               SPINAND_PROG_LOAD(false, 0, NULL, 0));
  68 +
  69 +static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
  70 +                                 struct mtd_oob_region *region)
  71 +{
  72 +       if (section > 3)
  73 +               return -ERANGE;
  74 +
  75 +       region->offset = (16 * section) + 8;
  76 +       region->length = 8;
  77 +
  78 +       return 0;
  79 +}
  80 +
  81 +static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
  82 +                                  struct mtd_oob_region *region)
  83 +{
  84 +       if (section > 3)
  85 +               return -ERANGE;
  86 +
  87 +       if (section) {
  88 +               region->offset = 16 * section;
  89 +               region->length = 8;
  90 +       } else {
  91 +               /* section 0 has one byte reserved for bad block mark */
  92 +               region->offset = 1;
  93 +               region->length = 7;
  94 +       }
  95 +       return 0;
  96 +}
  97 +
  98 +static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
  99 +                                        u8 status)
 100 +{
 101 +       switch (status & STATUS_ECC_MASK) {
 102 +       case STATUS_ECC_NO_BITFLIPS:
 103 +               return 0;
 104 +
 105 +       case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
 106 +               /* 1-7 bits are flipped. return the maximum. */
 107 +               return 7;
 108 +
 109 +       case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
 110 +               return 8;
 111 +
 112 +       case STATUS_ECC_UNCOR_ERROR:
 113 +               return -EBADMSG;
 114 +
 115 +       default:
 116 +               break;
 117 +       }
 118 +
 119 +       return -EINVAL;
 120 +}
 121 +
 122 +static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
 123 +       .ecc = gd5fxgq4xa_ooblayout_ecc,
 124 +       .free = gd5fxgq4xa_ooblayout_free,
 125 +};
 126 +
 127 +static const struct spinand_info gigadevice_spinand_table[] = {
 128 +       SPINAND_INFO("GD5F1GQ4xA", 0xF1,
 129 +                    NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
 130 +                    NAND_ECCREQ(8, 512),
 131 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 132 +                                             &write_cache_variants,
 133 +                                             &update_cache_variants),
 134 +                    0,
 135 +                    SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
 136 +                                    gd5fxgq4xa_ecc_get_status)),
 137 +       SPINAND_INFO("GD5F2GQ4xA", 0xF2,
 138 +                    NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
 139 +                    NAND_ECCREQ(8, 512),
 140 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 141 +                                             &write_cache_variants,
 142 +                                             &update_cache_variants),
 143 +                    0,
 144 +                    SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
 145 +                                    gd5fxgq4xa_ecc_get_status)),
 146 +       SPINAND_INFO("GD5F4GQ4xA", 0xF4,
 147 +                    NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
 148 +                    NAND_ECCREQ(8, 512),
 149 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 150 +                                             &write_cache_variants,
 151 +                                             &update_cache_variants),
 152 +                    0,
 153 +                    SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
 154 +                                    gd5fxgq4xa_ecc_get_status)),
 155 +};
 156 +
 157 +static int gigadevice_spinand_detect(struct spinand_device *spinand)
 158 +{
 159 +       u8 *id = spinand->id.data;
 160 +       int ret;
 161 +
 162 +       /*
 163 +        * For GD NANDs, There is an address byte needed to shift in before IDs
 164 +        * are read out, so the first byte in raw_id is dummy.
 165 +        */
 166 +       if (id[1] != SPINAND_MFR_GIGADEVICE)
 167 +               return 0;
 168 +
 169 +       ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
 170 +                                    ARRAY_SIZE(gigadevice_spinand_table),
 171 +                                    id[2]);
 172 +       if (ret)
 173 +               return ret;
 174 +
 175 +       return 1;
 176 +}
 177 +
 178 +static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
 179 +       .detect = gigadevice_spinand_detect,
 180 +};
 181 +
 182 +const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
 183 +       .id = SPINAND_MFR_GIGADEVICE,
 184 +       .name = "GigaDevice",
 185 +       .ops = &gigadevice_spinand_manuf_ops,
 186 +};
 187 --- a/include/linux/mtd/spinand.h
 188 +++ b/include/linux/mtd/spinand.h
 189 @@ -194,6 +194,7 @@ struct spinand_manufacturer {
 190  };
 191
 192  /* SPI NAND manufacturers */
 193 +extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
 194  extern const struct spinand_manufacturer macronix_spinand_manufacturer;
 195  extern const struct spinand_manufacturer micron_spinand_manufacturer;
 196  extern const struct spinand_manufacturer toshiba_spinand_manufacturer;