target/linux/generic/backport-4.19/451-v5.1-mtd-spinand-Add-support-for-GigaDevice-GD5F1GQ4UExxG.patch

   1 From c40c7a990a46e5102a1cc4190557bf315d32d80d Mon Sep 17 00:00:00 2001
   2 From: Stefan Roese <sr@denx.de>
   3 Date: Thu, 24 Jan 2019 13:48:06 +0100
   4 Subject: [PATCH] mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG
   5
   6 Add support for GigaDevice GD5F1GQ4UExxG SPI NAND chip.
   7
   8 Signed-off-by: Stefan Roese <sr@denx.de>
   9 Cc: Chuanhong Guo <gch981213@gmail.com>
  10 Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
  11 Cc: Miquel Raynal <miquel.raynal@bootlin.com>
  12 Cc: Boris Brezillon <bbrezillon@kernel.org>
  13 Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
  14 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  15 ---
  16  drivers/mtd/nand/spi/gigadevice.c | 83 +++++++++++++++++++++++++++++++++++++++
  17  1 file changed, 83 insertions(+)
  18
  19 --- a/drivers/mtd/nand/spi/gigadevice.c
  20 +++ b/drivers/mtd/nand/spi/gigadevice.c
  21 @@ -12,6 +12,8 @@
  22  #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS     (1 << 4)
  23  #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS       (3 << 4)
  24
  25 +#define GD5FXGQ4UEXXG_REG_STATUS2              0xf0
  26 +
  27  static SPINAND_OP_VARIANTS(read_cache_variants,
  28                 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  29                 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
  30 @@ -81,11 +83,83 @@ static int gd5fxgq4xa_ecc_get_status(str
  31         return -EINVAL;
  32  }
  33
  34 +static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
  35 +                                      struct mtd_oob_region *region)
  36 +{
  37 +       if (section)
  38 +               return -ERANGE;
  39 +
  40 +       region->offset = 64;
  41 +       region->length = 64;
  42 +
  43 +       return 0;
  44 +}
  45 +
  46 +static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
  47 +                                       struct mtd_oob_region *region)
  48 +{
  49 +       if (section)
  50 +               return -ERANGE;
  51 +
  52 +       /* Reserve 1 bytes for the BBM. */
  53 +       region->offset = 1;
  54 +       region->length = 63;
  55 +
  56 +       return 0;
  57 +}
  58 +
  59 +static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
  60 +                                       u8 status)
  61 +{
  62 +       u8 status2;
  63 +       struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
  64 +                                                     &status2);
  65 +       int ret;
  66 +
  67 +       switch (status & STATUS_ECC_MASK) {
  68 +       case STATUS_ECC_NO_BITFLIPS:
  69 +               return 0;
  70 +
  71 +       case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
  72 +               /*
  73 +                * Read status2 register to determine a more fine grained
  74 +                * bit error status
  75 +                */
  76 +               ret = spi_mem_exec_op(spinand->spimem, &op);
  77 +               if (ret)
  78 +                       return ret;
  79 +
  80 +               /*
  81 +                * 4 ... 7 bits are flipped (1..4 can't be detected, so
  82 +                * report the maximum of 4 in this case
  83 +                */
  84 +               /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
  85 +               return ((status & STATUS_ECC_MASK) >> 2) |
  86 +                       ((status2 & STATUS_ECC_MASK) >> 4);
  87 +
  88 +       case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
  89 +               return 8;
  90 +
  91 +       case STATUS_ECC_UNCOR_ERROR:
  92 +               return -EBADMSG;
  93 +
  94 +       default:
  95 +               break;
  96 +       }
  97 +
  98 +       return -EINVAL;
  99 +}
 100 +
 101  static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
 102         .ecc = gd5fxgq4xa_ooblayout_ecc,
 103         .free = gd5fxgq4xa_ooblayout_free,
 104  };
 105
 106 +static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
 107 +       .ecc = gd5fxgq4uexxg_ooblayout_ecc,
 108 +       .free = gd5fxgq4uexxg_ooblayout_free,
 109 +};
 110 +
 111  static const struct spinand_info gigadevice_spinand_table[] = {
 112         SPINAND_INFO("GD5F1GQ4xA", 0xF1,
 113                      NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
 114 @@ -114,6 +188,15 @@ static const struct spinand_info gigadev
 115                      0,
 116                      SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
 117                                      gd5fxgq4xa_ecc_get_status)),
 118 +       SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
 119 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 120 +                    NAND_ECCREQ(8, 512),
 121 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 122 +                                             &write_cache_variants,
 123 +                                             &update_cache_variants),
 124 +                    0,
 125 +                    SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
 126 +                                    gd5fxgq4uexxg_ecc_get_status)),
 127  };
 128
 129  static int gigadevice_spinand_detect(struct spinand_device *spinand)