1 --- a/arch/arm/mach-cns3xxx/Kconfig
2 +++ b/arch/arm/mach-cns3xxx/Kconfig
3 @@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX
4 select HAVE_ARM_SCU if SMP
9 Support for Cavium Networks CNS3XXX platform.
11 --- a/arch/arm/mach-cns3xxx/Makefile
12 +++ b/arch/arm/mach-cns3xxx/Makefile
13 @@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
14 cns3xxx-$(CONFIG_ATAGS) += devices.o
15 cns3xxx-$(CONFIG_PCI) += pcie.o
16 cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
17 -cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
18 +cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
19 cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
20 --- a/arch/arm/mach-cns3xxx/cns3xxx.h
21 +++ b/arch/arm/mach-cns3xxx/cns3xxx.h
23 #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
24 #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
26 +#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
28 * Power management and clock control
30 --- a/arch/arm/mm/Kconfig
31 +++ b/arch/arm/mm/Kconfig
32 @@ -849,7 +849,7 @@ config VDSO
35 bool "Enable read/write for ownership DMA cache maintenance"
36 - depends on CPU_V6K && SMP
37 + depends on CPU_V6K && SMP && !ARCH_CNS3XXX
40 The Snoop Control Unit on ARM11MPCore does not detect the