3 @@ -71,6 +71,7 @@ obj-$(CONFIG_PARIDE) += block/paride/
4 obj-$(CONFIG_TC) += tc/
5 obj-$(CONFIG_UWB) += uwb/
6 obj-$(CONFIG_USB_OTG_UTILS) += usb/
7 +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/
8 obj-$(CONFIG_USB) += usb/
9 obj-$(CONFIG_PCI) += usb/
10 obj-$(CONFIG_USB_GADGET) += usb/
11 --- a/drivers/usb/Kconfig
12 +++ b/drivers/usb/Kconfig
13 @@ -134,6 +134,8 @@ source "drivers/usb/musb/Kconfig"
15 source "drivers/usb/renesas_usbhs/Kconfig"
17 +source "drivers/usb/dwc/Kconfig"
19 source "drivers/usb/class/Kconfig"
21 source "drivers/usb/storage/Kconfig"
23 +++ b/drivers/usb/dwc/Kconfig
26 +# USB Dual Role (OTG-ready) Controller Drivers
27 +# for silicon based on Synopsys DesignWare IP
30 +comment "Enable Host or Gadget support for DesignWare OTG controller"
31 +depends on !USB && USB_GADGET=n
34 + tristate "Synopsys DWC OTG Controller"
37 + This driver provides USB Device Controller support for the
38 + Synopsys DesignWare USB OTG Core used on the Cavium CNS34xx SOC.
41 + bool "Enable DWC Debugging"
42 + depends on USB_DWC_OTG
45 + Enable DWC driver debugging
48 + prompt "DWC Mode Selection"
49 + depends on USB_DWC_OTG
50 + default DWC_HOST_ONLY
52 + Select the DWC Core in OTG, Host only, or Device only mode.
55 + bool "DWC Host Only Mode"
60 + select USB_GADGET_SELECTED
62 +config DWC_DEVICE_ONLY
63 + bool "DWC Device Only Mode"
65 + select USB_GADGET_SELECTED
70 +++ b/drivers/usb/dwc/Makefile
73 +# Makefile for DWC_otg Highspeed USB controller driver
76 +EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
77 +#EXTRA_CFLAGS += -Dlinux -DDWC_HS_ELECT_TST
78 +#EXTRA_CFLAGS += -DDWC_EN_ISOC
80 +ifneq ($(CONFIG_DWC_HOST_ONLY),)
81 +EXTRA_CFLAGS += -DDWC_HOST_ONLY
84 +ifneq ($(CONFIG_DWC_DEVICE_ONLY),)
85 +EXTRA_CFLAGS += -DDWC_DEVICE_ONLY
88 +ifneq ($(CONFIG_DWC_DEBUG),)
89 +EXTRA_CFLAGS += -DDEBUG
92 +obj-$(CONFIG_USB_DWC_OTG) := dwc_otg.o
94 +dwc_otg-objs := otg_driver.o otg_attr.o
95 +dwc_otg-objs += otg_cil.o otg_cil_intr.o
96 +dwc_otg-objs += otg_pcd.o otg_pcd_intr.o
97 +dwc_otg-objs += otg_hcd.o otg_hcd_intr.o otg_hcd_queue.o
99 +++ b/drivers/usb/dwc/otg_attr.c
101 +/* ==========================================================================
102 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
104 + * $Date: 2008/07/15 $
105 + * $Change: 1064918 $
107 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
108 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
109 + * otherwise expressly agreed to in writing between Synopsys and you.
111 + * The Software IS NOT an item of Licensed Software or Licensed Product under
112 + * any End User Software License Agreement or Agreement for Licensed Product
113 + * with Synopsys or any supplement thereto. You are permitted to use and
114 + * redistribute this Software in source and binary forms, with or without
115 + * modification, provided that redistributions of source code must retain this
116 + * notice. You may not view, use, disclose, copy or distribute this file or
117 + * any information contained herein except pursuant to this license grant from
118 + * Synopsys. If you do not agree with this notice, including the disclaimer
119 + * below, then you are not authorized to use the Software.
121 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
122 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
123 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
124 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
125 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
126 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
127 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
128 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
129 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
130 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
132 + * ========================================================================== */
136 + * The diagnostic interface will provide access to the controller for
137 + * bringing up the hardware and testing. The Linux driver attributes
138 + * feature will be used to provide the Linux Diagnostic
139 + * Interface. These attributes are accessed through sysfs.
142 +/** @page "Linux Module Attributes"
144 + * The Linux module attributes feature is used to provide the Linux
145 + * Diagnostic Interface. These attributes are accessed through sysfs.
146 + * The diagnostic interface will provide access to the controller for
147 + * bringing up the hardware and testing.
150 + The following table shows the attributes.
153 + <td><b> Name</b></td>
154 + <td><b> Description</b></td>
155 + <td><b> Access</b></td>
160 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
165 + <td> hnpcapable </td>
166 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
167 + Read returns the current value.</td>
168 + <td> Read/Write</td>
172 + <td> srpcapable </td>
173 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
174 + Read returns the current value.</td>
175 + <td> Read/Write</td>
180 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
181 + <td> Read/Write</td>
186 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
187 + <td> Read/Write</td>
191 + <td> buspower </td>
192 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
193 + <td> Read/Write</td>
197 + <td> bussuspend </td>
198 + <td> Suspends the USB bus.</td>
199 + <td> Read/Write</td>
203 + <td> busconnected </td>
204 + <td> Gets the connection status of the bus</td>
210 + <td> Gets or sets the Core Control Status Register.</td>
211 + <td> Read/Write</td>
216 + <td> Gets or sets the Core USB Configuration Register</td>
217 + <td> Read/Write</td>
222 + <td> Gets or sets the Receive FIFO Size Register</td>
223 + <td> Read/Write</td>
227 + <td> gnptxfsiz </td>
228 + <td> Gets or sets the non-periodic Transmit Size Register</td>
229 + <td> Read/Write</td>
233 + <td> gpvndctl </td>
234 + <td> Gets or sets the PHY Vendor Control Register</td>
235 + <td> Read/Write</td>
240 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
241 + or sets the upper 16 bits.</td>
242 + <td> Read/Write</td>
247 + <td> Gets or sets the value of the User ID Register</td>
248 + <td> Read/Write</td>
253 + <td> Gets the value of the Synopsys ID Regester</td>
258 + <td> devspeed </td>
259 + <td> Gets or sets the device speed setting in the DCFG register</td>
260 + <td> Read/Write</td>
264 + <td> enumspeed </td>
265 + <td> Gets the device enumeration Speed.</td>
270 + <td> hptxfsiz </td>
271 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
277 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
278 + <td> Read/Write</td>
282 + <td> regoffset </td>
283 + <td> Sets the register offset for the next Register Access</td>
284 + <td> Read/Write</td>
288 + <td> regvalue </td>
289 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
290 + <td> Read/Write</td>
294 + <td> remote_wakeup </td>
295 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
296 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
297 + Wakeup signalling bit in the Device Control Register is set for 1
299 + <td> Read/Write</td>
304 + <td> Dumps the contents of core registers.</td>
309 + <td> spramdump </td>
310 + <td> Dumps the contents of core registers.</td>
316 + <td> Dumps the current HCD state.</td>
321 + <td> hcd_frrem </td>
322 + <td> Shows the average value of the Frame Remaining
323 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
324 + occurs. This can be used to determine the average interrupt latency. Also
325 + shows the average Frame Remaining value for start_transfer and the "a" and
326 + "b" sample points. The "a" and "b" sample points may be used during debugging
327 + bto determine how long it takes to execute a section of the HCD code.</td>
332 + <td> rd_reg_test </td>
333 + <td> Displays the time required to read the GNPTXFSIZ register many times
334 + (the output shows the number of times the register is read).
339 + <td> wr_reg_test </td>
340 + <td> Displays the time required to write the GNPTXFSIZ register many times
341 + (the output shows the number of times the register is written).
348 + To get the current mode:
349 + cat /sys/devices/lm0/mode
351 + To power down the USB:
352 + echo 0 > /sys/devices/lm0/buspower
355 +#include <linux/kernel.h>
356 +#include <linux/module.h>
357 +#include <linux/moduleparam.h>
358 +#include <linux/init.h>
359 +#include <linux/device.h>
360 +#include <linux/platform_device.h>
361 +#include <linux/errno.h>
362 +#include <linux/types.h>
363 +#include <linux/stat.h> /* permission constants */
364 +#include <linux/version.h>
366 +#include <asm/sizes.h>
368 +#include <asm/sizes.h>
370 +#include "otg_plat.h"
371 +#include "otg_attr.h"
372 +#include "otg_driver.h"
373 +#include "otg_pcd.h"
374 +#include "otg_hcd.h"
377 + * MACROs for defining sysfs attribute
379 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
380 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
382 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
383 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
385 + val = dwc_read_reg32 (_addr_); \
386 + val = (val & (_mask_)) >> _shift_; \
387 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
389 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
390 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
391 + const char *buf, size_t count) \
393 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
394 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
395 + uint32_t set = simple_strtoul(buf, NULL, 16); \
396 + uint32_t clear = set; \
397 + clear = ((~clear) << _shift_) & _mask_; \
398 + set = (set << _shift_) & _mask_; \
399 + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
400 + dwc_modify_reg32(_addr_, clear, set); \
405 + * MACROs for defining sysfs attribute for 32-bit registers
407 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
408 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
410 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
411 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
413 + val = dwc_read_reg32 (_addr_); \
414 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
416 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
417 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
418 + const char *buf, size_t count) \
420 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
421 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
422 + uint32_t val = simple_strtoul(buf, NULL, 16); \
423 + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
424 + dwc_write_reg32(_addr_, val); \
428 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
429 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
430 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
431 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
433 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
434 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
435 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
437 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
438 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
439 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
440 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
442 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
443 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
444 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
447 +/** @name Functions for Show/Store of Attributes */
451 + * Show the register offset of the Register Access.
453 +static ssize_t regoffset_show( struct device *_dev,
454 + struct device_attribute *attr,
457 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
458 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
459 + return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
463 + * Set the register offset for the next Register Access Read/Write
465 +static ssize_t regoffset_store( struct device *_dev,
466 + struct device_attribute *attr,
470 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
471 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
472 + uint32_t offset = simple_strtoul(buf, NULL, 16);
473 + //dev_dbg(_dev, "Offset=0x%08x\n", offset);
474 + if (offset < SZ_256K ) {
475 + otg_dev->reg_offset = offset;
478 + dev_err( _dev, "invalid offset\n" );
483 +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store);
487 + * Show the value of the register at the offset in the reg_offset
490 +static ssize_t regvalue_show( struct device *_dev,
491 + struct device_attribute *attr,
494 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
495 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
497 + volatile uint32_t *addr;
499 + if (otg_dev->reg_offset != 0xFFFFFFFF &&
500 + 0 != otg_dev->base) {
501 + /* Calculate the address */
502 + addr = (uint32_t*)(otg_dev->reg_offset +
503 + (uint8_t*)otg_dev->base);
504 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
505 + val = dwc_read_reg32( addr );
506 + return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
507 + "Reg@0x%06x = 0x%08x\n",
508 + otg_dev->reg_offset, val);
511 + dev_err(_dev, "Invalid offset (0x%0x)\n",
512 + otg_dev->reg_offset);
513 + return sprintf(buf, "invalid offset\n" );
518 + * Store the value in the register at the offset in the reg_offset
522 +static ssize_t regvalue_store( struct device *_dev,
523 + struct device_attribute *attr,
527 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
528 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
529 + volatile uint32_t * addr;
530 + uint32_t val = simple_strtoul(buf, NULL, 16);
531 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
532 + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
533 + /* Calculate the address */
534 + addr = (uint32_t*)(otg_dev->reg_offset +
535 + (uint8_t*)otg_dev->base);
536 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
537 + dwc_write_reg32( addr, val );
540 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
541 + otg_dev->reg_offset);
545 +DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
550 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
551 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
552 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
554 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
555 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
556 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
558 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
559 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
560 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
561 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
562 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
563 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
564 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
565 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
566 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
567 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
569 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
570 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
574 + * @todo Add code to initiate the HNP.
577 + * Show the HNP status bit
579 +static ssize_t hnp_show( struct device *_dev,
580 + struct device_attribute *attr,
583 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
584 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
585 + gotgctl_data_t val;
586 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
587 + return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
591 + * Set the HNP Request bit
593 +static ssize_t hnp_store( struct device *_dev,
594 + struct device_attribute *attr,
598 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
599 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
600 + uint32_t in = simple_strtoul(buf, NULL, 16);
601 + uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
602 + gotgctl_data_t mem;
603 + mem.d32 = dwc_read_reg32(addr);
605 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
606 + dwc_write_reg32(addr, mem.d32);
609 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
612 + * @todo Add code to initiate the SRP.
615 + * Show the SRP status bit
617 +static ssize_t srp_show( struct device *_dev,
618 + struct device_attribute *attr,
621 +#ifndef DWC_HOST_ONLY
622 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
623 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
624 + gotgctl_data_t val;
625 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
626 + return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
628 + return sprintf(buf, "Host Only Mode!\n");
635 + * Set the SRP Request bit
637 +static ssize_t srp_store( struct device *_dev,
638 + struct device_attribute *attr,
642 +#ifndef DWC_HOST_ONLY
643 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
644 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
645 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
649 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
652 + * @todo Need to do more for power on/off?
655 + * Show the Bus Power status
657 +static ssize_t buspower_show( struct device *_dev,
658 + struct device_attribute *attr,
661 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
662 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
664 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
665 + return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
670 + * Set the Bus Power status
672 +static ssize_t buspower_store( struct device *_dev,
673 + struct device_attribute *attr,
677 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
678 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
679 + uint32_t on = simple_strtoul(buf, NULL, 16);
680 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
683 + mem.d32 = dwc_read_reg32(addr);
686 + //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
687 + dwc_write_reg32(addr, mem.d32);
691 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
694 + * @todo Need to do more for suspend?
697 + * Show the Bus Suspend status
699 +static ssize_t bussuspend_show( struct device *_dev,
700 + struct device_attribute *attr,
703 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
704 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
706 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
707 + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
711 + * Set the Bus Suspend status
713 +static ssize_t bussuspend_store( struct device *_dev,
714 + struct device_attribute *attr,
718 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
719 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
720 + uint32_t in = simple_strtoul(buf, NULL, 16);
721 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
723 + mem.d32 = dwc_read_reg32(addr);
724 + mem.b.prtsusp = in;
725 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
726 + dwc_write_reg32(addr, mem.d32);
729 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
732 + * Show the status of Remote Wakeup.
734 +static ssize_t remote_wakeup_show( struct device *_dev,
735 + struct device_attribute *attr,
738 +#ifndef DWC_HOST_ONLY
739 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
740 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
743 + dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
744 + return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
745 + val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
747 + return sprintf(buf, "Host Only Mode!\n");
751 + * Initiate a remote wakeup of the host. The Device control register
752 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
756 +static ssize_t remote_wakeup_store( struct device *_dev,
757 + struct device_attribute *attr,
761 +#ifndef DWC_HOST_ONLY
762 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
763 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
764 + uint32_t val = simple_strtoul(buf, NULL, 16);
766 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
769 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
774 +DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
775 + remote_wakeup_store);
778 + * Dump global registers and either host or device registers (depending on the
779 + * current mode of the core).
781 +static ssize_t regdump_show( struct device *_dev,
782 + struct device_attribute *attr,
785 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
786 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
787 + dwc_otg_dump_global_registers( otg_dev->core_if);
788 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
789 + dwc_otg_dump_host_registers( otg_dev->core_if);
791 + dwc_otg_dump_dev_registers( otg_dev->core_if);
794 + return sprintf( buf, "Register Dump\n" );
797 +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
800 + * Dump global registers and either host or device registers (depending on the
801 + * current mode of the core).
803 +static ssize_t spramdump_show( struct device *_dev,
804 + struct device_attribute *attr,
807 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
808 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
809 + dwc_otg_dump_spram( otg_dev->core_if);
811 + return sprintf( buf, "SPRAM Dump\n" );
814 +DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
817 + * Dump the current hcd state.
819 +static ssize_t hcddump_show( struct device *_dev,
820 + struct device_attribute *attr,
823 +#ifndef DWC_DEVICE_ONLY
824 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
825 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
826 + dwc_otg_hcd_dump_state(otg_dev->hcd);
828 + return sprintf( buf, "HCD Dump\n" );
831 +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
834 + * Dump the average frame remaining at SOF. This can be used to
835 + * determine average interrupt latency. Frame remaining is also shown for
836 + * start transfer and two additional sample points.
838 +static ssize_t hcd_frrem_show( struct device *_dev,
839 + struct device_attribute *attr,
842 +#ifndef DWC_DEVICE_ONLY
843 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
844 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
845 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
847 + return sprintf( buf, "HCD Dump Frame Remaining\n" );
850 +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
853 + * Displays the time required to read the GNPTXFSIZ register many times (the
854 + * output shows the number of times the register is read).
856 +#define RW_REG_COUNT 10000000
857 +#define MSEC_PER_JIFFIE 1000/HZ
858 +static ssize_t rd_reg_test_show( struct device *_dev,
859 + struct device_attribute *attr,
862 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
863 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
868 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
869 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
870 + start_jiffies = jiffies;
871 + for (i = 0; i < RW_REG_COUNT; i++) {
872 + dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
874 + time = jiffies - start_jiffies;
875 + return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
876 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
879 +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
882 + * Displays the time required to write the GNPTXFSIZ register many times (the
883 + * output shows the number of times the register is written).
885 +static ssize_t wr_reg_test_show( struct device *_dev,
886 + struct device_attribute *attr,
889 + struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
890 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
896 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
897 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
898 + reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
899 + start_jiffies = jiffies;
900 + for (i = 0; i < RW_REG_COUNT; i++) {
901 + dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
903 + time = jiffies - start_jiffies;
904 + return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
905 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
908 +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
912 + * Create the device files
914 +void dwc_otg_attr_create (struct platform_device *pdev)
916 + struct device *dev = &pdev->dev;
919 + error = device_create_file(dev, &dev_attr_regoffset);
920 + error = device_create_file(dev, &dev_attr_regvalue);
921 + error = device_create_file(dev, &dev_attr_mode);
922 + error = device_create_file(dev, &dev_attr_hnpcapable);
923 + error = device_create_file(dev, &dev_attr_srpcapable);
924 + error = device_create_file(dev, &dev_attr_hnp);
925 + error = device_create_file(dev, &dev_attr_srp);
926 + error = device_create_file(dev, &dev_attr_buspower);
927 + error = device_create_file(dev, &dev_attr_bussuspend);
928 + error = device_create_file(dev, &dev_attr_busconnected);
929 + error = device_create_file(dev, &dev_attr_gotgctl);
930 + error = device_create_file(dev, &dev_attr_gusbcfg);
931 + error = device_create_file(dev, &dev_attr_grxfsiz);
932 + error = device_create_file(dev, &dev_attr_gnptxfsiz);
933 + error = device_create_file(dev, &dev_attr_gpvndctl);
934 + error = device_create_file(dev, &dev_attr_ggpio);
935 + error = device_create_file(dev, &dev_attr_guid);
936 + error = device_create_file(dev, &dev_attr_gsnpsid);
937 + error = device_create_file(dev, &dev_attr_devspeed);
938 + error = device_create_file(dev, &dev_attr_enumspeed);
939 + error = device_create_file(dev, &dev_attr_hptxfsiz);
940 + error = device_create_file(dev, &dev_attr_hprt0);
941 + error = device_create_file(dev, &dev_attr_remote_wakeup);
942 + error = device_create_file(dev, &dev_attr_regdump);
943 + error = device_create_file(dev, &dev_attr_spramdump);
944 + error = device_create_file(dev, &dev_attr_hcddump);
945 + error = device_create_file(dev, &dev_attr_hcd_frrem);
946 + error = device_create_file(dev, &dev_attr_rd_reg_test);
947 + error = device_create_file(dev, &dev_attr_wr_reg_test);
951 + * Remove the device files
953 +void dwc_otg_attr_remove (struct platform_device *pdev)
955 + struct device *dev = &pdev->dev;
957 + device_remove_file(dev, &dev_attr_regoffset);
958 + device_remove_file(dev, &dev_attr_regvalue);
959 + device_remove_file(dev, &dev_attr_mode);
960 + device_remove_file(dev, &dev_attr_hnpcapable);
961 + device_remove_file(dev, &dev_attr_srpcapable);
962 + device_remove_file(dev, &dev_attr_hnp);
963 + device_remove_file(dev, &dev_attr_srp);
964 + device_remove_file(dev, &dev_attr_buspower);
965 + device_remove_file(dev, &dev_attr_bussuspend);
966 + device_remove_file(dev, &dev_attr_busconnected);
967 + device_remove_file(dev, &dev_attr_gotgctl);
968 + device_remove_file(dev, &dev_attr_gusbcfg);
969 + device_remove_file(dev, &dev_attr_grxfsiz);
970 + device_remove_file(dev, &dev_attr_gnptxfsiz);
971 + device_remove_file(dev, &dev_attr_gpvndctl);
972 + device_remove_file(dev, &dev_attr_ggpio);
973 + device_remove_file(dev, &dev_attr_guid);
974 + device_remove_file(dev, &dev_attr_gsnpsid);
975 + device_remove_file(dev, &dev_attr_devspeed);
976 + device_remove_file(dev, &dev_attr_enumspeed);
977 + device_remove_file(dev, &dev_attr_hptxfsiz);
978 + device_remove_file(dev, &dev_attr_hprt0);
979 + device_remove_file(dev, &dev_attr_remote_wakeup);
980 + device_remove_file(dev, &dev_attr_regdump);
981 + device_remove_file(dev, &dev_attr_spramdump);
982 + device_remove_file(dev, &dev_attr_hcddump);
983 + device_remove_file(dev, &dev_attr_hcd_frrem);
984 + device_remove_file(dev, &dev_attr_rd_reg_test);
985 + device_remove_file(dev, &dev_attr_wr_reg_test);
988 +++ b/drivers/usb/dwc/otg_attr.h
990 +/* ==========================================================================
991 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
993 + * $Date: 2005/03/28 $
994 + * $Change: 477051 $
996 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
997 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
998 + * otherwise expressly agreed to in writing between Synopsys and you.
1000 + * The Software IS NOT an item of Licensed Software or Licensed Product under
1001 + * any End User Software License Agreement or Agreement for Licensed Product
1002 + * with Synopsys or any supplement thereto. You are permitted to use and
1003 + * redistribute this Software in source and binary forms, with or without
1004 + * modification, provided that redistributions of source code must retain this
1005 + * notice. You may not view, use, disclose, copy or distribute this file or
1006 + * any information contained herein except pursuant to this license grant from
1007 + * Synopsys. If you do not agree with this notice, including the disclaimer
1008 + * below, then you are not authorized to use the Software.
1010 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1011 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1012 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1013 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1014 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1015 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1016 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1017 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1018 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1019 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1021 + * ========================================================================== */
1023 +#if !defined(__DWC_OTG_ATTR_H__)
1024 +#define __DWC_OTG_ATTR_H__
1027 + * This file contains the interface to the Linux device attributes.
1029 +extern struct device_attribute dev_attr_regoffset;
1030 +extern struct device_attribute dev_attr_regvalue;
1032 +extern struct device_attribute dev_attr_mode;
1033 +extern struct device_attribute dev_attr_hnpcapable;
1034 +extern struct device_attribute dev_attr_srpcapable;
1035 +extern struct device_attribute dev_attr_hnp;
1036 +extern struct device_attribute dev_attr_srp;
1037 +extern struct device_attribute dev_attr_buspower;
1038 +extern struct device_attribute dev_attr_bussuspend;
1039 +extern struct device_attribute dev_attr_busconnected;
1040 +extern struct device_attribute dev_attr_gotgctl;
1041 +extern struct device_attribute dev_attr_gusbcfg;
1042 +extern struct device_attribute dev_attr_grxfsiz;
1043 +extern struct device_attribute dev_attr_gnptxfsiz;
1044 +extern struct device_attribute dev_attr_gpvndctl;
1045 +extern struct device_attribute dev_attr_ggpio;
1046 +extern struct device_attribute dev_attr_guid;
1047 +extern struct device_attribute dev_attr_gsnpsid;
1048 +extern struct device_attribute dev_attr_devspeed;
1049 +extern struct device_attribute dev_attr_enumspeed;
1050 +extern struct device_attribute dev_attr_hptxfsiz;
1051 +extern struct device_attribute dev_attr_hprt0;
1053 +void dwc_otg_attr_create (struct platform_device *pdev);
1054 +void dwc_otg_attr_remove (struct platform_device *pdev);
1058 +++ b/drivers/usb/dwc/otg_cil.c
1060 +/* ==========================================================================
1061 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
1062 + * $Revision: #147 $
1063 + * $Date: 2008/10/16 $
1064 + * $Change: 1117667 $
1066 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
1067 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
1068 + * otherwise expressly agreed to in writing between Synopsys and you.
1070 + * The Software IS NOT an item of Licensed Software or Licensed Product under
1071 + * any End User Software License Agreement or Agreement for Licensed Product
1072 + * with Synopsys or any supplement thereto. You are permitted to use and
1073 + * redistribute this Software in source and binary forms, with or without
1074 + * modification, provided that redistributions of source code must retain this
1075 + * notice. You may not view, use, disclose, copy or distribute this file or
1076 + * any information contained herein except pursuant to this license grant from
1077 + * Synopsys. If you do not agree with this notice, including the disclaimer
1078 + * below, then you are not authorized to use the Software.
1080 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1081 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1082 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1083 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1084 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1085 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1086 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1087 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1088 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1089 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1091 + * ========================================================================== */
1095 + * The Core Interface Layer provides basic services for accessing and
1096 + * managing the DWC_otg hardware. These services are used by both the
1097 + * Host Controller Driver and the Peripheral Controller Driver.
1099 + * The CIL manages the memory map for the core so that the HCD and PCD
1100 + * don't have to do this separately. It also handles basic tasks like
1101 + * reading/writing the registers and data FIFOs in the controller.
1102 + * Some of the data access functions provide encapsulation of several
1103 + * operations required to perform a task, such as writing multiple
1104 + * registers to start a transfer. Finally, the CIL performs basic
1105 + * services that are not specific to either the host or device modes
1106 + * of operation. These services include management of the OTG Host
1107 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
1108 + * Diagnostic API is also provided to allow testing of the controller
1111 + * The Core Interface Layer has the following requirements:
1112 + * - Provides basic controller operations.
1113 + * - Minimal use of OS services.
1114 + * - The OS services used will be abstracted by using inline functions
1118 +#include <asm/unaligned.h>
1119 +#include <linux/dma-mapping.h>
1121 +#include <linux/jiffies.h>
1124 +#include "otg_plat.h"
1125 +#include "otg_regs.h"
1126 +#include "otg_cil.h"
1127 +#include "otg_pcd.h"
1131 + * This function is called to initialize the DWC_otg CSR data
1132 + * structures. The register addresses in the device and host
1133 + * structures are initialized from the base address supplied by the
1134 + * caller. The calling function must make the OS calls to get the
1135 + * base address of the DWC_otg controller registers. The core_params
1136 + * argument holds the parameters that specify how the core should be
1139 + * @param[in] reg_base_addr Base address of DWC_otg core registers
1140 + * @param[in] core_params Pointer to the core configuration parameters
1143 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr,
1144 + dwc_otg_core_params_t *core_params)
1146 + dwc_otg_core_if_t *core_if = 0;
1147 + dwc_otg_dev_if_t *dev_if = 0;
1148 + dwc_otg_host_if_t *host_if = 0;
1149 + uint8_t *reg_base = (uint8_t *)reg_base_addr;
1152 + DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params);
1154 + core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL);
1156 + if (core_if == 0) {
1157 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
1161 + memset(core_if, 0, sizeof(dwc_otg_core_if_t));
1163 + core_if->core_params = core_params;
1164 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
1167 + * Allocate the Device Mode structures.
1169 + dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
1171 + if (dev_if == 0) {
1172 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
1177 + dev_if->dev_global_regs =
1178 + (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
1180 + for (i=0; i<MAX_EPS_CHANNELS; i++)
1182 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
1183 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
1184 + (i * DWC_EP_REG_OFFSET));
1186 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
1187 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
1188 + (i * DWC_EP_REG_OFFSET));
1189 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
1190 + i, &dev_if->in_ep_regs[i]->diepctl);
1191 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
1192 + i, &dev_if->out_ep_regs[i]->doepctl);
1195 + dev_if->speed = 0; // unknown
1197 + core_if->dev_if = dev_if;
1200 + * Allocate the Host Mode structures.
1202 + host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL);
1204 + if (host_if == 0) {
1205 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
1211 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
1212 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
1214 + host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
1216 + for (i=0; i<MAX_EPS_CHANNELS; i++)
1218 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
1219 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
1220 + (i * DWC_OTG_CHAN_REGS_OFFSET));
1221 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
1222 + i, &host_if->hc_regs[i]->hcchar);
1225 + host_if->num_host_channels = MAX_EPS_CHANNELS;
1226 + core_if->host_if = host_if;
1228 + for (i=0; i<MAX_EPS_CHANNELS; i++)
1230 + core_if->data_fifo[i] =
1231 + (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
1232 + (i * DWC_OTG_DATA_FIFO_SIZE));
1233 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
1234 + i, (unsigned)core_if->data_fifo[i]);
1237 + core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
1240 + * Store the contents of the hardware configuration registers here for
1241 + * easy access later.
1243 + core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
1244 + core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
1245 + core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
1246 + core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
1248 + DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
1249 + DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
1250 + DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
1251 + DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
1253 + core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
1254 + core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
1256 + DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
1257 + DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
1259 + DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
1260 + DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
1261 + DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
1262 + DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
1263 + DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
1264 + DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
1265 + DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
1267 + DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
1268 + DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
1271 + * Set the SRP sucess bit for FS-I2c
1273 + core_if->srp_success = 0;
1274 + core_if->srp_timer_started = 0;
1278 + * Create new workqueue and init works
1280 + core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
1281 + if(core_if->wq_otg == 0) {
1282 + DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
1288 + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
1289 + INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
1295 + * This function frees the structures allocated by dwc_otg_cil_init().
1297 + * @param[in] core_if The core interface pointer returned from
1298 + * dwc_otg_cil_init().
1301 +void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
1303 + /* Disable all interrupts */
1304 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
1305 + dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
1307 + if (core_if->wq_otg) {
1308 + destroy_workqueue(core_if->wq_otg);
1310 + if (core_if->dev_if) {
1311 + kfree(core_if->dev_if);
1313 + if (core_if->host_if) {
1314 + kfree(core_if->host_if);
1320 + * This function enables the controller's Global Interrupt in the AHB Config
1323 + * @param[in] core_if Programming view of DWC_otg controller.
1325 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
1327 + gahbcfg_data_t ahbcfg = { .d32 = 0};
1328 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1329 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
1333 + * This function disables the controller's Global Interrupt in the AHB Config
1336 + * @param[in] core_if Programming view of DWC_otg controller.
1338 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
1340 + gahbcfg_data_t ahbcfg = { .d32 = 0};
1341 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1342 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
1346 + * This function initializes the commmon interrupts, used in both
1347 + * device and host modes.
1349 + * @param[in] core_if Programming view of the DWC_otg controller
1352 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
1354 + dwc_otg_core_global_regs_t *global_regs =
1355 + core_if->core_global_regs;
1356 + gintmsk_data_t intr_mask = { .d32 = 0};
1358 + /* Clear any pending OTG Interrupts */
1359 + dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
1361 + /* Clear any pending interrupts */
1362 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1365 + * Enable the interrupts in the GINTMSK.
1367 + intr_mask.b.modemismatch = 1;
1368 + intr_mask.b.otgintr = 1;
1370 + if (!core_if->dma_enable) {
1371 + intr_mask.b.rxstsqlvl = 1;
1374 + intr_mask.b.conidstschng = 1;
1375 + intr_mask.b.wkupintr = 1;
1376 + intr_mask.b.disconnect = 1;
1377 + intr_mask.b.usbsuspend = 1;
1378 + intr_mask.b.sessreqintr = 1;
1379 + dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
1383 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1386 +static void init_fslspclksel(dwc_otg_core_if_t *core_if)
1391 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1392 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
1393 + (core_if->core_params->ulpi_fs_ls)) ||
1394 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1395 + /* Full speed PHY */
1396 + val = DWC_HCFG_48_MHZ;
1399 + /* High speed PHY running at full speed or high speed */
1400 + val = DWC_HCFG_30_60_MHZ;
1403 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1404 + hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
1405 + hcfg.b.fslspclksel = val;
1406 + dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1410 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
1411 + * and the enumeration speed of the device.
1413 +static void init_devspd(dwc_otg_core_if_t *core_if)
1418 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1419 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
1420 + (core_if->core_params->ulpi_fs_ls)) ||
1421 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1422 + /* Full speed PHY */
1425 + else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1426 + /* High speed PHY running at full speed */
1430 + /* High speed PHY running at high speed */
1434 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1436 + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
1437 + dcfg.b.devspd = val;
1438 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1442 + * This function calculates the number of IN EPS
1443 + * using GHWCFG1 and GHWCFG2 registers values
1445 + * @param core_if Programming view of the DWC_otg controller
1447 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
1449 + uint32_t num_in_eps = 0;
1450 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1451 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1452 + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1456 + for(i = 0; i < num_eps; ++i)
1458 + if(!(hwcfg1 & 0x1))
1464 + if(core_if->hwcfg4.b.ded_fifo_en) {
1465 + num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1468 + return num_in_eps;
1473 + * This function calculates the number of OUT EPS
1474 + * using GHWCFG1 and GHWCFG2 registers values
1476 + * @param core_if Programming view of the DWC_otg controller
1478 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
1480 + uint32_t num_out_eps = 0;
1481 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1482 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1485 + for(i = 0; i < num_eps; ++i)
1487 + if(!(hwcfg1 & 0x2))
1492 + return num_out_eps;
1495 + * This function initializes the DWC_otg controller registers and
1496 + * prepares the core for device mode or host mode operation.
1498 + * @param core_if Programming view of the DWC_otg controller
1501 +void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
1504 + dwc_otg_core_global_regs_t *global_regs =
1505 + core_if->core_global_regs;
1506 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1507 + gahbcfg_data_t ahbcfg = { .d32 = 0 };
1508 + gusbcfg_data_t usbcfg = { .d32 = 0 };
1509 + gi2cctl_data_t i2cctl = { .d32 = 0 };
1511 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1513 + /* Common Initialization */
1515 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1517 +// usbcfg.b.tx_end_delay = 1;
1518 + /* Program the ULPI External VBUS bit if needed */
1519 + usbcfg.b.ulpi_ext_vbus_drv =
1520 + (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1522 + /* Set external TS Dline pulsing */
1523 + usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0;
1524 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1527 + /* Reset the Controller */
1528 + dwc_otg_core_reset(core_if);
1530 + /* Initialize parameters from Hardware configuration registers. */
1531 + dev_if->num_in_eps = calc_num_in_eps(core_if);
1532 + dev_if->num_out_eps = calc_num_out_eps(core_if);
1535 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep);
1537 + for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
1539 + dev_if->perio_tx_fifo_size[i] =
1540 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1541 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1542 + i, dev_if->perio_tx_fifo_size[i]);
1545 + for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++)
1547 + dev_if->tx_fifo_size[i] =
1548 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1549 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1550 + i, dev_if->perio_tx_fifo_size[i]);
1553 + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1554 + core_if->rx_fifo_size =
1555 + dwc_read_reg32(&global_regs->grxfsiz);
1556 + core_if->nperio_tx_fifo_size =
1557 + dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
1559 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1560 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1561 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size);
1563 + /* This programming sequence needs to happen in FS mode before any other
1564 + * programming occurs */
1565 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1566 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1567 + /* If FS mode with FS PHY */
1569 + /* core_init() is now called on every switch so only call the
1570 + * following for the first time through. */
1571 + if (!core_if->phy_init_done) {
1572 + core_if->phy_init_done = 1;
1573 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1574 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1575 + usbcfg.b.physel = 1;
1576 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1578 + /* Reset after a PHY select */
1579 + dwc_otg_core_reset(core_if);
1582 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1583 + * do this on HNP Dev/Host mode switches (done in dev_init and
1585 + if (dwc_otg_is_host_mode(core_if)) {
1586 + init_fslspclksel(core_if);
1589 + init_devspd(core_if);
1592 + if (core_if->core_params->i2c_enable) {
1593 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1594 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
1595 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1596 + usbcfg.b.otgutmifssel = 1;
1597 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1599 + /* Program GI2CCTL.I2CEn */
1600 + i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
1601 + i2cctl.b.i2cdevaddr = 1;
1602 + i2cctl.b.i2cen = 0;
1603 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1604 + i2cctl.b.i2cen = 1;
1605 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1608 + } /* endif speed == DWC_SPEED_PARAM_FULL */
1611 + /* High speed PHY. */
1612 + if (!core_if->phy_init_done) {
1613 + core_if->phy_init_done = 1;
1614 + /* HS PHY parameters. These parameters are preserved
1615 + * during soft reset so only program the first time. Do
1616 + * a soft reset immediately after setting phyif. */
1617 + usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
1618 + if (usbcfg.b.ulpi_utmi_sel == 1) {
1619 + /* ULPI interface */
1620 + usbcfg.b.phyif = 0;
1621 + usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr;
1624 + /* UTMI+ interface */
1625 + if (core_if->core_params->phy_utmi_width == 16) {
1626 + usbcfg.b.phyif = 1;
1629 + usbcfg.b.phyif = 0;
1633 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1635 + /* Reset after setting the PHY parameters */
1636 + dwc_otg_core_reset(core_if);
1640 + if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1641 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
1642 + (core_if->core_params->ulpi_fs_ls)) {
1643 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1644 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1645 + usbcfg.b.ulpi_fsls = 1;
1646 + usbcfg.b.ulpi_clk_sus_m = 1;
1647 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1650 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1651 + usbcfg.b.ulpi_fsls = 0;
1652 + usbcfg.b.ulpi_clk_sus_m = 0;
1653 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1656 + /* Program the GAHBCFG Register.*/
1657 + switch (core_if->hwcfg2.b.architecture) {
1659 + case DWC_SLAVE_ONLY_ARCH:
1660 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1661 + ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1662 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1663 + core_if->dma_enable = 0;
1664 + core_if->dma_desc_enable = 0;
1667 + case DWC_EXT_DMA_ARCH:
1668 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1669 + ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size;
1670 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1671 + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
1674 + case DWC_INT_DMA_ARCH:
1675 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1676 + ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
1677 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1678 + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
1682 + ahbcfg.b.dmaenable = core_if->dma_enable;
1683 + dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
1685 + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1687 + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1688 + core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1689 + DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled"));
1690 + DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled"));
1693 + * Program the GUSBCFG register.
1695 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1697 + switch (core_if->hwcfg2.b.op_mode) {
1698 + case DWC_MODE_HNP_SRP_CAPABLE:
1699 + usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1700 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1701 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1702 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1705 + case DWC_MODE_SRP_ONLY_CAPABLE:
1706 + usbcfg.b.hnpcap = 0;
1707 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1708 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1711 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
1712 + usbcfg.b.hnpcap = 0;
1713 + usbcfg.b.srpcap = 0;
1716 + case DWC_MODE_SRP_CAPABLE_DEVICE:
1717 + usbcfg.b.hnpcap = 0;
1718 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1719 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1722 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1723 + usbcfg.b.hnpcap = 0;
1724 + usbcfg.b.srpcap = 0;
1727 + case DWC_MODE_SRP_CAPABLE_HOST:
1728 + usbcfg.b.hnpcap = 0;
1729 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1730 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1733 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
1734 + usbcfg.b.hnpcap = 0;
1735 + usbcfg.b.srpcap = 0;
1739 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1741 + /* Enable common interrupts */
1742 + dwc_otg_enable_common_interrupts(core_if);
1744 + /* Do device or host intialization based on mode during PCD
1745 + * and HCD initialization */
1746 + if (dwc_otg_is_host_mode(core_if)) {
1747 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
1748 + core_if->op_state = A_HOST;
1751 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
1752 + core_if->op_state = B_PERIPHERAL;
1753 +#ifdef DWC_DEVICE_ONLY
1754 + dwc_otg_core_dev_init(core_if);
1761 + * This function enables the Device mode interrupts.
1763 + * @param core_if Programming view of DWC_otg controller
1765 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
1767 + gintmsk_data_t intr_mask = { .d32 = 0};
1768 + dwc_otg_core_global_regs_t *global_regs =
1769 + core_if->core_global_regs;
1771 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1773 + /* Disable all interrupts. */
1774 + dwc_write_reg32(&global_regs->gintmsk, 0);
1776 + /* Clear any pending interrupts */
1777 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1779 + /* Enable the common interrupts */
1780 + dwc_otg_enable_common_interrupts(core_if);
1782 + /* Enable interrupts */
1783 + intr_mask.b.usbreset = 1;
1784 + intr_mask.b.enumdone = 1;
1786 + if(!core_if->multiproc_int_enable) {
1787 + intr_mask.b.inepintr = 1;
1788 + intr_mask.b.outepintr = 1;
1791 + intr_mask.b.erlysuspend = 1;
1793 + if(core_if->en_multiple_tx_fifo == 0) {
1794 + intr_mask.b.epmismatch = 1;
1799 + if(core_if->dma_enable) {
1800 + if(core_if->dma_desc_enable == 0) {
1801 + if(core_if->pti_enh_enable) {
1802 + dctl_data_t dctl = { .d32 = 0 };
1803 + dctl.b.ifrmnum = 1;
1804 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1806 + intr_mask.b.incomplisoin = 1;
1807 + intr_mask.b.incomplisoout = 1;
1811 + intr_mask.b.incomplisoin = 1;
1812 + intr_mask.b.incomplisoout = 1;
1814 +#endif // DWC_EN_ISOC
1816 +/** @todo NGS: Should this be a module parameter? */
1817 +#ifdef USE_PERIODIC_EP
1818 + intr_mask.b.isooutdrop = 1;
1819 + intr_mask.b.eopframe = 1;
1820 + intr_mask.b.incomplisoin = 1;
1821 + intr_mask.b.incomplisoout = 1;
1824 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1826 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1827 + dwc_read_reg32(&global_regs->gintmsk));
1831 + * This function initializes the DWC_otg controller registers for
1834 + * @param core_if Programming view of DWC_otg controller
1837 +void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
1840 + u_int32_t *default_value_array;
1842 + dwc_otg_core_global_regs_t *global_regs =
1843 + core_if->core_global_regs;
1844 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1845 + dwc_otg_core_params_t *params = core_if->core_params;
1846 + dcfg_data_t dcfg = { .d32 = 0};
1847 + grstctl_t resetctl = { .d32 = 0 };
1848 + uint32_t rx_fifo_size;
1849 + fifosize_data_t nptxfifosize;
1850 + fifosize_data_t txfifosize;
1851 + dthrctl_data_t dthrctl;
1853 + /* Restart the Phy Clock */
1854 + dwc_write_reg32(core_if->pcgcctl, 0);
1856 + /* Device configuration register */
1857 + init_devspd(core_if);
1858 + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
1859 + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1860 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1862 + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1864 + /* Configure data FIFO sizes */
1865 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1866 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size);
1867 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
1868 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
1871 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1872 + dwc_read_reg32(&global_regs->grxfsiz));
1874 + rx_fifo_size = params->dev_rx_fifo_size;
1875 + dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
1877 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1878 + dwc_read_reg32(&global_regs->grxfsiz));
1880 + /** Set Periodic Tx FIFO Mask all bits 0 */
1881 + core_if->p_tx_msk = 0;
1883 + /** Set Tx FIFO Mask all bits 0 */
1884 + core_if->tx_msk = 0;
1886 + /* Non-periodic Tx FIFO */
1887 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1888 + dwc_read_reg32(&global_regs->gnptxfsiz));
1890 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1891 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1893 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1895 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1896 + dwc_read_reg32(&global_regs->gnptxfsiz));
1898 + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1899 + if(core_if->en_multiple_tx_fifo == 0) {
1900 + //core_if->hwcfg4.b.ded_fifo_en==0
1902 + /**@todo NGS: Fix Periodic FIFO Sizing! */
1904 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1905 + * Indexes of the FIFO size module parameters in the
1906 + * dev_perio_tx_fifo_size array and the FIFO size registers in
1907 + * the dptxfsiz array run from 0 to 14.
1909 + /** @todo Finish debug of this */
1910 + size=core_if->hwcfg4.b.num_dev_perio_in_ep;
1911 + default_value_array=params->dev_perio_tx_fifo_size;
1915 + //core_if->hwcfg4.b.ded_fifo_en==1
1917 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
1918 + * Indexes of the FIFO size module parameters in the
1919 + * dev_tx_fifo_size array and the FIFO size registers in
1920 + * the dptxfsiz_dieptxf array run from 0 to 14.
1923 + size=core_if->hwcfg4.b.num_in_eps;
1924 + default_value_array=params->dev_tx_fifo_size;
1927 + for (i=0; i < size; i++)
1930 + txfifosize.b.depth = default_value_array[i];
1931 + DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
1932 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1933 + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
1935 + DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
1936 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1937 + txfifosize.b.startaddr += txfifosize.b.depth;
1940 + /* Flush the FIFOs */
1941 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
1942 + dwc_otg_flush_rx_fifo(core_if);
1944 + /* Flush the Learning Queue. */
1945 + resetctl.b.intknqflsh = 1;
1946 + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
1948 + /* Clear all pending Device Interrupts */
1950 + if(core_if->multiproc_int_enable) {
1953 + /** @todo - if the condition needed to be checked
1954 + * or in any case all pending interrutps should be cleared?
1956 + if(core_if->multiproc_int_enable) {
1957 + for(i = 0; i < core_if->dev_if->num_in_eps; ++i) {
1958 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0);
1961 + for(i = 0; i < core_if->dev_if->num_out_eps; ++i) {
1962 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0);
1965 + dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
1966 + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
1968 + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
1969 + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
1970 + dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
1971 + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
1974 + for (i=0; i <= dev_if->num_in_eps; i++)
1976 + depctl_data_t depctl;
1977 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
1978 + if (depctl.b.epena) {
1980 + depctl.b.epdis = 1;
1981 + depctl.b.snak = 1;
1987 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1990 + dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1991 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
1992 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1995 + for (i=0; i <= dev_if->num_out_eps; i++)
1997 + depctl_data_t depctl;
1998 + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
1999 + if (depctl.b.epena) {
2001 + depctl.b.epdis = 1;
2002 + depctl.b.snak = 1;
2008 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
2010 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
2011 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
2012 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
2015 + if(core_if->en_multiple_tx_fifo && core_if->dma_enable) {
2016 + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
2017 + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
2018 + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
2020 + dev_if->rx_thr_length = params->rx_thr_length;
2021 + dev_if->tx_thr_length = params->tx_thr_length;
2023 + dev_if->setup_desc_index = 0;
2026 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
2027 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
2028 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
2029 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
2030 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
2032 + dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32);
2034 + DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
2035 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len);
2039 + dwc_otg_enable_device_interrupts(core_if);
2042 + diepmsk_data_t msk = { .d32 = 0 };
2043 + msk.b.txfifoundrn = 1;
2044 + if(core_if->multiproc_int_enable) {
2045 + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32);
2047 + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32);
2052 + if(core_if->multiproc_int_enable) {
2053 + /* Set NAK on Babble */
2054 + dctl_data_t dctl = { .d32 = 0};
2055 + dctl.b.nakonbble = 1;
2056 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
2061 + * This function enables the Host mode interrupts.
2063 + * @param core_if Programming view of DWC_otg controller
2065 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
2067 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2068 + gintmsk_data_t intr_mask = { .d32 = 0 };
2070 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2072 + /* Disable all interrupts. */
2073 + dwc_write_reg32(&global_regs->gintmsk, 0);
2075 + /* Clear any pending interrupts. */
2076 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
2078 + /* Enable the common interrupts */
2079 + dwc_otg_enable_common_interrupts(core_if);
2082 + * Enable host mode interrupts without disturbing common
2085 + intr_mask.b.sofintr = 1;
2086 + intr_mask.b.portintr = 1;
2087 + intr_mask.b.hcintr = 1;
2089 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2093 + * This function disables the Host Mode interrupts.
2095 + * @param core_if Programming view of DWC_otg controller
2097 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
2099 + dwc_otg_core_global_regs_t *global_regs =
2100 + core_if->core_global_regs;
2101 + gintmsk_data_t intr_mask = { .d32 = 0 };
2103 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2106 + * Disable host mode interrupts without disturbing common
2109 + intr_mask.b.sofintr = 1;
2110 + intr_mask.b.portintr = 1;
2111 + intr_mask.b.hcintr = 1;
2112 + intr_mask.b.ptxfempty = 1;
2113 + intr_mask.b.nptxfempty = 1;
2115 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
2119 + * This function initializes the DWC_otg controller registers for
2122 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2123 + * request queues. Host channels are reset to ensure that they are ready for
2124 + * performing transfers.
2126 + * @param core_if Programming view of DWC_otg controller
2129 +void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
2131 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2132 + dwc_otg_host_if_t *host_if = core_if->host_if;
2133 + dwc_otg_core_params_t *params = core_if->core_params;
2134 + hprt0_data_t hprt0 = { .d32 = 0 };
2135 + fifosize_data_t nptxfifosize;
2136 + fifosize_data_t ptxfifosize;
2138 + hcchar_data_t hcchar;
2140 + dwc_otg_hc_regs_t *hc_regs;
2142 + gotgctl_data_t gotgctl = { .d32 = 0 };
2144 + DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if);
2146 + /* Restart the Phy Clock */
2147 + dwc_write_reg32(core_if->pcgcctl, 0);
2149 + /* Initialize Host Configuration Register */
2150 + init_fslspclksel(core_if);
2151 + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL)
2153 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
2154 + hcfg.b.fslssupp = 1;
2155 + dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
2158 + /* Configure data FIFO sizes */
2159 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2160 + DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size);
2161 + DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
2162 + DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
2163 + DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
2166 + DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2167 + dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
2168 + DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2170 + /* Non-periodic Tx FIFO */
2171 + DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2172 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
2173 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
2174 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2175 + DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2177 + /* Periodic Tx FIFO */
2178 + DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2179 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
2180 + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2181 + dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
2182 + DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2185 + /* Clear Host Set HNP Enable in the OTG Control Register */
2186 + gotgctl.b.hstsethnpen = 1;
2187 + dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
2189 + /* Make sure the FIFOs are flushed. */
2190 + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */);
2191 + dwc_otg_flush_rx_fifo(core_if);
2193 + /* Flush out any leftover queued requests. */
2194 + num_channels = core_if->core_params->host_channels;
2195 + for (i = 0; i < num_channels; i++)
2197 + hc_regs = core_if->host_if->hc_regs[i];
2198 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2199 + hcchar.b.chen = 0;
2200 + hcchar.b.chdis = 1;
2201 + hcchar.b.epdir = 0;
2202 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2205 + /* Halt all channels to put them into a known state. */
2206 + for (i = 0; i < num_channels; i++)
2209 + hc_regs = core_if->host_if->hc_regs[i];
2210 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2211 + hcchar.b.chen = 1;
2212 + hcchar.b.chdis = 1;
2213 + hcchar.b.epdir = 0;
2214 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2215 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2217 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2218 + if (++count > 1000)
2220 + DWC_ERROR("%s: Unable to clear halt on channel %d\n",
2225 + while (hcchar.b.chen);
2228 + /* Turn on the vbus power. */
2229 + DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state);
2230 + if (core_if->op_state == A_HOST) {
2231 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
2232 + DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2233 + if (hprt0.b.prtpwr == 0) {
2234 + hprt0.b.prtpwr = 1;
2235 + dwc_write_reg32(host_if->hprt0, hprt0.d32);
2239 + dwc_otg_enable_host_interrupts(core_if);
2243 + * Prepares a host channel for transferring packets to/from a specific
2244 + * endpoint. The HCCHARn register is set up with the characteristics specified
2245 + * in _hc. Host channel interrupts that may need to be serviced while this
2246 + * transfer is in progress are enabled.
2248 + * @param core_if Programming view of DWC_otg controller
2249 + * @param hc Information needed to initialize the host channel
2251 +void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2253 + uint32_t intr_enable;
2254 + hcintmsk_data_t hc_intr_mask;
2255 + gintmsk_data_t gintmsk = { .d32 = 0 };
2256 + hcchar_data_t hcchar;
2257 + hcsplt_data_t hcsplt;
2259 + uint8_t hc_num = hc->hc_num;
2260 + dwc_otg_host_if_t *host_if = core_if->host_if;
2261 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2263 + /* Clear old interrupt conditions for this host channel. */
2264 + hc_intr_mask.d32 = 0xFFFFFFFF;
2265 + hc_intr_mask.b.reserved = 0;
2266 + dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
2268 + /* Enable channel interrupts required for this transfer. */
2269 + hc_intr_mask.d32 = 0;
2270 + hc_intr_mask.b.chhltd = 1;
2271 + if (core_if->dma_enable) {
2272 + hc_intr_mask.b.ahberr = 1;
2273 + if (hc->error_state && !hc->do_split &&
2274 + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2275 + hc_intr_mask.b.ack = 1;
2276 + if (hc->ep_is_in) {
2277 + hc_intr_mask.b.datatglerr = 1;
2278 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2279 + hc_intr_mask.b.nak = 1;
2285 + switch (hc->ep_type) {
2286 + case DWC_OTG_EP_TYPE_CONTROL:
2287 + case DWC_OTG_EP_TYPE_BULK:
2288 + hc_intr_mask.b.xfercompl = 1;
2289 + hc_intr_mask.b.stall = 1;
2290 + hc_intr_mask.b.xacterr = 1;
2291 + hc_intr_mask.b.datatglerr = 1;
2292 + if (hc->ep_is_in) {
2293 + hc_intr_mask.b.bblerr = 1;
2296 + hc_intr_mask.b.nak = 1;
2297 + hc_intr_mask.b.nyet = 1;
2298 + if (hc->do_ping) {
2299 + hc_intr_mask.b.ack = 1;
2303 + if (hc->do_split) {
2304 + hc_intr_mask.b.nak = 1;
2305 + if (hc->complete_split) {
2306 + hc_intr_mask.b.nyet = 1;
2309 + hc_intr_mask.b.ack = 1;
2313 + if (hc->error_state) {
2314 + hc_intr_mask.b.ack = 1;
2317 + case DWC_OTG_EP_TYPE_INTR:
2318 + hc_intr_mask.b.xfercompl = 1;
2319 + hc_intr_mask.b.nak = 1;
2320 + hc_intr_mask.b.stall = 1;
2321 + hc_intr_mask.b.xacterr = 1;
2322 + hc_intr_mask.b.datatglerr = 1;
2323 + hc_intr_mask.b.frmovrun = 1;
2325 + if (hc->ep_is_in) {
2326 + hc_intr_mask.b.bblerr = 1;
2328 + if (hc->error_state) {
2329 + hc_intr_mask.b.ack = 1;
2331 + if (hc->do_split) {
2332 + if (hc->complete_split) {
2333 + hc_intr_mask.b.nyet = 1;
2336 + hc_intr_mask.b.ack = 1;
2340 + case DWC_OTG_EP_TYPE_ISOC:
2341 + hc_intr_mask.b.xfercompl = 1;
2342 + hc_intr_mask.b.frmovrun = 1;
2343 + hc_intr_mask.b.ack = 1;
2345 + if (hc->ep_is_in) {
2346 + hc_intr_mask.b.xacterr = 1;
2347 + hc_intr_mask.b.bblerr = 1;
2352 + dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2354 +// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
2355 +// hc->max_packet = 512;
2356 + /* Enable the top level host channel interrupt. */
2357 + intr_enable = (1 << hc_num);
2358 + dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2360 + /* Make sure host channel interrupts are enabled. */
2361 + gintmsk.b.hcintr = 1;
2362 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2365 + * Program the HCCHARn register with the endpoint characteristics for
2366 + * the current transfer.
2369 + hcchar.b.devaddr = hc->dev_addr;
2370 + hcchar.b.epnum = hc->ep_num;
2371 + hcchar.b.epdir = hc->ep_is_in;
2372 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2373 + hcchar.b.eptype = hc->ep_type;
2374 + hcchar.b.mps = hc->max_packet;
2376 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2378 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2379 + DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
2380 + DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
2381 + DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
2382 + DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
2383 + DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
2384 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2385 + DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
2388 + * Program the HCSPLIT register for SPLITs
2391 + if (hc->do_split) {
2392 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num,
2393 + hc->complete_split ? "CSPLIT" : "SSPLIT");
2394 + hcsplt.b.compsplt = hc->complete_split;
2395 + hcsplt.b.xactpos = hc->xact_pos;
2396 + hcsplt.b.hubaddr = hc->hub_addr;
2397 + hcsplt.b.prtaddr = hc->port_addr;
2398 + DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split);
2399 + DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos);
2400 + DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr);
2401 + DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr);
2402 + DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in);
2403 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2404 + DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len);
2406 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2411 + * Attempts to halt a host channel. This function should only be called in
2412 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2413 + * normal circumstances in DMA mode, the controller halts the channel when the
2414 + * transfer is complete or a condition occurs that requires application
2417 + * In slave mode, checks for a free request queue entry, then sets the Channel
2418 + * Enable and Channel Disable bits of the Host Channel Characteristics
2419 + * register of the specified channel to intiate the halt. If there is no free
2420 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
2421 + * register to flush requests for this channel. In the latter case, sets a
2422 + * flag to indicate that the host channel needs to be halted when a request
2423 + * queue slot is open.
2425 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2426 + * HCCHARn register. The controller ensures there is space in the request
2427 + * queue before submitting the halt request.
2429 + * Some time may elapse before the core flushes any posted requests for this
2430 + * host channel and halts. The Channel Halted interrupt handler completes the
2431 + * deactivation of the host channel.
2433 + * @param core_if Controller register interface.
2434 + * @param hc Host channel to halt.
2435 + * @param halt_status Reason for halting the channel.
2437 +void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
2439 + dwc_otg_halt_status_e halt_status)
2441 + gnptxsts_data_t nptxsts;
2442 + hptxsts_data_t hptxsts;
2443 + hcchar_data_t hcchar;
2444 + dwc_otg_hc_regs_t *hc_regs;
2445 + dwc_otg_core_global_regs_t *global_regs;
2446 + dwc_otg_host_global_regs_t *host_global_regs;
2448 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2449 + global_regs = core_if->core_global_regs;
2450 + host_global_regs = core_if->host_if->host_global_regs;
2452 + WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
2454 + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2455 + halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2457 + * Disable all channel interrupts except Ch Halted. The QTD
2458 + * and QH state associated with this transfer has been cleared
2459 + * (in the case of URB_DEQUEUE), so the channel needs to be
2460 + * shut down carefully to prevent crashes.
2462 + hcintmsk_data_t hcintmsk;
2464 + hcintmsk.b.chhltd = 1;
2465 + dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
2468 + * Make sure no other interrupts besides halt are currently
2469 + * pending. Handling another interrupt could cause a crash due
2470 + * to the QTD and QH state.
2472 + dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
2475 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2476 + * even if the channel was already halted for some other
2479 + hc->halt_status = halt_status;
2481 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2482 + if (hcchar.b.chen == 0) {
2484 + * The channel is either already halted or it hasn't
2485 + * started yet. In DMA mode, the transfer may halt if
2486 + * it finishes normally or a condition occurs that
2487 + * requires driver intervention. Don't want to halt
2488 + * the channel again. In either Slave or DMA mode,
2489 + * it's possible that the transfer has been assigned
2490 + * to a channel, but not started yet when an URB is
2491 + * dequeued. Don't want to halt a channel that hasn't
2498 + if (hc->halt_pending) {
2500 + * A halt has already been issued for this channel. This might
2501 + * happen when a transfer is aborted by a higher level in
2505 + DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2506 + __func__, hc->hc_num);
2508 +/* dwc_otg_dump_global_registers(core_if); */
2509 +/* dwc_otg_dump_host_registers(core_if); */
2514 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2515 + hcchar.b.chen = 1;
2516 + hcchar.b.chdis = 1;
2518 + if (!core_if->dma_enable) {
2519 + /* Check for space in the request queue to issue the halt. */
2520 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2521 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2522 + nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2523 + if (nptxsts.b.nptxqspcavail == 0) {
2524 + hcchar.b.chen = 0;
2528 + hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
2529 + if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) {
2530 + hcchar.b.chen = 0;
2535 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2537 + hc->halt_status = halt_status;
2539 + if (hcchar.b.chen) {
2540 + hc->halt_pending = 1;
2541 + hc->halt_on_queue = 0;
2544 + hc->halt_on_queue = 1;
2547 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2548 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
2549 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
2550 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
2551 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
2557 + * Clears the transfer state for a host channel. This function is normally
2558 + * called after a transfer is done and the host channel is being released.
2560 + * @param core_if Programming view of DWC_otg controller.
2561 + * @param hc Identifies the host channel to clean up.
2563 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2565 + dwc_otg_hc_regs_t *hc_regs;
2567 + hc->xfer_started = 0;
2570 + * Clear channel interrupt enables and any unhandled channel interrupt
2573 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2574 + dwc_write_reg32(&hc_regs->hcintmsk, 0);
2575 + dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
2578 + del_timer(&core_if->hc_xfer_timer[hc->hc_num]);
2580 + hcchar_data_t hcchar;
2581 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2582 + if (hcchar.b.chdis) {
2583 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2584 + __func__, hc->hc_num, hcchar.d32);
2591 + * Sets the channel property that indicates in which frame a periodic transfer
2592 + * should occur. This is always set to the _next_ frame. This function has no
2593 + * effect on non-periodic transfers.
2595 + * @param core_if Programming view of DWC_otg controller.
2596 + * @param hc Identifies the host channel to set up and its properties.
2597 + * @param hcchar Current value of the HCCHAR register for the specified host
2600 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
2602 + hcchar_data_t *hcchar)
2604 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2605 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2606 + hfnum_data_t hfnum;
2607 + hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
2609 + /* 1 if _next_ frame is odd, 0 if it's even */
2610 + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2612 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) {
2613 + switch (hfnum.b.frnum & 0x7) {
2615 + core_if->hfnum_7_samples++;
2616 + core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2619 + core_if->hfnum_0_samples++;
2620 + core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2623 + core_if->hfnum_other_samples++;
2624 + core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
2633 +static void hc_xfer_timeout(unsigned long ptr)
2635 + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr;
2636 + int hc_num = xfer_info->hc->hc_num;
2637 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2638 + DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
2643 + * This function does the setup for a data transfer for a host channel and
2644 + * starts the transfer. May be called in either Slave mode or DMA mode. In
2645 + * Slave mode, the caller must ensure that there is sufficient space in the
2646 + * request queue and Tx Data FIFO.
2648 + * For an OUT transfer in Slave mode, it loads a data packet into the
2649 + * appropriate FIFO. If necessary, additional data packets will be loaded in
2652 + * For an IN transfer in Slave mode, a data packet is requested. The data
2653 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2654 + * additional data packets are requested in the Host ISR.
2656 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2657 + * register along with a packet count of 1 and the channel is enabled. This
2658 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
2659 + * simply set to 0 since no data transfer occurs in this case.
2661 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2662 + * all the information required to perform the subsequent data transfer. In
2663 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2664 + * controller performs the entire PING protocol, then starts the data
2667 + * @param core_if Programming view of DWC_otg controller.
2668 + * @param hc Information needed to initialize the host channel. The xfer_len
2669 + * value may be reduced to accommodate the max widths of the XferSize and
2670 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2671 + * to reflect the final xfer_len value.
2673 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2675 + hcchar_data_t hcchar;
2676 + hctsiz_data_t hctsiz;
2677 + uint16_t num_packets;
2678 + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
2679 + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
2680 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2684 + if (hc->do_ping) {
2685 + if (!core_if->dma_enable) {
2686 + dwc_otg_hc_do_ping(core_if, hc);
2687 + hc->xfer_started = 1;
2691 + hctsiz.b.dopng = 1;
2695 + if (hc->do_split) {
2698 + if (hc->complete_split && !hc->ep_is_in) {
2699 + /* For CSPLIT OUT Transfer, set the size to 0 so the
2700 + * core doesn't expect any data written to the FIFO */
2703 + else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
2704 + hc->xfer_len = hc->max_packet;
2706 + else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
2707 + hc->xfer_len = 188;
2710 + hctsiz.b.xfersize = hc->xfer_len;
2714 + * Ensure that the transfer length and packet count will fit
2715 + * in the widths allocated for them in the HCTSIZn register.
2717 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2718 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2720 + * Make sure the transfer size is no larger than one
2721 + * (micro)frame's worth of data. (A check was done
2722 + * when the periodic transfer was accepted to ensure
2723 + * that a (micro)frame's worth of data can be
2724 + * programmed into a channel.)
2726 + uint32_t max_periodic_len = hc->multi_count * hc->max_packet;
2727 + if (hc->xfer_len > max_periodic_len) {
2728 + hc->xfer_len = max_periodic_len;
2733 + else if (hc->xfer_len > max_hc_xfer_size) {
2734 + /* Make sure that xfer_len is a multiple of max packet size. */
2735 + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
2738 + if (hc->xfer_len > 0) {
2739 + num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
2740 + if (num_packets > max_hc_pkt_count) {
2741 + num_packets = max_hc_pkt_count;
2742 + hc->xfer_len = num_packets * hc->max_packet;
2746 + /* Need 1 packet for transfer length of 0. */
2751 +//host testusb item 10, would do series of Control transfer
2752 +//with URB_SHORT_NOT_OK set in transfer_flags ,
2753 +//changing the xfer_len would cause the test fail
2754 + if (hc->ep_is_in) {
2755 + /* Always program an integral # of max packets for IN transfers. */
2756 + hc->xfer_len = num_packets * hc->max_packet;
2760 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2761 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2763 + * Make sure that the multi_count field matches the
2764 + * actual transfer length.
2766 + hc->multi_count = num_packets;
2769 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2770 + /* Set up the initial PID for the transfer. */
2771 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2772 + if (hc->ep_is_in) {
2773 + if (hc->multi_count == 1) {
2774 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2776 + else if (hc->multi_count == 2) {
2777 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2780 + hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2784 + if (hc->multi_count == 1) {
2785 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2788 + hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2793 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2797 + hctsiz.b.xfersize = hc->xfer_len;
2800 + hc->start_pkt_count = num_packets;
2801 + hctsiz.b.pktcnt = num_packets;
2802 + hctsiz.b.pid = hc->data_pid_start;
2803 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2805 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2806 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
2807 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
2808 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2810 + if (core_if->dma_enable) {
2811 + dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff);
2814 + /* Start the split */
2815 + if (hc->do_split) {
2816 + hcsplt_data_t hcsplt;
2817 + hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
2818 + hcsplt.b.spltena = 1;
2819 + dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
2822 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2823 + hcchar.b.multicnt = hc->multi_count;
2824 + hc_set_even_odd_frame(core_if, hc, &hcchar);
2826 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2827 + if (hcchar.b.chdis) {
2828 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2829 + __func__, hc->hc_num, hcchar.d32);
2833 + /* Set host channel enable after all other setup is complete. */
2834 + hcchar.b.chen = 1;
2835 + hcchar.b.chdis = 0;
2836 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2838 + hc->xfer_started = 1;
2841 + if (!core_if->dma_enable &&
2842 + !hc->ep_is_in && hc->xfer_len > 0) {
2843 + /* Load OUT packet into the appropriate Tx FIFO. */
2844 + dwc_otg_hc_write_packet(core_if, hc);
2848 + /* Start a timer for this transfer. */
2849 + core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout;
2850 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
2851 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
2852 + core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]);
2853 + core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10);
2854 + add_timer(&core_if->hc_xfer_timer[hc->hc_num]);
2859 + * This function continues a data transfer that was started by previous call
2860 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
2861 + * sufficient space in the request queue and Tx Data FIFO. This function
2862 + * should only be called in Slave mode. In DMA mode, the controller acts
2863 + * autonomously to complete transfers programmed to a host channel.
2865 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2866 + * if there is any data remaining to be queued. For an IN transfer, another
2867 + * data packet is always requested. For the SETUP phase of a control transfer,
2868 + * this function does nothing.
2870 + * @return 1 if a new request is queued, 0 if no more requests are required
2871 + * for this transfer.
2873 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2875 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2877 + if (hc->do_split) {
2878 + /* SPLITs always queue just once per channel */
2881 + else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2882 + /* SETUPs are queued only once since they can't be NAKed. */
2885 + else if (hc->ep_is_in) {
2887 + * Always queue another request for other IN transfers. If
2888 + * back-to-back INs are issued and NAKs are received for both,
2889 + * the driver may still be processing the first NAK when the
2890 + * second NAK is received. When the interrupt handler clears
2891 + * the NAK interrupt for the first NAK, the second NAK will
2892 + * not be seen. So we can't depend on the NAK interrupt
2893 + * handler to requeue a NAKed request. Instead, IN requests
2894 + * are issued each time this function is called. When the
2895 + * transfer completes, the extra requests for the channel will
2898 + hcchar_data_t hcchar;
2899 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2901 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2902 + hc_set_even_odd_frame(core_if, hc, &hcchar);
2903 + hcchar.b.chen = 1;
2904 + hcchar.b.chdis = 0;
2905 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
2906 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2911 + /* OUT transfers. */
2912 + if (hc->xfer_count < hc->xfer_len) {
2913 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2914 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2915 + hcchar_data_t hcchar;
2916 + dwc_otg_hc_regs_t *hc_regs;
2917 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2918 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2919 + hc_set_even_odd_frame(core_if, hc, &hcchar);
2922 + /* Load OUT packet into the appropriate Tx FIFO. */
2923 + dwc_otg_hc_write_packet(core_if, hc);
2934 + * Starts a PING transfer. This function should only be called in Slave mode.
2935 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
2937 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2939 + hcchar_data_t hcchar;
2940 + hctsiz_data_t hctsiz;
2941 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2943 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2946 + hctsiz.b.dopng = 1;
2947 + hctsiz.b.pktcnt = 1;
2948 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2950 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2951 + hcchar.b.chen = 1;
2952 + hcchar.b.chdis = 0;
2953 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2957 + * This function writes a packet into the Tx FIFO associated with the Host
2958 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
2959 + * Tx FIFO is written. For a channel associated with a periodic EP, the
2960 + * periodic Tx FIFO is written. This function should only be called in Slave
2963 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
2964 + * then number of bytes written to the Tx FIFO.
2966 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2969 + uint32_t remaining_count;
2970 + uint32_t byte_count;
2971 + uint32_t dword_count;
2973 + uint32_t *data_buff = (uint32_t *)(hc->xfer_buff);
2974 + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
2976 + remaining_count = hc->xfer_len - hc->xfer_count;
2977 + if (remaining_count > hc->max_packet) {
2978 + byte_count = hc->max_packet;
2981 + byte_count = remaining_count;
2984 + dword_count = (byte_count + 3) / 4;
2986 + if ((((unsigned long)data_buff) & 0x3) == 0) {
2987 + /* xfer_buff is DWORD aligned. */
2988 + for (i = 0; i < dword_count; i++, data_buff++)
2990 + dwc_write_reg32(data_fifo, *data_buff);
2994 + /* xfer_buff is not DWORD aligned. */
2995 + for (i = 0; i < dword_count; i++, data_buff++)
2997 + dwc_write_reg32(data_fifo, get_unaligned(data_buff));
3001 + hc->xfer_count += byte_count;
3002 + hc->xfer_buff += byte_count;
3006 + * Gets the current USB frame number. This is the frame number from the last
3009 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
3012 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
3014 + /* read current frame/microframe number from DSTS register */
3015 + return dsts.b.soffn;
3019 + * This function reads a setup packet from the Rx FIFO into the destination
3020 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3021 + * Interrupt routine when a SETUP packet has been received in Slave mode.
3023 + * @param core_if Programming view of DWC_otg controller.
3024 + * @param dest Destination buffer for packet data.
3026 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
3028 + /* Get the 8 bytes of a setup transaction data */
3030 + /* Pop 2 DWORDS off the receive data FIFO into memory */
3031 + dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
3032 + dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
3037 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
3038 + * IN for transmitting packets. It is normally called when the
3039 + * "Enumeration Done" interrupt occurs.
3041 + * @param core_if Programming view of DWC_otg controller.
3042 + * @param ep The EP0 data.
3044 +void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3046 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3048 + depctl_data_t diepctl;
3049 + depctl_data_t doepctl;
3050 + dctl_data_t dctl = { .d32 = 0 };
3052 + /* Read the Device Status and Endpoint 0 Control registers */
3053 + dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
3054 + diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
3055 + doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
3057 + /* Set the MPS of the IN EP based on the enumeration speed */
3058 + switch (dsts.b.enumspd) {
3059 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3060 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3061 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3062 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3064 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3065 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3069 + dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3071 + /* Enable OUT EP for receive */
3072 + doepctl.b.epena = 1;
3073 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3076 + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
3077 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
3078 + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
3079 + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
3081 + dctl.b.cgnpinnak = 1;
3083 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3084 + DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
3085 + dwc_read_reg32(&dev_if->dev_global_regs->dctl));
3089 + * This function activates an EP. The Device EP control register for
3090 + * the EP is configured as defined in the ep structure. Note: This
3091 + * function is not used for EP0.
3093 + * @param core_if Programming view of DWC_otg controller.
3094 + * @param ep The EP to activate.
3096 +void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3098 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3099 + depctl_data_t depctl;
3100 + volatile uint32_t *addr;
3101 + daint_data_t daintmsk = { .d32 = 0 };
3103 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3104 + (ep->is_in?"IN":"OUT"));
3106 + /* Read DEPCTLn register */
3107 + if (ep->is_in == 1) {
3108 + addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3109 + daintmsk.ep.in = 1<<ep->num;
3112 + addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3113 + daintmsk.ep.out = 1<<ep->num;
3116 + /* If the EP is already active don't change the EP Control
3118 + depctl.d32 = dwc_read_reg32(addr);
3119 + if (!depctl.b.usbactep) {
3120 + depctl.b.mps = ep->maxpacket;
3121 + depctl.b.eptype = ep->type;
3122 + depctl.b.txfnum = ep->tx_fifo_num;
3124 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3125 + depctl.b.setd0pid = 1; // ???
3128 + depctl.b.setd0pid = 1;
3130 + depctl.b.usbactep = 1;
3132 + dwc_write_reg32(addr, depctl.d32);
3133 + DWC_DEBUGPL(DBG_PCDV,"DEPCTL(%.8x)=%08x\n",(u32)addr, dwc_read_reg32(addr));
3136 + /* Enable the Interrupt for this EP */
3137 + if(core_if->multiproc_int_enable) {
3138 + if (ep->is_in == 1) {
3139 + diepmsk_data_t diepmsk = { .d32 = 0};
3140 + diepmsk.b.xfercompl = 1;
3141 + diepmsk.b.timeout = 1;
3142 + diepmsk.b.epdisabled = 1;
3143 + diepmsk.b.ahberr = 1;
3144 + diepmsk.b.intknepmis = 1;
3145 + diepmsk.b.txfifoundrn = 1; //?????
3148 + if(core_if->dma_desc_enable) {
3149 + diepmsk.b.bna = 1;
3152 + if(core_if->dma_enable) {
3153 + doepmsk.b.nak = 1;
3156 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32);
3159 + doepmsk_data_t doepmsk = { .d32 = 0};
3160 + doepmsk.b.xfercompl = 1;
3161 + doepmsk.b.ahberr = 1;
3162 + doepmsk.b.epdisabled = 1;
3165 + if(core_if->dma_desc_enable) {
3166 + doepmsk.b.bna = 1;
3169 + doepmsk.b.babble = 1;
3170 + doepmsk.b.nyet = 1;
3171 + doepmsk.b.nak = 1;
3173 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32);
3175 + dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
3178 + dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
3182 + DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
3183 + dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
3185 + ep->stall_clear_flag = 0;
3190 + * This function deactivates an EP. This is done by clearing the USB Active
3191 + * EP bit in the Device EP control register. Note: This function is not used
3192 + * for EP0. EP0 cannot be deactivated.
3194 + * @param core_if Programming view of DWC_otg controller.
3195 + * @param ep The EP to deactivate.
3197 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3199 + depctl_data_t depctl = { .d32 = 0 };
3200 + volatile uint32_t *addr;
3201 + daint_data_t daintmsk = { .d32 = 0};
3203 + /* Read DEPCTLn register */
3204 + if (ep->is_in == 1) {
3205 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3206 + daintmsk.ep.in = 1<<ep->num;
3209 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3210 + daintmsk.ep.out = 1<<ep->num;
3213 + //disabled ep only when ep is enabled
3214 + //or got halt in the loop in test in cv9
3215 + depctl.d32=dwc_read_reg32(addr);
3216 + if(depctl.b.epena){
3217 + if (ep->is_in == 1) {
3218 + diepint_data_t diepint;
3219 + dwc_otg_dev_in_ep_regs_t *in_reg=core_if->dev_if->in_ep_regs[ep->num];
3222 + depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3224 + dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3226 + //wait for diepint.b.inepnakeff
3227 + diepint.d32=dwc_read_reg32(&in_reg->diepint);
3228 + while(!diepint.b.inepnakeff){
3230 + diepint.d32=dwc_read_reg32(&in_reg->diepint);
3233 + diepint.b.inepnakeff=1;
3234 + dwc_write_reg32(&in_reg->diepint,diepint.d32);
3236 + //set ep disable and snak
3237 + depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3240 + dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3242 + //wait for diepint.b.epdisabled
3243 + diepint.d32=dwc_read_reg32(&in_reg->diepint);
3244 + while(!diepint.b.epdisabled){
3246 + diepint.d32=dwc_read_reg32(&in_reg->diepint);
3249 + diepint.b.epdisabled=1;
3250 + dwc_write_reg32(&in_reg->diepint,diepint.d32);
3252 + //clear ep enable and disable bit
3253 + depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3256 + dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3260 +//following DWC OTG DataBook v2.72a, 6.4.2.1.3 Disabling an OUT Endpoint,
3261 +//but this doesn't work, the old code do.
3263 + doepint_data_t doepint;
3264 + dwc_otg_dev_out_ep_regs_t *out_reg=core_if->dev_if->out_ep_regs[ep->num];
3266 + gintsts_data_t gintsts;
3268 + //set dctl global out nak
3269 + dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
3270 + dctl.b.sgoutnak=1;
3271 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl,dctl.d32);
3273 + //wait for gintsts.goutnakeff
3274 + gintsts.d32=dwc_read_reg32(&core_if->core_global_regs->gintsts);
3275 + while(!gintsts.b.goutnakeff){
3277 + gintsts.d32=dwc_read_reg32(&core_if->core_global_regs->gintsts);
3280 + gintsts.b.goutnakeff=1;
3281 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
3283 + //set ep disable and snak
3284 + depctl.d32=dwc_read_reg32(&out_reg->doepctl);
3287 + dwc_write_reg32(&out_reg->doepctl,depctl.d32);
3289 + //wait for diepint.b.epdisabled
3290 + doepint.d32=dwc_read_reg32(&out_reg->doepint);
3291 + while(!doepint.b.epdisabled){
3293 + doepint.d32=dwc_read_reg32(&out_reg->doepint);
3296 + doepint.b.epdisabled=1;
3297 + dwc_write_reg32(&out_reg->doepint,doepint.d32);
3299 + //clear ep enable and disable bit
3300 + depctl.d32=dwc_read_reg32(&out_reg->doepctl);
3303 + dwc_write_reg32(&out_reg->doepctl,depctl.d32);
3308 + depctl.b.usbactep = 0;
3310 + if (ep->is_in == 0) {
3311 + if(core_if->dma_enable||core_if->dma_desc_enable)
3312 + depctl.b.epdis = 1;
3315 + dwc_write_reg32(addr, depctl.d32);
3318 + /* Disable the Interrupt for this EP */
3319 + if(core_if->multiproc_int_enable) {
3320 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
3323 + if (ep->is_in == 1) {
3324 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0);
3326 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0);
3329 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
3333 + if (ep->is_in == 1) {
3334 + DWC_DEBUGPL(DBG_PCD, "DIEPCTL(%.8x)=%08x DIEPTSIZ=%08x, DIEPINT=%.8x, DIEPDMA=%.8x, DTXFSTS=%.8x\n",
3335 + (u32)&core_if->dev_if->in_ep_regs[ep->num]->diepctl,
3336 + dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl),
3337 + dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz),
3338 + dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepint),
3339 + dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepdma),
3340 + dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts));
3341 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3342 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3343 + dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3346 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL(%.8x)=%08x DOEPTSIZ=%08x, DOEPINT=%.8x, DOEPDMA=%.8x\n",
3347 + (u32)&core_if->dev_if->out_ep_regs[ep->num]->doepctl,
3348 + dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl),
3349 + dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz),
3350 + dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepint),
3351 + dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepdma));
3353 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3354 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3355 + dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3361 + * This function does the setup for a data transfer for an EP and
3362 + * starts the transfer. For an IN transfer, the packets will be
3363 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3364 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3366 + * @param core_if Programming view of DWC_otg controller.
3367 + * @param ep The EP to start the transfer on.
3369 +static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3371 + dwc_otg_dma_desc_t* dma_desc;
3373 + uint32_t xfer_est;
3376 + ep->desc_cnt = ( ep->total_len / ep->maxxfer) +
3377 + ((ep->total_len % ep->maxxfer) ? 1 : 0);
3381 + dma_desc = ep->desc_addr;
3382 + xfer_est = ep->total_len;
3384 + for( i = 0; i < ep->desc_cnt; ++i) {
3385 + /** DMA Descriptor Setup */
3386 + if(xfer_est > ep->maxxfer) {
3387 + dma_desc->status.b.bs = BS_HOST_BUSY;
3388 + dma_desc->status.b.l = 0;
3389 + dma_desc->status.b.ioc = 0;
3390 + dma_desc->status.b.sp = 0;
3391 + dma_desc->status.b.bytes = ep->maxxfer;
3392 + dma_desc->buf = ep->dma_addr + offset;
3393 + dma_desc->status.b.bs = BS_HOST_READY;
3395 + xfer_est -= ep->maxxfer;
3396 + offset += ep->maxxfer;
3398 + dma_desc->status.b.bs = BS_HOST_BUSY;
3399 + dma_desc->status.b.l = 1;
3400 + dma_desc->status.b.ioc = 1;
3402 + dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ?
3403 + 1 : ((ep->sent_zlp) ? 1 : 0);
3404 + dma_desc->status.b.bytes = xfer_est;
3406 + dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ;
3409 + dma_desc->buf = ep->dma_addr + offset;
3410 + dma_desc->status.b.bs = BS_HOST_READY;
3417 + * This function does the setup for a data transfer for an EP and
3418 + * starts the transfer. For an IN transfer, the packets will be
3419 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3420 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3422 + * @param core_if Programming view of DWC_otg controller.
3423 + * @param ep The EP to start the transfer on.
3426 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3428 + depctl_data_t depctl;
3429 + deptsiz_data_t deptsiz;
3430 + gintmsk_data_t intr_mask = { .d32 = 0};
3432 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3434 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3435 + "xfer_buff=%p start_xfer_buff=%p\n",
3436 + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
3437 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
3440 + if (ep->is_in == 1) {
3441 + dwc_otg_dev_in_ep_regs_t *in_regs =
3442 + core_if->dev_if->in_ep_regs[ep->num];
3444 + gnptxsts_data_t gtxstatus;
3447 + dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3449 + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
3451 + DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3456 + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3457 + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3459 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3460 + ep->maxxfer : (ep->total_len - ep->xfer_len);
3462 + /* Zero Length Packet? */
3463 + if ((ep->xfer_len - ep->xfer_count) == 0) {
3464 + deptsiz.b.xfersize = 0;
3465 + deptsiz.b.pktcnt = 1;
3468 + /* Program the transfer size and packet count
3469 + * as follows: xfersize = N * maxpacket +
3470 + * short_packet pktcnt = N + (short_packet
3473 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3474 + deptsiz.b.pktcnt =
3475 + (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) /
3480 + /* Write the DMA register */
3481 + if (core_if->dma_enable) {
3482 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3483 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3485 + DWC_DEBUGPL(DBG_PCDV, "ep%d dma_addr=%.8x\n", ep->num, ep->dma_addr);
3487 + if (core_if->dma_desc_enable == 0) {
3488 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3490 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3491 + dwc_write_reg32 (&(in_regs->diepdma),
3492 + (uint32_t)ep->dma_addr);
3495 + init_dma_desc_chain(core_if, ep);
3496 + /** DIEPDMAn Register write */
3498 + VERIFY_PCD_DMA_ADDR(ep->dma_desc_addr);
3499 + dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr);
3504 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3505 + if(ep->type != DWC_OTG_EP_TYPE_ISOC) {
3507 + * Enable the Non-Periodic Tx FIFO empty interrupt,
3508 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3509 + * the data will be written into the fifo by the ISR.
3511 + if(core_if->en_multiple_tx_fifo == 0) {
3512 + intr_mask.b.nptxfempty = 1;
3513 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3514 + intr_mask.d32, intr_mask.d32);
3517 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3518 + if(ep->xfer_len > 0) {
3519 + uint32_t fifoemptymsk = 0;
3520 + fifoemptymsk = 1 << ep->num;
3521 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3529 + /* EP enable, IN data in FIFO */
3530 + depctl.b.cnak = 1;
3531 + depctl.b.epena = 1;
3532 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3534 + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
3535 + depctl.b.nextep = ep->num;
3536 + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3538 + DWC_DEBUGPL(DBG_PCD, "DIEPCTL(%.8x)=%08x DIEPTSIZ=%08x, DIEPINT=%.8x, DIEPDMA=%.8x, DTXFSTS=%.8x\n",
3539 + (u32)&in_regs->diepctl,
3540 + dwc_read_reg32(&in_regs->diepctl),
3541 + dwc_read_reg32(&in_regs->dieptsiz),
3542 + dwc_read_reg32(&in_regs->diepint),
3543 + dwc_read_reg32(&in_regs->diepdma),
3544 + dwc_read_reg32(&in_regs->dtxfsts));
3545 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3546 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3547 + dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3551 + /* OUT endpoint */
3552 + dwc_otg_dev_out_ep_regs_t *out_regs =
3553 + core_if->dev_if->out_ep_regs[ep->num];
3555 + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3556 + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3558 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3559 + ep->maxxfer : (ep->total_len - ep->xfer_len);
3561 + /* Program the transfer size and packet count as follows:
3564 + * xfersize = N * maxpacket
3566 + if ((ep->xfer_len - ep->xfer_count) == 0) {
3567 + /* Zero Length Packet */
3568 + deptsiz.b.xfersize = ep->maxpacket;
3569 + deptsiz.b.pktcnt = 1;
3572 + deptsiz.b.pktcnt =
3573 + (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) /
3575 + ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
3576 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3579 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3581 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
3583 + if (core_if->dma_enable) {
3584 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3585 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3587 + DWC_DEBUGPL(DBG_PCDV, "ep%d dma_addr=%.8x\n",
3590 + if (!core_if->dma_desc_enable) {
3591 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3593 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3594 + dwc_write_reg32 (&(out_regs->doepdma),
3595 + (uint32_t)ep->dma_addr);
3598 + init_dma_desc_chain(core_if, ep);
3600 + /** DOEPDMAn Register write */
3602 + VERIFY_PCD_DMA_ADDR(ep->dma_desc_addr);
3603 + dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr);
3607 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3611 + depctl.b.cnak = 1;
3612 + depctl.b.epena = 1;
3614 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3616 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL(%.8x)=%08x DOEPTSIZ=%08x, DOEPINT=%.8x, DOEPDMA=%.8x\n",
3617 + (u32)&out_regs->doepctl,
3618 + dwc_read_reg32(&out_regs->doepctl),
3619 + dwc_read_reg32(&out_regs->doeptsiz),
3620 + dwc_read_reg32(&out_regs->doepint),
3621 + dwc_read_reg32(&out_regs->doepdma));
3623 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3624 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3625 + dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3630 + * This function setup a zero length transfer in Buffer DMA and
3631 + * Slave modes for usb requests with zero field set
3633 + * @param core_if Programming view of DWC_otg controller.
3634 + * @param ep The EP to start the transfer on.
3637 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3640 + depctl_data_t depctl;
3641 + deptsiz_data_t deptsiz;
3642 + gintmsk_data_t intr_mask = { .d32 = 0};
3644 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3647 + if (ep->is_in == 1) {
3648 + dwc_otg_dev_in_ep_regs_t *in_regs =
3649 + core_if->dev_if->in_ep_regs[ep->num];
3651 + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3652 + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3654 + deptsiz.b.xfersize = 0;
3655 + deptsiz.b.pktcnt = 1;
3658 + /* Write the DMA register */
3659 + if (core_if->dma_enable) {
3660 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3661 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3663 + if (core_if->dma_desc_enable == 0) {
3664 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3666 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3667 + dwc_write_reg32 (&(in_regs->diepdma),
3668 + (uint32_t)ep->dma_addr);
3672 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3674 + * Enable the Non-Periodic Tx FIFO empty interrupt,
3675 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3676 + * the data will be written into the fifo by the ISR.
3678 + if(core_if->en_multiple_tx_fifo == 0) {
3679 + intr_mask.b.nptxfempty = 1;
3680 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3681 + intr_mask.d32, intr_mask.d32);
3684 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3685 + if(ep->xfer_len > 0) {
3686 + uint32_t fifoemptymsk = 0;
3687 + fifoemptymsk = 1 << ep->num;
3688 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3694 + /* EP enable, IN data in FIFO */
3695 + depctl.b.cnak = 1;
3696 + depctl.b.epena = 1;
3697 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3699 + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
3700 + depctl.b.nextep = ep->num;
3701 + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3705 + /* OUT endpoint */
3706 + dwc_otg_dev_out_ep_regs_t *out_regs =
3707 + core_if->dev_if->out_ep_regs[ep->num];
3709 + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3710 + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3712 + /* Zero Length Packet */
3713 + deptsiz.b.xfersize = ep->maxpacket;
3714 + deptsiz.b.pktcnt = 1;
3716 + if (core_if->dma_enable) {
3717 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3718 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3720 + if (!core_if->dma_desc_enable) {
3721 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3724 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3725 + dwc_write_reg32 (&(out_regs->doepdma),
3726 + (uint32_t)ep->dma_addr);
3730 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3734 + depctl.b.cnak = 1;
3735 + depctl.b.epena = 1;
3737 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3743 + * This function does the setup for a data transfer for EP0 and starts
3744 + * the transfer. For an IN transfer, the packets will be loaded into
3745 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
3746 + * unloaded from the Rx FIFO in the ISR.
3748 + * @param core_if Programming view of DWC_otg controller.
3749 + * @param ep The EP0 data.
3751 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3753 + depctl_data_t depctl;
3754 + deptsiz0_data_t deptsiz;
3755 + gintmsk_data_t intr_mask = { .d32 = 0};
3756 + dwc_otg_dma_desc_t* dma_desc;
3758 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3759 + "xfer_buff=%p start_xfer_buff=%p, dma_addr=%.8x\n",
3760 + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
3761 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,ep->dma_addr);
3763 + ep->total_len = ep->xfer_len;
3766 + if (ep->is_in == 1) {
3767 + dwc_otg_dev_in_ep_regs_t *in_regs =
3768 + core_if->dev_if->in_ep_regs[0];
3770 + gnptxsts_data_t gtxstatus;
3773 + dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3775 + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
3777 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3778 + DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
3779 + dwc_read_reg32(&in_regs->diepctl));
3780 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
3782 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
3783 + DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n",
3790 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3791 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3793 + /* Zero Length Packet? */
3794 + if (ep->xfer_len == 0) {
3795 + deptsiz.b.xfersize = 0;
3796 + deptsiz.b.pktcnt = 1;
3799 + /* Program the transfer size and packet count
3800 + * as follows: xfersize = N * maxpacket +
3801 + * short_packet pktcnt = N + (short_packet
3804 + if (ep->xfer_len > ep->maxpacket) {
3805 + ep->xfer_len = ep->maxpacket;
3806 + deptsiz.b.xfersize = ep->maxpacket;
3809 + deptsiz.b.xfersize = ep->xfer_len;
3811 + deptsiz.b.pktcnt = 1;
3814 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3816 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
3817 + /* Write the DMA register */
3818 + if (core_if->dma_enable) {
3819 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3820 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3822 + if(core_if->dma_desc_enable == 0) {
3823 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3825 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3826 + dwc_write_reg32 (&(in_regs->diepdma),
3827 + (uint32_t)ep->dma_addr);
3830 + dma_desc = core_if->dev_if->in_desc_addr;
3832 + /** DMA Descriptor Setup */
3833 + dma_desc->status.b.bs = BS_HOST_BUSY;
3834 + dma_desc->status.b.l = 1;
3835 + dma_desc->status.b.ioc = 1;
3836 + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
3837 + dma_desc->status.b.bytes = ep->xfer_len;
3838 + dma_desc->buf = ep->dma_addr;
3839 + dma_desc->status.b.bs = BS_HOST_READY;
3841 + /** DIEPDMA0 Register write */
3843 + VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_in_desc_addr);
3844 + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
3848 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3851 + /* EP enable, IN data in FIFO */
3852 + depctl.b.cnak = 1;
3853 + depctl.b.epena = 1;
3854 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3857 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
3858 + * data will be written into the fifo by the ISR.
3860 + if (!core_if->dma_enable) {
3861 + if(core_if->en_multiple_tx_fifo == 0) {
3862 + intr_mask.b.nptxfempty = 1;
3863 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3864 + intr_mask.d32, intr_mask.d32);
3867 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3868 + if(ep->xfer_len > 0) {
3869 + uint32_t fifoemptymsk = 0;
3870 + fifoemptymsk |= 1 << ep->num;
3871 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3878 + /* OUT endpoint */
3879 + dwc_otg_dev_out_ep_regs_t *out_regs =
3880 + core_if->dev_if->out_ep_regs[0];
3882 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3883 + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
3885 + /* Program the transfer size and packet count as follows:
3886 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
3888 + /* Zero Length Packet */
3889 + deptsiz.b.xfersize = ep->maxpacket;
3890 + deptsiz.b.pktcnt = 1;
3892 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
3894 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
3896 + if (core_if->dma_enable) {
3897 + if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3898 + ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3900 + if(!core_if->dma_desc_enable) {
3901 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3904 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3905 + dwc_write_reg32 (&(out_regs->doepdma),
3906 + (uint32_t)ep->dma_addr);
3909 + dma_desc = core_if->dev_if->out_desc_addr;
3911 + /** DMA Descriptor Setup */
3912 + dma_desc->status.b.bs = BS_HOST_BUSY;
3913 + dma_desc->status.b.l = 1;
3914 + dma_desc->status.b.ioc = 1;
3915 + dma_desc->status.b.bytes = ep->maxpacket;
3916 + dma_desc->buf = ep->dma_addr;
3917 + dma_desc->status.b.bs = BS_HOST_READY;
3919 + /** DOEPDMA0 Register write */
3920 + VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_out_desc_addr);
3921 + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
3925 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3929 + depctl.b.cnak = 1;
3930 + depctl.b.epena = 1;
3931 + dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
3936 + * This function continues control IN transfers started by
3937 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
3938 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
3939 + * bit for the packet count.
3941 + * @param core_if Programming view of DWC_otg controller.
3942 + * @param ep The EP0 data.
3944 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3946 + depctl_data_t depctl;
3947 + deptsiz0_data_t deptsiz;
3948 + gintmsk_data_t intr_mask = { .d32 = 0};
3949 + dwc_otg_dma_desc_t* dma_desc;
3951 + if (ep->is_in == 1) {
3952 + dwc_otg_dev_in_ep_regs_t *in_regs =
3953 + core_if->dev_if->in_ep_regs[0];
3954 + gnptxsts_data_t tx_status = { .d32 = 0 };
3956 + tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3957 + /** @todo Should there be check for room in the Tx
3958 + * Status Queue. If not remove the code above this comment. */
3960 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3961 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3963 + /* Program the transfer size and packet count
3964 + * as follows: xfersize = N * maxpacket +
3965 + * short_packet pktcnt = N + (short_packet
3970 + if(core_if->dma_desc_enable == 0) {
3971 + deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
3972 + (ep->total_len - ep->xfer_count);
3973 + deptsiz.b.pktcnt = 1;
3974 + if(core_if->dma_enable == 0) {
3975 + ep->xfer_len += deptsiz.b.xfersize;
3977 + ep->xfer_len = deptsiz.b.xfersize;
3979 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3982 + ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
3983 + (ep->total_len - ep->xfer_count);
3985 + dma_desc = core_if->dev_if->in_desc_addr;
3987 + /** DMA Descriptor Setup */
3988 + dma_desc->status.b.bs = BS_HOST_BUSY;
3989 + dma_desc->status.b.l = 1;
3990 + dma_desc->status.b.ioc = 1;
3991 + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
3992 + dma_desc->status.b.bytes = ep->xfer_len;
3993 + dma_desc->buf = ep->dma_addr;
3994 + dma_desc->status.b.bs = BS_HOST_READY;
3997 + /** DIEPDMA0 Register write */
3998 + VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_in_desc_addr);
3999 + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
4003 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4005 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
4007 + /* Write the DMA register */
4008 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4009 + if(core_if->dma_desc_enable == 0){
4011 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
4012 + dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr);
4016 + /* EP enable, IN data in FIFO */
4017 + depctl.b.cnak = 1;
4018 + depctl.b.epena = 1;
4019 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
4022 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
4023 + * data will be written into the fifo by the ISR.
4025 + if (!core_if->dma_enable) {
4026 + if(core_if->en_multiple_tx_fifo == 0) {
4027 + /* First clear it from GINTSTS */
4028 + intr_mask.b.nptxfempty = 1;
4029 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
4030 + intr_mask.d32, intr_mask.d32);
4034 + /* Enable the Tx FIFO Empty Interrupt for this EP */
4035 + if(ep->xfer_len > 0) {
4036 + uint32_t fifoemptymsk = 0;
4037 + fifoemptymsk |= 1 << ep->num;
4038 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4045 + dwc_otg_dev_out_ep_regs_t *out_regs =
4046 + core_if->dev_if->out_ep_regs[0];
4049 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
4050 + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
4052 + /* Program the transfer size and packet count
4053 + * as follows: xfersize = N * maxpacket +
4054 + * short_packet pktcnt = N + (short_packet
4057 + deptsiz.b.xfersize = ep->maxpacket;
4058 + deptsiz.b.pktcnt = 1;
4061 + if(core_if->dma_desc_enable == 0) {
4062 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
4065 + dma_desc = core_if->dev_if->out_desc_addr;
4067 + /** DMA Descriptor Setup */
4068 + dma_desc->status.b.bs = BS_HOST_BUSY;
4069 + dma_desc->status.b.l = 1;
4070 + dma_desc->status.b.ioc = 1;
4071 + dma_desc->status.b.bytes = ep->maxpacket;
4072 + dma_desc->buf = ep->dma_addr;
4073 + dma_desc->status.b.bs = BS_HOST_READY;
4075 + /** DOEPDMA0 Register write */
4076 + VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_out_desc_addr);
4077 + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
4081 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4083 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
4085 + /* Write the DMA register */
4086 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4087 + if(core_if->dma_desc_enable == 0){
4089 + VERIFY_PCD_DMA_ADDR(ep->dma_addr);
4090 + dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr);
4094 + /* EP enable, IN data in FIFO */
4095 + depctl.b.cnak = 1;
4096 + depctl.b.epena = 1;
4097 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
4103 +void dump_msg(const u8 *buf, unsigned int length)
4105 + unsigned int start, num, i;
4106 + char line[52], *p;
4108 + if (length >= 512)
4111 + while (length > 0) {
4112 + num = min(length, 16u);
4114 + for (i = 0; i < num; ++i)
4118 + sprintf(p, " %02x", buf[i]);
4122 + DWC_PRINT("%6x: %s\n", start, line);
4129 +static inline void dump_msg(const u8 *buf, unsigned int length)
4135 + * This function writes a packet into the Tx FIFO associated with the
4136 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
4137 + * periodic EPs the periodic Tx FIFO associated with the EP is written
4138 + * with all packets for the next micro-frame.
4140 + * @param core_if Programming view of DWC_otg controller.
4141 + * @param ep The EP to write packet for.
4142 + * @param dma Indicates if DMA is being used.
4144 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
4147 + * The buffer is padded to DWORD on a per packet basis in
4148 + * slave/dma mode if the MPS is not DWORD aligned. The last
4149 + * packet, if short, is also padded to a multiple of DWORD.
4151 + * ep->xfer_buff always starts DWORD aligned in memory and is a
4152 + * multiple of DWORD in length
4154 + * ep->xfer_len can be any number of bytes
4156 + * ep->xfer_count is a multiple of ep->maxpacket until the last
4159 + * FIFO access is DWORD */
4162 + uint32_t byte_count;
4163 + uint32_t dword_count;
4165 + uint32_t *data_buff = (uint32_t *)ep->xfer_buff;
4167 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep);
4168 + if (ep->xfer_count >= ep->xfer_len) {
4169 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4173 + /* Find the byte length of the packet either short packet or MPS */
4174 + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
4175 + byte_count = ep->xfer_len - ep->xfer_count;
4178 + byte_count = ep->maxpacket;
4181 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4182 + * is not a multiple of DWORD */
4183 + dword_count = (byte_count + 3) / 4;
4186 + dump_msg(ep->xfer_buff, byte_count);
4189 + /**@todo NGS Where are the Periodic Tx FIFO addresses
4190 + * intialized? What should this be? */
4192 + fifo = core_if->data_fifo[ep->num];
4195 + DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count);
4198 + for (i=0; i<dword_count; i++, data_buff++) {
4199 + dwc_write_reg32(fifo, *data_buff);
4203 + ep->xfer_count += byte_count;
4204 + ep->xfer_buff += byte_count;
4205 + ep->dma_addr += byte_count;
4209 + * Set the EP STALL.
4211 + * @param core_if Programming view of DWC_otg controller.
4212 + * @param ep The EP to set the stall on.
4214 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4216 + depctl_data_t depctl;
4217 + volatile uint32_t *depctl_addr;
4219 + DWC_DEBUGPL(DBG_PCDV, "%s ep%d-%s1\n", __func__, ep->num,
4220 + (ep->is_in?"IN":"OUT"));
4222 + DWC_PRINT("%s ep%d-%s\n", __func__, ep->num,
4223 + (ep->is_in?"in":"out"));
4225 + if (ep->is_in == 1) {
4226 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4227 + depctl.d32 = dwc_read_reg32(depctl_addr);
4229 + /* set the disable and stall bits */
4231 +//epdis is set here but not cleared at latter dwc_otg_ep_clear_stall,
4232 +//which cause the testusb item 13 failed(Host:pc, device: otg device)
4233 + if (depctl.b.epena) {
4234 + depctl.b.epdis = 1;
4237 + depctl.b.stall = 1;
4238 + dwc_write_reg32(depctl_addr, depctl.d32);
4241 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4242 + depctl.d32 = dwc_read_reg32(depctl_addr);
4244 + /* set the stall bit */
4245 + depctl.b.stall = 1;
4246 + dwc_write_reg32(depctl_addr, depctl.d32);
4249 + DWC_DEBUGPL(DBG_PCDV,"%s: DEPCTL(%.8x)=%0x\n",__func__,(u32)depctl_addr,dwc_read_reg32(depctl_addr));
4255 + * Clear the EP STALL.
4257 + * @param core_if Programming view of DWC_otg controller.
4258 + * @param ep The EP to clear stall from.
4260 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4262 + depctl_data_t depctl;
4263 + volatile uint32_t *depctl_addr;
4265 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4266 + (ep->is_in?"IN":"OUT"));
4268 + if (ep->is_in == 1) {
4269 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4272 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4275 + depctl.d32 = dwc_read_reg32(depctl_addr);
4277 + /* clear the stall bits */
4278 + depctl.b.stall = 0;
4281 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
4282 + * of whether an endpoint has the Halt feature set, a
4283 + * ClearFeature(ENDPOINT_HALT) request always results in the
4284 + * data toggle being reinitialized to DATA0.
4286 + if (ep->type == DWC_OTG_EP_TYPE_INTR ||
4287 + ep->type == DWC_OTG_EP_TYPE_BULK) {
4288 + depctl.b.setd0pid = 1; /* DATA0 */
4291 + dwc_write_reg32(depctl_addr, depctl.d32);
4292 + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
4297 + * This function reads a packet from the Rx FIFO into the destination
4298 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
4300 + * @param core_if Programming view of DWC_otg controller.
4301 + * @param dest Destination buffer for the packet.
4302 + * @param bytes Number of bytes to copy to the destination.
4304 +void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
4309 + int word_count = (bytes + 3) / 4;
4311 + volatile uint32_t *fifo = core_if->data_fifo[0];
4312 + uint32_t *data_buff = (uint32_t *)dest;
4315 + * @todo Account for the case where _dest is not dword aligned. This
4316 + * requires reading data from the FIFO into a uint32_t temp buffer,
4317 + * then moving it into the data buffer.
4320 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
4321 + core_if, dest, bytes);
4323 + for (i=0; i<word_count; i++, data_buff++)
4325 + *data_buff = dwc_read_reg32(fifo);
4334 + * This functions reads the device registers and prints them
4336 + * @param core_if Programming view of DWC_otg controller.
4338 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
4341 + volatile uint32_t *addr;
4343 + DWC_PRINT("Device Global Registers\n");
4344 + addr=&core_if->dev_if->dev_global_regs->dcfg;
4345 + DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4346 + addr=&core_if->dev_if->dev_global_regs->dctl;
4347 + DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4348 + addr=&core_if->dev_if->dev_global_regs->dsts;
4349 + DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4350 + addr=&core_if->dev_if->dev_global_regs->diepmsk;
4351 + DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4352 + addr=&core_if->dev_if->dev_global_regs->doepmsk;
4353 + DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4354 + addr=&core_if->dev_if->dev_global_regs->daint;
4355 + DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4356 + addr=&core_if->dev_if->dev_global_regs->daintmsk;
4357 + DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4358 + addr=&core_if->dev_if->dev_global_regs->dtknqr1;
4359 + DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4360 + if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
4361 + addr=&core_if->dev_if->dev_global_regs->dtknqr2;
4362 + DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
4363 + (uint32_t)addr,dwc_read_reg32(addr));
4366 + addr=&core_if->dev_if->dev_global_regs->dvbusdis;
4367 + DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4369 + addr=&core_if->dev_if->dev_global_regs->dvbuspulse;
4370 + DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
4371 + (uint32_t)addr,dwc_read_reg32(addr));
4373 + if (core_if->hwcfg2.b.dev_token_q_depth > 14) {
4374 + addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
4375 + DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n",
4376 + (uint32_t)addr, dwc_read_reg32(addr));
4379 + if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
4380 + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4381 + DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n",
4382 + (uint32_t)addr, dwc_read_reg32(addr));
4385 + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4386 + DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr));
4388 + addr=&core_if->dev_if->dev_global_regs->deachint;
4389 + DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4390 + addr=&core_if->dev_if->dev_global_regs->deachintmsk;
4391 + DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4393 + for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
4394 + addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i];
4395 + DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
4399 + for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
4400 + addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i];
4401 + DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
4404 + for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
4405 + DWC_PRINT("Device IN EP %d Registers\n", i);
4406 + addr=&core_if->dev_if->in_ep_regs[i]->diepctl;
4407 + DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4408 + addr=&core_if->dev_if->in_ep_regs[i]->diepint;
4409 + DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4410 + addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz;
4411 + DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4412 + addr=&core_if->dev_if->in_ep_regs[i]->diepdma;
4413 + DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4414 + addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts;
4415 + DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4416 + //reading depdmab in non desc dma mode would halt the ahb bus...
4417 + if(core_if->dma_desc_enable){
4418 + addr=&core_if->dev_if->in_ep_regs[i]->diepdmab;
4419 + DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4424 + for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
4425 + DWC_PRINT("Device OUT EP %d Registers\n", i);
4426 + addr=&core_if->dev_if->out_ep_regs[i]->doepctl;
4427 + DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4428 + addr=&core_if->dev_if->out_ep_regs[i]->doepfn;
4429 + DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4430 + addr=&core_if->dev_if->out_ep_regs[i]->doepint;
4431 + DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4432 + addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz;
4433 + DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4434 + addr=&core_if->dev_if->out_ep_regs[i]->doepdma;
4435 + DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4437 + //reading depdmab in non desc dma mode would halt the ahb bus...
4438 + if(core_if->dma_desc_enable){
4439 + addr=&core_if->dev_if->out_ep_regs[i]->doepdmab;
4440 + DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4451 + * This functions reads the SPRAM and prints its content
4453 + * @param core_if Programming view of DWC_otg controller.
4455 +void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
4457 + volatile uint8_t *addr, *start_addr, *end_addr;
4459 + DWC_PRINT("SPRAM Data:\n");
4460 + start_addr = (void*)core_if->core_global_regs;
4461 + DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
4462 + start_addr += 0x00028000;
4463 + end_addr=(void*)core_if->core_global_regs;
4464 + end_addr += 0x000280e0;
4466 + for(addr = start_addr; addr < end_addr; addr+=16)
4468 + DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr,
4491 + * This function reads the host registers and prints them
4493 + * @param core_if Programming view of DWC_otg controller.
4495 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
4498 + volatile uint32_t *addr;
4500 + DWC_PRINT("Host Global Registers\n");
4501 + addr=&core_if->host_if->host_global_regs->hcfg;
4502 + DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4503 + addr=&core_if->host_if->host_global_regs->hfir;
4504 + DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4505 + addr=&core_if->host_if->host_global_regs->hfnum;
4506 + DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4507 + addr=&core_if->host_if->host_global_regs->hptxsts;
4508 + DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4509 + addr=&core_if->host_if->host_global_regs->haint;
4510 + DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4511 + addr=&core_if->host_if->host_global_regs->haintmsk;
4512 + DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4513 + addr=core_if->host_if->hprt0;
4514 + DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4516 + for (i=0; i<core_if->core_params->host_channels; i++)
4518 + DWC_PRINT("Host Channel %d Specific Registers\n", i);
4519 + addr=&core_if->host_if->hc_regs[i]->hcchar;
4520 + DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4521 + addr=&core_if->host_if->hc_regs[i]->hcsplt;
4522 + DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4523 + addr=&core_if->host_if->hc_regs[i]->hcint;
4524 + DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4525 + addr=&core_if->host_if->hc_regs[i]->hcintmsk;
4526 + DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4527 + addr=&core_if->host_if->hc_regs[i]->hctsiz;
4528 + DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4529 + addr=&core_if->host_if->hc_regs[i]->hcdma;
4530 + DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4536 + * This function reads the core global registers and prints them
4538 + * @param core_if Programming view of DWC_otg controller.
4540 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
4544 + volatile uint32_t *addr;
4546 + DWC_PRINT("Core Global Registers\n");
4547 + addr=&core_if->core_global_regs->gotgctl;
4548 + DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4549 + addr=&core_if->core_global_regs->gotgint;
4550 + DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4551 + addr=&core_if->core_global_regs->gahbcfg;
4552 + DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4553 + addr=&core_if->core_global_regs->gusbcfg;
4554 + DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4555 + addr=&core_if->core_global_regs->grstctl;
4556 + DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4557 + addr=&core_if->core_global_regs->gintsts;
4558 + DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4559 + addr=&core_if->core_global_regs->gintmsk;
4560 + DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4561 + addr=&core_if->core_global_regs->grxstsr;
4562 + DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4563 + //addr=&core_if->core_global_regs->grxstsp;
4564 + //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4565 + addr=&core_if->core_global_regs->grxfsiz;
4566 + DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4567 + addr=&core_if->core_global_regs->gnptxfsiz;
4568 + DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4569 + addr=&core_if->core_global_regs->gnptxsts;
4570 + DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4571 + addr=&core_if->core_global_regs->gi2cctl;
4572 + DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4573 + addr=&core_if->core_global_regs->gpvndctl;
4574 + DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4575 + addr=&core_if->core_global_regs->ggpio;
4576 + DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4577 + addr=&core_if->core_global_regs->guid;
4578 + DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4579 + addr=&core_if->core_global_regs->gsnpsid;
4580 + DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4581 + addr=&core_if->core_global_regs->ghwcfg1;
4582 + DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4583 + addr=&core_if->core_global_regs->ghwcfg2;
4584 + DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4585 + addr=&core_if->core_global_regs->ghwcfg3;
4586 + DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4587 + addr=&core_if->core_global_regs->ghwcfg4;
4588 + DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4589 + addr=&core_if->core_global_regs->hptxfsiz;
4590 + DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4592 + size=(core_if->hwcfg4.b.ded_fifo_en)?
4593 + core_if->hwcfg4.b.num_in_eps:core_if->hwcfg4.b.num_dev_perio_in_ep;
4594 + str=(core_if->hwcfg4.b.ded_fifo_en)?"DIEPTXF":"DPTXFSIZ";
4595 + for (i=0; i<size; i++)
4597 + addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i];
4598 + DWC_PRINT("%s[%d] @0x%08X : 0x%08X\n",str,i,(uint32_t)addr,dwc_read_reg32(addr));
4603 + * Flush a Tx FIFO.
4605 + * @param core_if Programming view of DWC_otg controller.
4606 + * @param num Tx FIFO to flush.
4608 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if,
4611 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4612 + volatile grstctl_t greset = { .d32 = 0};
4615 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num);
4617 + greset.b.txfflsh = 1;
4618 + greset.b.txfnum = num;
4619 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
4622 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4623 + if (++count > 10000) {
4624 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
4625 + __func__, greset.d32,
4626 + dwc_read_reg32(&global_regs->gnptxsts));
4630 + while (greset.b.txfflsh == 1);
4632 + /* Wait for 3 PHY Clocks*/
4639 + * @param core_if Programming view of DWC_otg controller.
4641 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
4643 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4644 + volatile grstctl_t greset = { .d32 = 0};
4647 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
4651 + greset.b.rxfflsh = 1;
4652 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
4655 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4656 + if (++count > 10000) {
4657 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
4662 + while (greset.b.rxfflsh == 1);
4664 + /* Wait for 3 PHY Clocks*/
4669 + * Do core a soft reset of the core. Be careful with this because it
4670 + * resets all the internal state machines of the core.
4672 +void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
4674 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4675 + volatile grstctl_t greset = { .d32 = 0};
4678 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
4679 + /* Wait for AHB master IDLE state. */
4682 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4683 + if (++count > 100000) {
4684 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
4689 + while (greset.b.ahbidle == 0);
4691 + /* Core Soft Reset */
4693 + greset.b.csftrst = 1;
4694 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
4696 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4697 + if (++count > 10000) {
4698 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
4703 + while (greset.b.csftrst == 1);
4705 + /* Wait for 3 PHY Clocks*/
4708 + DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4709 + DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4710 + DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4717 + * Register HCD callbacks. The callbacks are used to start and stop
4718 + * the HCD for interrupt processing.
4720 + * @param core_if Programming view of DWC_otg controller.
4721 + * @param cb the HCD callback structure.
4722 + * @param p pointer to be passed to callback function (usb_hcd*).
4724 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
4725 + dwc_otg_cil_callbacks_t *cb,
4728 + core_if->hcd_cb = cb;
4733 + * Register PCD callbacks. The callbacks are used to start and stop
4734 + * the PCD for interrupt processing.
4736 + * @param core_if Programming view of DWC_otg controller.
4737 + * @param cb the PCD callback structure.
4738 + * @param p pointer to be passed to callback function (pcd*).
4740 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
4741 + dwc_otg_cil_callbacks_t *cb,
4744 + core_if->pcd_cb = cb;
4751 + * This function writes isoc data per 1 (micro)frame into tx fifo
4753 + * @param core_if Programming view of DWC_otg controller.
4754 + * @param ep The EP to start the transfer on.
4757 +void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4759 + dwc_otg_dev_in_ep_regs_t *ep_regs;
4760 + dtxfsts_data_t txstatus = {.d32 = 0};
4764 + ep->xfer_len = ep->data_per_frame;
4765 + ep->xfer_count = 0;
4767 + ep_regs = core_if->dev_if->in_ep_regs[ep->num];
4769 + len = ep->xfer_len - ep->xfer_count;
4771 + if (len > ep->maxpacket) {
4772 + len = ep->maxpacket;
4775 + dwords = (len + 3)/4;
4777 + /* While there is space in the queue and space in the FIFO and
4778 + * More data to tranfer, Write packets to the Tx FIFO */
4779 + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
4780 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32);
4782 + while (txstatus.b.txfspcavail > dwords &&
4783 + ep->xfer_count < ep->xfer_len &&
4784 + ep->xfer_len != 0) {
4785 + /* Write the FIFO */
4786 + dwc_otg_ep_write_packet(core_if, ep, 0);
4788 + len = ep->xfer_len - ep->xfer_count;
4789 + if (len > ep->maxpacket) {
4790 + len = ep->maxpacket;
4793 + dwords = (len + 3)/4;
4794 + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
4795 + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
4801 + * This function initializes a descriptor chain for Isochronous transfer
4803 + * @param core_if Programming view of DWC_otg controller.
4804 + * @param ep The EP to start the transfer on.
4807 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4809 + deptsiz_data_t deptsiz = { .d32 = 0 };
4810 + depctl_data_t depctl = { .d32 = 0 };
4811 + dsts_data_t dsts = { .d32 = 0 };
4812 + volatile uint32_t *addr;
4815 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
4817 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
4820 + ep->xfer_len = ep->data_per_frame;
4821 + ep->xfer_count = 0;
4822 + ep->xfer_buff = ep->cur_pkt_addr;
4823 + ep->dma_addr = ep->cur_pkt_dma_addr;
4826 + /* Program the transfer size and packet count
4827 + * as follows: xfersize = N * maxpacket +
4828 + * short_packet pktcnt = N + (short_packet
4831 + deptsiz.b.xfersize = ep->xfer_len;
4832 + deptsiz.b.pktcnt =
4833 + (ep->xfer_len - 1 + ep->maxpacket) /
4835 + deptsiz.b.mc = deptsiz.b.pktcnt;
4836 + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
4838 + /* Write the DMA register */
4839 + if (core_if->dma_enable) {
4840 + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
4843 + deptsiz.b.pktcnt =
4844 + (ep->xfer_len + (ep->maxpacket - 1)) /
4846 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
4848 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
4850 + if (core_if->dma_enable) {
4851 + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma),
4852 + (uint32_t)ep->dma_addr);
4857 + /** Enable endpoint, clear nak */
4860 + if(ep->bInterval == 1) {
4861 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
4862 + ep->next_frame = dsts.b.soffn + ep->bInterval;
4864 + if(ep->next_frame & 0x1) {
4865 + depctl.b.setd1pid = 1;
4867 + depctl.b.setd0pid = 1;
4870 + ep->next_frame += ep->bInterval;
4872 + if(ep->next_frame & 0x1) {
4873 + depctl.b.setd1pid = 1;
4875 + depctl.b.setd0pid = 1;
4878 + depctl.b.epena = 1;
4879 + depctl.b.cnak = 1;
4881 + dwc_modify_reg32(addr, 0, depctl.d32);
4882 + depctl.d32 = dwc_read_reg32(addr);
4884 + if(ep->is_in && core_if->dma_enable == 0) {
4885 + write_isoc_frame_data(core_if, ep);
4890 +#endif //DWC_EN_ISOC
4892 +++ b/drivers/usb/dwc/otg_cil.h
4894 +/* ==========================================================================
4895 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
4896 + * $Revision: #91 $
4897 + * $Date: 2008/09/19 $
4898 + * $Change: 1099526 $
4900 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
4901 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
4902 + * otherwise expressly agreed to in writing between Synopsys and you.
4904 + * The Software IS NOT an item of Licensed Software or Licensed Product under
4905 + * any End User Software License Agreement or Agreement for Licensed Product
4906 + * with Synopsys or any supplement thereto. You are permitted to use and
4907 + * redistribute this Software in source and binary forms, with or without
4908 + * modification, provided that redistributions of source code must retain this
4909 + * notice. You may not view, use, disclose, copy or distribute this file or
4910 + * any information contained herein except pursuant to this license grant from
4911 + * Synopsys. If you do not agree with this notice, including the disclaimer
4912 + * below, then you are not authorized to use the Software.
4914 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
4915 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4916 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4917 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
4918 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4919 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
4920 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
4921 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
4922 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
4923 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4925 + * ========================================================================== */
4927 +#if !defined(__DWC_CIL_H__)
4928 +#define __DWC_CIL_H__
4930 +#include <linux/workqueue.h>
4931 +#include <linux/version.h>
4932 +#include <asm/param.h>
4933 +//#include <asm/arch/regs-irq.h>
4935 +#include "otg_plat.h"
4936 +#include "otg_regs.h"
4938 +#include "linux/timer.h"
4943 + * This file contains the interface to the Core Interface Layer.
4947 +/** Macros defined for DWC OTG HW Release verison */
4948 +#define OTG_CORE_REV_2_00 0x4F542000
4949 +#define OTG_CORE_REV_2_60a 0x4F54260A
4950 +#define OTG_CORE_REV_2_71a 0x4F54271A
4951 +#define OTG_CORE_REV_2_72a 0x4F54272A
4955 +typedef struct iso_pkt_info
4962 + * The <code>dwc_ep</code> structure represents the state of a single
4963 + * endpoint when acting in device mode. It contains the data items
4964 + * needed for an endpoint to be activated and transfer packets.
4966 +typedef struct dwc_ep
4968 + /** EP number used for register address lookup */
4970 + /** EP direction 0 = OUT */
4971 + unsigned is_in : 1;
4973 + unsigned active : 1;
4975 + /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
4976 + If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
4977 + unsigned tx_fifo_num : 4;
4978 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
4979 + unsigned type : 2;
4980 +#define DWC_OTG_EP_TYPE_CONTROL 0
4981 +#define DWC_OTG_EP_TYPE_ISOC 1
4982 +#define DWC_OTG_EP_TYPE_BULK 2
4983 +#define DWC_OTG_EP_TYPE_INTR 3
4985 + /** DATA start PID for INTR and BULK EP */
4986 + unsigned data_pid_start : 1;
4987 + /** Frame (even/odd) for ISOC EP */
4988 + unsigned even_odd_frame : 1;
4989 + /** Max Packet bytes */
4990 + unsigned maxpacket : 11;
4992 + /** Max Transfer size */
4993 + unsigned maxxfer : 16;
4995 + /** @name Transfer state */
4999 + * Pointer to the beginning of the transfer buffer -- do not modify
5000 + * during transfer.
5003 + uint32_t dma_addr;
5005 + uint32_t dma_desc_addr;
5006 + dwc_otg_dma_desc_t* desc_addr;
5009 + uint8_t *start_xfer_buff;
5010 + /** pointer to the transfer buffer */
5011 + uint8_t *xfer_buff;
5012 + /** Number of bytes to transfer */
5013 + unsigned xfer_len : 19;
5014 + /** Number of bytes transferred. */
5015 + unsigned xfer_count : 19;
5017 + unsigned sent_zlp : 1;
5018 + /** Total len for control transfer */
5019 + unsigned total_len : 19;
5021 + /** stall clear flag */
5022 + unsigned stall_clear_flag : 1;
5024 + /** Allocated DMA Desc count */
5025 + uint32_t desc_cnt;
5027 + uint32_t aligned_dma_addr;
5028 + uint32_t aligned_buf_size;
5029 + uint8_t *aligned_buf;
5034 + * Variables specific for ISOC EPs
5037 + /** DMA addresses of ISOC buffers */
5038 + uint32_t dma_addr0;
5039 + uint32_t dma_addr1;
5041 + uint32_t iso_dma_desc_addr;
5042 + dwc_otg_dma_desc_t* iso_desc_addr;
5044 + /** pointer to the transfer buffers */
5045 + uint8_t *xfer_buff0;
5046 + uint8_t *xfer_buff1;
5048 + /** number of ISOC Buffer is processing */
5049 + uint32_t proc_buf_num;
5050 + /** Interval of ISOC Buffer processing */
5051 + uint32_t buf_proc_intrvl;
5052 + /** Data size for regular frame */
5053 + uint32_t data_per_frame;
5055 + /* todo - pattern data support is to be implemented in the future */
5056 + /** Data size for pattern frame */
5057 + uint32_t data_pattern_frame;
5058 + /** Frame number of pattern data */
5059 + uint32_t sync_frame;
5062 + uint32_t bInterval;
5063 + /** ISO Packet number per frame */
5064 + uint32_t pkt_per_frm;
5065 + /** Next frame num for which will be setup DMA Desc */
5066 + uint32_t next_frame;
5067 + /** Number of packets per buffer processing */
5069 + /** Info for all isoc packets */
5070 + iso_pkt_info_t *pkt_info;
5071 + /** current pkt number */
5073 + /** current pkt number */
5074 + uint8_t *cur_pkt_addr;
5075 + /** current pkt number */
5076 + uint32_t cur_pkt_dma_addr;
5077 +#endif //DWC_EN_ISOC
5082 + * Reasons for halting a host channel.
5084 +typedef enum dwc_otg_halt_status
5086 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
5087 + DWC_OTG_HC_XFER_COMPLETE,
5088 + DWC_OTG_HC_XFER_URB_COMPLETE,
5089 + DWC_OTG_HC_XFER_ACK,
5090 + DWC_OTG_HC_XFER_NAK,
5091 + DWC_OTG_HC_XFER_NYET,
5092 + DWC_OTG_HC_XFER_STALL,
5093 + DWC_OTG_HC_XFER_XACT_ERR,
5094 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
5095 + DWC_OTG_HC_XFER_BABBLE_ERR,
5096 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
5097 + DWC_OTG_HC_XFER_AHB_ERR,
5098 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
5099 + DWC_OTG_HC_XFER_URB_DEQUEUE
5100 +} dwc_otg_halt_status_e;
5103 + * Host channel descriptor. This structure represents the state of a single
5104 + * host channel when acting in host mode. It contains the data items needed to
5105 + * transfer packets to an endpoint via a host channel.
5107 +typedef struct dwc_hc
5109 + /** Host channel number used for register address lookup */
5112 + /** Device to access */
5113 + unsigned dev_addr : 7;
5115 + /** EP to access */
5116 + unsigned ep_num : 4;
5118 + /** EP direction. 0: OUT, 1: IN */
5119 + unsigned ep_is_in : 1;
5123 + * One of the following values:
5124 + * - DWC_OTG_EP_SPEED_LOW
5125 + * - DWC_OTG_EP_SPEED_FULL
5126 + * - DWC_OTG_EP_SPEED_HIGH
5128 + unsigned speed : 2;
5129 +#define DWC_OTG_EP_SPEED_LOW 0
5130 +#define DWC_OTG_EP_SPEED_FULL 1
5131 +#define DWC_OTG_EP_SPEED_HIGH 2
5135 + * One of the following values:
5136 + * - DWC_OTG_EP_TYPE_CONTROL: 0
5137 + * - DWC_OTG_EP_TYPE_ISOC: 1
5138 + * - DWC_OTG_EP_TYPE_BULK: 2
5139 + * - DWC_OTG_EP_TYPE_INTR: 3
5141 + unsigned ep_type : 2;
5143 + /** Max packet size in bytes */
5144 + unsigned max_packet : 11;
5147 + * PID for initial transaction.
5151 + * 3: MDATA (non-Control EP),
5152 + * SETUP (Control EP)
5154 + unsigned data_pid_start : 2;
5155 +#define DWC_OTG_HC_PID_DATA0 0
5156 +#define DWC_OTG_HC_PID_DATA2 1
5157 +#define DWC_OTG_HC_PID_DATA1 2
5158 +#define DWC_OTG_HC_PID_MDATA 3
5159 +#define DWC_OTG_HC_PID_SETUP 3
5161 + /** Number of periodic transactions per (micro)frame */
5162 + unsigned multi_count: 2;
5164 + /** @name Transfer State */
5167 + /** Pointer to the current transfer buffer position. */
5168 + uint8_t *xfer_buff;
5169 + /** Total number of bytes to transfer. */
5170 + uint32_t xfer_len;
5171 + /** Number of bytes transferred so far. */
5172 + uint32_t xfer_count;
5173 + /** Packet count at start of transfer.*/
5174 + uint16_t start_pkt_count;
5177 + * Flag to indicate whether the transfer has been started. Set to 1 if
5178 + * it has been started, 0 otherwise.
5180 + uint8_t xfer_started;
5183 + * Set to 1 to indicate that a PING request should be issued on this
5184 + * channel. If 0, process normally.
5189 + * Set to 1 to indicate that the error count for this transaction is
5190 + * non-zero. Set to 0 if the error count is 0.
5192 + uint8_t error_state;
5195 + * Set to 1 to indicate that this channel should be halted the next
5196 + * time a request is queued for the channel. This is necessary in
5197 + * slave mode if no request queue space is available when an attempt
5198 + * is made to halt the channel.
5200 + uint8_t halt_on_queue;
5203 + * Set to 1 if the host channel has been halted, but the core is not
5204 + * finished flushing queued requests. Otherwise 0.
5206 + uint8_t halt_pending;
5209 + * Reason for halting the host channel.
5211 + dwc_otg_halt_status_e halt_status;
5214 + * Split settings for the host channel
5216 + uint8_t do_split; /**< Enable split for the channel */
5217 + uint8_t complete_split; /**< Enable complete split */
5218 + uint8_t hub_addr; /**< Address of high speed hub */
5220 + uint8_t port_addr; /**< Port of the low/full speed device */
5221 + /** Split transaction position
5222 + * One of the following values:
5223 + * - DWC_HCSPLIT_XACTPOS_MID
5224 + * - DWC_HCSPLIT_XACTPOS_BEGIN
5225 + * - DWC_HCSPLIT_XACTPOS_END
5226 + * - DWC_HCSPLIT_XACTPOS_ALL */
5229 + /** Set when the host channel does a short read. */
5230 + uint8_t short_read;
5233 + * Number of requests issued for this channel since it was assigned to
5234 + * the current transfer (not counting PINGs).
5239 + * Queue Head for the transfer being processed by this channel.
5241 + struct dwc_otg_qh *qh;
5245 + /** Entry in list of host channels. */
5246 + struct list_head hc_list_entry;
5250 + * The following parameters may be specified when starting the module. These
5251 + * parameters define how the DWC_otg controller should be configured.
5252 + * Parameter values are passed to the CIL initialization function
5253 + * dwc_otg_cil_init.
5255 +typedef struct dwc_otg_core_params
5258 +#define dwc_param_opt_default 1
5261 + * Specifies the OTG capabilities. The driver will automatically
5262 + * detect the value for this parameter if none is specified.
5263 + * 0 - HNP and SRP capable (default)
5264 + * 1 - SRP Only capable
5265 + * 2 - No HNP/SRP capable
5268 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
5269 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
5270 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
5271 +//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
5272 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
5275 + * Specifies whether to use slave or DMA mode for accessing the data
5276 + * FIFOs. The driver will automatically detect the value for this
5277 + * parameter if none is specified.
5279 + * 1 - DMA (default, if available)
5281 + int32_t dma_enable;
5282 +#define dwc_param_dma_enable_default 1
5285 + * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
5286 + * FIFOs in device mode. The driver will automatically detect the value for this
5287 + * parameter if none is specified.
5289 + * 1 - DMA Descriptor(default, if available)
5291 + int32_t dma_desc_enable;
5292 +#define dwc_param_dma_desc_enable_default 0
5293 + /** The DMA Burst size (applicable only for External DMA
5294 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
5296 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
5297 +//#define dwc_param_dma_burst_size_default 32
5298 +#define dwc_param_dma_burst_size_default 1
5301 + * Specifies the maximum speed of operation in host and device mode.
5302 + * The actual speed depends on the speed of the attached device and
5303 + * the value of phy_type. The actual speed depends on the speed of the
5304 + * attached device.
5305 + * 0 - High Speed (default)
5309 +#define dwc_param_speed_default 0
5310 +#define DWC_SPEED_PARAM_HIGH 0
5311 +#define DWC_SPEED_PARAM_FULL 1
5313 + /** Specifies whether low power mode is supported when attached
5314 + * to a Full Speed or Low Speed device in host mode.
5315 + * 0 - Don't support low power mode (default)
5316 + * 1 - Support low power mode
5318 + int32_t host_support_fs_ls_low_power;
5319 +#define dwc_param_host_support_fs_ls_low_power_default 0
5321 + /** Specifies the PHY clock rate in low power mode when connected to a
5322 + * Low Speed device in host mode. This parameter is applicable only if
5323 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
5324 + * then defaults to 6 MHZ otherwise 48 MHZ.
5329 + int32_t host_ls_low_power_phy_clk;
5330 +#define dwc_param_host_ls_low_power_phy_clk_default 0
5331 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
5332 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
5335 + * 0 - Use cC FIFO size parameters
5336 + * 1 - Allow dynamic FIFO sizing (default)
5338 + int32_t enable_dynamic_fifo;
5339 +#define dwc_param_enable_dynamic_fifo_default 1
5341 + /** Total number of 4-byte words in the data FIFO memory. This
5342 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
5344 + * 32 to 32768 (default 8192)
5345 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
5347 + int32_t data_fifo_size;
5348 +#define dwc_param_data_fifo_size_default 8192
5350 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
5351 + * FIFO sizing is enabled.
5352 + * 16 to 32768 (default 1064)
5354 + int32_t dev_rx_fifo_size;
5355 +//#define dwc_param_dev_rx_fifo_size_default 1064
5356 +#define dwc_param_dev_rx_fifo_size_default 0x100
5359 + * Specifies whether dedicated transmit FIFOs are
5360 + * enabled for non periodic IN endpoints in device mode
5364 + int32_t en_multiple_tx_fifo;
5365 +#define dwc_param_en_multiple_tx_fifo_default 1
5367 + /** Number of 4-byte words in each of the Tx FIFOs in device
5368 + * mode when dynamic FIFO sizing is enabled.
5369 + * 4 to 768 (default 256)
5371 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
5372 +//#define dwc_param_dev_tx_fifo_size_default 256
5373 +#define dwc_param_dev_tx_fifo_size_default 0x80
5375 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
5376 + * when dynamic FIFO sizing is enabled.
5377 + * 16 to 32768 (default 1024)
5379 + int32_t dev_nperio_tx_fifo_size;
5380 +//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
5381 +#define dwc_param_dev_nperio_tx_fifo_size_default 0x80
5383 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
5384 + * mode when dynamic FIFO sizing is enabled.
5385 + * 4 to 768 (default 256)
5387 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
5388 +//#define dwc_param_dev_perio_tx_fifo_size_default 256
5389 +#define dwc_param_dev_perio_tx_fifo_size_default 0x80
5391 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
5392 + * FIFO sizing is enabled.
5393 + * 16 to 32768 (default 1024)
5395 + int32_t host_rx_fifo_size;
5396 +//#define dwc_param_host_rx_fifo_size_default 1024
5397 +#define dwc_param_host_rx_fifo_size_default 0x292
5399 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
5400 + * when Dynamic FIFO sizing is enabled in the core.
5401 + * 16 to 32768 (default 1024)
5403 + int32_t host_nperio_tx_fifo_size;
5404 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
5405 +//#define dwc_param_host_nperio_tx_fifo_size_default 0x292
5406 +#define dwc_param_host_nperio_tx_fifo_size_default 0x80
5408 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
5409 + * FIFO sizing is enabled.
5410 + * 16 to 32768 (default 1024)
5412 + int32_t host_perio_tx_fifo_size;
5413 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
5414 +#define dwc_param_host_perio_tx_fifo_size_default 0x292
5416 + /** The maximum transfer size supported in bytes.
5417 + * 2047 to 65,535 (default 65,535)
5419 + int32_t max_transfer_size;
5420 +#define dwc_param_max_transfer_size_default 65535
5422 + /** The maximum number of packets in a transfer.
5423 + * 15 to 511 (default 511)
5425 + int32_t max_packet_count;
5426 +#define dwc_param_max_packet_count_default 511
5428 + /** The number of host channel registers to use.
5429 + * 1 to 16 (default 12)
5430 + * Note: The FPGA configuration supports a maximum of 12 host channels.
5432 + int32_t host_channels;
5433 +//#define dwc_param_host_channels_default 12
5434 +#define dwc_param_host_channels_default 16
5436 + /** The number of endpoints in addition to EP0 available for device
5437 + * mode operations.
5438 + * 1 to 15 (default 6 IN and OUT)
5439 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
5440 + * endpoints in addition to EP0.
5442 + int32_t dev_endpoints;
5443 +//#define dwc_param_dev_endpoints_default 6
5444 +#define dwc_param_dev_endpoints_default 8
5447 + * Specifies the type of PHY interface to use. By default, the driver
5448 + * will automatically detect the phy_type.
5450 + * 0 - Full Speed PHY
5451 + * 1 - UTMI+ (default)
5455 +#define DWC_PHY_TYPE_PARAM_FS 0
5456 +#define DWC_PHY_TYPE_PARAM_UTMI 1
5457 +#define DWC_PHY_TYPE_PARAM_ULPI 2
5458 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
5461 + * Specifies the UTMI+ Data Width. This parameter is
5462 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
5463 + * PHY_TYPE, this parameter indicates the data width between
5464 + * the MAC and the ULPI Wrapper.) Also, this parameter is
5465 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
5466 + * to "8 and 16 bits", meaning that the core has been
5467 + * configured to work at either data path width.
5469 + * 8 or 16 bits (default 16)
5471 + int32_t phy_utmi_width;
5472 +#define dwc_param_phy_utmi_width_default 16
5475 + * Specifies whether the ULPI operates at double or single
5476 + * data rate. This parameter is only applicable if PHY_TYPE is
5479 + * 0 - single data rate ULPI interface with 8 bit wide data
5481 + * 1 - double data rate ULPI interface with 4 bit wide data
5484 + int32_t phy_ulpi_ddr;
5485 +#define dwc_param_phy_ulpi_ddr_default 0
5488 + * Specifies whether to use the internal or external supply to
5489 + * drive the vbus with a ULPI phy.
5491 + int32_t phy_ulpi_ext_vbus;
5492 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
5493 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
5494 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
5497 + * Specifies whether to use the I2Cinterface for full speed PHY. This
5498 + * parameter is only applicable if PHY_TYPE is FS.
5499 + * 0 - No (default)
5502 + int32_t i2c_enable;
5503 +#define dwc_param_i2c_enable_default 0
5505 + int32_t ulpi_fs_ls;
5506 +#define dwc_param_ulpi_fs_ls_default 0
5509 +#define dwc_param_ts_dline_default 0
5511 + /** Thresholding enable flag-
5512 + * bit 0 - enable non-ISO Tx thresholding
5513 + * bit 1 - enable ISO Tx thresholding
5514 + * bit 2 - enable Rx thresholding
5517 +#define dwc_param_thr_ctl_default 0
5519 + /** Thresholding length for Tx
5520 + * FIFOs in 32 bit DWORDs
5522 + uint32_t tx_thr_length;
5523 +#define dwc_param_tx_thr_length_default 64
5525 + /** Thresholding length for Rx
5526 + * FIFOs in 32 bit DWORDs
5528 + uint32_t rx_thr_length;
5529 +#define dwc_param_rx_thr_length_default 64
5531 + /** Per Transfer Interrupt
5532 + * mode enable flag
5536 + uint32_t pti_enable;
5537 +#define dwc_param_pti_enable_default 0
5539 + /** Molti Processor Interrupt
5540 + * mode enable flag
5544 + uint32_t mpi_enable;
5545 +#define dwc_param_mpi_enable_default 0
5547 +} dwc_otg_core_params_t;
5550 +struct dwc_otg_core_if;
5551 +typedef struct hc_xfer_info
5553 + struct dwc_otg_core_if *core_if;
5559 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
5560 + * the DWC_otg controller acting in either host or device mode. It
5561 + * represents the programming view of the controller as a whole.
5563 +typedef struct dwc_otg_core_if
5565 + /** Parameters that define how the core should be configured.*/
5566 + dwc_otg_core_params_t *core_params;
5568 + /** Core Global registers starting at offset 000h. */
5569 + dwc_otg_core_global_regs_t *core_global_regs;
5571 + /** Device-specific information */
5572 + dwc_otg_dev_if_t *dev_if;
5573 + /** Host-specific information */
5574 + dwc_otg_host_if_t *host_if;
5576 + /** Value from SNPSID register */
5580 + * Set to 1 if the core PHY interface bits in USBCFG have been
5583 + uint8_t phy_init_done;
5586 + * SRP Success flag, set by srp success interrupt in FS I2C mode
5588 + uint8_t srp_success;
5589 + uint8_t srp_timer_started;
5591 + /* Common configuration information */
5592 + /** Power and Clock Gating Control Register */
5593 + volatile uint32_t *pcgcctl;
5594 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
5596 + /** Push/pop addresses for endpoints or host channels.*/
5597 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
5598 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
5599 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
5601 + /** Total RAM for FIFOs (Bytes) */
5602 + uint16_t total_fifo_size;
5603 + /** Size of Rx FIFO (Bytes) */
5604 + uint16_t rx_fifo_size;
5605 + /** Size of Non-periodic Tx FIFO (Bytes) */
5606 + uint16_t nperio_tx_fifo_size;
5609 + /** 1 if DMA is enabled, 0 otherwise. */
5610 + uint8_t dma_enable;
5612 + /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
5613 + uint8_t dma_desc_enable;
5615 + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
5616 + uint8_t pti_enh_enable;
5618 + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
5619 + uint8_t multiproc_int_enable;
5621 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
5622 + uint8_t en_multiple_tx_fifo;
5624 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
5625 + * process of being queued */
5626 + uint8_t queuing_high_bandwidth;
5628 + /** Hardware Configuration -- stored here for convenience.*/
5629 + hwcfg1_data_t hwcfg1;
5630 + hwcfg2_data_t hwcfg2;
5631 + hwcfg3_data_t hwcfg3;
5632 + hwcfg4_data_t hwcfg4;
5634 + /** Host and Device Configuration -- stored here for convenience.*/
5638 + /** The operational State, during transations
5639 + * (a_host>>a_peripherial and b_device=>b_host) this may not
5640 + * match the core but allows the software to determine
5646 + * Set to 1 if the HCD needs to be restarted on a session request
5647 + * interrupt. This is required if no connector ID status change has
5648 + * occurred since the HCD was last disconnected.
5650 + uint8_t restart_hcd_on_session_req;
5652 + /** HCD callbacks */
5653 + /** A-Device is a_host */
5655 + /** A-Device is a_suspend */
5656 +#define A_SUSPEND (2)
5657 + /** A-Device is a_peripherial */
5658 +#define A_PERIPHERAL (3)
5659 + /** B-Device is operating as a Peripheral. */
5660 +#define B_PERIPHERAL (4)
5661 + /** B-Device is operating as a Host. */
5664 + /** HCD callbacks */
5665 + struct dwc_otg_cil_callbacks *hcd_cb;
5666 + /** PCD callbacks */
5667 + struct dwc_otg_cil_callbacks *pcd_cb;
5669 + /** Device mode Periodic Tx FIFO Mask */
5670 + uint32_t p_tx_msk;
5671 + /** Device mode Periodic Tx FIFO Mask */
5674 + /** Workqueue object used for handling several interrupts */
5675 + struct workqueue_struct *wq_otg;
5677 + /** Work object used for handling "Connector ID Status Change" Interrupt */
5678 + struct work_struct w_conn_id;
5680 + /** Work object used for handling "Wakeup Detected" Interrupt */
5681 + struct delayed_work w_wkp;
5684 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
5686 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
5687 + struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
5689 + uint32_t hfnum_7_samples;
5690 + uint64_t hfnum_7_frrem_accum;
5691 + uint32_t hfnum_0_samples;
5692 + uint64_t hfnum_0_frrem_accum;
5693 + uint32_t hfnum_other_samples;
5694 + uint64_t hfnum_other_frrem_accum;
5698 +} dwc_otg_core_if_t;
5700 +/*We must clear S3C24XX_EINTPEND external interrupt register
5701 + * because after clearing in this register trigerred IRQ from
5702 + * H/W core in kernel interrupt can be occured again before OTG
5703 + * handlers clear all IRQ sources of Core registers because of
5704 + * timing latencies and Low Level IRQ Type.
5707 +#ifdef CONFIG_MACH_IPMATE
5708 +#define S3C2410X_CLEAR_EINTPEND() \
5710 + if (!dwc_otg_read_core_intr(core_if)) { \
5711 + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
5715 +#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
5719 + * The following functions are functions for works
5720 + * using during handling some interrupts
5722 +extern void w_conn_id_status_change(struct work_struct *p);
5723 +extern void w_wakeup_detected(struct work_struct *p);
5727 + * The following functions support initialization of the CIL driver component
5728 + * and the DWC_otg controller.
5730 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
5731 + dwc_otg_core_params_t *_core_params);
5732 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
5733 +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
5734 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
5735 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
5736 +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
5737 +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
5739 +/** @name Device CIL Functions
5740 + * The following functions support managing the DWC_otg controller in device
5744 +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
5745 +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
5746 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
5747 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5748 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5749 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5750 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5751 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5752 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5753 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5754 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
5755 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5756 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5757 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
5758 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
5759 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
5761 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
5762 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
5763 +#endif //DWC_EN_ISOC
5766 +/** @name Host CIL Functions
5767 + * The following functions support managing the DWC_otg controller in host
5771 +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5772 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
5774 + dwc_otg_halt_status_e _halt_status);
5775 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5776 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5777 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5778 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5779 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5780 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
5781 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
5784 + * This function Reads HPRT0 in preparation to modify. It keeps the
5785 + * WC bits 0 so that if they are read as 1, they won't clear when you
5788 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
5790 + hprt0_data_t hprt0;
5791 + hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
5792 + hprt0.b.prtena = 0;
5793 + hprt0.b.prtconndet = 0;
5794 + hprt0.b.prtenchng = 0;
5795 + hprt0.b.prtovrcurrchng = 0;
5799 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
5802 +/** @name Common CIL Functions
5803 + * The following functions support managing the DWC_otg controller in either
5804 + * device or host mode.
5808 +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5812 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
5814 +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
5816 +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
5817 +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
5819 +extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
5820 +extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
5823 + * This function returns the Core Interrupt register.
5825 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
5827 + return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
5828 + dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
5832 + * This function returns the OTG Interrupt register.
5834 +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
5836 + return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
5840 + * This function reads the Device All Endpoints Interrupt register and
5841 + * returns the IN endpoint interrupt bits.
5843 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
5847 + if(core_if->multiproc_int_enable) {
5848 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
5849 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
5851 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
5852 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
5854 + return (v & 0xffff);
5859 + * This function reads the Device All Endpoints Interrupt register and
5860 + * returns the OUT endpoint interrupt bits.
5862 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
5866 + if(core_if->multiproc_int_enable) {
5867 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
5868 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
5870 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
5871 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
5874 + return ((v & 0xffff0000) >> 16);
5878 + * This function returns the Device IN EP Interrupt register
5880 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
5883 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
5884 + uint32_t v, msk, emp;
5886 + if(core_if->multiproc_int_enable) {
5887 + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
5888 + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
5889 + msk |= ((emp >> ep->num) & 0x1) << 7;
5890 + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
5892 + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
5893 + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
5894 + msk |= ((emp >> ep->num) & 0x1) << 7;
5895 + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
5902 + * This function returns the Device OUT EP Interrupt register
5904 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
5907 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
5909 + doepmsk_data_t msk = { .d32 = 0 };
5911 + if(_core_if->multiproc_int_enable) {
5912 + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
5913 + if(_core_if->pti_enh_enable) {
5914 + msk.b.pktdrpsts = 1;
5916 + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
5918 + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
5919 + if(_core_if->pti_enh_enable) {
5920 + msk.b.pktdrpsts = 1;
5922 + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
5928 + * This function returns the Host All Channel Interrupt register
5930 +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
5932 + return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
5935 +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
5937 + return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
5942 + * This function returns the mode of the operation, host or device.
5944 + * @return 0 - Device Mode, 1 - Host Mode
5946 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
5948 + return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
5951 +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
5953 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5955 +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
5957 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5960 +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
5966 + * DWC_otg CIL callback structure. This structure allows the HCD and
5967 + * PCD to register functions used for starting and stopping the PCD
5968 + * and HCD for role change on for a DRD.
5970 +typedef struct dwc_otg_cil_callbacks
5972 + /** Start function for role change */
5973 + int (*start) (void *_p);
5974 + /** Stop Function for role change */
5975 + int (*stop) (void *_p);
5976 + /** Disconnect Function for role change */
5977 + int (*disconnect) (void *_p);
5978 + /** Resume/Remote wakeup Function */
5979 + int (*resume_wakeup) (void *_p);
5980 + /** Suspend function */
5981 + int (*suspend) (void *_p);
5982 + /** Session Start (SRP) */
5983 + int (*session_start) (void *_p);
5984 + /** Pointer passed to start() and stop() */
5986 +} dwc_otg_cil_callbacks_t;
5988 +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
5989 + dwc_otg_cil_callbacks_t *_cb,
5991 +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
5992 + dwc_otg_cil_callbacks_t *_cb,
5995 +#define warn printk
6001 +++ b/drivers/usb/dwc/otg_cil_intr.c
6003 +/* ==========================================================================
6004 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
6005 + * $Revision: #10 $
6006 + * $Date: 2008/07/16 $
6007 + * $Change: 1065567 $
6009 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6010 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6011 + * otherwise expressly agreed to in writing between Synopsys and you.
6013 + * The Software IS NOT an item of Licensed Software or Licensed Product under
6014 + * any End User Software License Agreement or Agreement for Licensed Product
6015 + * with Synopsys or any supplement thereto. You are permitted to use and
6016 + * redistribute this Software in source and binary forms, with or without
6017 + * modification, provided that redistributions of source code must retain this
6018 + * notice. You may not view, use, disclose, copy or distribute this file or
6019 + * any information contained herein except pursuant to this license grant from
6020 + * Synopsys. If you do not agree with this notice, including the disclaimer
6021 + * below, then you are not authorized to use the Software.
6023 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6024 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6025 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6026 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6027 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6028 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6029 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6030 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6031 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6032 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6034 + * ========================================================================== */
6038 + * The Core Interface Layer provides basic services for accessing and
6039 + * managing the DWC_otg hardware. These services are used by both the
6040 + * Host Controller Driver and the Peripheral Controller Driver.
6042 + * This file contains the Common Interrupt handlers.
6044 +#include "otg_plat.h"
6045 +#include "otg_regs.h"
6046 +#include "otg_cil.h"
6047 +#include "otg_pcd.h"
6050 +inline const char *op_state_str(dwc_otg_core_if_t *core_if)
6052 + return (core_if->op_state==A_HOST?"a_host":
6053 + (core_if->op_state==A_SUSPEND?"a_suspend":
6054 + (core_if->op_state==A_PERIPHERAL?"a_peripheral":
6055 + (core_if->op_state==B_PERIPHERAL?"b_peripheral":
6056 + (core_if->op_state==B_HOST?"b_host":
6061 +/** This function will log a debug message
6063 + * @param core_if Programming view of DWC_otg controller.
6065 +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
6067 + gintsts_data_t gintsts;
6068 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
6069 + dwc_otg_mode(core_if) ? "Host" : "Device");
6071 + /* Clear interrupt */
6073 + gintsts.b.modemismatch = 1;
6074 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6078 +/** Start the HCD. Helper function for using the HCD callbacks.
6080 + * @param core_if Programming view of DWC_otg controller.
6082 +static inline void hcd_start(dwc_otg_core_if_t *core_if)
6084 + if (core_if->hcd_cb && core_if->hcd_cb->start) {
6085 + core_if->hcd_cb->start(core_if->hcd_cb->p);
6088 +/** Stop the HCD. Helper function for using the HCD callbacks.
6090 + * @param core_if Programming view of DWC_otg controller.
6092 +static inline void hcd_stop(dwc_otg_core_if_t *core_if)
6094 + if (core_if->hcd_cb && core_if->hcd_cb->stop) {
6095 + core_if->hcd_cb->stop(core_if->hcd_cb->p);
6098 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
6100 + * @param core_if Programming view of DWC_otg controller.
6102 +static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
6104 + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
6105 + core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
6108 +/** Inform the HCD the a New Session has begun. Helper function for
6109 + * using the HCD callbacks.
6111 + * @param core_if Programming view of DWC_otg controller.
6113 +static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
6115 + if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
6116 + core_if->hcd_cb->session_start(core_if->hcd_cb->p);
6120 +/** Start the PCD. Helper function for using the PCD callbacks.
6122 + * @param core_if Programming view of DWC_otg controller.
6124 +static inline void pcd_start(dwc_otg_core_if_t *core_if)
6126 + if (core_if->pcd_cb && core_if->pcd_cb->start) {
6127 + core_if->pcd_cb->start(core_if->pcd_cb->p);
6130 +/** Stop the PCD. Helper function for using the PCD callbacks.
6132 + * @param core_if Programming view of DWC_otg controller.
6134 +static inline void pcd_stop(dwc_otg_core_if_t *core_if)
6136 + if (core_if->pcd_cb && core_if->pcd_cb->stop) {
6137 + core_if->pcd_cb->stop(core_if->pcd_cb->p);
6140 +/** Suspend the PCD. Helper function for using the PCD callbacks.
6142 + * @param core_if Programming view of DWC_otg controller.
6144 +static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
6146 + if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
6147 + core_if->pcd_cb->suspend(core_if->pcd_cb->p);
6150 +/** Resume the PCD. Helper function for using the PCD callbacks.
6152 + * @param core_if Programming view of DWC_otg controller.
6154 +static inline void pcd_resume(dwc_otg_core_if_t *core_if)
6156 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
6157 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
6162 + * This function handles the OTG Interrupts. It reads the OTG
6163 + * Interrupt Register (GOTGINT) to determine what interrupt has
6166 + * @param core_if Programming view of DWC_otg controller.
6168 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
6170 + dwc_otg_core_global_regs_t *global_regs =
6171 + core_if->core_global_regs;
6172 + gotgint_data_t gotgint;
6173 + gotgctl_data_t gotgctl;
6174 + gintmsk_data_t gintmsk;
6175 + gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
6176 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6177 + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
6178 + op_state_str(core_if));
6179 + //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
6181 + if (gotgint.b.sesenddet) {
6182 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6183 + "Session End Detected++ (%s)\n",
6184 + op_state_str(core_if));
6185 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6187 + if (core_if->op_state == B_HOST) {
6189 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)core_if->pcd_cb->p;
6190 + if(unlikely(!pcd)) {
6191 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6194 + SPIN_LOCK(&pcd->lock);
6196 + pcd_start(core_if);
6198 + SPIN_UNLOCK(&pcd->lock);
6199 + core_if->op_state = B_PERIPHERAL;
6201 + dwc_otg_pcd_t *pcd;
6203 + /* If not B_HOST and Device HNP still set. HNP
6204 + * Did not succeed!*/
6205 + if (gotgctl.b.devhnpen) {
6206 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
6207 + DWC_ERROR("Device Not Connected/Responding!\n");
6210 + /* If Session End Detected the B-Cable has
6211 + * been disconnected. */
6212 + /* Reset PCD and Gadget driver to a
6215 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6216 + if(unlikely(!pcd)) {
6217 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6220 + SPIN_LOCK(&pcd->lock);
6222 + pcd_stop(core_if);
6224 + SPIN_UNLOCK(&pcd->lock);
6227 + gotgctl.b.devhnpen = 1;
6228 + dwc_modify_reg32(&global_regs->gotgctl,
6231 + if (gotgint.b.sesreqsucstschng) {
6232 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6233 + "Session Reqeust Success Status Change++\n");
6234 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6235 + if (gotgctl.b.sesreqscs) {
6236 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
6237 + (core_if->core_params->i2c_enable)) {
6238 + core_if->srp_success = 1;
6241 + dwc_otg_pcd_t *pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6242 + if(unlikely(!pcd)) {
6243 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6246 + SPIN_LOCK(&pcd->lock);
6248 + pcd_resume(core_if);
6250 + SPIN_UNLOCK(&pcd->lock);
6251 + /* Clear Session Request */
6253 + gotgctl.b.sesreq = 1;
6254 + dwc_modify_reg32(&global_regs->gotgctl,
6259 + if (gotgint.b.hstnegsucstschng) {
6260 + /* Print statements during the HNP interrupt handling
6261 + * can cause it to fail.*/
6262 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6263 + if (gotgctl.b.hstnegscs) {
6264 + if (dwc_otg_is_host_mode(core_if)) {
6265 + dwc_otg_pcd_t *pcd;
6267 + core_if->op_state = B_HOST;
6269 + * Need to disable SOF interrupt immediately.
6270 + * When switching from device to host, the PCD
6271 + * interrupt handler won't handle the
6272 + * interrupt if host mode is already set. The
6273 + * HCD interrupt handler won't get called if
6274 + * the HCD state is HALT. This means that the
6275 + * interrupt does not get handled and Linux
6276 + * complains loudly.
6279 + gintmsk.b.sofintr = 1;
6280 + dwc_modify_reg32(&global_regs->gintmsk,
6283 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6284 + if(unlikely(!pcd)) {
6285 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6288 + SPIN_LOCK(&pcd->lock);
6290 + pcd_stop(core_if);
6292 + SPIN_UNLOCK(&pcd->lock);
6294 + * Initialize the Core for Host mode.
6296 + hcd_start(core_if);
6297 + core_if->op_state = B_HOST;
6301 + gotgctl.b.hnpreq = 1;
6302 + gotgctl.b.devhnpen = 1;
6303 + dwc_modify_reg32(&global_regs->gotgctl,
6305 + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
6306 + DWC_ERROR("Device Not Connected/Responding\n");
6309 + if (gotgint.b.hstnegdet) {
6310 + /* The disconnect interrupt is set at the same time as
6311 + * Host Negotiation Detected. During the mode
6312 + * switch all interrupts are cleared so the disconnect
6313 + * interrupt handler will not get executed.
6315 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6316 + "Host Negotiation Detected++ (%s)\n",
6317 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
6318 + if (dwc_otg_is_device_mode(core_if)){
6319 + dwc_otg_pcd_t *pcd;
6321 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
6322 + hcd_disconnect(core_if);
6324 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6325 + if(unlikely(!pcd)) {
6326 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6329 + SPIN_LOCK(&pcd->lock);
6331 + pcd_start(core_if);
6333 + SPIN_UNLOCK(&pcd->lock);
6334 + core_if->op_state = A_PERIPHERAL;
6336 + dwc_otg_pcd_t *pcd;
6339 + * Need to disable SOF interrupt immediately. When
6340 + * switching from device to host, the PCD interrupt
6341 + * handler won't handle the interrupt if host mode is
6342 + * already set. The HCD interrupt handler won't get
6343 + * called if the HCD state is HALT. This means that
6344 + * the interrupt does not get handled and Linux
6345 + * complains loudly.
6348 + gintmsk.b.sofintr = 1;
6349 + dwc_modify_reg32(&global_regs->gintmsk,
6352 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6353 + if(unlikely(!pcd)) {
6354 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6357 + SPIN_LOCK(&pcd->lock);
6359 + pcd_stop(core_if);
6361 + SPIN_UNLOCK(&pcd->lock);
6362 + hcd_start(core_if);
6363 + core_if->op_state = A_HOST;
6366 + if (gotgint.b.adevtoutchng) {
6367 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6368 + "A-Device Timeout Change++\n");
6370 + if (gotgint.b.debdone) {
6371 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6372 + "Debounce Done++\n");
6375 + /* Clear GOTGINT */
6376 + dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
6382 +void w_conn_id_status_change(struct work_struct *p)
6384 + dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
6386 + uint32_t count = 0;
6387 + gotgctl_data_t gotgctl = { .d32 = 0 };
6389 + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
6390 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
6391 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
6393 + /* B-Device connector (Device Mode) */
6394 + if (gotgctl.b.conidsts) {
6395 + dwc_otg_pcd_t *pcd;
6397 + /* Wait for switch to device mode. */
6398 + while (!dwc_otg_is_device_mode(core_if)){
6399 + DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
6400 + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
6402 + if (++count > 10000) *(uint32_t*)NULL=0;
6404 + core_if->op_state = B_PERIPHERAL;
6405 + dwc_otg_core_init(core_if);
6406 + dwc_otg_enable_global_interrupts(core_if);
6408 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6409 + if(unlikely(!pcd)) {
6410 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6413 + SPIN_LOCK(&pcd->lock);
6415 + pcd_start(core_if);
6417 + SPIN_UNLOCK(&pcd->lock);
6419 + /* A-Device connector (Host Mode) */
6420 + while (!dwc_otg_is_host_mode(core_if)) {
6421 + DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
6422 + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
6424 + if (++count > 10000) *(uint32_t*)NULL=0;
6426 + core_if->op_state = A_HOST;
6428 + * Initialize the Core for Host mode.
6430 + dwc_otg_core_init(core_if);
6431 + dwc_otg_enable_global_interrupts(core_if);
6432 + hcd_start(core_if);
6438 + * This function handles the Connector ID Status Change Interrupt. It
6439 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
6440 + * is a Device to Host Mode transition or a Host Mode to Device
6443 + * This only occurs when the cable is connected/removed from the PHY
6446 + * @param core_if Programming view of DWC_otg controller.
6448 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
6452 + * Need to disable SOF interrupt immediately. If switching from device
6453 + * to host, the PCD interrupt handler won't handle the interrupt if
6454 + * host mode is already set. The HCD interrupt handler won't get
6455 + * called if the HCD state is HALT. This means that the interrupt does
6456 + * not get handled and Linux complains loudly.
6458 + gintmsk_data_t gintmsk = { .d32 = 0 };
6459 + gintsts_data_t gintsts = { .d32 = 0 };
6461 + gintmsk.b.sofintr = 1;
6462 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
6464 + DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
6465 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
6468 + * Need to schedule a work, as there are possible DELAY function calls
6470 + queue_work(core_if->wq_otg, &core_if->w_conn_id);
6472 + /* Set flag and clear interrupt */
6473 + gintsts.b.conidstschng = 1;
6474 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6480 + * This interrupt indicates that a device is initiating the Session
6481 + * Request Protocol to request the host to turn on bus power so a new
6482 + * session can begin. The handler responds by turning on bus power. If
6483 + * the DWC_otg controller is in low power mode, the handler brings the
6484 + * controller out of low power mode before turning on bus power.
6486 + * @param core_if Programming view of DWC_otg controller.
6488 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
6490 + hprt0_data_t hprt0;
6491 + gintsts_data_t gintsts;
6493 +#ifndef DWC_HOST_ONLY
6494 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
6496 + if (dwc_otg_is_device_mode(core_if)) {
6497 + DWC_PRINT("SRP: Device mode\n");
6499 + DWC_PRINT("SRP: Host mode\n");
6501 + /* Turn on the port power bit. */
6502 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
6503 + hprt0.b.prtpwr = 1;
6504 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
6506 + /* Start the Connection timer. So a message can be displayed
6507 + * if connect does not occur within 10 seconds. */
6508 + hcd_session_start(core_if);
6512 + /* Clear interrupt */
6514 + gintsts.b.sessreqintr = 1;
6515 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6521 +void w_wakeup_detected(struct work_struct *p)
6523 + struct delayed_work *dw = container_of(p, struct delayed_work, work);
6524 + dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
6527 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
6528 + * so that OPT tests pass with all PHYs).
6530 + hprt0_data_t hprt0 = {.d32=0};
6531 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
6532 + DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
6534 + hprt0.b.prtres = 0; /* Resume */
6535 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
6536 + DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
6539 + * This interrupt indicates that the DWC_otg controller has detected a
6540 + * resume or remote wakeup sequence. If the DWC_otg controller is in
6541 + * low power mode, the handler must brings the controller out of low
6542 + * power mode. The controller automatically begins resume
6543 + * signaling. The handler schedules a time to stop resume signaling.
6545 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
6547 + gintsts_data_t gintsts;
6549 + DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
6551 + if (dwc_otg_is_device_mode(core_if)) {
6552 + dctl_data_t dctl = {.d32=0};
6553 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
6554 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
6555 +#ifdef PARTIAL_POWER_DOWN
6556 + if (core_if->hwcfg4.b.power_optimiz) {
6557 + pcgcctl_data_t power = {.d32=0};
6559 + power.d32 = dwc_read_reg32(core_if->pcgcctl);
6560 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
6562 + power.b.stoppclk = 0;
6563 + dwc_write_reg32(core_if->pcgcctl, power.d32);
6565 + power.b.pwrclmp = 0;
6566 + dwc_write_reg32(core_if->pcgcctl, power.d32);
6568 + power.b.rstpdwnmodule = 0;
6569 + dwc_write_reg32(core_if->pcgcctl, power.d32);
6572 + /* Clear the Remote Wakeup Signalling */
6573 + dctl.b.rmtwkupsig = 1;
6574 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
6577 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
6578 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
6582 + pcgcctl_data_t pcgcctl = {.d32=0};
6584 + /* Restart the Phy Clock */
6585 + pcgcctl.b.stoppclk = 1;
6586 + dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
6588 + queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
6591 + /* Clear interrupt */
6593 + gintsts.b.wkupintr = 1;
6594 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6600 + * This interrupt indicates that a device has been disconnected from
6603 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
6605 + gintsts_data_t gintsts;
6607 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
6608 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
6609 + op_state_str(core_if));
6611 +/** @todo Consolidate this if statement. */
6612 +#ifndef DWC_HOST_ONLY
6613 + if (core_if->op_state == B_HOST) {
6614 + dwc_otg_pcd_t *pcd;
6616 + /* If in device mode Disconnect and stop the HCD, then
6617 + * start the PCD. */
6618 + hcd_disconnect(core_if);
6620 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6621 + if(unlikely(!pcd)) {
6622 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6625 + SPIN_LOCK(&pcd->lock);
6627 + pcd_start(core_if);
6629 + SPIN_UNLOCK(&pcd->lock);
6630 + core_if->op_state = B_PERIPHERAL;
6631 + } else if (dwc_otg_is_device_mode(core_if)) {
6632 + gotgctl_data_t gotgctl = { .d32 = 0 };
6633 + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
6634 + if (gotgctl.b.hstsethnpen==1) {
6635 + /* Do nothing, if HNP in process the OTG
6636 + * interrupt "Host Negotiation Detected"
6637 + * interrupt will do the mode switch.
6639 + } else if (gotgctl.b.devhnpen == 0) {
6640 + dwc_otg_pcd_t *pcd;
6642 + /* If in device mode Disconnect and stop the HCD, then
6643 + * start the PCD. */
6644 + hcd_disconnect(core_if);
6646 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6647 + if(unlikely(!pcd)) {
6648 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6651 + SPIN_LOCK(&pcd->lock);
6653 + pcd_start(core_if);
6655 + SPIN_UNLOCK(&pcd->lock);
6657 + core_if->op_state = B_PERIPHERAL;
6659 + DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
6662 + if (core_if->op_state == A_HOST) {
6663 + /* A-Cable still connected but device disconnected. */
6664 + hcd_disconnect(core_if);
6670 + gintsts.b.disconnect = 1;
6671 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6675 + * This interrupt indicates that SUSPEND state has been detected on
6678 + * For HNP the USB Suspend interrupt signals the change from
6679 + * "a_peripheral" to "a_host".
6681 + * When power management is enabled the core will be put in low power
6684 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
6687 + gintsts_data_t gintsts;
6689 + DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
6691 + if (dwc_otg_is_device_mode(core_if)) {
6692 + dwc_otg_pcd_t *pcd;
6694 + /* Check the Device status register to determine if the Suspend
6695 + * state is active. */
6696 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
6697 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
6698 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
6699 + "HWCFG4.power Optimize=%d\n",
6700 + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
6703 +#ifdef PARTIAL_POWER_DOWN
6704 +/** @todo Add a module parameter for power management. */
6705 + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
6706 + pcgcctl_data_t power = {.d32=0};
6707 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
6709 + power.b.pwrclmp = 1;
6710 + dwc_write_reg32(core_if->pcgcctl, power.d32);
6712 + power.b.rstpdwnmodule = 1;
6713 + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
6715 + power.b.stoppclk = 1;
6716 + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
6718 + DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
6721 + /* PCD callback for suspend. */
6722 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6723 + if(unlikely(!pcd)) {
6724 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6727 + SPIN_LOCK(&pcd->lock);
6729 + pcd_suspend(core_if);
6731 + SPIN_UNLOCK(&pcd->lock);
6733 + if (core_if->op_state == A_PERIPHERAL) {
6734 + dwc_otg_pcd_t *pcd;
6736 + DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
6737 + /* Clear the a_peripheral flag, back to a_host. */
6739 + pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6740 + if(unlikely(!pcd)) {
6741 + DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6744 + SPIN_LOCK(&pcd->lock);
6746 + pcd_stop(core_if);
6748 + SPIN_UNLOCK(&pcd->lock);
6750 + hcd_start(core_if);
6751 + core_if->op_state = A_HOST;
6755 + /* Clear interrupt */
6757 + gintsts.b.usbsuspend = 1;
6758 + dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
6765 + * This function returns the Core Interrupt register.
6767 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
6769 + gintsts_data_t gintsts;
6770 + gintmsk_data_t gintmsk;
6771 + gintmsk_data_t gintmsk_common = {.d32=0};
6772 + gintmsk_common.b.wkupintr = 1;
6773 + gintmsk_common.b.sessreqintr = 1;
6774 + gintmsk_common.b.conidstschng = 1;
6775 + gintmsk_common.b.otgintr = 1;
6776 + gintmsk_common.b.modemismatch = 1;
6777 + gintmsk_common.b.disconnect = 1;
6778 + gintmsk_common.b.usbsuspend = 1;
6779 + /** @todo: The port interrupt occurs while in device
6780 + * mode. Added code to CIL to clear the interrupt for now!
6782 + gintmsk_common.b.portintr = 1;
6784 + gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
6785 + gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
6787 + /* if any common interrupts set */
6788 + if (gintsts.d32 & gintmsk_common.d32) {
6789 + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
6790 + gintsts.d32, gintmsk.d32);
6794 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
6799 + * Common interrupt handler.
6801 + * The common interrupts are those that occur in both Host and Device mode.
6802 + * This handler handles the following interrupts:
6803 + * - Mode Mismatch Interrupt
6804 + * - Disconnect Interrupt
6806 + * - Connector ID Status Change Interrupt
6807 + * - Session Request Interrupt.
6808 + * - Resume / Remote Wakeup Detected Interrupt.
6811 +int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
6814 + gintsts_data_t gintsts;
6816 + gintsts.d32 = dwc_otg_read_common_intr(core_if);
6818 + if (gintsts.b.modemismatch) {
6819 + retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
6821 + if (gintsts.b.otgintr) {
6822 + retval |= dwc_otg_handle_otg_intr(core_if);
6824 + if (gintsts.b.conidstschng) {
6825 + retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
6827 + if (gintsts.b.disconnect) {
6828 + retval |= dwc_otg_handle_disconnect_intr(core_if);
6830 + if (gintsts.b.sessreqintr) {
6831 + retval |= dwc_otg_handle_session_req_intr(core_if);
6833 + if (gintsts.b.wkupintr) {
6834 + retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
6836 + if (gintsts.b.usbsuspend) {
6837 + retval |= dwc_otg_handle_usb_suspend_intr(core_if);
6839 + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
6840 + /* The port interrupt occurs while in device mode with HPRT0
6841 + * Port Enable/Disable.
6844 + gintsts.b.portintr = 1;
6845 + dwc_write_reg32(&core_if->core_global_regs->gintsts,
6851 + S3C2410X_CLEAR_EINTPEND();
6856 +++ b/drivers/usb/dwc/otg_driver.c
6858 +/* ==========================================================================
6859 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
6860 + * $Revision: #63 $
6861 + * $Date: 2008/09/24 $
6862 + * $Change: 1101777 $
6864 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6865 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6866 + * otherwise expressly agreed to in writing between Synopsys and you.
6868 + * The Software IS NOT an item of Licensed Software or Licensed Product under
6869 + * any End User Software License Agreement or Agreement for Licensed Product
6870 + * with Synopsys or any supplement thereto. You are permitted to use and
6871 + * redistribute this Software in source and binary forms, with or without
6872 + * modification, provided that redistributions of source code must retain this
6873 + * notice. You may not view, use, disclose, copy or distribute this file or
6874 + * any information contained herein except pursuant to this license grant from
6875 + * Synopsys. If you do not agree with this notice, including the disclaimer
6876 + * below, then you are not authorized to use the Software.
6878 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6879 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6880 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6881 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6882 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6883 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6884 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6885 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6886 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6887 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6889 + * ========================================================================== */
6892 + * The dwc_otg_driver module provides the initialization and cleanup entry
6893 + * points for the DWC_otg driver. This module will be dynamically installed
6894 + * after Linux is booted using the insmod command. When the module is
6895 + * installed, the dwc_otg_driver_init function is called. When the module is
6896 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
6898 + * This module also defines a data structure for the dwc_otg_driver, which is
6899 + * used in conjunction with the standard ARM lm_device structure. These
6900 + * structures allow the OTG driver to comply with the standard Linux driver
6901 + * model in which devices and drivers are registered with a bus driver. This
6902 + * has the benefit that Linux can expose attributes of the driver and device
6903 + * in its special sysfs file system. Users can then read or write files in
6904 + * this file system to perform diagnostics on the driver components or the
6908 +#include <linux/kernel.h>
6909 +#include <linux/module.h>
6910 +#include <linux/moduleparam.h>
6911 +#include <linux/init.h>
6912 +#include <linux/device.h>
6913 +#include <linux/errno.h>
6914 +#include <linux/types.h>
6915 +#include <linux/stat.h> /* permission constants */
6916 +#include <linux/version.h>
6917 +#include <linux/platform_device.h>
6918 +#include <linux/io.h>
6919 +#include <linux/irq.h>
6920 +#include <asm/io.h>
6922 +#include <asm/sizes.h>
6923 +#include <mach/pm.h>
6925 +#include "otg_plat.h"
6926 +#include "otg_attr.h"
6927 +#include "otg_driver.h"
6928 +#include "otg_cil.h"
6929 +#include "otg_pcd.h"
6930 +#include "otg_hcd.h"
6932 +#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
6933 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
6935 +static const char dwc_driver_name[] = "dwc_otg";
6937 +/*-------------------------------------------------------------------------*/
6938 +/* Encapsulate the module parameter settings */
6940 +static dwc_otg_core_params_t dwc_otg_module_params = {
6944 + .dma_desc_enable = -1,
6945 + .dma_burst_size = -1,
6947 + .host_support_fs_ls_low_power = -1,
6948 + .host_ls_low_power_phy_clk = -1,
6949 + .enable_dynamic_fifo = -1,
6950 + .data_fifo_size = -1,
6951 + .dev_rx_fifo_size = -1,
6952 + .dev_nperio_tx_fifo_size = -1,
6953 + .dev_perio_tx_fifo_size = {
6954 + /* dev_perio_tx_fifo_size_1 */
6972 + .host_rx_fifo_size = -1,
6973 + .host_nperio_tx_fifo_size = -1,
6974 + .host_perio_tx_fifo_size = -1,
6975 + .max_transfer_size = -1,
6976 + .max_packet_count = -1,
6977 + .host_channels = -1,
6978 + .dev_endpoints = -1,
6980 + .phy_utmi_width = -1,
6981 + .phy_ulpi_ddr = -1,
6982 + .phy_ulpi_ext_vbus = -1,
6986 + .en_multiple_tx_fifo = -1,
6987 + .dev_tx_fifo_size = {
6988 + /* dev_tx_fifo_size */
7007 + .tx_thr_length = -1,
7008 + .rx_thr_length = -1,
7014 + * Global Debug Level Mask.
7016 +uint32_t g_dbg_lvl = 0; /* OFF */
7019 + * This function is called during module intialization to verify that
7020 + * the module parameters are in a valid state.
7022 +static int check_parameters(dwc_otg_core_if_t *core_if)
7027 +/* Checks if the parameter is outside of its valid range of values */
7028 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
7029 + ((dwc_otg_module_params._param_ < (_low_)) || \
7030 + (dwc_otg_module_params._param_ > (_high_)))
7032 +/* If the parameter has been set by the user, check that the parameter value is
7033 + * within the value range of values. If not, report a module error. */
7034 +#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
7036 + if (dwc_otg_module_params._param_ != -1) { \
7037 + if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
7038 + DWC_ERROR("`%d' invalid for parameter `%s'\n", \
7039 + dwc_otg_module_params._param_, _string_); \
7040 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
7046 + DWC_OTG_PARAM_ERR(opt,0,1,"opt");
7047 + DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
7048 + DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
7049 + DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
7050 + DWC_OTG_PARAM_ERR(speed,0,1,"speed");
7051 + DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
7052 + DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
7053 + DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
7054 + DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
7055 + DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
7056 + DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
7057 + DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
7058 + DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
7059 + DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
7060 + DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
7061 + DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
7062 + DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
7063 + DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
7064 + DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
7065 + DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
7066 + DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
7067 + DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
7068 + DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
7069 + DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
7071 + if (dwc_otg_module_params.dma_burst_size != -1) {
7072 + if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
7073 + DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
7074 + DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
7075 + DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
7076 + DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
7077 + DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
7078 + DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
7079 + DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
7080 + DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
7081 + dwc_otg_module_params.dma_burst_size);
7082 + dwc_otg_module_params.dma_burst_size = 32;
7087 + uint8_t brst_sz = 0;
7088 + while(dwc_otg_module_params.dma_burst_size > 1) {
7090 + dwc_otg_module_params.dma_burst_size >>= 1;
7092 + dwc_otg_module_params.dma_burst_size = brst_sz;
7096 + if (dwc_otg_module_params.phy_utmi_width != -1) {
7097 + if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
7098 + DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
7099 + DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
7100 + dwc_otg_module_params.phy_utmi_width);
7101 + dwc_otg_module_params.phy_utmi_width = 16;
7106 + for (i = 0; i < 15; i++) {
7107 + /** @todo should be like above */
7108 + //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
7109 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
7110 + if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
7111 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
7112 + dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
7113 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
7119 + DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
7121 + for (i = 0; i < 15; i++) {
7122 + /** @todo should be like above */
7123 + //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
7124 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
7125 + if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
7126 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
7127 + dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
7128 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
7134 + DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
7135 + DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
7136 + DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
7138 + DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
7139 + DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
7141 + /* At this point, all module parameters that have been set by the user
7142 + * are valid, and those that have not are left unset. Now set their
7143 + * default values and/or check the parameters against the hardware
7144 + * configurations of the OTG core. */
7146 +/* This sets the parameter to the default value if it has not been set by the
7148 +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
7150 + int changed = 1; \
7151 + if (dwc_otg_module_params._param_ == -1) { \
7153 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
7158 +/* This checks the macro agains the hardware configuration to see if it is
7159 + * valid. It is possible that the default value could be invalid. In this
7160 + * case, it will report a module error if the user touched the parameter.
7161 + * Otherwise it will adjust the value without any error. */
7162 +#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
7164 + int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
7166 + if (!(_is_valid_)) { \
7168 + DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
7171 + dwc_otg_module_params._param_ = (_set_valid_); \
7177 + retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
7181 + switch (dwc_otg_module_params.otg_cap) {
7182 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
7183 + if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
7186 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
7187 + if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
7188 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
7189 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
7190 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
7194 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
7195 + /* always valid */
7200 + (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
7201 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
7202 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
7203 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
7204 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
7205 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
7207 + retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
7208 + ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
7211 + retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
7212 + ((dwc_otg_module_params.dma_desc_enable == 1) &&
7213 + ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
7216 + retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
7218 + DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
7220 + retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
7221 + "host_support_fs_ls_low_power",
7224 + retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
7225 + "enable_dynamic_fifo",
7226 + ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
7227 + (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
7229 + retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
7231 + (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
7232 + core_if->hwcfg3.b.dfifo_depth);
7234 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
7235 + "dev_rx_fifo_size",
7236 + (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
7237 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
7239 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
7240 + "dev_nperio_tx_fifo_size",
7241 + (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
7242 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
7244 + retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
7245 + "host_rx_fifo_size",
7246 + (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
7247 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
7249 + retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
7250 + "host_nperio_tx_fifo_size",
7251 + (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
7252 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
7254 + retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
7255 + "host_perio_tx_fifo_size",
7256 + (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
7257 + ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
7259 + retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
7260 + "max_transfer_size",
7261 + (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
7262 + ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
7264 + retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
7265 + "max_packet_count",
7266 + (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
7267 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
7269 + retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
7271 + (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
7272 + (core_if->hwcfg2.b.num_host_chan + 1));
7274 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
7276 + (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
7277 + core_if->hwcfg2.b.num_dev_ep);
7280 + * Define the following to disable the FS PHY Hardware checking. This is for
7281 + * internal testing only.
7283 + * #define NO_FS_PHY_HW_CHECKS
7286 +#ifdef NO_FS_PHY_HW_CHECKS
7287 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
7288 + "phy_type", 1, 0);
7290 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
7294 + if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
7295 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
7296 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
7299 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
7300 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
7301 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
7304 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
7305 + (core_if->hwcfg2.b.fs_phy_type == 1)) {
7311 + int set = DWC_PHY_TYPE_PARAM_FS;
7312 + if (core_if->hwcfg2.b.hs_phy_type) {
7313 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
7314 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
7315 + set = DWC_PHY_TYPE_PARAM_UTMI;
7318 + set = DWC_PHY_TYPE_PARAM_ULPI;
7325 + retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
7326 + (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
7327 + dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
7329 + retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
7330 + "host_ls_low_power_phy_clk",
7331 + ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
7332 + ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
7334 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
7335 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
7336 + DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
7337 + DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
7338 + DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
7340 +#ifdef NO_FS_PHY_HW_CHECKS
7341 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
7343 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
7345 + (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
7349 + for (i = 0; i < 15; i++) {
7353 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
7355 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
7357 + if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
7359 + DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
7362 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
7367 + retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
7368 + ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
7371 + for (i = 0; i < 15; i++) {
7375 + if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
7377 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
7379 + if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
7381 + DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
7384 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
7389 + retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
7390 + ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
7393 + DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
7394 + DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
7396 + retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
7397 + ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
7400 + retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
7401 + ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
7407 + * This function is the top level interrupt handler for the Common
7408 + * (Device and host modes) interrupts.
7410 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
7412 + dwc_otg_device_t *otg_dev = dev;
7413 + int32_t retval = IRQ_NONE;
7415 + retval = dwc_otg_handle_common_intr(otg_dev->core_if);
7416 + return IRQ_RETVAL(retval);
7420 + * This function is called when a lm_device is unregistered with the
7421 + * dwc_otg_driver. This happens, for example, when the rmmod command is
7422 + * executed. The device may or may not be electrically present. If it is
7423 + * present, the driver stops device processing. Any resources used on behalf
7424 + * of this device are freed.
7426 + * @param[in] lmdev
7428 +static int dwc_otg_driver_cleanup(struct platform_device *pdev)
7430 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
7431 + DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
7434 + /* Memory allocation for the dwc_otg_device failed. */
7435 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
7442 + if (otg_dev->common_irq_installed) {
7443 + free_irq(otg_dev->irq, otg_dev);
7446 +#ifndef DWC_DEVICE_ONLY
7447 + if (otg_dev->hcd) {
7448 + dwc_otg_hcd_remove(pdev);
7450 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
7455 +#ifndef DWC_HOST_ONLY
7456 + if (otg_dev->pcd) {
7457 + dwc_otg_pcd_remove(pdev);
7460 + if (otg_dev->core_if) {
7461 + dwc_otg_cil_remove(otg_dev->core_if);
7465 + * Remove the device attributes
7467 + dwc_otg_attr_remove(pdev);
7470 + * Return the memory.
7472 + if (otg_dev->base) {
7473 + iounmap(otg_dev->base);
7478 + * Clear the drvdata pointer.
7480 + platform_set_drvdata(pdev, 0);
7486 + * This function is called when an lm_device is bound to a
7487 + * dwc_otg_driver. It creates the driver components required to
7488 + * control the device (CIL, HCD, and PCD) and it initializes the
7489 + * device. The driver components are stored in a dwc_otg_device
7490 + * structure. A reference to the dwc_otg_device is saved in the
7491 + * lm_device. This allows the driver to access the dwc_otg_device
7492 + * structure on subsequent calls to driver methods for this device.
7494 + * @param[in] lmdev lm_device definition
7496 +static int __devinit dwc_otg_driver_probe(struct platform_device *pdev)
7498 + struct device *dev = &pdev->dev;
7501 + dwc_otg_device_t *dwc_otg_device;
7502 + struct resource *res;
7504 + dev_dbg(dev, "dwc_otg_driver_probe(%p)\n", pdev);
7506 + dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
7508 + if (!dwc_otg_device) {
7509 + dev_err(dev, "kmalloc of dwc_otg_device failed\n");
7514 + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
7515 + dwc_otg_device->reg_offset = 0xFFFFFFFF;
7517 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7519 + dev_err(dev, "Found OTG with no register addr.\n");
7523 + dwc_otg_device->rsrc_start = res->start;
7524 + dwc_otg_device->rsrc_len = res->end - res->start + 1;
7526 + dwc_otg_device->base = ioremap(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
7528 + if (!dwc_otg_device->base) {
7529 + dev_err(dev, "ioremap() failed\n");
7533 + dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
7536 + * Attempt to ensure this device is really a DWC_otg Controller.
7537 + * Read and verify the SNPSID register contents. The value should be
7538 + * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
7540 + snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
7542 + if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
7543 + dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
7548 + DWC_PRINT("Core Release: %x.%x%x%x\n",
7549 + (snpsid >> 12 & 0xF),
7550 + (snpsid >> 8 & 0xF),
7551 + (snpsid >> 4 & 0xF),
7555 + * Initialize driver data to point to the global DWC_otg
7556 + * Device structure.
7558 + platform_set_drvdata(pdev, dwc_otg_device);
7560 + dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
7562 + dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base,
7563 + &dwc_otg_module_params);
7565 + dwc_otg_device->core_if->snpsid = snpsid;
7567 + if (!dwc_otg_device->core_if) {
7568 + dev_err(dev, "CIL initialization failed!\n");
7574 + * Validate parameter values.
7576 + if (check_parameters(dwc_otg_device->core_if)) {
7582 + * Create Device Attributes in sysfs
7584 + dwc_otg_attr_create(pdev);
7587 + * Disable the global interrupt until all the interrupt
7588 + * handlers are installed.
7590 + dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
7593 + * Install the interrupt handler for the common interrupts before
7594 + * enabling common interrupts in core_init below.
7596 + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
7598 + dev_err(dev, "Fount OTG with to IRQ.\n");
7602 + dwc_otg_device->irq = res->start;
7604 + retval = request_irq(res->start, dwc_otg_common_irq,
7605 + IRQF_SHARED, "dwc_otg", dwc_otg_device);
7607 + DWC_ERROR("request of irq%d failed\n", res->start);
7611 + dwc_otg_device->common_irq_installed = 1;
7615 + * Initialize the DWC_otg core.
7617 + dwc_otg_core_init(dwc_otg_device->core_if);
7619 +#ifndef DWC_HOST_ONLY
7621 + * Initialize the PCD
7623 + retval = dwc_otg_pcd_init(pdev);
7624 + if (retval != 0) {
7625 + DWC_ERROR("dwc_otg_pcd_init failed\n");
7626 + dwc_otg_device->pcd = NULL;
7630 +#ifndef DWC_DEVICE_ONLY
7632 + * Initialize the HCD
7634 + retval = dwc_otg_hcd_init(pdev);
7635 + if (retval != 0) {
7636 + DWC_ERROR("dwc_otg_hcd_init failed\n");
7637 + dwc_otg_device->hcd = NULL;
7643 + * Enable the global interrupt after all the interrupt
7644 + * handlers are installed.
7646 + dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
7651 + dwc_otg_driver_cleanup(pdev);
7655 +static int __devexit dwc_otg_driver_remove(struct platform_device *pdev)
7657 + return dwc_otg_driver_cleanup(pdev);
7660 +static struct platform_driver dwc_otg_platform_driver = {
7661 + .driver.name = "dwc_otg",
7662 + .probe = dwc_otg_driver_probe,
7663 + .remove = __devexit_p(dwc_otg_driver_remove),
7666 +static int __init dwc_otg_init_module(void)
7668 + return platform_driver_register(&dwc_otg_platform_driver);
7671 +static void __exit dwc_otg_cleanup_module(void)
7673 + platform_driver_unregister(&dwc_otg_platform_driver);
7676 +module_init(dwc_otg_init_module);
7677 +module_exit(dwc_otg_cleanup_module);
7680 + * This function is called when the driver is removed from the kernel
7681 + * with the rmmod command. The driver unregisters itself with its bus
7686 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
7687 +MODULE_AUTHOR("Synopsys Inc.");
7688 +MODULE_LICENSE("GPL");
7690 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
7691 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
7692 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
7693 +MODULE_PARM_DESC(opt, "OPT Mode");
7694 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
7695 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
7697 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
7698 +MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
7700 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
7701 +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
7702 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
7703 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
7704 +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
7705 +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
7706 +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
7707 +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
7708 +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
7709 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
7710 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
7711 +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
7712 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
7713 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
7714 +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
7715 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
7716 +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
7717 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
7718 +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
7719 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
7720 +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
7721 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
7722 +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
7723 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
7724 +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
7725 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
7726 +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
7727 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
7728 +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
7729 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
7730 +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
7731 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
7732 +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
7733 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
7734 +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
7735 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
7736 +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
7737 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
7738 +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
7739 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
7740 +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
7741 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
7742 +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
7743 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
7744 +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
7745 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
7746 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
7747 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
7748 +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
7749 +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
7750 +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
7751 +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
7752 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
7753 +/** @todo Set the max to 512K, modify checks */
7754 +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
7755 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
7756 +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
7757 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
7758 +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
7759 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
7760 +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
7761 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
7762 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
7763 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
7764 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
7765 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
7766 +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
7767 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
7768 +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
7769 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
7770 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
7771 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
7772 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
7773 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
7774 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
7775 +module_param_named(debug, g_dbg_lvl, int, 0444);
7776 +MODULE_PARM_DESC(debug, "");
7778 +module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
7779 +MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
7780 +module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
7781 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
7782 +module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
7783 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
7784 +module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
7785 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
7786 +module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
7787 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
7788 +module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
7789 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
7790 +module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
7791 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
7792 +module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
7793 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
7794 +module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
7795 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
7796 +module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
7797 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
7798 +module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
7799 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
7800 +module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
7801 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
7802 +module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
7803 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
7804 +module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
7805 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
7806 +module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
7807 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
7808 +module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
7809 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
7811 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
7812 +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
7813 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
7814 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
7815 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
7816 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
7818 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
7819 +MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
7821 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
7822 +MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
7824 +++ b/drivers/usb/dwc/otg_driver.h
7826 +/* ==========================================================================
7827 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
7828 + * $Revision: #12 $
7829 + * $Date: 2008/07/15 $
7830 + * $Change: 1064918 $
7832 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7833 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7834 + * otherwise expressly agreed to in writing between Synopsys and you.
7836 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7837 + * any End User Software License Agreement or Agreement for Licensed Product
7838 + * with Synopsys or any supplement thereto. You are permitted to use and
7839 + * redistribute this Software in source and binary forms, with or without
7840 + * modification, provided that redistributions of source code must retain this
7841 + * notice. You may not view, use, disclose, copy or distribute this file or
7842 + * any information contained herein except pursuant to this license grant from
7843 + * Synopsys. If you do not agree with this notice, including the disclaimer
7844 + * below, then you are not authorized to use the Software.
7846 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7847 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7848 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7849 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7850 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7851 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7852 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7853 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7854 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7855 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7857 + * ========================================================================== */
7859 +#ifndef __DWC_OTG_DRIVER_H__
7860 +#define __DWC_OTG_DRIVER_H__
7863 + * This file contains the interface to the Linux driver.
7865 +#include "otg_cil.h"
7867 +/* Type declarations */
7868 +struct dwc_otg_pcd;
7869 +struct dwc_otg_hcd;
7872 + * This structure is a wrapper that encapsulates the driver components used to
7873 + * manage a single DWC_otg controller.
7875 +typedef struct dwc_otg_device {
7877 + dwc_otg_core_if_t *core_if;
7878 + uint32_t reg_offset;
7879 + struct dwc_otg_pcd *pcd;
7880 + struct dwc_otg_hcd *hcd;
7881 + uint8_t common_irq_installed;
7883 + uint32_t rsrc_start;
7884 + uint32_t rsrc_len;
7885 +} dwc_otg_device_t;
7889 +++ b/drivers/usb/dwc/otg_hcd.c
7891 +/* ==========================================================================
7892 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7893 + * $Revision: #75 $
7894 + * $Date: 2008/07/15 $
7895 + * $Change: 1064940 $
7897 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7898 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7899 + * otherwise expressly agreed to in writing between Synopsys and you.
7901 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7902 + * any End User Software License Agreement or Agreement for Licensed Product
7903 + * with Synopsys or any supplement thereto. You are permitted to use and
7904 + * redistribute this Software in source and binary forms, with or without
7905 + * modification, provided that redistributions of source code must retain this
7906 + * notice. You may not view, use, disclose, copy or distribute this file or
7907 + * any information contained herein except pursuant to this license grant from
7908 + * Synopsys. If you do not agree with this notice, including the disclaimer
7909 + * below, then you are not authorized to use the Software.
7911 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7912 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7913 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7914 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7915 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7916 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7917 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7918 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7919 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7920 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7922 + * ========================================================================== */
7923 +#ifndef DWC_DEVICE_ONLY
7928 + * This file contains the implementation of the HCD. In Linux, the HCD
7929 + * implements the hc_driver API.
7931 +#include <linux/kernel.h>
7932 +#include <linux/module.h>
7933 +#include <linux/moduleparam.h>
7934 +#include <linux/init.h>
7935 +#include <linux/device.h>
7936 +#include <linux/platform_device.h>
7937 +#include <linux/errno.h>
7938 +#include <linux/list.h>
7939 +#include <linux/interrupt.h>
7940 +#include <linux/string.h>
7941 +#include <linux/dma-mapping.h>
7942 +#include <linux/version.h>
7944 +#include <mach/irqs.h>
7946 +#include "otg_driver.h"
7947 +#include "otg_hcd.h"
7948 +#include "otg_regs.h"
7950 +static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
7952 +static const struct hc_driver dwc_otg_hc_driver = {
7954 + .description = dwc_otg_hcd_name,
7955 + .product_desc = "DWC OTG Controller",
7956 + .hcd_priv_size = sizeof(dwc_otg_hcd_t),
7957 + .irq = dwc_otg_hcd_irq,
7958 + .flags = HCD_MEMORY | HCD_USB2,
7959 + .start = dwc_otg_hcd_start,
7960 + .stop = dwc_otg_hcd_stop,
7961 + .urb_enqueue = dwc_otg_hcd_urb_enqueue,
7962 + .urb_dequeue = dwc_otg_hcd_urb_dequeue,
7963 + .endpoint_disable = dwc_otg_hcd_endpoint_disable,
7964 + .get_frame_number = dwc_otg_hcd_get_frame_number,
7965 + .hub_status_data = dwc_otg_hcd_hub_status_data,
7966 + .hub_control = dwc_otg_hcd_hub_control,
7970 + * Work queue function for starting the HCD when A-Cable is connected.
7971 + * The dwc_otg_hcd_start() must be called in a process context.
7973 +static void hcd_start_func(struct work_struct *_work)
7975 + struct delayed_work *dw = container_of(_work, struct delayed_work, work);
7976 + struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work);
7977 + struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv);
7978 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
7980 + dwc_otg_hcd_start(usb_hcd);
7985 + * HCD Callback function for starting the HCD when A-Cable is
7988 + * @param p void pointer to the <code>struct usb_hcd</code>
7990 +static int32_t dwc_otg_hcd_start_cb(void *p)
7992 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
7993 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7994 + hprt0_data_t hprt0;
7996 + if (core_if->op_state == B_HOST) {
7998 + * Reset the port. During a HNP mode switch the reset
7999 + * needs to occur within 1ms and have a duration of at
8002 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
8003 + hprt0.b.prtrst = 1;
8004 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8005 + ((struct usb_hcd *)p)->self.is_b_host = 1;
8007 + ((struct usb_hcd *)p)->self.is_b_host = 0;
8010 + /* Need to start the HCD in a non-interrupt context. */
8011 +// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
8012 + INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
8013 +// schedule_work(&dwc_otg_hcd->start_work);
8014 + queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000);
8020 + * HCD Callback function for stopping the HCD.
8022 + * @param p void pointer to the <code>struct usb_hcd</code>
8024 +static int32_t dwc_otg_hcd_stop_cb(void *p)
8026 + struct usb_hcd *usb_hcd = (struct usb_hcd *)p;
8027 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8028 + dwc_otg_hcd_stop(usb_hcd);
8032 +static void del_xfer_timers(dwc_otg_hcd_t *hcd)
8036 + int num_channels = hcd->core_if->core_params->host_channels;
8037 + for (i = 0; i < num_channels; i++) {
8038 + del_timer(&hcd->core_if->hc_xfer_timer[i]);
8043 +static void del_timers(dwc_otg_hcd_t *hcd)
8045 + del_xfer_timers(hcd);
8046 + del_timer(&hcd->conn_timer);
8050 + * Processes all the URBs in a single list of QHs. Completes them with
8051 + * -ETIMEDOUT and frees the QTD.
8053 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
8055 + struct list_head *qh_item;
8057 + struct list_head *qtd_item;
8058 + dwc_otg_qtd_t *qtd;
8060 + list_for_each(qh_item, qh_list) {
8061 + qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
8062 + for (qtd_item = qh->qtd_list.next;
8063 + qtd_item != &qh->qtd_list;
8064 + qtd_item = qh->qtd_list.next) {
8065 + qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
8066 + if (qtd->urb != NULL) {
8067 + dwc_otg_hcd_complete_urb(hcd, qtd->urb,
8070 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
8076 + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
8077 + * and periodic schedules. The QTD associated with each URB is removed from
8078 + * the schedule and freed. This function may be called when a disconnect is
8079 + * detected or when the HCD is being stopped.
8081 +static void kill_all_urbs(dwc_otg_hcd_t *hcd)
8083 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
8084 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
8085 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
8086 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
8087 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
8088 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
8092 + * HCD Callback function for disconnect of the HCD.
8094 + * @param p void pointer to the <code>struct usb_hcd</code>
8096 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
8098 + gintsts_data_t intr;
8099 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
8101 + //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8104 + * Set status flags for the hub driver.
8106 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
8107 + dwc_otg_hcd->flags.b.port_connect_status = 0;
8110 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
8111 + * interrupt mask and status bits and disabling subsequent host
8112 + * channel interrupts.
8115 + intr.b.nptxfempty = 1;
8116 + intr.b.ptxfempty = 1;
8117 + intr.b.hcintr = 1;
8118 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
8119 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
8121 + del_timers(dwc_otg_hcd);
8124 + * Turn off the vbus power only if the core has transitioned to device
8125 + * mode. If still in host mode, need to keep power on to detect a
8128 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
8129 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
8130 + hprt0_data_t hprt0 = { .d32=0 };
8131 + DWC_PRINT("Disconnect: PortPower off\n");
8132 + hprt0.b.prtpwr = 0;
8133 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
8136 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
8139 + /* Respond with an error status to all URBs in the schedule. */
8140 + kill_all_urbs(dwc_otg_hcd);
8142 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
8143 + /* Clean up any host channels that were in use. */
8146 + dwc_hc_t *channel;
8147 + dwc_otg_hc_regs_t *hc_regs;
8148 + hcchar_data_t hcchar;
8150 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
8152 + if (!dwc_otg_hcd->core_if->dma_enable) {
8153 + /* Flush out any channel requests in slave mode. */
8154 + for (i = 0; i < num_channels; i++) {
8155 + channel = dwc_otg_hcd->hc_ptr_array[i];
8156 + if (list_empty(&channel->hc_list_entry)) {
8157 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
8158 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8159 + if (hcchar.b.chen) {
8160 + hcchar.b.chen = 0;
8161 + hcchar.b.chdis = 1;
8162 + hcchar.b.epdir = 0;
8163 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8169 + for (i = 0; i < num_channels; i++) {
8170 + channel = dwc_otg_hcd->hc_ptr_array[i];
8171 + if (list_empty(&channel->hc_list_entry)) {
8172 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
8173 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8174 + if (hcchar.b.chen) {
8175 + /* Halt the channel. */
8176 + hcchar.b.chdis = 1;
8177 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8180 + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
8181 + list_add_tail(&channel->hc_list_entry,
8182 + &dwc_otg_hcd->free_hc_list);
8187 + /* A disconnect will end the session so the B-Device is no
8188 + * longer a B-host. */
8189 + ((struct usb_hcd *)p)->self.is_b_host = 0;
8194 + * Connection timeout function. An OTG host is required to display a
8195 + * message if the device does not connect within 10 seconds.
8197 +void dwc_otg_hcd_connect_timeout(unsigned long ptr)
8199 + DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr);
8200 + DWC_PRINT("Connect Timeout\n");
8201 + DWC_ERROR("Device Not Connected/Responding\n");
8205 + * Start the connection timer. An OTG host is required to display a
8206 + * message if the device does not connect within 10 seconds. The
8207 + * timer is deleted if a port connect interrupt occurs before the
8210 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
8212 + init_timer(&hcd->conn_timer);
8213 + hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
8214 + hcd->conn_timer.data = 0;
8215 + hcd->conn_timer.expires = jiffies + (HZ * 10);
8216 + add_timer(&hcd->conn_timer);
8220 + * HCD Callback function for disconnect of the HCD.
8222 + * @param p void pointer to the <code>struct usb_hcd</code>
8224 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
8226 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
8227 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8228 + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
8233 + * HCD Callback structure for handling mode switching.
8235 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
8236 + .start = dwc_otg_hcd_start_cb,
8237 + .stop = dwc_otg_hcd_stop_cb,
8238 + .disconnect = dwc_otg_hcd_disconnect_cb,
8239 + .session_start = dwc_otg_hcd_session_start_cb,
8244 + * Reset tasklet function
8246 +static void reset_tasklet_func(unsigned long data)
8248 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data;
8249 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
8250 + hprt0_data_t hprt0;
8252 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
8254 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
8255 + hprt0.b.prtrst = 1;
8256 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8259 + hprt0.b.prtrst = 0;
8260 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8261 + dwc_otg_hcd->flags.b.port_reset_change = 1;
8264 +static struct tasklet_struct reset_tasklet = {
8267 + .count = ATOMIC_INIT(0),
8268 + .func = reset_tasklet_func,
8273 + * Initializes the HCD. This function allocates memory for and initializes the
8274 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
8275 + * USB bus with the core and calls the hc_driver->start() function. It returns
8276 + * a negative error on failure.
8278 +int dwc_otg_hcd_init(struct platform_device *pdev)
8280 + struct usb_hcd *hcd = NULL;
8281 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
8282 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8286 + dwc_hc_t *channel;
8290 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
8292 + /* Set device flags indicating whether the HCD supports DMA. */
8293 + if (otg_dev->core_if->dma_enable) {
8294 + DWC_PRINT("Using DMA mode\n");
8296 + if (otg_dev->core_if->dma_desc_enable) {
8297 + DWC_PRINT("Device using Descriptor DMA mode\n");
8299 + DWC_PRINT("Device using Buffer DMA mode\n");
8303 + * Allocate memory for the base HCD plus the DWC OTG HCD.
8304 + * Initialize the base HCD.
8307 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &pdev->dev, "gadget");
8313 + hcd->regs = otg_dev->base;
8314 + hcd->self.otg_port = 1;
8316 + /* Initialize the DWC OTG HCD. */
8317 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8318 + dwc_otg_hcd->core_if = otg_dev->core_if;
8319 + otg_dev->hcd = dwc_otg_hcd;
8322 + spin_lock_init(&dwc_otg_hcd->lock);
8324 + /* Register the HCD CIL Callbacks */
8325 + dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
8326 + &hcd_cil_callbacks, hcd);
8328 + /* Initialize the non-periodic schedule. */
8329 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
8330 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
8332 + /* Initialize the periodic schedule. */
8333 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
8334 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
8335 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
8336 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
8339 + * Create a host channel descriptor for each host channel implemented
8340 + * in the controller. Initialize the channel descriptor array.
8342 + INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
8343 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
8344 + memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array));
8345 + for (i = 0; i < num_channels; i++) {
8346 + channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
8347 + if (channel == NULL) {
8349 + DWC_ERROR("%s: host channel allocation failed\n", __func__);
8352 + memset(channel, 0, sizeof(dwc_hc_t));
8353 + channel->hc_num = i;
8354 + dwc_otg_hcd->hc_ptr_array[i] = channel;
8356 + init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
8358 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
8361 + /* Initialize the Connection timeout timer. */
8362 + init_timer(&dwc_otg_hcd->conn_timer);
8364 + /* Initialize reset tasklet. */
8365 + reset_tasklet.data = (unsigned long) dwc_otg_hcd;
8366 + dwc_otg_hcd->reset_tasklet = &reset_tasklet;
8369 + * Finish generic HCD initialization and start the HCD. This function
8370 + * allocates the DMA buffer pool, registers the USB bus, requests the
8371 + * IRQ line, and calls dwc_otg_hcd_start method.
8373 + retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
8379 + * Allocate space for storing data on status transactions. Normally no
8380 + * data is sent, but this space acts as a bit bucket. This must be
8381 + * done after usb_add_hcd since that function allocates the DMA buffer
8384 + if (otg_dev->core_if->dma_enable) {
8385 + dwc_otg_hcd->status_buf =
8386 + dma_alloc_coherent(&pdev->dev,
8387 + DWC_OTG_HCD_STATUS_BUF_SIZE,
8388 + &dwc_otg_hcd->status_buf_dma,
8389 + GFP_KERNEL | GFP_DMA);
8391 + dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
8394 + if (!dwc_otg_hcd->status_buf) {
8396 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
8400 + dwc_otg_hcd->otg_dev = otg_dev;
8402 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, usbbus=%d\n",
8403 + hcd->self.busnum);
8406 + /* Error conditions */
8408 + usb_remove_hcd(hcd);
8410 + dwc_otg_hcd_free(hcd);
8417 + * Removes the HCD.
8418 + * Frees memory and resources associated with the HCD and deregisters the bus.
8420 +void dwc_otg_hcd_remove(struct platform_device *pdev)
8422 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8423 + dwc_otg_hcd_t *dwc_otg_hcd;
8424 + struct usb_hcd *hcd;
8426 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
8429 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
8433 + dwc_otg_hcd = otg_dev->hcd;
8435 + if (!dwc_otg_hcd) {
8436 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
8440 + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
8443 + DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__);
8447 + /* Turn off all interrupts */
8448 + dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
8449 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
8451 + usb_remove_hcd(hcd);
8452 + dwc_otg_hcd_free(hcd);
8456 +/* =========================================================================
8457 + * Linux HC Driver Functions
8458 + * ========================================================================= */
8461 + * Initializes dynamic portions of the DWC_otg HCD state.
8463 +static void hcd_reinit(dwc_otg_hcd_t *hcd)
8465 + struct list_head *item;
8468 + dwc_hc_t *channel;
8470 + hcd->flags.d32 = 0;
8472 + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
8473 + hcd->non_periodic_channels = 0;
8474 + hcd->periodic_channels = 0;
8477 + * Put all channels in the free channel list and clean up channel
8480 + item = hcd->free_hc_list.next;
8481 + while (item != &hcd->free_hc_list) {
8483 + item = hcd->free_hc_list.next;
8485 + num_channels = hcd->core_if->core_params->host_channels;
8486 + for (i = 0; i < num_channels; i++) {
8487 + channel = hcd->hc_ptr_array[i];
8488 + list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list);
8489 + dwc_otg_hc_cleanup(hcd->core_if, channel);
8492 + /* Initialize the DWC core for host mode operation. */
8493 + dwc_otg_core_host_init(hcd->core_if);
8496 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
8497 + * mode operation. Activates the root port. Returns 0 on success and a negative
8498 + * error code on failure. */
8499 +int dwc_otg_hcd_start(struct usb_hcd *hcd)
8501 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8502 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
8503 + struct usb_bus *bus;
8506 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
8508 + bus = hcd_to_bus(hcd);
8510 + /* Initialize the bus state. If the core is in Device Mode
8511 + * HALT the USB bus and return. */
8512 + if (dwc_otg_is_device_mode(core_if)) {
8513 + hcd->state = HC_STATE_RUNNING;
8516 + hcd->state = HC_STATE_RUNNING;
8518 + /* Initialize and connect root hub if one is not already attached */
8519 + if (bus->root_hub) {
8520 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
8521 + /* Inform the HUB driver to resume. */
8522 + usb_hcd_resume_root_hub(hcd);
8525 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n");
8528 + hcd_reinit(dwc_otg_hcd);
8533 +static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
8535 + struct list_head *item;
8538 + if (!qh_list->next) {
8539 + /* The list hasn't been initialized yet. */
8543 + /* Ensure there are no QTDs or URBs left. */
8544 + kill_urbs_in_qh_list(hcd, qh_list);
8546 + for (item = qh_list->next; item != qh_list; item = qh_list->next) {
8547 + qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8548 + dwc_otg_hcd_qh_remove_and_free(hcd, qh);
8553 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
8556 +void dwc_otg_hcd_stop(struct usb_hcd *hcd)
8558 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8559 + hprt0_data_t hprt0 = { .d32=0 };
8561 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
8563 + /* Turn off all host-specific interrupts. */
8564 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
8567 + * The root hub should be disconnected before this function is called.
8568 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
8569 + * and the QH lists (via ..._hcd_endpoint_disable).
8572 + /* Turn off the vbus power */
8573 + DWC_PRINT("PortPower off\n");
8574 + hprt0.b.prtpwr = 0;
8575 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
8578 +/** Returns the current frame number. */
8579 +int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd)
8581 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8582 + hfnum_data_t hfnum;
8584 + hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
8585 + host_if->host_global_regs->hfnum);
8588 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
8590 + return hfnum.b.frnum;
8594 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
8595 + * in the struct usb_hcd field.
8597 +void dwc_otg_hcd_free(struct usb_hcd *hcd)
8599 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8602 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
8604 + del_timers(dwc_otg_hcd);
8606 + /* Free memory for QH/QTD lists */
8607 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
8608 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
8609 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
8610 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
8611 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
8612 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
8614 + /* Free memory for the host channels. */
8615 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
8616 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
8618 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
8623 + if (dwc_otg_hcd->core_if->dma_enable) {
8624 + if (dwc_otg_hcd->status_buf_dma) {
8625 + dma_free_coherent(hcd->self.controller,
8626 + DWC_OTG_HCD_STATUS_BUF_SIZE,
8627 + dwc_otg_hcd->status_buf,
8628 + dwc_otg_hcd->status_buf_dma);
8630 + } else if (dwc_otg_hcd->status_buf != NULL) {
8631 + kfree(dwc_otg_hcd->status_buf);
8636 +static void dump_urb_info(struct urb *urb, char* fn_name)
8638 + DWC_PRINT("%s, urb %p\n", fn_name, urb);
8639 + DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe));
8640 + DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
8641 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
8642 + DWC_PRINT(" Endpoint type: %s\n",
8644 + switch (usb_pipetype(urb->pipe)) {
8645 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
8646 + case PIPE_BULK: pipetype = "BULK"; break;
8647 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
8648 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
8649 + default: pipetype = "UNKNOWN"; break;
8651 + DWC_PRINT(" Speed: %s\n",
8653 + switch (urb->dev->speed) {
8654 + case USB_SPEED_HIGH: speed = "HIGH"; break;
8655 + case USB_SPEED_FULL: speed = "FULL"; break;
8656 + case USB_SPEED_LOW: speed = "LOW"; break;
8657 + default: speed = "UNKNOWN"; break;
8659 + DWC_PRINT(" Max packet size: %d\n",
8660 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
8661 + DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length);
8662 + DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
8663 + urb->transfer_buffer, (void *)urb->transfer_dma);
8664 + DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
8665 + urb->setup_packet, (void *)urb->setup_dma);
8666 + DWC_PRINT(" Interval: %d\n", urb->interval);
8667 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
8669 + for (i = 0; i < urb->number_of_packets; i++) {
8670 + DWC_PRINT(" ISO Desc %d:\n", i);
8671 + DWC_PRINT(" offset: %d, length %d\n",
8672 + urb->iso_frame_desc[i].offset,
8673 + urb->iso_frame_desc[i].length);
8678 +static void dump_channel_info(dwc_otg_hcd_t *hcd,
8681 + if (qh->channel != NULL) {
8682 + dwc_hc_t *hc = qh->channel;
8683 + struct list_head *item;
8684 + dwc_otg_qh_t *qh_item;
8685 + int num_channels = hcd->core_if->core_params->host_channels;
8688 + dwc_otg_hc_regs_t *hc_regs;
8689 + hcchar_data_t hcchar;
8690 + hcsplt_data_t hcsplt;
8691 + hctsiz_data_t hctsiz;
8694 + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
8695 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8696 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
8697 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
8698 + hcdma = dwc_read_reg32(&hc_regs->hcdma);
8700 + DWC_PRINT(" Assigned to channel %p:\n", hc);
8701 + DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
8702 + DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
8703 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
8704 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
8705 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
8706 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
8707 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
8708 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
8709 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
8710 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
8711 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
8712 + DWC_PRINT(" qh: %p\n", hc->qh);
8713 + DWC_PRINT(" NP inactive sched:\n");
8714 + list_for_each(item, &hcd->non_periodic_sched_inactive) {
8715 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8716 + DWC_PRINT(" %p\n", qh_item);
8718 + DWC_PRINT(" NP active sched:\n");
8719 + list_for_each(item, &hcd->non_periodic_sched_active) {
8720 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8721 + DWC_PRINT(" %p\n", qh_item);
8723 + DWC_PRINT(" Channels: \n");
8724 + for (i = 0; i < num_channels; i++) {
8725 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
8726 + DWC_PRINT(" %2d: %p\n", i, hc);
8733 +//OTG host require the DMA addr is DWORD-aligned,
8734 +//patch it if the buffer is not DWORD-aligned
8736 +void hcd_check_and_patch_dma_addr(struct urb *urb){
8738 + if((!urb->transfer_buffer)||!urb->transfer_dma||urb->transfer_dma==0xffffffff)
8741 + if(((u32)urb->transfer_buffer)& 0x3){
8745 + "transfer_buffer=%.8x, "
8746 + "transfer_dma=%.8x, "
8747 + "transfer_buffer_length=%d, "
8748 + "actual_length=%d(%x), "
8750 + ((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_OUT)?"OUT":"IN",
8752 + urb->transfer_buffer,
8753 + urb->transfer_dma,
8754 + urb->transfer_buffer_length,
8755 + urb->actual_length,urb->actual_length
8758 + if(!urb->aligned_transfer_buffer||urb->aligned_transfer_buffer_length<urb->transfer_buffer_length){
8759 + urb->aligned_transfer_buffer_length=urb->transfer_buffer_length;
8760 + if(urb->aligned_transfer_buffer) {
8761 + kfree(urb->aligned_transfer_buffer);
8763 + urb->aligned_transfer_buffer=kmalloc(urb->aligned_transfer_buffer_length,GFP_KERNEL|GFP_DMA|GFP_ATOMIC);
8764 + urb->aligned_transfer_dma=dma_map_single(NULL,(void *)(urb->aligned_transfer_buffer),(urb->aligned_transfer_buffer_length),DMA_FROM_DEVICE);
8765 + if(!urb->aligned_transfer_buffer){
8766 + DWC_ERROR("Cannot alloc required buffer!!\n");
8769 + //printk(" new allocated aligned_buf=%.8x aligned_buf_len=%d\n", (u32)urb->aligned_transfer_buffer, urb->aligned_transfer_buffer_length);
8771 + urb->transfer_dma=urb->aligned_transfer_dma;
8772 + if((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_OUT) {
8773 + memcpy(urb->aligned_transfer_buffer,urb->transfer_buffer,urb->transfer_buffer_length);
8774 + dma_sync_single_for_device(NULL,urb->transfer_dma,urb->transfer_buffer_length,DMA_TO_DEVICE);
8781 +/** Starts processing a USB transfer request specified by a USB Request Block
8782 + * (URB). mem_flags indicates the type of memory allocation to use while
8783 + * processing this URB. */
8784 +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
8785 +// struct usb_host_endpoint *ep,
8791 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8792 + dwc_otg_qtd_t *qtd;
8795 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8796 + dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
8799 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
8800 + /* No longer connected. */
8804 + hcd_check_and_patch_dma_addr(urb);
8805 + qtd = dwc_otg_hcd_qtd_create(urb);
8806 + if (qtd == NULL) {
8807 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
8811 + retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
8813 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
8814 + "Error status %d\n", retval);
8815 + dwc_otg_hcd_qtd_free(qtd);
8821 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
8823 +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
8824 + struct urb *urb, int status)
8826 + unsigned long flags;
8827 + dwc_otg_hcd_t *dwc_otg_hcd;
8828 + dwc_otg_qtd_t *urb_qtd;
8830 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
8832 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
8834 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8836 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
8838 + urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
8839 + qh = (dwc_otg_qh_t *)ep->hcpriv;
8842 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8843 + dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
8844 + if (urb_qtd == qh->qtd_in_process) {
8845 + dump_channel_info(dwc_otg_hcd, qh);
8850 + if (urb_qtd == qh->qtd_in_process) {
8851 + /* The QTD is in process (it has been assigned to a channel). */
8853 + if (dwc_otg_hcd->flags.b.port_connect_status) {
8855 + * If still connected (i.e. in host mode), halt the
8856 + * channel so it can be used for other transfers. If
8857 + * no longer connected, the host registers can't be
8858 + * written to halt the channel since the core is in
8861 + dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
8862 + DWC_OTG_HC_XFER_URB_DEQUEUE);
8867 + * Free the QTD and clean up the associated QH. Leave the QH in the
8868 + * schedule if it has any remaining QTDs.
8870 + dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
8871 + if (urb_qtd == qh->qtd_in_process) {
8872 + dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
8873 + qh->channel = NULL;
8874 + qh->qtd_in_process = NULL;
8875 + } else if (list_empty(&qh->qtd_list)) {
8876 + dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
8879 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8881 + urb->hcpriv = NULL;
8883 + /* Higher layer software sets URB status. */
8884 + usb_hcd_giveback_urb(hcd, urb, status);
8885 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8886 + DWC_PRINT("Called usb_hcd_giveback_urb()\n");
8887 + DWC_PRINT(" urb->status = %d\n", urb->status);
8893 +/** Frees resources in the DWC_otg controller related to a given endpoint. Also
8894 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
8895 + * must already be dequeued. */
8896 +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
8897 + struct usb_host_endpoint *ep)
8899 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8902 + unsigned long flags;
8905 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
8906 + "endpoint=%d\n", ep->desc.bEndpointAddress,
8907 + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
8910 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
8911 + qh = (dwc_otg_qh_t *)(ep->hcpriv);
8915 + /** Check that the QTD list is really empty */
8916 + if (!list_empty(&qh->qtd_list)) {
8917 + if (retry++ < 250) {
8918 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8919 + schedule_timeout_uninterruptible(1);
8923 + DWC_WARN("DWC OTG HCD EP DISABLE:"
8924 + " QTD List for this endpoint is not empty\n");
8927 + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
8928 + ep->hcpriv = NULL;
8930 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8934 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
8935 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
8938 + * This function is called by the USB core when an interrupt occurs */
8939 +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
8942 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8943 + retVal = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
8944 + if (dwc_otg_hcd->flags.b.port_connect_status_change == 1)
8945 + usb_hcd_poll_rh_status(hcd);
8946 + return IRQ_RETVAL(retVal);
8949 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
8950 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
8951 + * is the status change indicator for the single root port. Returns 1 if either
8952 + * change indicator is 1, otherwise returns 0. */
8953 +int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
8955 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8958 + buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
8959 + dwc_otg_hcd->flags.b.port_reset_change ||
8960 + dwc_otg_hcd->flags.b.port_enable_change ||
8961 + dwc_otg_hcd->flags.b.port_suspend_change ||
8962 + dwc_otg_hcd->flags.b.port_over_current_change) << 1;
8966 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
8967 + " Root port status changed\n");
8968 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
8969 + dwc_otg_hcd->flags.b.port_connect_status_change);
8970 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
8971 + dwc_otg_hcd->flags.b.port_reset_change);
8972 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
8973 + dwc_otg_hcd->flags.b.port_enable_change);
8974 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
8975 + dwc_otg_hcd->flags.b.port_suspend_change);
8976 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
8977 + dwc_otg_hcd->flags.b.port_over_current_change);
8980 + return (buf[0] != 0);
8983 +#ifdef DWC_HS_ELECT_TST
8985 + * Quick and dirty hack to implement the HS Electrical Test
8986 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
8988 + * This code was copied from our userspace app "hset". It sends a
8989 + * Get Device Descriptor control sequence in two parts, first the
8990 + * Setup packet by itself, followed some time later by the In and
8991 + * Ack packets. Rather than trying to figure out how to add this
8992 + * functionality to the normal driver code, we just hijack the
8993 + * hardware, using these two function to drive the hardware
8997 +dwc_otg_core_global_regs_t *global_regs;
8998 +dwc_otg_host_global_regs_t *hc_global_regs;
8999 +dwc_otg_hc_regs_t *hc_regs;
9000 +uint32_t *data_fifo;
9002 +static void do_setup(void)
9004 + gintsts_data_t gintsts;
9005 + hctsiz_data_t hctsiz;
9006 + hcchar_data_t hcchar;
9007 + haint_data_t haint;
9008 + hcint_data_t hcint;
9010 + /* Enable HAINTs */
9011 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
9013 + /* Enable HCINTs */
9014 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
9016 + /* Read GINTSTS */
9017 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9018 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9021 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9022 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9025 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9026 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9029 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9030 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9033 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9036 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9038 + /* Clear GINTSTS */
9039 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9041 + /* Read GINTSTS */
9042 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9043 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9046 + * Send Setup packet (Get Device Descriptor)
9049 + /* Make sure channel is disabled */
9050 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9051 + if (hcchar.b.chen) {
9052 + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
9053 + hcchar.b.chdis = 1;
9054 +// hcchar.b.chen = 1;
9055 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9059 + /* Read GINTSTS */
9060 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9061 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9064 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9065 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9068 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9069 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9072 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9073 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9076 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9079 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9081 + /* Clear GINTSTS */
9082 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9084 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9085 + //if (hcchar.b.chen) {
9086 + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
9092 + hctsiz.b.xfersize = 8;
9093 + hctsiz.b.pktcnt = 1;
9094 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
9095 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9098 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9099 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9100 + hcchar.b.epdir = 0;
9101 + hcchar.b.epnum = 0;
9103 + hcchar.b.chen = 1;
9104 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9106 + /* Fill FIFO with Setup data for Get Device Descriptor */
9107 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9108 + dwc_write_reg32(data_fifo++, 0x01000680);
9109 + dwc_write_reg32(data_fifo++, 0x00080000);
9111 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9112 + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
9114 + /* Wait for host channel interrupt */
9116 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9117 + } while (gintsts.b.hcintr == 0);
9119 + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
9121 + /* Disable HCINTs */
9122 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
9124 + /* Disable HAINTs */
9125 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
9128 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9129 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9132 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9133 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9136 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9137 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9140 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9143 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9145 + /* Clear GINTSTS */
9146 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9148 + /* Read GINTSTS */
9149 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9150 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9153 +static void do_in_ack(void)
9155 + gintsts_data_t gintsts;
9156 + hctsiz_data_t hctsiz;
9157 + hcchar_data_t hcchar;
9158 + haint_data_t haint;
9159 + hcint_data_t hcint;
9160 + host_grxsts_data_t grxsts;
9162 + /* Enable HAINTs */
9163 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
9165 + /* Enable HCINTs */
9166 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
9168 + /* Read GINTSTS */
9169 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9170 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9173 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9174 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9177 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9178 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9181 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9182 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9185 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9188 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9190 + /* Clear GINTSTS */
9191 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9193 + /* Read GINTSTS */
9194 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9195 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9198 + * Receive Control In packet
9201 + /* Make sure channel is disabled */
9202 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9203 + if (hcchar.b.chen) {
9204 + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
9205 + hcchar.b.chdis = 1;
9206 + hcchar.b.chen = 1;
9207 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9211 + /* Read GINTSTS */
9212 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9213 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9216 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9217 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9220 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9221 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9224 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9225 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9228 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9231 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9233 + /* Clear GINTSTS */
9234 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9236 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9237 + //if (hcchar.b.chen) {
9238 + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
9244 + hctsiz.b.xfersize = 8;
9245 + hctsiz.b.pktcnt = 1;
9246 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
9247 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9250 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9251 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9252 + hcchar.b.epdir = 1;
9253 + hcchar.b.epnum = 0;
9255 + hcchar.b.chen = 1;
9256 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9258 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9259 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
9261 + /* Wait for receive status queue interrupt */
9263 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9264 + } while (gintsts.b.rxstsqlvl == 0);
9266 + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
9269 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
9270 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
9272 + /* Clear RXSTSQLVL in GINTSTS */
9274 + gintsts.b.rxstsqlvl = 1;
9275 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9277 + switch (grxsts.b.pktsts) {
9278 + case DWC_GRXSTS_PKTSTS_IN:
9279 + /* Read the data into the host buffer */
9280 + if (grxsts.b.bcnt > 0) {
9282 + int word_count = (grxsts.b.bcnt + 3) / 4;
9284 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9286 + for (i = 0; i < word_count; i++) {
9287 + (void)dwc_read_reg32(data_fifo++);
9291 + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
9295 + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
9299 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9300 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
9302 + /* Wait for receive status queue interrupt */
9304 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9305 + } while (gintsts.b.rxstsqlvl == 0);
9307 + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
9310 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
9311 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
9313 + /* Clear RXSTSQLVL in GINTSTS */
9315 + gintsts.b.rxstsqlvl = 1;
9316 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9318 + switch (grxsts.b.pktsts) {
9319 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
9323 + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
9327 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9328 + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
9330 + /* Wait for host channel interrupt */
9332 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9333 + } while (gintsts.b.hcintr == 0);
9335 + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
9338 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9339 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9342 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9343 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9346 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9347 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9350 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9353 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9355 + /* Clear GINTSTS */
9356 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9358 + /* Read GINTSTS */
9359 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9360 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9367 + * Send handshake packet
9371 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9372 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9375 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9376 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9379 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9380 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9383 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9386 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9388 + /* Clear GINTSTS */
9389 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9391 + /* Read GINTSTS */
9392 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9393 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9395 + /* Make sure channel is disabled */
9396 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9397 + if (hcchar.b.chen) {
9398 + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
9399 + hcchar.b.chdis = 1;
9400 + hcchar.b.chen = 1;
9401 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9405 + /* Read GINTSTS */
9406 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9407 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9410 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9411 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9414 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9415 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9418 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9419 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9422 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9425 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9427 + /* Clear GINTSTS */
9428 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9430 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9431 + //if (hcchar.b.chen) {
9432 + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
9438 + hctsiz.b.xfersize = 0;
9439 + hctsiz.b.pktcnt = 1;
9440 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
9441 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9444 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9445 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9446 + hcchar.b.epdir = 0;
9447 + hcchar.b.epnum = 0;
9449 + hcchar.b.chen = 1;
9450 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9452 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9453 + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
9455 + /* Wait for host channel interrupt */
9457 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9458 + } while (gintsts.b.hcintr == 0);
9460 + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
9462 + /* Disable HCINTs */
9463 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
9465 + /* Disable HAINTs */
9466 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
9469 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9470 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9473 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9474 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9477 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9478 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9481 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9484 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9486 + /* Clear GINTSTS */
9487 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9489 + /* Read GINTSTS */
9490 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9491 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9493 +#endif /* DWC_HS_ELECT_TST */
9495 +/** Handles hub class-specific requests. */
9496 +int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
9505 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
9506 + dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if;
9507 + struct usb_hub_descriptor *desc;
9508 + hprt0_data_t hprt0 = {.d32 = 0};
9510 + uint32_t port_status;
9512 + switch (typeReq) {
9513 + case ClearHubFeature:
9514 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9515 + "ClearHubFeature 0x%x\n", wValue);
9517 + case C_HUB_LOCAL_POWER:
9518 + case C_HUB_OVER_CURRENT:
9519 + /* Nothing required here */
9523 + DWC_ERROR("DWC OTG HCD - "
9524 + "ClearHubFeature request %xh unknown\n", wValue);
9527 + case ClearPortFeature:
9528 + if (!wIndex || wIndex > 1)
9532 + case USB_PORT_FEAT_ENABLE:
9533 + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
9534 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
9535 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9536 + hprt0.b.prtena = 1;
9537 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9539 + case USB_PORT_FEAT_SUSPEND:
9540 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9541 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
9542 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9543 + hprt0.b.prtres = 1;
9544 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9545 + /* Clear Resume bit */
9547 + hprt0.b.prtres = 0;
9548 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9550 + case USB_PORT_FEAT_POWER:
9551 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9552 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
9553 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9554 + hprt0.b.prtpwr = 0;
9555 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9557 + case USB_PORT_FEAT_INDICATOR:
9558 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9559 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
9560 + /* Port inidicator not supported */
9562 + case USB_PORT_FEAT_C_CONNECTION:
9563 + /* Clears drivers internal connect status change
9565 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9566 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
9567 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
9569 + case USB_PORT_FEAT_C_RESET:
9570 + /* Clears the driver's internal Port Reset Change
9572 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9573 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
9574 + dwc_otg_hcd->flags.b.port_reset_change = 0;
9576 + case USB_PORT_FEAT_C_ENABLE:
9577 + /* Clears the driver's internal Port
9578 + * Enable/Disable Change flag */
9579 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9580 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
9581 + dwc_otg_hcd->flags.b.port_enable_change = 0;
9583 + case USB_PORT_FEAT_C_SUSPEND:
9584 + /* Clears the driver's internal Port Suspend
9585 + * Change flag, which is set when resume signaling on
9586 + * the host port is complete */
9587 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9588 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
9589 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
9591 + case USB_PORT_FEAT_C_OVER_CURRENT:
9592 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9593 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
9594 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
9598 + DWC_ERROR("DWC OTG HCD - "
9599 + "ClearPortFeature request %xh "
9600 + "unknown or unsupported\n", wValue);
9603 + case GetHubDescriptor:
9604 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9605 + "GetHubDescriptor\n");
9606 + desc = (struct usb_hub_descriptor *)buf;
9607 + desc->bDescLength = 9;
9608 + desc->bDescriptorType = 0x29;
9609 + desc->bNbrPorts = 1;
9610 + desc->wHubCharacteristics = 0x08;
9611 + desc->bPwrOn2PwrGood = 1;
9612 + desc->bHubContrCurrent = 0;
9613 + desc->u.hs.DeviceRemovable[0] = 0;
9614 + desc->u.hs.DeviceRemovable[1] = 0xff;
9616 + case GetHubStatus:
9617 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9618 + "GetHubStatus\n");
9619 + memset(buf, 0, 4);
9621 + case GetPortStatus:
9622 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9623 + "GetPortStatus\n");
9625 + if (!wIndex || wIndex > 1)
9630 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
9631 + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
9633 + if (dwc_otg_hcd->flags.b.port_enable_change)
9634 + port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
9636 + if (dwc_otg_hcd->flags.b.port_suspend_change)
9637 + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
9639 + if (dwc_otg_hcd->flags.b.port_reset_change)
9640 + port_status |= (1 << USB_PORT_FEAT_C_RESET);
9642 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
9643 + DWC_ERROR("Device Not Supported\n");
9644 + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
9647 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
9649 + * The port is disconnected, which means the core is
9650 + * either in device mode or it soon will be. Just
9651 + * return 0's for the remainder of the port status
9652 + * since the port register can't be read if the core
9653 + * is in device mode.
9655 + *((__le32 *) buf) = cpu_to_le32(port_status);
9659 + hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
9660 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
9662 + if (hprt0.b.prtconnsts)
9663 + port_status |= (1 << USB_PORT_FEAT_CONNECTION);
9665 + if (hprt0.b.prtena)
9666 + port_status |= (1 << USB_PORT_FEAT_ENABLE);
9668 + if (hprt0.b.prtsusp)
9669 + port_status |= (1 << USB_PORT_FEAT_SUSPEND);
9671 + if (hprt0.b.prtovrcurract)
9672 + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
9674 + if (hprt0.b.prtrst)
9675 + port_status |= (1 << USB_PORT_FEAT_RESET);
9677 + if (hprt0.b.prtpwr)
9678 + port_status |= (1 << USB_PORT_FEAT_POWER);
9680 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
9681 + port_status |= (USB_PORT_STAT_HIGH_SPEED);
9682 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
9683 + port_status |= (USB_PORT_STAT_LOW_SPEED);
9685 + if (hprt0.b.prttstctl)
9686 + port_status |= (1 << USB_PORT_FEAT_TEST);
9688 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
9690 + *((__le32 *) buf) = cpu_to_le32(port_status);
9693 + case SetHubFeature:
9694 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9695 + "SetHubFeature\n");
9696 + /* No HUB features supported */
9698 + case SetPortFeature:
9699 + if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1))
9702 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
9704 + * The port is disconnected, which means the core is
9705 + * either in device mode or it soon will be. Just
9706 + * return without doing anything since the port
9707 + * register can't be written if the core is in device
9714 + case USB_PORT_FEAT_SUSPEND:
9715 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9716 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
9717 + if (hcd->self.otg_port == wIndex &&
9718 + hcd->self.b_hnp_enable) {
9719 + gotgctl_data_t gotgctl = {.d32=0};
9720 + gotgctl.b.hstsethnpen = 1;
9721 + dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
9723 + core_if->op_state = A_SUSPEND;
9725 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9726 + hprt0.b.prtsusp = 1;
9727 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9728 + //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32);
9729 + /* Suspend the Phy Clock */
9731 + pcgcctl_data_t pcgcctl = {.d32=0};
9732 + pcgcctl.b.stoppclk = 1;
9733 + dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
9736 + /* For HNP the bus must be suspended for at least 200ms. */
9737 + if (hcd->self.b_hnp_enable) {
9739 + //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);
9742 + case USB_PORT_FEAT_POWER:
9743 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9744 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
9745 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9746 + hprt0.b.prtpwr = 1;
9747 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9749 + case USB_PORT_FEAT_RESET:
9750 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9751 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
9752 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9753 + /* When B-Host the Port reset bit is set in
9754 + * the Start HCD Callback function, so that
9755 + * the reset is started within 1ms of the HNP
9756 + * success interrupt. */
9757 + if (!hcd->self.is_b_host) {
9758 + hprt0.b.prtrst = 1;
9759 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9761 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
9763 + hprt0.b.prtrst = 0;
9764 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9767 +#ifdef DWC_HS_ELECT_TST
9768 + case USB_PORT_FEAT_TEST:
9771 + gintmsk_data_t gintmsk;
9773 + t = (wIndex >> 8); /* MSB wIndex USB */
9774 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9775 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
9776 + warn("USB_PORT_FEAT_TEST %d\n", t);
9778 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9779 + hprt0.b.prttstctl = t;
9780 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9782 + /* Setup global vars with reg addresses (quick and
9783 + * dirty hack, should be cleaned up)
9785 + global_regs = core_if->core_global_regs;
9786 + hc_global_regs = core_if->host_if->host_global_regs;
9787 + hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
9788 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9790 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
9791 + /* Save current interrupt mask */
9792 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9794 + /* Disable all interrupts while we muck with
9795 + * the hardware directly
9797 + dwc_write_reg32(&global_regs->gintmsk, 0);
9799 + /* 15 second delay per the test spec */
9802 + /* Drive suspend on the root port */
9803 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9804 + hprt0.b.prtsusp = 1;
9805 + hprt0.b.prtres = 0;
9806 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9808 + /* 15 second delay per the test spec */
9811 + /* Drive resume on the root port */
9812 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9813 + hprt0.b.prtsusp = 0;
9814 + hprt0.b.prtres = 1;
9815 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9818 + /* Clear the resume bit */
9819 + hprt0.b.prtres = 0;
9820 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9822 + /* Restore interrupts */
9823 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9824 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
9825 + /* Save current interrupt mask */
9826 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9828 + /* Disable all interrupts while we muck with
9829 + * the hardware directly
9831 + dwc_write_reg32(&global_regs->gintmsk, 0);
9833 + /* 15 second delay per the test spec */
9836 + /* Send the Setup packet */
9839 + /* 15 second delay so nothing else happens for awhile */
9842 + /* Restore interrupts */
9843 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9844 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
9845 + /* Save current interrupt mask */
9846 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9848 + /* Disable all interrupts while we muck with
9849 + * the hardware directly
9851 + dwc_write_reg32(&global_regs->gintmsk, 0);
9853 + /* Send the Setup packet */
9856 + /* 15 second delay so nothing else happens for awhile */
9859 + /* Send the In and Ack packets */
9862 + /* 15 second delay so nothing else happens for awhile */
9865 + /* Restore interrupts */
9866 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9871 +#endif /* DWC_HS_ELECT_TST */
9873 + case USB_PORT_FEAT_INDICATOR:
9874 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9875 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
9876 + /* Not supported */
9880 + DWC_ERROR("DWC OTG HCD - "
9881 + "SetPortFeature request %xh "
9882 + "unknown or unsupported\n", wValue);
9889 + DWC_WARN("DWC OTG HCD - "
9890 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
9891 + typeReq, wIndex, wValue);
9899 + * Assigns transactions from a QTD to a free host channel and initializes the
9900 + * host channel to perform the transactions. The host channel is removed from
9903 + * @param hcd The HCD state structure.
9904 + * @param qh Transactions from the first QTD for this QH are selected and
9905 + * assigned to a free host channel.
9907 +static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
9910 + dwc_otg_qtd_t *qtd;
9913 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
9915 + hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
9917 + /* Remove the host channel from the free list. */
9918 + list_del_init(&hc->hc_list_entry);
9920 + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
9923 + qh->qtd_in_process = qtd;
9926 + * Use usb_pipedevice to determine device address. This address is
9927 + * 0 before the SET_ADDRESS command and the correct address afterward.
9929 + hc->dev_addr = usb_pipedevice(urb->pipe);
9930 + hc->ep_num = usb_pipeendpoint(urb->pipe);
9932 + if (urb->dev->speed == USB_SPEED_LOW) {
9933 + hc->speed = DWC_OTG_EP_SPEED_LOW;
9934 + } else if (urb->dev->speed == USB_SPEED_FULL) {
9935 + hc->speed = DWC_OTG_EP_SPEED_FULL;
9937 + hc->speed = DWC_OTG_EP_SPEED_HIGH;
9940 + hc->max_packet = dwc_max_packet(qh->maxp);
9942 + hc->xfer_started = 0;
9943 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
9944 + hc->error_state = (qtd->error_count > 0);
9945 + hc->halt_on_queue = 0;
9946 + hc->halt_pending = 0;
9950 + * The following values may be modified in the transfer type section
9951 + * below. The xfer_len value may be reduced when the transfer is
9952 + * started to accommodate the max widths of the XferSize and PktCnt
9953 + * fields in the HCTSIZn register.
9955 + hc->do_ping = qh->ping_state;
9956 + hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
9957 + hc->data_pid_start = qh->data_toggle;
9958 + hc->multi_count = 1;
9960 + if (hcd->core_if->dma_enable) {
9961 + hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
9963 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
9965 + hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
9966 + hc->xfer_count = 0;
9969 + * Set the split attributes
9972 + if (qh->do_split) {
9974 + hc->xact_pos = qtd->isoc_split_pos;
9975 + hc->complete_split = qtd->complete_split;
9976 + hc->hub_addr = urb->dev->tt->hub->devnum;
9977 + hc->port_addr = urb->dev->ttport;
9980 + switch (usb_pipetype(urb->pipe)) {
9981 + case PIPE_CONTROL:
9982 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
9983 + switch (qtd->control_phase) {
9984 + case DWC_OTG_CONTROL_SETUP:
9985 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
9988 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
9989 + if (hcd->core_if->dma_enable) {
9990 + hc->xfer_buff = (uint8_t *)urb->setup_dma;
9992 + hc->xfer_buff = (uint8_t *)urb->setup_packet;
9996 + case DWC_OTG_CONTROL_DATA:
9997 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
9998 + hc->data_pid_start = qtd->data_toggle;
10000 + case DWC_OTG_CONTROL_STATUS:
10002 + * Direction is opposite of data direction or IN if no
10005 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
10006 + if (urb->transfer_buffer_length == 0) {
10007 + hc->ep_is_in = 1;
10009 + hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
10011 + if (hc->ep_is_in) {
10014 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
10015 + hc->xfer_len = 0;
10016 + if (hcd->core_if->dma_enable) {
10017 + hc->xfer_buff = (uint8_t *)hcd->status_buf_dma;
10019 + hc->xfer_buff = (uint8_t *)hcd->status_buf;
10025 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
10027 + case PIPE_INTERRUPT:
10028 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
10030 + case PIPE_ISOCHRONOUS:
10032 + struct usb_iso_packet_descriptor *frame_desc;
10033 + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
10034 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
10035 + if (hcd->core_if->dma_enable) {
10036 + hc->xfer_buff = (uint8_t *)urb->transfer_dma;
10038 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
10040 + hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
10041 + hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
10043 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
10044 + if (hc->xfer_len <= 188) {
10045 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
10048 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
10055 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
10056 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
10058 + * This value may be modified when the transfer is started to
10059 + * reflect the actual transfer length.
10061 + hc->multi_count = dwc_hb_mult(qh->maxp);
10064 + dwc_otg_hc_init(hcd->core_if, hc);
10069 + * This function selects transactions from the HCD transfer schedule and
10070 + * assigns them to available host channels. It is called from HCD interrupt
10071 + * handler functions.
10073 + * @param hcd The HCD state structure.
10075 + * @return The types of new transactions that were assigned to host channels.
10077 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
10079 + struct list_head *qh_ptr;
10080 + dwc_otg_qh_t *qh;
10081 + int num_channels;
10082 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
10085 + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
10088 + /* Process entries in the periodic ready list. */
10089 + qh_ptr = hcd->periodic_sched_ready.next;
10090 + while (qh_ptr != &hcd->periodic_sched_ready &&
10091 + !list_empty(&hcd->free_hc_list)) {
10093 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10094 + assign_and_init_hc(hcd, qh);
10097 + * Move the QH from the periodic ready schedule to the
10098 + * periodic assigned schedule.
10100 + qh_ptr = qh_ptr->next;
10101 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned);
10103 + ret_val = DWC_OTG_TRANSACTION_PERIODIC;
10107 + * Process entries in the inactive portion of the non-periodic
10108 + * schedule. Some free host channels may not be used if they are
10109 + * reserved for periodic transfers.
10111 + qh_ptr = hcd->non_periodic_sched_inactive.next;
10112 + num_channels = hcd->core_if->core_params->host_channels;
10113 + while (qh_ptr != &hcd->non_periodic_sched_inactive &&
10114 + (hcd->non_periodic_channels <
10115 + num_channels - hcd->periodic_channels) &&
10116 + !list_empty(&hcd->free_hc_list)) {
10118 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10119 + assign_and_init_hc(hcd, qh);
10122 + * Move the QH from the non-periodic inactive schedule to the
10123 + * non-periodic active schedule.
10125 + qh_ptr = qh_ptr->next;
10126 + list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
10128 + if (ret_val == DWC_OTG_TRANSACTION_NONE) {
10129 + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
10131 + ret_val = DWC_OTG_TRANSACTION_ALL;
10134 + hcd->non_periodic_channels++;
10141 + * Attempts to queue a single transaction request for a host channel
10142 + * associated with either a periodic or non-periodic transfer. This function
10143 + * assumes that there is space available in the appropriate request queue. For
10144 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
10145 + * is available in the appropriate Tx FIFO.
10147 + * @param hcd The HCD state structure.
10148 + * @param hc Host channel descriptor associated with either a periodic or
10149 + * non-periodic transfer.
10150 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
10151 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
10154 + * @return 1 if a request is queued and more requests may be needed to
10155 + * complete the transfer, 0 if no more requests are required for this
10156 + * transfer, -1 if there is insufficient space in the Tx FIFO.
10158 +static int queue_transaction(dwc_otg_hcd_t *hcd,
10160 + uint16_t fifo_dwords_avail)
10164 + if (hcd->core_if->dma_enable) {
10165 + if (!hc->xfer_started) {
10166 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
10167 + hc->qh->ping_state = 0;
10170 + } else if (hc->halt_pending) {
10171 + /* Don't queue a request if the channel has been halted. */
10173 + } else if (hc->halt_on_queue) {
10174 + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
10176 + } else if (hc->do_ping) {
10177 + if (!hc->xfer_started) {
10178 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
10181 + } else if (!hc->ep_is_in ||
10182 + hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
10183 + if ((fifo_dwords_avail * 4) >= hc->max_packet) {
10184 + if (!hc->xfer_started) {
10185 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
10188 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
10194 + if (!hc->xfer_started) {
10195 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
10198 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
10206 + * Processes active non-periodic channels and queues transactions for these
10207 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
10208 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
10209 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
10210 + * FIFO Empty interrupt is disabled.
10212 +static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
10214 + gnptxsts_data_t tx_status;
10215 + struct list_head *orig_qh_ptr;
10216 + dwc_otg_qh_t *qh;
10218 + int no_queue_space = 0;
10219 + int no_fifo_space = 0;
10220 + int more_to_do = 0;
10222 + dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs;
10224 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
10226 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10227 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
10228 + tx_status.b.nptxqspcavail);
10229 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
10230 + tx_status.b.nptxfspcavail);
10233 + * Keep track of the starting point. Skip over the start-of-list
10236 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
10237 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10239 + orig_qh_ptr = hcd->non_periodic_qh_ptr;
10242 + * Process once through the active list or until no more space is
10243 + * available in the request queue or the Tx FIFO.
10246 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10247 + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
10248 + no_queue_space = 1;
10252 + qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
10253 + status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail);
10255 + if (status > 0) {
10257 + } else if (status < 0) {
10258 + no_fifo_space = 1;
10262 + /* Advance to next QH, skipping start-of-list entry. */
10263 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10264 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
10265 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10268 + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
10270 + if (!hcd->core_if->dma_enable) {
10271 + gintmsk_data_t intr_mask = {.d32 = 0};
10272 + intr_mask.b.nptxfempty = 1;
10275 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10276 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
10277 + tx_status.b.nptxqspcavail);
10278 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
10279 + tx_status.b.nptxfspcavail);
10281 + if (more_to_do || no_queue_space || no_fifo_space) {
10283 + * May need to queue more transactions as the request
10284 + * queue or Tx FIFO empties. Enable the non-periodic
10285 + * Tx FIFO empty interrupt. (Always use the half-empty
10286 + * level to ensure that new requests are loaded as
10287 + * soon as possible.)
10289 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
10292 + * Disable the Tx FIFO empty interrupt since there are
10293 + * no more transactions that need to be queued right
10294 + * now. This function is called from interrupt
10295 + * handlers to queue more transactions as transfer
10298 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
10304 + * Processes periodic channels for the next frame and queues transactions for
10305 + * these channels to the DWC_otg controller. After queueing transactions, the
10306 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
10307 + * to queue as Periodic Tx FIFO or request queue space becomes available.
10308 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
10310 +static void process_periodic_channels(dwc_otg_hcd_t *hcd)
10312 + hptxsts_data_t tx_status;
10313 + struct list_head *qh_ptr;
10314 + dwc_otg_qh_t *qh;
10316 + int no_queue_space = 0;
10317 + int no_fifo_space = 0;
10319 + dwc_otg_host_global_regs_t *host_regs;
10320 + host_regs = hcd->core_if->host_if->host_global_regs;
10322 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
10324 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10325 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
10326 + tx_status.b.ptxqspcavail);
10327 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
10328 + tx_status.b.ptxfspcavail);
10331 + qh_ptr = hcd->periodic_sched_assigned.next;
10332 + while (qh_ptr != &hcd->periodic_sched_assigned) {
10333 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10334 + if (tx_status.b.ptxqspcavail == 0) {
10335 + no_queue_space = 1;
10339 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10342 + * Set a flag if we're queuing high-bandwidth in slave mode.
10343 + * The flag prevents any halts to get into the request queue in
10344 + * the middle of multiple high-bandwidth packets getting queued.
10346 + if (!hcd->core_if->dma_enable &&
10347 + qh->channel->multi_count > 1)
10349 + hcd->core_if->queuing_high_bandwidth = 1;
10352 + status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail);
10353 + if (status < 0) {
10354 + no_fifo_space = 1;
10359 + * In Slave mode, stay on the current transfer until there is
10360 + * nothing more to do or the high-bandwidth request count is
10361 + * reached. In DMA mode, only need to queue one request. The
10362 + * controller automatically handles multiple packets for
10363 + * high-bandwidth transfers.
10365 + if (hcd->core_if->dma_enable || status == 0 ||
10366 + qh->channel->requests == qh->channel->multi_count) {
10367 + qh_ptr = qh_ptr->next;
10369 + * Move the QH from the periodic assigned schedule to
10370 + * the periodic queued schedule.
10372 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued);
10374 + /* done queuing high bandwidth */
10375 + hcd->core_if->queuing_high_bandwidth = 0;
10379 + if (!hcd->core_if->dma_enable) {
10380 + dwc_otg_core_global_regs_t *global_regs;
10381 + gintmsk_data_t intr_mask = {.d32 = 0};
10383 + global_regs = hcd->core_if->core_global_regs;
10384 + intr_mask.b.ptxfempty = 1;
10386 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10387 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
10388 + tx_status.b.ptxqspcavail);
10389 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
10390 + tx_status.b.ptxfspcavail);
10392 + if (!list_empty(&hcd->periodic_sched_assigned) ||
10393 + no_queue_space || no_fifo_space) {
10395 + * May need to queue more transactions as the request
10396 + * queue or Tx FIFO empties. Enable the periodic Tx
10397 + * FIFO empty interrupt. (Always use the half-empty
10398 + * level to ensure that new requests are loaded as
10399 + * soon as possible.)
10401 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
10404 + * Disable the Tx FIFO empty interrupt since there are
10405 + * no more transactions that need to be queued right
10406 + * now. This function is called from interrupt
10407 + * handlers to queue more transactions as transfer
10410 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
10416 + * This function processes the currently active host channels and queues
10417 + * transactions for these channels to the DWC_otg controller. It is called
10418 + * from HCD interrupt handler functions.
10420 + * @param hcd The HCD state structure.
10421 + * @param tr_type The type(s) of transactions to queue (non-periodic,
10422 + * periodic, or both).
10424 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
10425 + dwc_otg_transaction_type_e tr_type)
10428 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
10430 + /* Process host channels associated with periodic transfers. */
10431 + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
10432 + tr_type == DWC_OTG_TRANSACTION_ALL) &&
10433 + !list_empty(&hcd->periodic_sched_assigned)) {
10435 + process_periodic_channels(hcd);
10438 + /* Process host channels associated with non-periodic transfers. */
10439 + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
10440 + tr_type == DWC_OTG_TRANSACTION_ALL) {
10441 + if (!list_empty(&hcd->non_periodic_sched_active)) {
10442 + process_non_periodic_channels(hcd);
10445 + * Ensure NP Tx FIFO empty interrupt is disabled when
10446 + * there are no non-periodic transfers to process.
10448 + gintmsk_data_t gintmsk = {.d32 = 0};
10449 + gintmsk.b.nptxfempty = 1;
10450 + dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk,
10457 + * Sets the final status of an URB and returns it to the device driver. Any
10458 + * required cleanup of the URB is performed.
10460 +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
10463 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10464 + DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
10465 + __func__, urb, usb_pipedevice(urb->pipe),
10466 + usb_pipeendpoint(urb->pipe),
10467 + usb_pipein(urb->pipe) ? "IN" : "OUT", status);
10468 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
10470 + for (i = 0; i < urb->number_of_packets; i++) {
10471 + DWC_PRINT(" ISO Desc %d status: %d\n",
10472 + i, urb->iso_frame_desc[i].status);
10478 + //if we use the aligned buffer instead of the original unaligned buffer,
10479 + //for IN data, we have to move the data to the original buffer
10480 + if((urb->transfer_dma==urb->aligned_transfer_dma)&&((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_IN)){
10481 + dma_sync_single_for_device(NULL,urb->transfer_dma,urb->actual_length,DMA_FROM_DEVICE);
10482 + memcpy(urb->transfer_buffer,urb->aligned_transfer_buffer,urb->actual_length);
10486 + urb->status = status;
10487 + urb->hcpriv = NULL;
10488 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
10492 + * Returns the Queue Head for an URB.
10494 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb)
10496 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
10497 + return (dwc_otg_qh_t *)ep->hcpriv;
10501 +void dwc_print_setup_data(uint8_t *setup)
10504 + if (CHK_DEBUG_LEVEL(DBG_HCD)){
10505 + DWC_PRINT("Setup Data = MSB ");
10506 + for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]);
10508 + DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device");
10509 + DWC_PRINT(" bmRequestType Type = ");
10510 + switch ((setup[0] & 0x60) >> 5) {
10511 + case 0: DWC_PRINT("Standard\n"); break;
10512 + case 1: DWC_PRINT("Class\n"); break;
10513 + case 2: DWC_PRINT("Vendor\n"); break;
10514 + case 3: DWC_PRINT("Reserved\n"); break;
10516 + DWC_PRINT(" bmRequestType Recipient = ");
10517 + switch (setup[0] & 0x1f) {
10518 + case 0: DWC_PRINT("Device\n"); break;
10519 + case 1: DWC_PRINT("Interface\n"); break;
10520 + case 2: DWC_PRINT("Endpoint\n"); break;
10521 + case 3: DWC_PRINT("Other\n"); break;
10522 + default: DWC_PRINT("Reserved\n"); break;
10524 + DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
10525 + DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
10526 + DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
10527 + DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
10532 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) {
10535 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
10538 + int num_channels;
10540 + gnptxsts_data_t np_tx_status;
10541 + hptxsts_data_t p_tx_status;
10543 + num_channels = hcd->core_if->core_params->host_channels;
10545 + DWC_PRINT("************************************************************\n");
10546 + DWC_PRINT("HCD State:\n");
10547 + DWC_PRINT(" Num channels: %d\n", num_channels);
10548 + for (i = 0; i < num_channels; i++) {
10549 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
10550 + DWC_PRINT(" Channel %d:\n", i);
10551 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
10552 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
10553 + DWC_PRINT(" speed: %d\n", hc->speed);
10554 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
10555 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
10556 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
10557 + DWC_PRINT(" multi_count: %d\n", hc->multi_count);
10558 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
10559 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
10560 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
10561 + DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
10562 + DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
10563 + DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
10564 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
10565 + DWC_PRINT(" do_split: %d\n", hc->do_split);
10566 + DWC_PRINT(" complete_split: %d\n", hc->complete_split);
10567 + DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
10568 + DWC_PRINT(" port_addr: %d\n", hc->port_addr);
10569 + DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
10570 + DWC_PRINT(" requests: %d\n", hc->requests);
10571 + DWC_PRINT(" qh: %p\n", hc->qh);
10572 + if (hc->xfer_started) {
10573 + hfnum_data_t hfnum;
10574 + hcchar_data_t hcchar;
10575 + hctsiz_data_t hctsiz;
10576 + hcint_data_t hcint;
10577 + hcintmsk_data_t hcintmsk;
10578 + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
10579 + hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar);
10580 + hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz);
10581 + hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint);
10582 + hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk);
10583 + DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
10584 + DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
10585 + DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
10586 + DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
10587 + DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
10589 + if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) {
10590 + dwc_otg_qtd_t *qtd;
10592 + qtd = hc->qh->qtd_in_process;
10594 + DWC_PRINT(" URB Info:\n");
10595 + DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
10597 + DWC_PRINT(" Dev: %d, EP: %d %s\n",
10598 + usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
10599 + usb_pipein(urb->pipe) ? "IN" : "OUT");
10600 + DWC_PRINT(" Max packet size: %d\n",
10601 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
10602 + DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
10603 + DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
10604 + DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
10605 + DWC_PRINT(" actual_length: %d\n", urb->actual_length);
10609 + DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
10610 + DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels);
10611 + DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs);
10612 + np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
10613 + DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
10614 + DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
10615 + p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
10616 + DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
10617 + DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
10618 + dwc_otg_hcd_dump_frrem(hcd);
10619 + dwc_otg_dump_global_registers(hcd->core_if);
10620 + dwc_otg_dump_host_registers(hcd->core_if);
10621 + DWC_PRINT("************************************************************\n");
10625 +#endif /* DWC_DEVICE_ONLY */
10627 +++ b/drivers/usb/dwc/otg_hcd.h
10629 +/* ==========================================================================
10630 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
10631 + * $Revision: #45 $
10632 + * $Date: 2008/07/15 $
10633 + * $Change: 1064918 $
10635 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
10636 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
10637 + * otherwise expressly agreed to in writing between Synopsys and you.
10639 + * The Software IS NOT an item of Licensed Software or Licensed Product under
10640 + * any End User Software License Agreement or Agreement for Licensed Product
10641 + * with Synopsys or any supplement thereto. You are permitted to use and
10642 + * redistribute this Software in source and binary forms, with or without
10643 + * modification, provided that redistributions of source code must retain this
10644 + * notice. You may not view, use, disclose, copy or distribute this file or
10645 + * any information contained herein except pursuant to this license grant from
10646 + * Synopsys. If you do not agree with this notice, including the disclaimer
10647 + * below, then you are not authorized to use the Software.
10649 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
10650 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10651 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10652 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
10653 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10654 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
10655 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
10656 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10657 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10658 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10660 + * ========================================================================== */
10661 +#ifndef DWC_DEVICE_ONLY
10662 +#ifndef __DWC_HCD_H__
10663 +#define __DWC_HCD_H__
10665 +#include <linux/list.h>
10666 +#include <linux/usb.h>
10667 +#include <linux/usb/hcd.h>
10669 +struct dwc_otg_device;
10671 +#include "otg_cil.h"
10676 + * This file contains the structures, constants, and interfaces for
10677 + * the Host Contoller Driver (HCD).
10679 + * The Host Controller Driver (HCD) is responsible for translating requests
10680 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
10681 + * It isolates the USBD from the specifics of the controller by providing an
10682 + * API to the USBD.
10686 + * Phases for control transfers.
10688 +typedef enum dwc_otg_control_phase {
10689 + DWC_OTG_CONTROL_SETUP,
10690 + DWC_OTG_CONTROL_DATA,
10691 + DWC_OTG_CONTROL_STATUS
10692 +} dwc_otg_control_phase_e;
10694 +/** Transaction types. */
10695 +typedef enum dwc_otg_transaction_type {
10696 + DWC_OTG_TRANSACTION_NONE,
10697 + DWC_OTG_TRANSACTION_PERIODIC,
10698 + DWC_OTG_TRANSACTION_NON_PERIODIC,
10699 + DWC_OTG_TRANSACTION_ALL
10700 +} dwc_otg_transaction_type_e;
10703 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
10704 + * interrupt, or isochronous transfer. A single QTD is created for each URB
10705 + * (of one of these types) submitted to the HCD. The transfer associated with
10706 + * a QTD may require one or multiple transactions.
10708 + * A QTD is linked to a Queue Head, which is entered in either the
10709 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
10710 + * execution, some or all of its transactions may be executed. After
10711 + * execution, the state of the QTD is updated. The QTD may be retired if all
10712 + * its transactions are complete or if an error occurred. Otherwise, it
10713 + * remains in the schedule so more transactions can be executed later.
10715 +typedef struct dwc_otg_qtd {
10717 + * Determines the PID of the next data packet for the data phase of
10718 + * control transfers. Ignored for other transfer types.<br>
10719 + * One of the following values:
10720 + * - DWC_OTG_HC_PID_DATA0
10721 + * - DWC_OTG_HC_PID_DATA1
10723 + uint8_t data_toggle;
10725 + /** Current phase for control transfers (Setup, Data, or Status). */
10726 + dwc_otg_control_phase_e control_phase;
10728 + /** Keep track of the current split type
10729 + * for FS/LS endpoints on a HS Hub */
10730 + uint8_t complete_split;
10732 + /** How many bytes transferred during SSPLIT OUT */
10733 + uint32_t ssplit_out_xfer_count;
10736 + * Holds the number of bus errors that have occurred for a transaction
10737 + * within this transfer.
10739 + uint8_t error_count;
10742 + * Index of the next frame descriptor for an isochronous transfer. A
10743 + * frame descriptor describes the buffer position and length of the
10744 + * data to be transferred in the next scheduled (micro)frame of an
10745 + * isochronous transfer. It also holds status for that transaction.
10746 + * The frame index starts at 0.
10748 + int isoc_frame_index;
10750 + /** Position of the ISOC split on full/low speed */
10751 + uint8_t isoc_split_pos;
10753 + /** Position of the ISOC split in the buffer for the current frame */
10754 + uint16_t isoc_split_offset;
10756 + /** URB for this transfer */
10759 + /** This list of QTDs */
10760 + struct list_head qtd_list_entry;
10765 + * A Queue Head (QH) holds the static characteristics of an endpoint and
10766 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
10767 + * be entered in either the non-periodic or periodic schedule.
10769 +typedef struct dwc_otg_qh {
10772 + * One of the following values:
10773 + * - USB_ENDPOINT_XFER_CONTROL
10774 + * - USB_ENDPOINT_XFER_ISOC
10775 + * - USB_ENDPOINT_XFER_BULK
10776 + * - USB_ENDPOINT_XFER_INT
10779 + uint8_t ep_is_in;
10781 + /** wMaxPacketSize Field of Endpoint Descriptor. */
10785 + * Determines the PID of the next data packet for non-control
10786 + * transfers. Ignored for control transfers.<br>
10787 + * One of the following values:
10788 + * - DWC_OTG_HC_PID_DATA0
10789 + * - DWC_OTG_HC_PID_DATA1
10791 + uint8_t data_toggle;
10793 + /** Ping state if 1. */
10794 + uint8_t ping_state;
10797 + * List of QTDs for this QH.
10799 + struct list_head qtd_list;
10801 + /** Host channel currently processing transfers for this QH. */
10802 + dwc_hc_t *channel;
10804 + /** QTD currently assigned to a host channel for this QH. */
10805 + dwc_otg_qtd_t *qtd_in_process;
10807 + /** Full/low speed endpoint on high-speed hub requires split. */
10808 + uint8_t do_split;
10810 + /** @name Periodic schedule information */
10813 + /** Bandwidth in microseconds per (micro)frame. */
10816 + /** Interval between transfers in (micro)frames. */
10817 + uint16_t interval;
10820 + * (micro)frame to initialize a periodic transfer. The transfer
10821 + * executes in the following (micro)frame.
10823 + uint16_t sched_frame;
10825 + /** (micro)frame at which last start split was initialized. */
10826 + uint16_t start_split_frame;
10830 + /** Entry for QH in either the periodic or non-periodic schedule. */
10831 + struct list_head qh_list_entry;
10835 + * This structure holds the state of the HCD, including the non-periodic and
10836 + * periodic schedules.
10838 +typedef struct dwc_otg_hcd {
10839 + /** The DWC otg device pointer */
10840 + struct dwc_otg_device *otg_dev;
10842 + /** DWC OTG Core Interface Layer */
10843 + dwc_otg_core_if_t *core_if;
10845 + /** Internal DWC HCD Flags */
10846 + volatile union dwc_otg_hcd_internal_flags {
10849 + unsigned port_connect_status_change : 1;
10850 + unsigned port_connect_status : 1;
10851 + unsigned port_reset_change : 1;
10852 + unsigned port_enable_change : 1;
10853 + unsigned port_suspend_change : 1;
10854 + unsigned port_over_current_change : 1;
10855 + unsigned reserved : 27;
10860 + * Inactive items in the non-periodic schedule. This is a list of
10861 + * Queue Heads. Transfers associated with these Queue Heads are not
10862 + * currently assigned to a host channel.
10864 + struct list_head non_periodic_sched_inactive;
10867 + * Active items in the non-periodic schedule. This is a list of
10868 + * Queue Heads. Transfers associated with these Queue Heads are
10869 + * currently assigned to a host channel.
10871 + struct list_head non_periodic_sched_active;
10874 + * Pointer to the next Queue Head to process in the active
10875 + * non-periodic schedule.
10877 + struct list_head *non_periodic_qh_ptr;
10880 + * Inactive items in the periodic schedule. This is a list of QHs for
10881 + * periodic transfers that are _not_ scheduled for the next frame.
10882 + * Each QH in the list has an interval counter that determines when it
10883 + * needs to be scheduled for execution. This scheduling mechanism
10884 + * allows only a simple calculation for periodic bandwidth used (i.e.
10885 + * must assume that all periodic transfers may need to execute in the
10886 + * same frame). However, it greatly simplifies scheduling and should
10887 + * be sufficient for the vast majority of OTG hosts, which need to
10888 + * connect to a small number of peripherals at one time.
10890 + * Items move from this list to periodic_sched_ready when the QH
10891 + * interval counter is 0 at SOF.
10893 + struct list_head periodic_sched_inactive;
10896 + * List of periodic QHs that are ready for execution in the next
10897 + * frame, but have not yet been assigned to host channels.
10899 + * Items move from this list to periodic_sched_assigned as host
10900 + * channels become available during the current frame.
10902 + struct list_head periodic_sched_ready;
10905 + * List of periodic QHs to be executed in the next frame that are
10906 + * assigned to host channels.
10908 + * Items move from this list to periodic_sched_queued as the
10909 + * transactions for the QH are queued to the DWC_otg controller.
10911 + struct list_head periodic_sched_assigned;
10914 + * List of periodic QHs that have been queued for execution.
10916 + * Items move from this list to either periodic_sched_inactive or
10917 + * periodic_sched_ready when the channel associated with the transfer
10918 + * is released. If the interval for the QH is 1, the item moves to
10919 + * periodic_sched_ready because it must be rescheduled for the next
10920 + * frame. Otherwise, the item moves to periodic_sched_inactive.
10922 + struct list_head periodic_sched_queued;
10925 + * Total bandwidth claimed so far for periodic transfers. This value
10926 + * is in microseconds per (micro)frame. The assumption is that all
10927 + * periodic transfers may occur in the same (micro)frame.
10929 + uint16_t periodic_usecs;
10932 + * Frame number read from the core at SOF. The value ranges from 0 to
10933 + * DWC_HFNUM_MAX_FRNUM.
10935 + uint16_t frame_number;
10938 + * Free host channels in the controller. This is a list of
10939 + * dwc_hc_t items.
10941 + struct list_head free_hc_list;
10944 + * Number of host channels assigned to periodic transfers. Currently
10945 + * assuming that there is a dedicated host channel for each periodic
10946 + * transaction and at least one host channel available for
10947 + * non-periodic transactions.
10949 + int periodic_channels;
10952 + * Number of host channels assigned to non-periodic transfers.
10954 + int non_periodic_channels;
10957 + * Array of pointers to the host channel descriptors. Allows accessing
10958 + * a host channel descriptor given the host channel number. This is
10959 + * useful in interrupt handlers.
10961 + dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
10964 + * Buffer to use for any data received during the status phase of a
10965 + * control transfer. Normally no data is transferred during the status
10966 + * phase. This buffer is used as a bit bucket.
10968 + uint8_t *status_buf;
10971 + * DMA address for status_buf.
10973 + dma_addr_t status_buf_dma;
10974 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
10977 + * Structure to allow starting the HCD in a non-interrupt context
10978 + * during an OTG role change.
10980 + struct delayed_work start_work;
10983 + * Connection timer. An OTG host must display a message if the device
10984 + * does not connect. Started when the VBus power is turned on via
10985 + * sysfs attribute "buspower".
10987 + struct timer_list conn_timer;
10989 + /* Tasket to do a reset */
10990 + struct tasklet_struct *reset_tasklet;
10996 + uint32_t frrem_samples;
10997 + uint64_t frrem_accum;
10999 + uint32_t hfnum_7_samples_a;
11000 + uint64_t hfnum_7_frrem_accum_a;
11001 + uint32_t hfnum_0_samples_a;
11002 + uint64_t hfnum_0_frrem_accum_a;
11003 + uint32_t hfnum_other_samples_a;
11004 + uint64_t hfnum_other_frrem_accum_a;
11006 + uint32_t hfnum_7_samples_b;
11007 + uint64_t hfnum_7_frrem_accum_b;
11008 + uint32_t hfnum_0_samples_b;
11009 + uint64_t hfnum_0_frrem_accum_b;
11010 + uint32_t hfnum_other_samples_b;
11011 + uint64_t hfnum_other_frrem_accum_b;
11015 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
11016 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
11018 + return (dwc_otg_hcd_t *)(hcd->hcd_priv);
11021 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
11022 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
11024 + return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
11027 +/** @name HCD Create/Destroy Functions */
11029 +extern int dwc_otg_hcd_init(struct platform_device *pdev);
11030 +extern void dwc_otg_hcd_remove(struct platform_device *pdev);
11033 +/** @name Linux HC Driver API Functions */
11036 +extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
11037 +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
11038 +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
11039 +extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
11040 +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
11041 + // struct usb_host_endpoint *ep,
11045 +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
11046 + struct urb *urb, int status);
11047 +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
11048 + struct usb_host_endpoint *ep);
11049 +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
11050 +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
11052 +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
11061 +/** @name Transaction Execution Functions */
11063 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
11064 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
11065 + dwc_otg_transaction_type_e tr_type);
11066 +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
11070 +/** @name Interrupt Handler Functions */
11072 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11073 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11074 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11075 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11076 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11077 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11078 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11079 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11080 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11081 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11082 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
11083 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11084 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11088 +/** @name Schedule Queue Functions */
11091 +/* Implemented in dwc_otg_hcd_queue.c */
11092 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
11093 +extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
11094 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11095 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11096 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11097 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
11099 +/** Remove and free a QH */
11100 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
11101 + dwc_otg_qh_t *qh)
11103 + dwc_otg_hcd_qh_remove(hcd, qh);
11104 + dwc_otg_hcd_qh_free(hcd, qh);
11107 +/** Allocates memory for a QH structure.
11108 + * @return Returns the memory allocate or NULL on error. */
11109 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
11111 + return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
11114 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
11115 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
11116 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
11118 +/** Allocates memory for a QTD structure.
11119 + * @return Returns the memory allocate or NULL on error. */
11120 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
11122 + return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
11125 +/** Frees the memory for a QTD structure. QTD should already be removed from
11127 + * @param[in] qtd QTD to free.*/
11128 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
11133 +/** Removes a QTD from list.
11134 + * @param[in] hcd HCD instance.
11135 + * @param[in] qtd QTD to remove from list. */
11136 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
11138 + unsigned long flags;
11139 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
11140 + list_del(&qtd->qtd_list_entry);
11141 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
11144 +/** Remove and free a QTD */
11145 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
11147 + dwc_otg_hcd_qtd_remove(hcd, qtd);
11148 + dwc_otg_hcd_qtd_free(qtd);
11154 +/** @name Internal Functions */
11156 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
11157 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
11158 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
11161 +/** Gets the usb_host_endpoint associated with an URB. */
11162 +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
11164 + struct usb_device *dev = urb->dev;
11165 + int ep_num = usb_pipeendpoint(urb->pipe);
11167 + if (usb_pipein(urb->pipe))
11168 + return dev->ep_in[ep_num];
11170 + return dev->ep_out[ep_num];
11174 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
11175 + * qualified with its direction (possible 32 endpoints per device).
11177 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
11178 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
11180 +/** Gets the QH that contains the list_head */
11181 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
11183 +/** Gets the QTD that contains the list_head */
11184 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
11186 +/** Check if QH is non-periodic */
11187 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
11188 + (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
11190 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
11191 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
11193 +/** Packet size for any kind of endpoint descriptor */
11194 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
11197 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
11198 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
11199 + * frame number when the max frame number is reached.
11201 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
11203 + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
11204 + (DWC_HFNUM_MAX_FRNUM >> 1);
11208 + * Returns true if _frame1 is greater than _frame2. The comparison is done
11209 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
11210 + * number when the max frame number is reached.
11212 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
11214 + return (frame1 != frame2) &&
11215 + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
11216 + (DWC_HFNUM_MAX_FRNUM >> 1));
11220 + * Increments _frame by the amount specified by _inc. The addition is done
11221 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
11223 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
11225 + return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
11228 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
11230 + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
11233 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
11235 + return frame & 0x7;
11240 + * Macro to sample the remaining PHY clocks left in the current frame. This
11241 + * may be used during debugging to determine the average time it takes to
11242 + * execute sections of code. There are two possible sample points, "a" and
11243 + * "b", so the _letter argument must be one of these values.
11245 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
11246 + * example, "cat /sys/devices/lm0/hcd_frrem".
11248 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
11250 + hfnum_data_t hfnum; \
11251 + dwc_otg_qtd_t *qtd; \
11252 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
11253 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
11254 + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
11255 + switch (hfnum.b.frnum & 0x7) { \
11257 + _hcd->hfnum_7_samples_##_letter++; \
11258 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
11261 + _hcd->hfnum_0_samples_##_letter++; \
11262 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
11265 + _hcd->hfnum_other_samples_##_letter++; \
11266 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
11272 +#define dwc_sample_frrem(_hcd, _qh, _letter)
11275 +#endif /* DWC_DEVICE_ONLY */
11277 +++ b/drivers/usb/dwc/otg_hcd_intr.c
11279 +/* ==========================================================================
11280 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
11281 + * $Revision: #70 $
11282 + * $Date: 2008/10/16 $
11283 + * $Change: 1117667 $
11285 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
11286 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
11287 + * otherwise expressly agreed to in writing between Synopsys and you.
11289 + * The Software IS NOT an item of Licensed Software or Licensed Product under
11290 + * any End User Software License Agreement or Agreement for Licensed Product
11291 + * with Synopsys or any supplement thereto. You are permitted to use and
11292 + * redistribute this Software in source and binary forms, with or without
11293 + * modification, provided that redistributions of source code must retain this
11294 + * notice. You may not view, use, disclose, copy or distribute this file or
11295 + * any information contained herein except pursuant to this license grant from
11296 + * Synopsys. If you do not agree with this notice, including the disclaimer
11297 + * below, then you are not authorized to use the Software.
11299 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
11300 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11301 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11302 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
11303 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11304 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11305 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
11306 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
11307 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
11308 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11310 + * ========================================================================== */
11311 +#ifndef DWC_DEVICE_ONLY
11313 +#include <linux/version.h>
11315 +#include "otg_driver.h"
11316 +#include "otg_hcd.h"
11317 +#include "otg_regs.h"
11320 + * This file contains the implementation of the HCD Interrupt handlers.
11323 +/** This function handles interrupts for the HCD. */
11324 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11328 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
11329 + gintsts_data_t gintsts;
11331 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
11334 + /* Check if HOST Mode */
11335 + if (dwc_otg_is_host_mode(core_if)) {
11336 + gintsts.d32 = dwc_otg_read_core_intr(core_if);
11337 + if (!gintsts.d32) {
11342 + /* Don't print debug message in the interrupt handler on SOF */
11343 +# ifndef DEBUG_SOF
11344 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
11346 + DWC_DEBUGPL(DBG_HCD, "\n");
11350 +# ifndef DEBUG_SOF
11351 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
11353 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
11355 + if (gintsts.b.usbreset) {
11356 + DWC_PRINT("Usb Reset In Host Mode\n");
11358 + if (gintsts.b.sofintr) {
11359 + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
11361 + if (gintsts.b.rxstsqlvl) {
11362 + retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd);
11364 + if (gintsts.b.nptxfempty) {
11365 + retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd);
11367 + if (gintsts.b.i2cintr) {
11368 + /** @todo Implement i2cintr handler. */
11370 + if (gintsts.b.portintr) {
11371 + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
11373 + if (gintsts.b.hcintr) {
11374 + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
11376 + if (gintsts.b.ptxfempty) {
11377 + retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd);
11380 +# ifndef DEBUG_SOF
11381 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
11384 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
11385 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
11386 + dwc_read_reg32(&global_regs->gintsts));
11387 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
11388 + dwc_read_reg32(&global_regs->gintmsk));
11393 +# ifndef DEBUG_SOF
11394 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
11396 + DWC_DEBUGPL(DBG_HCD, "\n");
11400 + S3C2410X_CLEAR_EINTPEND();
11405 +#ifdef DWC_TRACK_MISSED_SOFS
11406 +#warning Compiling code to track missed SOFs
11407 +#define FRAME_NUM_ARRAY_SIZE 1000
11409 + * This function is for debug only.
11411 +static inline void track_missed_sofs(uint16_t curr_frame_number)
11413 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
11414 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
11415 + static int frame_num_idx = 0;
11416 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
11417 + static int dumped_frame_num_array = 0;
11419 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
11420 + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) {
11421 + frame_num_array[frame_num_idx] = curr_frame_number;
11422 + last_frame_num_array[frame_num_idx++] = last_frame_num;
11424 + } else if (!dumped_frame_num_array) {
11426 + printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
11427 + printk(KERN_EMERG USB_DWC "----- ----------\n");
11428 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
11429 + printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
11430 + frame_num_array[i], last_frame_num_array[i]);
11432 + dumped_frame_num_array = 1;
11434 + last_frame_num = curr_frame_number;
11439 + * Handles the start-of-frame interrupt in host mode. Non-periodic
11440 + * transactions may be queued to the DWC_otg controller for the current
11441 + * (micro)frame. Periodic transactions may be queued to the controller for the
11442 + * next (micro)frame.
11444 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
11446 + hfnum_data_t hfnum;
11447 + struct list_head *qh_entry;
11448 + dwc_otg_qh_t *qh;
11449 + dwc_otg_transaction_type_e tr_type;
11450 + gintsts_data_t gintsts = {.d32 = 0};
11452 + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
11455 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
11457 + hcd->frame_number = hfnum.b.frnum;
11460 + hcd->frrem_accum += hfnum.b.frrem;
11461 + hcd->frrem_samples++;
11464 +#ifdef DWC_TRACK_MISSED_SOFS
11465 + track_missed_sofs(hcd->frame_number);
11468 + /* Determine whether any periodic QHs should be executed. */
11469 + qh_entry = hcd->periodic_sched_inactive.next;
11470 + while (qh_entry != &hcd->periodic_sched_inactive) {
11471 + qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
11472 + qh_entry = qh_entry->next;
11473 + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
11475 + * Move QH to the ready list to be executed next
11478 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready);
11482 + tr_type = dwc_otg_hcd_select_transactions(hcd);
11483 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
11484 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
11487 + /* Clear interrupt */
11488 + gintsts.b.sofintr = 1;
11489 + dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
11494 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
11495 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
11496 + * memory if the DWC_otg controller is operating in Slave mode. */
11497 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11499 + host_grxsts_data_t grxsts;
11500 + dwc_hc_t *hc = NULL;
11502 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
11504 + grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
11506 + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
11508 + /* Packet Status */
11509 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
11510 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
11511 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
11512 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
11514 + switch (grxsts.b.pktsts) {
11515 + case DWC_GRXSTS_PKTSTS_IN:
11516 + /* Read the data into the host buffer. */
11517 + if (grxsts.b.bcnt > 0) {
11518 + dwc_otg_read_packet(dwc_otg_hcd->core_if,
11522 + /* Update the HC fields for the next packet received. */
11523 + hc->xfer_count += grxsts.b.bcnt;
11524 + hc->xfer_buff += grxsts.b.bcnt;
11527 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
11528 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
11529 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
11530 + /* Handled in interrupt, just ignore data */
11533 + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
11540 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
11541 + * data packets may be written to the FIFO for OUT transfers. More requests
11542 + * may be written to the non-periodic request queue for IN transfers. This
11543 + * interrupt is enabled only in Slave mode. */
11544 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11546 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
11547 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
11548 + DWC_OTG_TRANSACTION_NON_PERIODIC);
11552 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
11553 + * packets may be written to the FIFO for OUT transfers. More requests may be
11554 + * written to the periodic request queue for IN transfers. This interrupt is
11555 + * enabled only in Slave mode. */
11556 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11558 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
11559 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
11560 + DWC_OTG_TRANSACTION_PERIODIC);
11564 +/** There are multiple conditions that can cause a port interrupt. This function
11565 + * determines which interrupt conditions have occurred and handles them
11566 + * appropriately. */
11567 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11570 + hprt0_data_t hprt0;
11571 + hprt0_data_t hprt0_modify;
11573 + hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
11574 + hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
11576 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
11579 + hprt0_modify.b.prtena = 0;
11580 + hprt0_modify.b.prtconndet = 0;
11581 + hprt0_modify.b.prtenchng = 0;
11582 + hprt0_modify.b.prtovrcurrchng = 0;
11584 + /* Port Connect Detected
11585 + * Set flag and clear if detected */
11586 + if (hprt0.b.prtconndet) {
11587 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
11588 + "Port Connect Detected--\n", hprt0.d32);
11589 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
11590 + dwc_otg_hcd->flags.b.port_connect_status = 1;
11591 + hprt0_modify.b.prtconndet = 1;
11593 + /* B-Device has connected, Delete the connection timer. */
11594 + del_timer( &dwc_otg_hcd->conn_timer );
11596 + /* The Hub driver asserts a reset when it sees port connect
11597 + * status change flag */
11601 + /* Port Enable Changed
11602 + * Clear if detected - Set internal flag if disabled */
11603 + if (hprt0.b.prtenchng) {
11604 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11605 + "Port Enable Changed--\n", hprt0.d32);
11606 + hprt0_modify.b.prtenchng = 1;
11607 + if (hprt0.b.prtena == 1) {
11608 + int do_reset = 0;
11609 + dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params;
11610 + dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs;
11611 + dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if;
11613 + /* Check if we need to adjust the PHY clock speed for
11614 + * low power and adjust it */
11615 + if (params->host_support_fs_ls_low_power) {
11616 + gusbcfg_data_t usbcfg;
11618 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
11620 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
11621 + hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
11625 + hcfg_data_t hcfg;
11626 + if (usbcfg.b.phylpwrclksel == 0) {
11627 + /* Set PHY low power clock select for FS/LS devices */
11628 + usbcfg.b.phylpwrclksel = 1;
11629 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11633 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
11635 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
11636 + params->host_ls_low_power_phy_clk ==
11637 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
11639 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
11640 + if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
11641 + hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
11642 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
11648 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
11649 + if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
11650 + hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
11651 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
11660 + if (usbcfg.b.phylpwrclksel == 1) {
11661 + usbcfg.b.phylpwrclksel = 0;
11662 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11668 + tasklet_schedule(dwc_otg_hcd->reset_tasklet);
11673 + /* Port has been enabled set the reset change flag */
11674 + dwc_otg_hcd->flags.b.port_reset_change = 1;
11677 + dwc_otg_hcd->flags.b.port_enable_change = 1;
11682 + /** Overcurrent Change Interrupt */
11683 + if (hprt0.b.prtovrcurrchng) {
11684 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11685 + "Port Overcurrent Changed--\n", hprt0.d32);
11686 + dwc_otg_hcd->flags.b.port_over_current_change = 1;
11687 + hprt0_modify.b.prtovrcurrchng = 1;
11691 + /* Clear Port Interrupts */
11692 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
11697 +/** This interrupt indicates that one or more host channels has a pending
11698 + * interrupt. There are multiple conditions that can cause each host channel
11699 + * interrupt. This function determines which conditions have occurred for each
11700 + * host channel interrupt and handles them appropriately. */
11701 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11705 + haint_data_t haint;
11707 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
11710 + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
11712 + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
11713 + if (haint.b2.chint & (1 << i)) {
11714 + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
11721 +/* Macro used to clear one channel interrupt */
11722 +#define clear_hc_int(_hc_regs_, _intr_) \
11724 + hcint_data_t hcint_clear = {.d32 = 0}; \
11725 + hcint_clear.b._intr_ = 1; \
11726 + dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
11730 + * Macro used to disable one channel interrupt. Channel interrupts are
11731 + * disabled when the channel is halted or released by the interrupt handler.
11732 + * There is no need to handle further interrupts of that type until the
11733 + * channel is re-assigned. In fact, subsequent handling may cause crashes
11734 + * because the channel structures are cleaned up when the channel is released.
11736 +#define disable_hc_int(_hc_regs_, _intr_) \
11738 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
11739 + hcintmsk.b._intr_ = 1; \
11740 + dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
11744 + * Gets the actual length of a transfer after the transfer halts. _halt_status
11745 + * holds the reason for the halt.
11747 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
11748 + * *short_read is set to 1 upon return if less than the requested
11749 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
11750 + * return. short_read may also be NULL on entry, in which case it remains
11753 +static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
11754 + dwc_otg_hc_regs_t *hc_regs,
11755 + dwc_otg_qtd_t *qtd,
11756 + dwc_otg_halt_status_e halt_status,
11759 + hctsiz_data_t hctsiz;
11762 + if (short_read != NULL) {
11765 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11767 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
11768 + if (hc->ep_is_in) {
11769 + length = hc->xfer_len - hctsiz.b.xfersize;
11770 + if (short_read != NULL) {
11771 + *short_read = (hctsiz.b.xfersize != 0);
11773 + } else if (hc->qh->do_split) {
11774 + length = qtd->ssplit_out_xfer_count;
11776 + length = hc->xfer_len;
11780 + * Must use the hctsiz.pktcnt field to determine how much data
11781 + * has been transferred. This field reflects the number of
11782 + * packets that have been transferred via the USB. This is
11783 + * always an integral number of packets if the transfer was
11784 + * halted before its normal completion. (Can't use the
11785 + * hctsiz.xfersize field because that reflects the number of
11786 + * bytes transferred via the AHB, not the USB).
11788 + length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
11795 + * Updates the state of the URB after a Transfer Complete interrupt on the
11796 + * host channel. Updates the actual_length field of the URB based on the
11797 + * number of bytes transferred via the host channel. Sets the URB status
11798 + * if the data transfer is finished.
11800 + * @return 1 if the data transfer specified by the URB is completely finished,
11803 +static int update_urb_state_xfer_comp(dwc_hc_t *hc,
11804 + dwc_otg_hc_regs_t *hc_regs,
11806 + dwc_otg_qtd_t *qtd)
11808 + int xfer_done = 0;
11809 + int short_read = 0;
11811 + urb->actual_length += get_actual_xfer_length(hc, hc_regs, qtd,
11812 + DWC_OTG_HC_XFER_COMPLETE,
11815 + if (short_read || urb->actual_length == urb->transfer_buffer_length) {
11817 + if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) {
11818 + urb->status = -EREMOTEIO;
11826 + hctsiz_data_t hctsiz;
11827 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11828 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11829 + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
11830 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
11831 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
11832 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
11833 + urb->transfer_buffer_length);
11834 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
11835 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
11836 + short_read, xfer_done);
11840 + return xfer_done;
11844 + * Save the starting data toggle for the next transfer. The data toggle is
11845 + * saved in the QH for non-control transfers and it's saved in the QTD for
11846 + * control transfers.
11848 +static void save_data_toggle(dwc_hc_t *hc,
11849 + dwc_otg_hc_regs_t *hc_regs,
11850 + dwc_otg_qtd_t *qtd)
11852 + hctsiz_data_t hctsiz;
11853 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11855 + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
11856 + dwc_otg_qh_t *qh = hc->qh;
11857 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11858 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
11860 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
11863 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11864 + qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
11866 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
11872 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
11873 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
11874 + * still linked to the QH, the QH is added to the end of the inactive
11875 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
11876 + * schedule if no more QTDs are linked to the QH.
11878 +static void deactivate_qh(dwc_otg_hcd_t *hcd,
11879 + dwc_otg_qh_t *qh,
11882 + int continue_split = 0;
11883 + dwc_otg_qtd_t *qtd;
11885 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
11887 + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11889 + if (qtd->complete_split) {
11890 + continue_split = 1;
11891 + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
11892 + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
11893 + continue_split = 1;
11897 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
11898 + continue_split = 0;
11901 + qh->channel = NULL;
11902 + qh->qtd_in_process = NULL;
11903 + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
11907 + * Updates the state of an Isochronous URB when the transfer is stopped for
11908 + * any reason. The fields of the current entry in the frame descriptor array
11909 + * are set based on the transfer state and the input _halt_status. Completes
11910 + * the Isochronous URB if all the URB frames have been completed.
11912 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
11913 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
11915 +static dwc_otg_halt_status_e
11916 +update_isoc_urb_state(dwc_otg_hcd_t *hcd,
11918 + dwc_otg_hc_regs_t *hc_regs,
11919 + dwc_otg_qtd_t *qtd,
11920 + dwc_otg_halt_status_e halt_status)
11922 + struct urb *urb = qtd->urb;
11923 + dwc_otg_halt_status_e ret_val = halt_status;
11924 + struct usb_iso_packet_descriptor *frame_desc;
11926 + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
11927 + switch (halt_status) {
11928 + case DWC_OTG_HC_XFER_COMPLETE:
11929 + frame_desc->status = 0;
11930 + frame_desc->actual_length =
11931 + get_actual_xfer_length(hc, hc_regs, qtd,
11932 + halt_status, NULL);
11934 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
11935 + urb->error_count++;
11936 + if (hc->ep_is_in) {
11937 + frame_desc->status = -ENOSR;
11939 + frame_desc->status = -ECOMM;
11941 + frame_desc->actual_length = 0;
11943 + case DWC_OTG_HC_XFER_BABBLE_ERR:
11944 + urb->error_count++;
11945 + frame_desc->status = -EOVERFLOW;
11946 + /* Don't need to update actual_length in this case. */
11948 + case DWC_OTG_HC_XFER_XACT_ERR:
11949 + urb->error_count++;
11950 + frame_desc->status = -EPROTO;
11951 + frame_desc->actual_length =
11952 + get_actual_xfer_length(hc, hc_regs, qtd,
11953 + halt_status, NULL);
11955 + DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
11961 + if (++qtd->isoc_frame_index == urb->number_of_packets) {
11963 + * urb->status is not used for isoc transfers.
11964 + * The individual frame_desc statuses are used instead.
11966 + dwc_otg_hcd_complete_urb(hcd, urb, 0);
11967 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
11969 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
11976 + * Releases a host channel for use by other transfers. Attempts to select and
11977 + * queue more transactions since at least one host channel is available.
11979 + * @param hcd The HCD state structure.
11980 + * @param hc The host channel to release.
11981 + * @param qtd The QTD associated with the host channel. This QTD may be freed
11982 + * if the transfer is complete or an error has occurred.
11983 + * @param halt_status Reason the channel is being released. This status
11984 + * determines the actions taken by this function.
11986 +static void release_channel(dwc_otg_hcd_t *hcd,
11988 + dwc_otg_qtd_t *qtd,
11989 + dwc_otg_halt_status_e halt_status)
11991 + dwc_otg_transaction_type_e tr_type;
11994 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n",
11995 + __func__, hc->hc_num, halt_status);
11997 + switch (halt_status) {
11998 + case DWC_OTG_HC_XFER_URB_COMPLETE:
12001 + case DWC_OTG_HC_XFER_AHB_ERR:
12002 + case DWC_OTG_HC_XFER_STALL:
12003 + case DWC_OTG_HC_XFER_BABBLE_ERR:
12006 + case DWC_OTG_HC_XFER_XACT_ERR:
12007 + if (qtd->error_count >= 3) {
12008 + DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
12010 + qtd->urb->status = -EPROTO;
12011 + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
12016 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
12018 + * The QTD has already been removed and the QH has been
12019 + * deactivated. Don't want to do anything except release the
12020 + * host channel and try to queue more transfers.
12023 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
12024 + DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num);
12032 + deactivate_qh(hcd, hc->qh, free_qtd);
12036 + * Release the host channel for use by other transfers. The cleanup
12037 + * function clears the channel interrupt enables and conditions, so
12038 + * there's no need to clear the Channel Halted interrupt separately.
12040 + dwc_otg_hc_cleanup(hcd->core_if, hc);
12041 + list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
12043 + switch (hc->ep_type) {
12044 + case DWC_OTG_EP_TYPE_CONTROL:
12045 + case DWC_OTG_EP_TYPE_BULK:
12046 + hcd->non_periodic_channels--;
12051 + * Don't release reservations for periodic channels here.
12052 + * That's done when a periodic transfer is descheduled (i.e.
12053 + * when the QH is removed from the periodic schedule).
12058 + /* Try to queue more transfers now that there's a free channel. */
12059 + tr_type = dwc_otg_hcd_select_transactions(hcd);
12060 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
12061 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
12066 + * Halts a host channel. If the channel cannot be halted immediately because
12067 + * the request queue is full, this function ensures that the FIFO empty
12068 + * interrupt for the appropriate queue is enabled so that the halt request can
12069 + * be queued when there is space in the request queue.
12071 + * This function may also be called in DMA mode. In that case, the channel is
12072 + * simply released since the core always halts the channel automatically in
12075 +static void halt_channel(dwc_otg_hcd_t *hcd,
12077 + dwc_otg_qtd_t *qtd,
12078 + dwc_otg_halt_status_e halt_status)
12080 + if (hcd->core_if->dma_enable) {
12081 + release_channel(hcd, hc, qtd, halt_status);
12085 + /* Slave mode processing... */
12086 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
12088 + if (hc->halt_on_queue) {
12089 + gintmsk_data_t gintmsk = {.d32 = 0};
12090 + dwc_otg_core_global_regs_t *global_regs;
12091 + global_regs = hcd->core_if->core_global_regs;
12093 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
12094 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
12096 + * Make sure the Non-periodic Tx FIFO empty interrupt
12097 + * is enabled so that the non-periodic schedule will
12100 + gintmsk.b.nptxfempty = 1;
12101 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
12104 + * Move the QH from the periodic queued schedule to
12105 + * the periodic assigned schedule. This allows the
12106 + * halt to be queued when the periodic schedule is
12109 + list_move(&hc->qh->qh_list_entry,
12110 + &hcd->periodic_sched_assigned);
12113 + * Make sure the Periodic Tx FIFO Empty interrupt is
12114 + * enabled so that the periodic schedule will be
12117 + gintmsk.b.ptxfempty = 1;
12118 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
12124 + * Performs common cleanup for non-periodic transfers after a Transfer
12125 + * Complete interrupt. This function should be called after any endpoint type
12126 + * specific handling is finished to release the host channel.
12128 +static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
12130 + dwc_otg_hc_regs_t *hc_regs,
12131 + dwc_otg_qtd_t *qtd,
12132 + dwc_otg_halt_status_e halt_status)
12134 + hcint_data_t hcint;
12136 + qtd->error_count = 0;
12138 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12139 + if (hcint.b.nyet) {
12141 + * Got a NYET on the last transaction of the transfer. This
12142 + * means that the endpoint should be in the PING state at the
12143 + * beginning of the next transfer.
12145 + hc->qh->ping_state = 1;
12146 + clear_hc_int(hc_regs, nyet);
12150 + * Always halt and release the host channel to make it available for
12151 + * more transfers. There may still be more phases for a control
12152 + * transfer or more data packets for a bulk transfer at this point,
12153 + * but the host channel is still halted. A channel will be reassigned
12154 + * to the transfer when the non-periodic schedule is processed after
12155 + * the channel is released. This allows transactions to be queued
12156 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
12157 + * Tx FIFO Empty interrupt if necessary.
12159 + if (hc->ep_is_in) {
12161 + * IN transfers in Slave mode require an explicit disable to
12162 + * halt the channel. (In DMA mode, this call simply releases
12165 + halt_channel(hcd, hc, qtd, halt_status);
12168 + * The channel is automatically disabled by the core for OUT
12169 + * transfers in Slave mode.
12171 + release_channel(hcd, hc, qtd, halt_status);
12176 + * Performs common cleanup for periodic transfers after a Transfer Complete
12177 + * interrupt. This function should be called after any endpoint type specific
12178 + * handling is finished to release the host channel.
12180 +static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
12182 + dwc_otg_hc_regs_t *hc_regs,
12183 + dwc_otg_qtd_t *qtd,
12184 + dwc_otg_halt_status_e halt_status)
12186 + hctsiz_data_t hctsiz;
12187 + qtd->error_count = 0;
12189 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12190 + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
12191 + /* Core halts channel in these cases. */
12192 + release_channel(hcd, hc, qtd, halt_status);
12194 + /* Flush any outstanding requests from the Tx queue. */
12195 + halt_channel(hcd, hc, qtd, halt_status);
12200 + * Handles a host channel Transfer Complete interrupt. This handler may be
12201 + * called in either DMA mode or Slave mode.
12203 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
12205 + dwc_otg_hc_regs_t *hc_regs,
12206 + dwc_otg_qtd_t *qtd)
12208 + int urb_xfer_done;
12209 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
12210 + struct urb *urb = qtd->urb;
12211 + int pipe_type = usb_pipetype(urb->pipe);
12213 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12214 + "Transfer Complete--\n", hc->hc_num);
12217 + * Handle xfer complete on CSPLIT.
12219 + if (hc->qh->do_split) {
12220 + qtd->complete_split = 0;
12223 + /* Update the QTD and URB states. */
12224 + switch (pipe_type) {
12225 + case PIPE_CONTROL:
12226 + switch (qtd->control_phase) {
12227 + case DWC_OTG_CONTROL_SETUP:
12228 + if (urb->transfer_buffer_length > 0) {
12229 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
12231 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
12233 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
12234 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
12236 + case DWC_OTG_CONTROL_DATA: {
12237 + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12238 + if (urb_xfer_done) {
12239 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
12240 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
12242 + save_data_toggle(hc, hc_regs, qtd);
12244 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
12247 + case DWC_OTG_CONTROL_STATUS:
12248 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
12249 + if (urb->status == -EINPROGRESS) {
12252 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12253 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
12257 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12260 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
12261 + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12262 + if (urb_xfer_done) {
12263 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12264 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
12266 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
12269 + save_data_toggle(hc, hc_regs, qtd);
12270 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12272 + case PIPE_INTERRUPT:
12273 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
12274 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12277 + * Interrupt URB is done on the first transfer complete
12280 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12281 + save_data_toggle(hc, hc_regs, qtd);
12282 + complete_periodic_xfer(hcd, hc, hc_regs, qtd,
12283 + DWC_OTG_HC_XFER_URB_COMPLETE);
12285 + case PIPE_ISOCHRONOUS:
12286 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
12287 + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
12288 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12289 + DWC_OTG_HC_XFER_COMPLETE);
12291 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12295 + disable_hc_int(hc_regs, xfercompl);
12301 + * Handles a host channel STALL interrupt. This handler may be called in
12302 + * either DMA mode or Slave mode.
12304 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
12306 + dwc_otg_hc_regs_t *hc_regs,
12307 + dwc_otg_qtd_t *qtd)
12309 + struct urb *urb = qtd->urb;
12310 + int pipe_type = usb_pipetype(urb->pipe);
12312 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12313 + "STALL Received--\n", hc->hc_num);
12315 + if (pipe_type == PIPE_CONTROL) {
12316 + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
12319 + if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
12320 + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
12322 + * USB protocol requires resetting the data toggle for bulk
12323 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
12324 + * setup command is issued to the endpoint. Anticipate the
12325 + * CLEAR_FEATURE command since a STALL has occurred and reset
12326 + * the data toggle now.
12328 + hc->qh->data_toggle = 0;
12331 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
12333 + disable_hc_int(hc_regs, stall);
12339 + * Updates the state of the URB when a transfer has been stopped due to an
12340 + * abnormal condition before the transfer completes. Modifies the
12341 + * actual_length field of the URB to reflect the number of bytes that have
12342 + * actually been transferred via the host channel.
12344 +static void update_urb_state_xfer_intr(dwc_hc_t *hc,
12345 + dwc_otg_hc_regs_t *hc_regs,
12347 + dwc_otg_qtd_t *qtd,
12348 + dwc_otg_halt_status_e halt_status)
12350 + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
12351 + halt_status, NULL);
12352 + urb->actual_length += bytes_transferred;
12356 + hctsiz_data_t hctsiz;
12357 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12358 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
12359 + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
12360 + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count);
12361 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
12362 + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
12363 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
12364 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
12365 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
12366 + urb->transfer_buffer_length);
12372 + * Handles a host channel NAK interrupt. This handler may be called in either
12373 + * DMA mode or Slave mode.
12375 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
12377 + dwc_otg_hc_regs_t *hc_regs,
12378 + dwc_otg_qtd_t *qtd)
12380 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12381 + "NAK Received--\n", hc->hc_num);
12384 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
12385 + * interrupt. Re-start the SSPLIT transfer.
12387 + if (hc->do_split) {
12388 + if (hc->complete_split) {
12389 + qtd->error_count = 0;
12391 + qtd->complete_split = 0;
12392 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12393 + goto handle_nak_done;
12396 + switch (usb_pipetype(qtd->urb->pipe)) {
12397 + case PIPE_CONTROL:
12399 + if (hcd->core_if->dma_enable && hc->ep_is_in) {
12401 + * NAK interrupts are enabled on bulk/control IN
12402 + * transfers in DMA mode for the sole purpose of
12403 + * resetting the error count after a transaction error
12404 + * occurs. The core will continue transferring data.
12406 + qtd->error_count = 0;
12407 + goto handle_nak_done;
12411 + * NAK interrupts normally occur during OUT transfers in DMA
12412 + * or Slave mode. For IN transfers, more requests will be
12413 + * queued as request queue space is available.
12415 + qtd->error_count = 0;
12417 + if (!hc->qh->ping_state) {
12418 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
12419 + qtd, DWC_OTG_HC_XFER_NAK);
12420 + save_data_toggle(hc, hc_regs, qtd);
12421 + if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
12422 + hc->qh->ping_state = 1;
12427 + * Halt the channel so the transfer can be re-started from
12428 + * the appropriate point or the PING protocol will
12429 + * start/continue.
12431 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12433 + case PIPE_INTERRUPT:
12434 + qtd->error_count = 0;
12435 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12437 + case PIPE_ISOCHRONOUS:
12438 + /* Should never get called for isochronous transfers. */
12444 + disable_hc_int(hc_regs, nak);
12450 + * Handles a host channel ACK interrupt. This interrupt is enabled when
12451 + * performing the PING protocol in Slave mode, when errors occur during
12452 + * either Slave mode or DMA mode, and during Start Split transactions.
12454 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
12456 + dwc_otg_hc_regs_t *hc_regs,
12457 + dwc_otg_qtd_t *qtd)
12459 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12460 + "ACK Received--\n", hc->hc_num);
12462 + if (hc->do_split) {
12464 + * Handle ACK on SSPLIT.
12465 + * ACK should not occur in CSPLIT.
12467 + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
12468 + qtd->ssplit_out_xfer_count = hc->xfer_len;
12470 + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
12471 + /* Don't need complete for isochronous out transfers. */
12472 + qtd->complete_split = 1;
12476 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
12477 + switch (hc->xact_pos) {
12478 + case DWC_HCSPLIT_XACTPOS_ALL:
12480 + case DWC_HCSPLIT_XACTPOS_END:
12481 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
12482 + qtd->isoc_split_offset = 0;
12484 + case DWC_HCSPLIT_XACTPOS_BEGIN:
12485 + case DWC_HCSPLIT_XACTPOS_MID:
12487 + * For BEGIN or MID, calculate the length for
12488 + * the next microframe to determine the correct
12489 + * SSPLIT token, either MID or END.
12492 + struct usb_iso_packet_descriptor *frame_desc;
12494 + frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
12495 + qtd->isoc_split_offset += 188;
12497 + if ((frame_desc->length - qtd->isoc_split_offset) <= 188) {
12498 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
12500 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
12507 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
12510 + qtd->error_count = 0;
12512 + if (hc->qh->ping_state) {
12513 + hc->qh->ping_state = 0;
12515 + * Halt the channel so the transfer can be re-started
12516 + * from the appropriate point. This only happens in
12517 + * Slave mode. In DMA mode, the ping_state is cleared
12518 + * when the transfer is started because the core
12519 + * automatically executes the PING, then the transfer.
12521 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
12526 + * If the ACK occurred when _not_ in the PING state, let the channel
12527 + * continue transferring data after clearing the error count.
12530 + disable_hc_int(hc_regs, ack);
12536 + * Handles a host channel NYET interrupt. This interrupt should only occur on
12537 + * Bulk and Control OUT endpoints and for complete split transactions. If a
12538 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
12539 + * handled in the xfercomp interrupt handler, not here. This handler may be
12540 + * called in either DMA mode or Slave mode.
12542 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
12544 + dwc_otg_hc_regs_t *hc_regs,
12545 + dwc_otg_qtd_t *qtd)
12547 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12548 + "NYET Received--\n", hc->hc_num);
12552 + * re-do the CSPLIT immediately on non-periodic
12554 + if (hc->do_split && hc->complete_split) {
12555 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
12556 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
12557 + int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
12559 + if (dwc_full_frame_num(frnum) !=
12560 + dwc_full_frame_num(hc->qh->sched_frame)) {
12562 + * No longer in the same full speed frame.
12563 + * Treat this as a transaction error.
12566 + /** @todo Fix system performance so this can
12567 + * be treated as an error. Right now complete
12568 + * splits cannot be scheduled precisely enough
12569 + * due to other system activity, so this error
12570 + * occurs regularly in Slave mode.
12572 + qtd->error_count++;
12574 + qtd->complete_split = 0;
12575 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12576 + /** @todo add support for isoc release */
12577 + goto handle_nyet_done;
12581 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
12582 + goto handle_nyet_done;
12585 + hc->qh->ping_state = 1;
12586 + qtd->error_count = 0;
12588 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
12589 + DWC_OTG_HC_XFER_NYET);
12590 + save_data_toggle(hc, hc_regs, qtd);
12593 + * Halt the channel and re-start the transfer so the PING
12594 + * protocol will start.
12596 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
12599 + disable_hc_int(hc_regs, nyet);
12604 + * Handles a host channel babble interrupt. This handler may be called in
12605 + * either DMA mode or Slave mode.
12607 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
12609 + dwc_otg_hc_regs_t *hc_regs,
12610 + dwc_otg_qtd_t *qtd)
12612 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12613 + "Babble Error--\n", hc->hc_num);
12614 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
12615 + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
12616 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
12618 + dwc_otg_halt_status_e halt_status;
12619 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12620 + DWC_OTG_HC_XFER_BABBLE_ERR);
12621 + halt_channel(hcd, hc, qtd, halt_status);
12623 + disable_hc_int(hc_regs, bblerr);
12628 + * Handles a host channel AHB error interrupt. This handler is only called in
12631 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
12633 + dwc_otg_hc_regs_t *hc_regs,
12634 + dwc_otg_qtd_t *qtd)
12636 + hcchar_data_t hcchar;
12637 + hcsplt_data_t hcsplt;
12638 + hctsiz_data_t hctsiz;
12640 + struct urb *urb = qtd->urb;
12642 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12643 + "AHB Error--\n", hc->hc_num);
12645 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12646 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
12647 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12648 + hcdma = dwc_read_reg32(&hc_regs->hcdma);
12650 + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
12651 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
12652 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
12653 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
12654 + DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
12655 + DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
12656 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
12657 + DWC_ERROR(" Endpoint type: %s\n",
12658 + ({char *pipetype;
12659 + switch (usb_pipetype(urb->pipe)) {
12660 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
12661 + case PIPE_BULK: pipetype = "BULK"; break;
12662 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
12663 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
12664 + default: pipetype = "UNKNOWN"; break;
12666 + DWC_ERROR(" Speed: %s\n",
12668 + switch (urb->dev->speed) {
12669 + case USB_SPEED_HIGH: speed = "HIGH"; break;
12670 + case USB_SPEED_FULL: speed = "FULL"; break;
12671 + case USB_SPEED_LOW: speed = "LOW"; break;
12672 + default: speed = "UNKNOWN"; break;
12674 + DWC_ERROR(" Max packet size: %d\n",
12675 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12676 + DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
12677 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
12678 + urb->transfer_buffer, (void *)urb->transfer_dma);
12679 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
12680 + urb->setup_packet, (void *)urb->setup_dma);
12681 + DWC_ERROR(" Interval: %d\n", urb->interval);
12683 + dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
12686 + * Force a channel halt. Don't call halt_channel because that won't
12687 + * write to the HCCHARn register in DMA mode to force the halt.
12689 + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
12691 + disable_hc_int(hc_regs, ahberr);
12696 + * Handles a host channel transaction error interrupt. This handler may be
12697 + * called in either DMA mode or Slave mode.
12699 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
12701 + dwc_otg_hc_regs_t *hc_regs,
12702 + dwc_otg_qtd_t *qtd)
12704 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12705 + "Transaction Error--\n", hc->hc_num);
12707 + switch (usb_pipetype(qtd->urb->pipe)) {
12708 + case PIPE_CONTROL:
12710 + qtd->error_count++;
12711 + if (!hc->qh->ping_state) {
12712 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
12713 + qtd, DWC_OTG_HC_XFER_XACT_ERR);
12714 + save_data_toggle(hc, hc_regs, qtd);
12715 + if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) {
12716 + hc->qh->ping_state = 1;
12721 + * Halt the channel so the transfer can be re-started from
12722 + * the appropriate point or the PING protocol will start.
12724 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12726 + case PIPE_INTERRUPT:
12727 + qtd->error_count++;
12728 + if (hc->do_split && hc->complete_split) {
12729 + qtd->complete_split = 0;
12731 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12733 + case PIPE_ISOCHRONOUS:
12735 + dwc_otg_halt_status_e halt_status;
12736 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12737 + DWC_OTG_HC_XFER_XACT_ERR);
12739 + halt_channel(hcd, hc, qtd, halt_status);
12744 + disable_hc_int(hc_regs, xacterr);
12750 + * Handles a host channel frame overrun interrupt. This handler may be called
12751 + * in either DMA mode or Slave mode.
12753 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
12755 + dwc_otg_hc_regs_t *hc_regs,
12756 + dwc_otg_qtd_t *qtd)
12758 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12759 + "Frame Overrun--\n", hc->hc_num);
12761 + switch (usb_pipetype(qtd->urb->pipe)) {
12762 + case PIPE_CONTROL:
12765 + case PIPE_INTERRUPT:
12766 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
12768 + case PIPE_ISOCHRONOUS:
12770 + dwc_otg_halt_status_e halt_status;
12771 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12772 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
12774 + halt_channel(hcd, hc, qtd, halt_status);
12779 + disable_hc_int(hc_regs, frmovrun);
12785 + * Handles a host channel data toggle error interrupt. This handler may be
12786 + * called in either DMA mode or Slave mode.
12788 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
12790 + dwc_otg_hc_regs_t *hc_regs,
12791 + dwc_otg_qtd_t *qtd)
12793 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12794 + "Data Toggle Error--\n", hc->hc_num);
12796 + if (hc->ep_is_in) {
12797 + qtd->error_count = 0;
12799 + DWC_ERROR("Data Toggle Error on OUT transfer,"
12800 + "channel %d\n", hc->hc_num);
12803 + disable_hc_int(hc_regs, datatglerr);
12810 + * This function is for debug only. It checks that a valid halt status is set
12811 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
12812 + * taken and a warning is issued.
12813 + * @return 1 if halt status is ok, 0 otherwise.
12815 +static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
12817 + dwc_otg_hc_regs_t *hc_regs,
12818 + dwc_otg_qtd_t *qtd)
12820 + hcchar_data_t hcchar;
12821 + hctsiz_data_t hctsiz;
12822 + hcint_data_t hcint;
12823 + hcintmsk_data_t hcintmsk;
12824 + hcsplt_data_t hcsplt;
12826 + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
12828 + * This code is here only as a check. This condition should
12829 + * never happen. Ignore the halt if it does occur.
12831 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12832 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12833 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12834 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12835 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
12836 + DWC_WARN("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
12837 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
12838 + "hcint 0x%08x, hcintmsk 0x%08x, "
12839 + "hcsplt 0x%08x, qtd->complete_split %d\n",
12840 + __func__, hc->hc_num, hcchar.d32, hctsiz.d32,
12841 + hcint.d32, hcintmsk.d32,
12842 + hcsplt.d32, qtd->complete_split);
12844 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
12845 + __func__, hc->hc_num);
12847 + clear_hc_int(hc_regs, chhltd);
12852 + * This code is here only as a check. hcchar.chdis should
12853 + * never be set when the halt interrupt occurs. Halt the
12854 + * channel again if it does occur.
12856 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12857 + if (hcchar.b.chdis) {
12858 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
12859 + "hcchar 0x%08x, trying to halt again\n",
12860 + __func__, hcchar.d32);
12861 + clear_hc_int(hc_regs, chhltd);
12862 + hc->halt_pending = 0;
12863 + halt_channel(hcd, hc, qtd, hc->halt_status);
12872 + * Handles a host Channel Halted interrupt in DMA mode. This handler
12873 + * determines the reason the channel halted and proceeds accordingly.
12875 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
12877 + dwc_otg_hc_regs_t *hc_regs,
12878 + dwc_otg_qtd_t *qtd)
12880 + hcint_data_t hcint;
12881 + hcintmsk_data_t hcintmsk;
12882 + int out_nak_enh = 0;
12884 + /* For core with OUT NAK enhancement, the flow for high-
12885 + * speed CONTROL/BULK OUT is handled a little differently.
12887 + if (hcd->core_if->snpsid >= 0x4F54271A) {
12888 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
12889 + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
12890 + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
12891 + DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
12894 + DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
12897 + DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
12900 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
12901 + hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
12903 + * Just release the channel. A dequeue can happen on a
12904 + * transfer timeout. In the case of an AHB Error, the channel
12905 + * was forced to halt because there's no way to gracefully
12908 + release_channel(hcd, hc, qtd, hc->halt_status);
12912 + /* Read the HCINTn register to determine the cause for the halt. */
12913 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12914 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12916 + if (hcint.b.xfercomp) {
12917 + /** @todo This is here because of a possible hardware bug. Spec
12918 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
12919 + * interrupt w/ACK bit set should occur, but I only see the
12920 + * XFERCOMP bit, even with it masked out. This is a workaround
12921 + * for that behavior. Should fix this when hardware is fixed.
12923 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
12924 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
12926 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
12927 + } else if (hcint.b.stall) {
12928 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
12929 + } else if (hcint.b.xacterr) {
12930 + if (out_nak_enh) {
12931 + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
12932 + printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
12933 + qtd->error_count = 0;
12935 + printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
12940 + * Must handle xacterr before nak or ack. Could get a xacterr
12941 + * at the same time as either of these on a BULK/CONTROL OUT
12942 + * that started with a PING. The xacterr takes precedence.
12944 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
12945 + } else if (!out_nak_enh) {
12946 + if (hcint.b.nyet) {
12948 + * Must handle nyet before nak or ack. Could get a nyet at the
12949 + * same time as either of those on a BULK/CONTROL OUT that
12950 + * started with a PING. The nyet takes precedence.
12952 + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
12953 + } else if (hcint.b.bblerr) {
12954 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
12955 + } else if (hcint.b.frmovrun) {
12956 + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
12957 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
12959 + * If nak is not masked, it's because a non-split IN transfer
12960 + * is in an error state. In that case, the nak is handled by
12961 + * the nak interrupt handler, not here. Handle nak here for
12962 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
12963 + * rewinding the buffer pointer.
12965 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
12966 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
12968 + * If ack is not masked, it's because a non-split IN transfer
12969 + * is in an error state. In that case, the ack is handled by
12970 + * the ack interrupt handler, not here. Handle ack here for
12971 + * split transfers. Start splits halt on ACK.
12973 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
12975 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
12976 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
12978 + * A periodic transfer halted with no other channel
12979 + * interrupts set. Assume it was halted by the core
12980 + * because it could not be completed in its scheduled
12984 + DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
12985 + __func__, hc->hc_num);
12987 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
12989 + DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
12990 + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
12991 + __func__, hc->hc_num, hcint.d32,
12992 + dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
12996 + printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
13001 + * Handles a host channel Channel Halted interrupt.
13003 + * In slave mode, this handler is called only when the driver specifically
13004 + * requests a halt. This occurs during handling other host channel interrupts
13005 + * (e.g. nak, xacterr, stall, nyet, etc.).
13007 + * In DMA mode, this is the interrupt that occurs when the core has finished
13008 + * processing a transfer on a channel. Other host channel interrupts (except
13009 + * ahberr) are disabled in DMA mode.
13011 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
13013 + dwc_otg_hc_regs_t *hc_regs,
13014 + dwc_otg_qtd_t *qtd)
13016 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
13017 + "Channel Halted--\n", hc->hc_num);
13019 + if (hcd->core_if->dma_enable) {
13020 + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
13023 + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
13027 + release_channel(hcd, hc, qtd, hc->halt_status);
13033 +/** Handles interrupt for a specific Host Channel */
13034 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
13037 + hcint_data_t hcint;
13038 + hcintmsk_data_t hcintmsk;
13040 + dwc_otg_hc_regs_t *hc_regs;
13041 + dwc_otg_qtd_t *qtd;
13043 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
13045 + hc = dwc_otg_hcd->hc_ptr_array[num];
13046 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
13047 + qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
13049 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
13050 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
13051 + DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
13052 + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
13053 + hcint.d32 = hcint.d32 & hcintmsk.d32;
13055 + if (!dwc_otg_hcd->core_if->dma_enable) {
13056 + if (hcint.b.chhltd && hcint.d32 != 0x2) {
13057 + hcint.b.chhltd = 0;
13061 + if (hcint.b.xfercomp) {
13062 + retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13064 + * If NYET occurred at same time as Xfer Complete, the NYET is
13065 + * handled by the Xfer Complete interrupt handler. Don't want
13066 + * to call the NYET interrupt handler in this case.
13068 + hcint.b.nyet = 0;
13070 + if (hcint.b.chhltd) {
13071 + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13073 + if (hcint.b.ahberr) {
13074 + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13076 + if (hcint.b.stall) {
13077 + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13079 + if (hcint.b.nak) {
13080 + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13082 + if (hcint.b.ack) {
13083 + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13085 + if (hcint.b.nyet) {
13086 + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13088 + if (hcint.b.xacterr) {
13089 + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13091 + if (hcint.b.bblerr) {
13092 + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13094 + if (hcint.b.frmovrun) {
13095 + retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13097 + if (hcint.b.datatglerr) {
13098 + retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13104 +#endif /* DWC_DEVICE_ONLY */
13106 +++ b/drivers/usb/dwc/otg_hcd_queue.c
13108 +/* ==========================================================================
13109 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
13110 + * $Revision: #33 $
13111 + * $Date: 2008/07/15 $
13112 + * $Change: 1064918 $
13114 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13115 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13116 + * otherwise expressly agreed to in writing between Synopsys and you.
13118 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13119 + * any End User Software License Agreement or Agreement for Licensed Product
13120 + * with Synopsys or any supplement thereto. You are permitted to use and
13121 + * redistribute this Software in source and binary forms, with or without
13122 + * modification, provided that redistributions of source code must retain this
13123 + * notice. You may not view, use, disclose, copy or distribute this file or
13124 + * any information contained herein except pursuant to this license grant from
13125 + * Synopsys. If you do not agree with this notice, including the disclaimer
13126 + * below, then you are not authorized to use the Software.
13128 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13129 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13130 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13131 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13132 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13133 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13134 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13135 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13136 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13137 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13139 + * ========================================================================== */
13140 +#ifndef DWC_DEVICE_ONLY
13145 + * This file contains the functions to manage Queue Heads and Queue
13146 + * Transfer Descriptors.
13148 +#include <linux/kernel.h>
13149 +#include <linux/module.h>
13150 +#include <linux/moduleparam.h>
13151 +#include <linux/init.h>
13152 +#include <linux/device.h>
13153 +#include <linux/errno.h>
13154 +#include <linux/list.h>
13155 +#include <linux/interrupt.h>
13156 +#include <linux/string.h>
13157 +#include <linux/version.h>
13159 +#include <mach/irqs.h>
13161 +#include "otg_driver.h"
13162 +#include "otg_hcd.h"
13163 +#include "otg_regs.h"
13166 + * This function allocates and initializes a QH.
13168 + * @param hcd The HCD state structure for the DWC OTG controller.
13169 + * @param[in] urb Holds the information about the device/endpoint that we need
13170 + * to initialize the QH.
13172 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
13173 +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
13175 + dwc_otg_qh_t *qh;
13177 + /* Allocate memory */
13178 + /** @todo add memflags argument */
13179 + qh = dwc_otg_hcd_qh_alloc ();
13180 + if (qh == NULL) {
13184 + dwc_otg_hcd_qh_init (hcd, qh, urb);
13188 +/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
13189 + * removed from a list. QTD list should already be empty if called from URB
13192 + * @param[in] hcd HCD instance.
13193 + * @param[in] qh The QH to free.
13195 +void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13197 + dwc_otg_qtd_t *qtd;
13198 + struct list_head *pos;
13199 + //unsigned long flags;
13201 + /* Free each QTD in the QTD list */
13204 + //the spinlock is locked before this function get called,
13205 + //but in case the lock is needed, the check function is preserved
13207 + //but in non-SMP mode, all spinlock is lockable.
13208 + //don't do the test in non-SMP mode
13210 + if(spin_trylock(&hcd->lock)) {
13211 + printk("%s: It is not supposed to be lockable!!\n",__func__);
13215 +// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
13216 + for (pos = qh->qtd_list.next;
13217 + pos != &qh->qtd_list;
13218 + pos = qh->qtd_list.next)
13221 + qtd = dwc_list_to_qtd (pos);
13222 + dwc_otg_hcd_qtd_free (qtd);
13224 +// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
13230 +/** Initializes a QH structure.
13232 + * @param[in] hcd The HCD state structure for the DWC OTG controller.
13233 + * @param[in] qh The QH to init.
13234 + * @param[in] urb Holds the information about the device/endpoint that we need
13235 + * to initialize the QH. */
13236 +#define SCHEDULE_SLOP 10
13237 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
13239 + char *speed, *type;
13240 + memset (qh, 0, sizeof (dwc_otg_qh_t));
13242 + /* Initialize QH */
13243 + switch (usb_pipetype(urb->pipe)) {
13244 + case PIPE_CONTROL:
13245 + qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
13248 + qh->ep_type = USB_ENDPOINT_XFER_BULK;
13250 + case PIPE_ISOCHRONOUS:
13251 + qh->ep_type = USB_ENDPOINT_XFER_ISOC;
13253 + case PIPE_INTERRUPT:
13254 + qh->ep_type = USB_ENDPOINT_XFER_INT;
13258 + qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
13260 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
13261 + qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
13262 + INIT_LIST_HEAD(&qh->qtd_list);
13263 + INIT_LIST_HEAD(&qh->qh_list_entry);
13264 + qh->channel = NULL;
13266 + /* FS/LS Enpoint on HS Hub
13267 + * NOT virtual root hub */
13268 + qh->do_split = 0;
13269 + if (((urb->dev->speed == USB_SPEED_LOW) ||
13270 + (urb->dev->speed == USB_SPEED_FULL)) &&
13271 + (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
13273 + DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
13274 + usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
13275 + urb->dev->ttport);
13276 + qh->do_split = 1;
13279 + if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
13280 + qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
13281 + /* Compute scheduling parameters once and save them. */
13282 + hprt0_data_t hprt;
13284 + /** @todo Account for split transfers in the bus time. */
13285 + int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
13286 + qh->usecs = usb_calc_bus_time(urb->dev->speed,
13287 + usb_pipein(urb->pipe),
13288 + (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
13291 + /* Start in a slightly future (micro)frame. */
13292 + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
13294 + qh->interval = urb->interval;
13296 + /* Increase interrupt polling rate for debugging. */
13297 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13298 + qh->interval = 8;
13301 + hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
13302 + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
13303 + ((urb->dev->speed == USB_SPEED_LOW) ||
13304 + (urb->dev->speed == USB_SPEED_FULL))) {
13305 + qh->interval *= 8;
13306 + qh->sched_frame |= 0x7;
13307 + qh->start_split_frame = qh->sched_frame;
13312 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
13313 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
13314 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
13315 + urb->dev->devnum);
13316 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
13317 + usb_pipeendpoint(urb->pipe),
13318 + usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
13320 + switch(urb->dev->speed) {
13321 + case USB_SPEED_LOW:
13324 + case USB_SPEED_FULL:
13327 + case USB_SPEED_HIGH:
13334 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
13336 + switch (qh->ep_type) {
13337 + case USB_ENDPOINT_XFER_ISOC:
13338 + type = "isochronous";
13340 + case USB_ENDPOINT_XFER_INT:
13341 + type = "interrupt";
13343 + case USB_ENDPOINT_XFER_CONTROL:
13344 + type = "control";
13346 + case USB_ENDPOINT_XFER_BULK:
13353 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
13356 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13357 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
13359 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
13368 + * Checks that a channel is available for a periodic transfer.
13370 + * @return 0 if successful, negative error code otherise.
13372 +static int periodic_channel_available(dwc_otg_hcd_t *hcd)
13375 + * Currently assuming that there is a dedicated host channnel for each
13376 + * periodic transaction plus at least one host channel for
13377 + * non-periodic transactions.
13380 + int num_channels;
13382 + num_channels = hcd->core_if->core_params->host_channels;
13383 + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
13384 + (hcd->periodic_channels < num_channels - 1)) {
13388 + DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
13389 + __func__, num_channels, hcd->periodic_channels,
13390 + hcd->non_periodic_channels);
13391 + status = -ENOSPC;
13398 + * Checks that there is sufficient bandwidth for the specified QH in the
13399 + * periodic schedule. For simplicity, this calculation assumes that all the
13400 + * transfers in the periodic schedule may occur in the same (micro)frame.
13402 + * @param hcd The HCD state structure for the DWC OTG controller.
13403 + * @param qh QH containing periodic bandwidth required.
13405 + * @return 0 if successful, negative error code otherwise.
13407 +static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13410 + uint16_t max_claimed_usecs;
13414 + if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
13416 + * High speed mode.
13417 + * Max periodic usecs is 80% x 125 usec = 100 usec.
13419 + max_claimed_usecs = 100 - qh->usecs;
13422 + * Full speed mode.
13423 + * Max periodic usecs is 90% x 1000 usec = 900 usec.
13425 + max_claimed_usecs = 900 - qh->usecs;
13428 + if (hcd->periodic_usecs > max_claimed_usecs) {
13429 + DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
13430 + __func__, hcd->periodic_usecs, qh->usecs);
13431 + status = -ENOSPC;
13438 + * Checks that the max transfer size allowed in a host channel is large enough
13439 + * to handle the maximum data transfer in a single (micro)frame for a periodic
13442 + * @param hcd The HCD state structure for the DWC OTG controller.
13443 + * @param qh QH for a periodic endpoint.
13445 + * @return 0 if successful, negative error code otherwise.
13447 +static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13450 + uint32_t max_xfer_size;
13451 + uint32_t max_channel_xfer_size;
13455 + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
13456 + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
13458 + if (max_xfer_size > max_channel_xfer_size) {
13459 + DWC_NOTICE("%s: Periodic xfer length %d > "
13460 + "max xfer length for channel %d\n",
13461 + __func__, max_xfer_size, max_channel_xfer_size);
13462 + status = -ENOSPC;
13469 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
13471 + * @param hcd The HCD state structure for the DWC OTG controller.
13472 + * @param qh QH for the periodic transfer. The QH should already contain the
13473 + * scheduling information.
13475 + * @return 0 if successful, negative error code otherwise.
13477 +static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13481 + status = periodic_channel_available(hcd);
13483 + DWC_NOTICE("%s: No host channel available for periodic "
13484 + "transfer.\n", __func__);
13488 + status = check_periodic_bandwidth(hcd, qh);
13490 + DWC_NOTICE("%s: Insufficient periodic bandwidth for "
13491 + "periodic transfer.\n", __func__);
13495 + status = check_max_xfer_size(hcd, qh);
13497 + DWC_NOTICE("%s: Channel max transfer size too small "
13498 + "for periodic transfer.\n", __func__);
13502 + /* Always start in the inactive schedule. */
13503 + list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
13505 + /* Reserve the periodic channel. */
13506 + hcd->periodic_channels++;
13508 + /* Update claimed usecs per (micro)frame. */
13509 + hcd->periodic_usecs += qh->usecs;
13511 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
13512 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval;
13513 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13514 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++;
13515 + DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
13516 + qh, qh->usecs, qh->interval);
13518 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++;
13519 + DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
13520 + qh, qh->usecs, qh->interval);
13527 + * This function adds a QH to either the non periodic or periodic schedule if
13528 + * it is not already in the schedule. If the QH is already in the schedule, no
13529 + * action is taken.
13531 + * @return 0 if successful, negative error code otherwise.
13533 +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13535 + //unsigned long flags;
13539 + //the spinlock is locked before this function get called,
13540 + //but in case the lock is needed, the check function is preserved
13541 + //but in non-SMP mode, all spinlock is lockable.
13542 + //don't do the test in non-SMP mode
13544 + if(spin_trylock(&hcd->lock)) {
13545 + printk("%s: It is not supposed to be lockable!!\n",__func__);
13549 +// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
13551 + if (!list_empty(&qh->qh_list_entry)) {
13552 + /* QH already in a schedule. */
13556 + /* Add the new QH to the appropriate schedule */
13557 + if (dwc_qh_is_non_per(qh)) {
13558 + /* Always start in the inactive schedule. */
13559 + list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
13561 + status = schedule_periodic(hcd, qh);
13565 +// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
13571 + * Removes an interrupt or isochronous transfer from the periodic schedule.
13573 + * @param hcd The HCD state structure for the DWC OTG controller.
13574 + * @param qh QH for the periodic transfer.
13576 +static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13578 + list_del_init(&qh->qh_list_entry);
13580 + /* Release the periodic channel reservation. */
13581 + hcd->periodic_channels--;
13583 + /* Update claimed usecs per (micro)frame. */
13584 + hcd->periodic_usecs -= qh->usecs;
13586 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
13587 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval;
13589 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13590 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--;
13591 + DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
13592 + qh, qh->usecs, qh->interval);
13594 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--;
13595 + DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
13596 + qh, qh->usecs, qh->interval);
13601 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
13604 + * @param[in] hcd The HCD state structure.
13605 + * @param[in] qh QH to remove from schedule. */
13606 +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13608 + //unsigned long flags;
13611 + //the spinlock is locked before this function get called,
13612 + //but in case the lock is needed, the check function is preserved
13613 + //but in non-SMP mode, all spinlock is lockable.
13614 + //don't do the test in non-SMP mode
13616 + if(spin_trylock(&hcd->lock)) {
13617 + printk("%s: It is not supposed to be lockable!!\n",__func__);
13621 +// SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13623 + if (list_empty(&qh->qh_list_entry)) {
13624 + /* QH is not in a schedule. */
13628 + if (dwc_qh_is_non_per(qh)) {
13629 + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
13630 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
13632 + list_del_init(&qh->qh_list_entry);
13634 + deschedule_periodic(hcd, qh);
13638 +// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13643 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
13644 + * non-periodic schedule. The QH is added to the inactive non-periodic
13645 + * schedule if any QTDs are still attached to the QH.
13647 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
13648 + * there are any QTDs still attached to the QH, the QH is added to either the
13649 + * periodic inactive schedule or the periodic ready schedule and its next
13650 + * scheduled frame is calculated. The QH is placed in the ready schedule if
13651 + * the scheduled frame has been reached already. Otherwise it's placed in the
13652 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
13653 + * completely removed from the periodic schedule.
13655 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
13657 + unsigned long flags;
13658 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13660 + if (dwc_qh_is_non_per(qh)) {
13661 + dwc_otg_hcd_qh_remove(hcd, qh);
13662 + if (!list_empty(&qh->qtd_list)) {
13663 + /* Add back to inactive non-periodic schedule. */
13664 + dwc_otg_hcd_qh_add(hcd, qh);
13667 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
13669 + if (qh->do_split) {
13670 + /* Schedule the next continuing periodic split transfer */
13671 + if (sched_next_periodic_split) {
13673 + qh->sched_frame = frame_number;
13674 + if (dwc_frame_num_le(frame_number,
13675 + dwc_frame_num_inc(qh->start_split_frame, 1))) {
13677 + * Allow one frame to elapse after start
13678 + * split microframe before scheduling
13679 + * complete split, but DONT if we are
13680 + * doing the next start split in the
13681 + * same frame for an ISOC out.
13683 + if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
13684 + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
13688 + qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
13690 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
13691 + qh->sched_frame = frame_number;
13693 + qh->sched_frame |= 0x7;
13694 + qh->start_split_frame = qh->sched_frame;
13697 + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
13698 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
13699 + qh->sched_frame = frame_number;
13703 + if (list_empty(&qh->qtd_list)) {
13704 + dwc_otg_hcd_qh_remove(hcd, qh);
13707 + * Remove from periodic_sched_queued and move to
13708 + * appropriate queue.
13710 + if (qh->sched_frame == frame_number) {
13711 + list_move(&qh->qh_list_entry,
13712 + &hcd->periodic_sched_ready);
13714 + list_move(&qh->qh_list_entry,
13715 + &hcd->periodic_sched_inactive);
13720 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13724 + * This function allocates and initializes a QTD.
13726 + * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up
13727 + * pointing to each other so each pair should have a unique correlation.
13729 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
13730 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
13732 + dwc_otg_qtd_t *qtd;
13734 + qtd = dwc_otg_hcd_qtd_alloc ();
13735 + if (qtd == NULL) {
13739 + dwc_otg_hcd_qtd_init (qtd, urb);
13744 + * Initializes a QTD structure.
13746 + * @param[in] qtd The QTD to initialize.
13747 + * @param[in] urb The URB to use for initialization. */
13748 +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
13750 + memset (qtd, 0, sizeof (dwc_otg_qtd_t));
13752 + if (usb_pipecontrol(urb->pipe)) {
13754 + * The only time the QTD data toggle is used is on the data
13755 + * phase of control transfers. This phase always starts with
13758 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13759 + qtd->control_phase = DWC_OTG_CONTROL_SETUP;
13762 + /* start split */
13763 + qtd->complete_split = 0;
13764 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
13765 + qtd->isoc_split_offset = 0;
13767 + /* Store the qtd ptr in the urb to reference what QTD. */
13768 + urb->hcpriv = qtd;
13773 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
13774 + * QH to place the QTD into. If it does not find a QH, then it will create a
13775 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
13776 + * is placed into the proper schedule based on its EP type.
13778 + * @param[in] qtd The QTD to add
13779 + * @param[in] dwc_otg_hcd The DWC HCD structure
13781 + * @return 0 if successful, negative error code otherwise.
13783 +int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
13784 + dwc_otg_hcd_t *dwc_otg_hcd)
13786 + struct usb_host_endpoint *ep;
13787 + dwc_otg_qh_t *qh;
13788 + unsigned long flags;
13791 + struct urb *urb = qtd->urb;
13793 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
13796 + * Get the QH which holds the QTD-list to insert to. Create QH if it
13799 + ep = dwc_urb_to_endpoint(urb);
13800 + qh = (dwc_otg_qh_t *)ep->hcpriv;
13801 + if (qh == NULL) {
13802 + qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
13803 + if (qh == NULL) {
13809 + retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
13810 + if (retval == 0) {
13811 + list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
13815 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
13820 +#endif /* DWC_DEVICE_ONLY */
13822 +++ b/drivers/usb/dwc/otg_pcd.c
13824 +/* ==========================================================================
13825 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
13826 + * $Revision: #70 $
13827 + * $Date: 2008/10/14 $
13828 + * $Change: 1115682 $
13830 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13831 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13832 + * otherwise expressly agreed to in writing between Synopsys and you.
13834 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13835 + * any End User Software License Agreement or Agreement for Licensed Product
13836 + * with Synopsys or any supplement thereto. You are permitted to use and
13837 + * redistribute this Software in source and binary forms, with or without
13838 + * modification, provided that redistributions of source code must retain this
13839 + * notice. You may not view, use, disclose, copy or distribute this file or
13840 + * any information contained herein except pursuant to this license grant from
13841 + * Synopsys. If you do not agree with this notice, including the disclaimer
13842 + * below, then you are not authorized to use the Software.
13844 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13845 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13846 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13847 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13848 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13849 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13850 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13851 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13852 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13853 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13855 + * ========================================================================== */
13856 +#ifndef DWC_HOST_ONLY
13859 + * This file implements the Peripheral Controller Driver.
13861 + * The Peripheral Controller Driver (PCD) is responsible for
13862 + * translating requests from the Function Driver into the appropriate
13863 + * actions on the DWC_otg controller. It isolates the Function Driver
13864 + * from the specifics of the controller by providing an API to the
13865 + * Function Driver.
13867 + * The Peripheral Controller Driver for Linux will implement the
13868 + * Gadget API, so that the existing Gadget drivers can be used.
13869 + * (Gadget Driver is the Linux terminology for a Function Driver.)
13871 + * The Linux Gadget API is defined in the header file
13872 + * <code><linux/usb_gadget.h></code>. The USB EP operations API is
13873 + * defined in the structure <code>usb_ep_ops</code> and the USB
13874 + * Controller API is defined in the structure
13875 + * <code>usb_gadget_ops</code>.
13877 + * An important function of the PCD is managing interrupts generated
13878 + * by the DWC_otg controller. The implementation of the DWC_otg device
13879 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
13881 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
13882 + * @todo Does it work when the request size is greater than DEPTSIZ
13888 +#include <linux/kernel.h>
13889 +#include <linux/module.h>
13890 +#include <linux/moduleparam.h>
13891 +#include <linux/init.h>
13892 +#include <linux/device.h>
13893 +#include <linux/platform_device.h>
13894 +#include <linux/errno.h>
13895 +#include <linux/list.h>
13896 +#include <linux/interrupt.h>
13897 +#include <linux/string.h>
13898 +#include <linux/dma-mapping.h>
13899 +#include <linux/version.h>
13901 +#include <mach/irqs.h>
13902 +#include <linux/usb/ch9.h>
13904 +//#include <linux/usb_gadget.h>
13906 +#include "otg_driver.h"
13907 +#include "otg_pcd.h"
13912 + * Static PCD pointer for use in usb_gadget_register_driver and
13913 + * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
13915 +static dwc_otg_pcd_t *s_pcd = 0;
13918 +/* Display the contents of the buffer */
13919 +extern void dump_msg(const u8 *buf, unsigned int length);
13923 + * This function completes a request. It call's the request call back.
13925 +void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req,
13928 + unsigned stopped = ep->stopped;
13930 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
13931 + list_del_init(&req->queue);
13933 + if (req->req.status == -EINPROGRESS) {
13934 + req->req.status = status;
13936 + status = req->req.status;
13939 + /* don't modify queue heads during completion callback */
13941 + SPIN_UNLOCK(&ep->pcd->lock);
13942 + req->req.complete(&ep->ep, &req->req);
13943 + SPIN_LOCK(&ep->pcd->lock);
13945 + if (ep->pcd->request_pending > 0) {
13946 + --ep->pcd->request_pending;
13949 + ep->stopped = stopped;
13953 + * This function terminates all the requsts in the EP request queue.
13955 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep)
13957 + dwc_otg_pcd_request_t *req;
13961 + /* called with irqs blocked?? */
13962 + while (!list_empty(&ep->queue)) {
13963 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
13965 + dwc_otg_request_done(ep, req, -ESHUTDOWN);
13969 +/* USB Endpoint Operations */
13971 + * The following sections briefly describe the behavior of the Gadget
13972 + * API endpoint operations implemented in the DWC_otg driver
13973 + * software. Detailed descriptions of the generic behavior of each of
13974 + * these functions can be found in the Linux header file
13975 + * include/linux/usb_gadget.h.
13977 + * The Gadget API provides wrapper functions for each of the function
13978 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
13979 + * function, which then calls the underlying PCD function. The
13980 + * following sections are named according to the wrapper
13981 + * functions. Within each section, the corresponding DWC_otg PCD
13982 + * function name is specified.
13987 + * This function assigns periodic Tx FIFO to an periodic EP
13988 + * in shared Tx FIFO mode
13990 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if)
13992 + uint32_t PerTxMsk = 1;
13994 + for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i)
13996 + if((PerTxMsk & core_if->p_tx_msk) == 0) {
13997 + core_if->p_tx_msk |= PerTxMsk;
14005 + * This function releases periodic Tx FIFO
14006 + * in shared Tx FIFO mode
14008 +static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
14010 + core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
14013 + * This function assigns periodic Tx FIFO to an periodic EP
14014 + * in shared Tx FIFO mode
14016 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
14018 + uint32_t TxMsk = 1;
14021 + for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i)
14023 + if((TxMsk & core_if->tx_msk) == 0) {
14024 + core_if->tx_msk |= TxMsk;
14032 + * This function releases periodic Tx FIFO
14033 + * in shared Tx FIFO mode
14035 +static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
14037 + core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
14041 + * This function is called by the Gadget Driver for each EP to be
14042 + * configured for the current configuration (SET_CONFIGURATION).
14044 + * This function initializes the dwc_otg_ep_t data structure, and then
14045 + * calls dwc_otg_ep_activate.
14047 +static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep,
14048 + const struct usb_endpoint_descriptor *ep_desc)
14050 + dwc_otg_pcd_ep_t *ep = 0;
14051 + dwc_otg_pcd_t *pcd = 0;
14052 + unsigned long flags;
14054 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc);
14056 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14057 + if (!usb_ep || !ep_desc || ep->desc ||
14058 + ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
14059 + DWC_WARN("%s, bad ep or descriptor\n", __func__);
14062 + if (ep == &ep->pcd->ep0) {
14063 + DWC_WARN("%s, bad ep(0)\n", __func__);
14067 + /* Check FIFO size? */
14068 + if (!ep_desc->wMaxPacketSize) {
14069 + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
14074 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14075 + DWC_WARN("%s, bogus device state\n", __func__);
14076 + return -ESHUTDOWN;
14079 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
14081 + ep->desc = ep_desc;
14082 + ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize);
14085 + * Activate the EP
14089 + ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0;
14090 + ep->dwc_ep.maxpacket = ep->ep.maxpacket;
14092 + ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
14094 + if(ep->dwc_ep.is_in) {
14095 + if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) {
14096 + ep->dwc_ep.tx_fifo_num = 0;
14098 + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) {
14100 + * if ISOC EP then assign a Periodic Tx FIFO.
14102 + ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if);
14106 + * if Dedicated FIFOs mode is on then assign a Tx FIFO.
14108 + ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if);
14112 + /* Set initial data PID. */
14113 + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) {
14114 + ep->dwc_ep.data_pid_start = 0;
14117 + DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n",
14118 + ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"),
14119 + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
14121 + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) {
14122 + ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
14125 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
14126 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14132 + * This function is called when an EP is disabled due to disconnect or
14133 + * change in configuration. Any pending requests will terminate with a
14134 + * status of -ESHUTDOWN.
14136 + * This function modifies the dwc_otg_ep_t data structure for this EP,
14137 + * and then calls dwc_otg_ep_deactivate.
14139 +static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep)
14141 + dwc_otg_pcd_ep_t *ep;
14142 + dwc_otg_pcd_t *pcd = 0;
14143 + unsigned long flags;
14145 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep);
14146 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14147 + if (!usb_ep || !ep->desc) {
14148 + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
14149 + usb_ep ? ep->ep.name : NULL);
14153 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14155 + dwc_otg_request_nuke(ep);
14157 + dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
14161 + if(ep->dwc_ep.is_in) {
14162 + dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14163 + release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14164 + release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14167 + /* Free DMA Descriptors */
14170 + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
14172 + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) {
14173 + dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
14176 + DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name);
14182 + * This function allocates a request object to use with the specified
14185 + * @param ep The endpoint to be used with with the request
14186 + * @param gfp_flags the GFP_* flags to use.
14188 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
14191 + dwc_otg_pcd_request_t *req;
14193 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags);
14195 + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
14198 + req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags);
14200 + DWC_WARN("%s() %s\n", __func__,
14201 + "request allocation failed!\n");
14204 + memset(req, 0, sizeof(dwc_otg_pcd_request_t));
14205 + req->req.dma = DMA_ADDR_INVALID;
14206 + INIT_LIST_HEAD(&req->queue);
14207 + return &req->req;
14211 + * This function frees a request object.
14213 + * @param ep The endpoint associated with the request
14214 + * @param req The request being freed
14216 +static void dwc_otg_pcd_free_request(struct usb_ep *ep,
14217 + struct usb_request *req)
14219 + dwc_otg_pcd_request_t *request;
14220 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req);
14222 + if (0 == ep || 0 == req) {
14223 + DWC_WARN("%s() %s\n", __func__,
14224 + "Invalid ep or req argument!\n");
14228 + request = container_of(req, dwc_otg_pcd_request_t, req);
14234 + * This function allocates an I/O buffer to be used for a transfer
14235 + * to/from the specified endpoint.
14237 + * @param usb_ep The endpoint to be used with with the request
14238 + * @param bytes The desired number of bytes for the buffer
14239 + * @param dma Pointer to the buffer's DMA address; must be valid
14240 + * @param gfp_flags the GFP_* flags to use.
14241 + * @return address of a new buffer or null is buffer could not be allocated.
14243 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
14248 + dwc_otg_pcd_ep_t *ep;
14249 + dwc_otg_pcd_t *pcd = 0;
14251 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14254 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
14257 + /* Check dword alignment */
14258 + if ((bytes & 0x3UL) != 0) {
14259 + DWC_WARN("%s() Buffer size is not a multiple of"
14260 + "DWORD size (%d)",__func__, bytes);
14263 + if (GET_CORE_IF(pcd)->dma_enable) {
14264 + buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags);
14267 + buf = kmalloc(bytes, gfp_flags);
14270 + /* Check dword alignment */
14271 + if (((int)buf & 0x3UL) != 0) {
14272 + DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
14280 + * This function frees an I/O buffer that was allocated by alloc_buffer.
14282 + * @param usb_ep the endpoint associated with the buffer
14283 + * @param buf address of the buffer
14284 + * @param dma The buffer's DMA address
14285 + * @param bytes The number of bytes of the buffer
14287 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
14288 + dma_addr_t dma, unsigned bytes)
14290 + dwc_otg_pcd_ep_t *ep;
14291 + dwc_otg_pcd_t *pcd = 0;
14293 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14296 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes);
14298 + if (GET_CORE_IF(pcd)->dma_enable) {
14299 + dma_free_coherent (NULL, bytes, buf, dma);
14308 + * This function is used to submit an I/O Request to an EP.
14310 + * - When the request completes the request's completion callback
14311 + * is called to return the request to the driver.
14312 + * - An EP, except control EPs, may have multiple requests
14314 + * - Once submitted the request cannot be examined or modified.
14315 + * - Each request is turned into one or more packets.
14316 + * - A BULK EP can queue any amount of data; the transfer is
14318 + * - Zero length Packets are specified with the request 'zero'
14321 +static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep,
14322 + struct usb_request *usb_req,
14325 + int prevented = 0;
14326 + dwc_otg_pcd_request_t *req;
14327 + dwc_otg_pcd_ep_t *ep;
14328 + dwc_otg_pcd_t *pcd;
14329 + unsigned long flags = 0;
14331 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n",
14332 + __func__, usb_ep, usb_req, gfp_flags);
14334 + req = container_of(usb_req, dwc_otg_pcd_request_t, req);
14335 + if (!usb_req || !usb_req->complete || !usb_req->buf ||
14336 + !list_empty(&req->queue)) {
14337 + DWC_WARN("%s, bad params\n", __func__);
14341 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14342 + if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) {
14343 + DWC_WARN("%s, bad ep\n", __func__);
14348 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14349 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
14350 + DWC_WARN("%s, bogus device state\n", __func__);
14351 + return -ESHUTDOWN;
14355 + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
14356 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
14358 + if (!GET_CORE_IF(pcd)->core_params->opt) {
14359 + if (ep->dwc_ep.num != 0) {
14360 + DWC_ERROR("%s queue req %p, len %d buf %p\n",
14361 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
14365 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14367 +#if defined(DEBUG) & defined(VERBOSE)
14368 + dump_msg(usb_req->buf, usb_req->length);
14371 + usb_req->status = -EINPROGRESS;
14372 + usb_req->actual = 0;
14375 + * For EP0 IN without premature status, zlp is required?
14377 + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
14378 + DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name);
14379 + //_req->zero = 1;
14382 + /* Start the transfer */
14383 + if (list_empty(&ep->queue) && !ep->stopped) {
14384 + /* EP0 Transfer? */
14385 + if (ep->dwc_ep.num == 0) {
14386 + switch (pcd->ep0state) {
14387 + case EP0_IN_DATA_PHASE:
14388 + DWC_DEBUGPL(DBG_PCD,
14389 + "%s ep0: EP0_IN_DATA_PHASE\n",
14393 + case EP0_OUT_DATA_PHASE:
14394 + DWC_DEBUGPL(DBG_PCD,
14395 + "%s ep0: EP0_OUT_DATA_PHASE\n",
14397 + if (pcd->request_config) {
14398 + /* Complete STATUS PHASE */
14399 + ep->dwc_ep.is_in = 1;
14400 + pcd->ep0state = EP0_IN_STATUS_PHASE;
14404 + case EP0_IN_STATUS_PHASE:
14405 + DWC_DEBUGPL(DBG_PCD,
14406 + "%s ep0: EP0_IN_STATUS_PHASE\n",
14411 + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
14413 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14416 + ep->dwc_ep.dma_addr = usb_req->dma;
14417 + ep->dwc_ep.start_xfer_buff = usb_req->buf;
14418 + ep->dwc_ep.xfer_buff = usb_req->buf;
14419 + ep->dwc_ep.xfer_len = usb_req->length;
14420 + ep->dwc_ep.xfer_count = 0;
14421 + ep->dwc_ep.sent_zlp = 0;
14422 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
14424 + if(usb_req->zero) {
14425 + if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0)
14426 + && (ep->dwc_ep.xfer_len != 0)) {
14427 + ep->dwc_ep.sent_zlp = 1;
14432 + ep_check_and_patch_dma_addr(ep);
14433 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
14437 + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
14439 + /* Setup and start the Transfer */
14440 + ep->dwc_ep.dma_addr = usb_req->dma;
14441 + ep->dwc_ep.start_xfer_buff = usb_req->buf;
14442 + ep->dwc_ep.xfer_buff = usb_req->buf;
14443 + ep->dwc_ep.sent_zlp = 0;
14444 + ep->dwc_ep.total_len = usb_req->length;
14445 + ep->dwc_ep.xfer_len = 0;
14446 + ep->dwc_ep.xfer_count = 0;
14448 + if(max_transfer > MAX_TRANSFER_SIZE) {
14449 + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
14451 + ep->dwc_ep.maxxfer = max_transfer;
14454 + if(usb_req->zero) {
14455 + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
14456 + && (ep->dwc_ep.total_len != 0)) {
14457 + ep->dwc_ep.sent_zlp = 1;
14462 + ep_check_and_patch_dma_addr(ep);
14463 + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
14467 + if ((req != 0) || prevented) {
14468 + ++pcd->request_pending;
14469 + list_add_tail(&req->queue, &ep->queue);
14470 + if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) {
14471 + /** @todo NGS Create a function for this. */
14472 + diepmsk_data_t diepmsk = { .d32 = 0};
14473 + diepmsk.b.intktxfemp = 1;
14474 + if(&GET_CORE_IF(pcd)->multiproc_int_enable) {
14475 + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num],
14478 + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
14483 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14488 + * This function cancels an I/O request from an EP.
14490 +static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep,
14491 + struct usb_request *usb_req)
14493 + dwc_otg_pcd_request_t *req;
14494 + dwc_otg_pcd_ep_t *ep;
14495 + dwc_otg_pcd_t *pcd;
14496 + unsigned long flags;
14498 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req);
14500 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14501 + if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) {
14502 + DWC_WARN("%s, bad argument\n", __func__);
14506 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14507 + DWC_WARN("%s, bogus device state\n", __func__);
14508 + return -ESHUTDOWN;
14511 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
14512 + DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name,
14513 + ep->dwc_ep.is_in ? "IN" : "OUT",
14516 + /* make sure it's actually queued on this endpoint */
14517 + list_for_each_entry(req, &ep->queue, queue)
14519 + if (&req->req == usb_req) {
14524 + if (&req->req != usb_req) {
14525 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14529 + if (!list_empty(&req->queue)) {
14530 + dwc_otg_request_done(ep, req, -ECONNRESET);
14536 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14538 + return req ? 0 : -EOPNOTSUPP;
14542 + * usb_ep_set_halt stalls an endpoint.
14544 + * usb_ep_clear_halt clears an endpoint halt and resets its data
14547 + * Both of these functions are implemented with the same underlying
14548 + * function. The behavior depends on the value argument.
14550 + * @param[in] usb_ep the Endpoint to halt or clear halt.
14551 + * @param[in] value
14552 + * - 0 means clear_halt.
14553 + * - 1 means set_halt,
14554 + * - 2 means clear stall lock flag.
14555 + * - 3 means set stall lock flag.
14557 +static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value)
14560 + unsigned long flags;
14561 + dwc_otg_pcd_ep_t *ep = 0;
14564 + DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value);
14566 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14568 + if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) ||
14569 + ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
14570 + DWC_WARN("%s, bad ep\n", __func__);
14574 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14575 + if (!list_empty(&ep->queue)) {
14576 + DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name);
14577 + retval = -EAGAIN;
14579 + else if (value == 0) {
14580 + dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if,
14583 + else if(value == 1) {
14584 + if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) {
14585 + dtxfsts_data_t txstatus;
14586 + fifosize_data_t txfifosize;
14588 + txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]);
14589 + txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts);
14591 + if(txstatus.b.txfspcavail < txfifosize.b.depth) {
14592 + DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name);
14593 + retval = -EAGAIN;
14596 + if (ep->dwc_ep.num == 0) {
14597 + ep->pcd->ep0state = EP0_STALL;
14601 + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
14606 + if (ep->dwc_ep.num == 0) {
14607 + ep->pcd->ep0state = EP0_STALL;
14611 + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
14615 + else if (value == 2) {
14616 + ep->dwc_ep.stall_clear_flag = 0;
14618 + else if (value == 3) {
14619 + ep->dwc_ep.stall_clear_flag = 1;
14622 + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
14627 + * This function allocates a DMA Descriptor chain for the Endpoint
14628 + * buffer to be used for a transfer to/from the specified endpoint.
14630 +dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count)
14633 + return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL);
14636 +LIST_HEAD(tofree_list);
14637 +DEFINE_SPINLOCK(tofree_list_lock);
14639 +struct free_param {
14640 + struct list_head list;
14643 + dma_addr_t dma_addr;
14646 +void free_list_agent_fn(void *data){
14647 + struct list_head free_list;
14648 + struct free_param *cur,*next;
14650 + spin_lock(&tofree_list_lock);
14651 + list_add(&free_list,&tofree_list);
14652 + list_del_init(&tofree_list);
14653 + spin_unlock(&tofree_list_lock);
14655 + list_for_each_entry_safe(cur,next,&free_list,list){
14656 + if(cur==&free_list) break;
14657 + dma_free_coherent(NULL,cur->size,cur->addr,cur->dma_addr);
14658 + list_del(&cur->list);
14662 +DECLARE_WORK(free_list_agent,free_list_agent_fn);
14664 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
14666 +void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count)
14668 + if(irqs_disabled()){
14669 + struct free_param* fp=kmalloc(sizeof(struct free_param),GFP_KERNEL);
14670 + fp->addr=desc_addr;
14671 + fp->dma_addr=dma_desc_addr;
14672 + fp->size=count*sizeof(dwc_otg_dma_desc_t);
14674 + spin_lock(&tofree_list_lock);
14675 + list_add(&fp->list,&tofree_list);
14676 + spin_unlock(&tofree_list_lock);
14678 + schedule_work(&free_list_agent);
14681 + dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr);
14684 +#ifdef DWC_EN_ISOC
14687 + * This function initializes a descriptor chain for Isochronous transfer
14689 + * @param core_if Programming view of DWC_otg controller.
14690 + * @param dwc_ep The EP to start the transfer on.
14693 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
14696 + dsts_data_t dsts = { .d32 = 0};
14697 + depctl_data_t depctl = { .d32 = 0 };
14698 + volatile uint32_t *addr;
14701 + if(dwc_ep->is_in)
14702 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
14704 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
14707 + /** Allocate descriptors for double buffering */
14708 + dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2);
14709 + if(dwc_ep->desc_addr) {
14710 + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
14714 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
14716 + /** ISO OUT EP */
14717 + if(dwc_ep->is_in == 0) {
14718 + desc_sts_data_t sts = { .d32 =0 };
14719 + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
14720 + dma_addr_t dma_ad;
14721 + uint32_t data_per_desc;
14722 + dwc_otg_dev_out_ep_regs_t *out_regs =
14723 + core_if->dev_if->out_ep_regs[dwc_ep->num];
14726 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
14727 + dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma));
14729 + /** Buffer 0 descriptors setup */
14730 + dma_ad = dwc_ep->dma_addr0;
14732 + sts.b_iso_out.bs = BS_HOST_READY;
14733 + sts.b_iso_out.rxsts = 0;
14734 + sts.b_iso_out.l = 0;
14735 + sts.b_iso_out.sp = 0;
14736 + sts.b_iso_out.ioc = 0;
14737 + sts.b_iso_out.pid = 0;
14738 + sts.b_iso_out.framenum = 0;
14741 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14744 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
14746 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14747 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14749 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14750 + sts.b_iso_out.rxbytes = data_per_desc;
14751 + writel((uint32_t)dma_ad, &dma_desc->buf);
14752 + writel(sts.d32, &dma_desc->status);
14754 + offset += data_per_desc;
14756 + //(uint32_t)dma_ad += data_per_desc;
14757 + dma_ad = (uint32_t)dma_ad + data_per_desc;
14761 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
14763 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14764 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14765 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14766 + sts.b_iso_out.rxbytes = data_per_desc;
14767 + writel((uint32_t)dma_ad, &dma_desc->buf);
14768 + writel(sts.d32, &dma_desc->status);
14770 + offset += data_per_desc;
14772 + //(uint32_t)dma_ad += data_per_desc;
14773 + dma_ad = (uint32_t)dma_ad + data_per_desc;
14776 + sts.b_iso_out.ioc = 1;
14777 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14778 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14779 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14780 + sts.b_iso_out.rxbytes = data_per_desc;
14782 + writel((uint32_t)dma_ad, &dma_desc->buf);
14783 + writel(sts.d32, &dma_desc->status);
14786 + /** Buffer 1 descriptors setup */
14787 + sts.b_iso_out.ioc = 0;
14788 + dma_ad = dwc_ep->dma_addr1;
14791 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14793 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
14795 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14796 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14797 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14798 + sts.b_iso_out.rxbytes = data_per_desc;
14799 + writel((uint32_t)dma_ad, &dma_desc->buf);
14800 + writel(sts.d32, &dma_desc->status);
14802 + offset += data_per_desc;
14804 + //(uint32_t)dma_ad += data_per_desc;
14805 + dma_ad = (uint32_t)dma_ad + data_per_desc;
14808 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
14810 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14811 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14812 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14813 + sts.b_iso_out.rxbytes = data_per_desc;
14814 + writel((uint32_t)dma_ad, &dma_desc->buf);
14815 + writel(sts.d32, &dma_desc->status);
14817 + offset += data_per_desc;
14819 + //(uint32_t)dma_ad += data_per_desc;
14820 + dma_ad = (uint32_t)dma_ad + data_per_desc;
14823 + sts.b_iso_out.ioc = 1;
14824 + sts.b_iso_out.l = 1;
14825 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14826 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14827 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14828 + sts.b_iso_out.rxbytes = data_per_desc;
14830 + writel((uint32_t)dma_ad, &dma_desc->buf);
14831 + writel(sts.d32, &dma_desc->status);
14833 + dwc_ep->next_frame = 0;
14835 + /** Write dma_ad into DOEPDMA register */
14836 + dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
14841 + desc_sts_data_t sts = { .d32 =0 };
14842 + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
14843 + dma_addr_t dma_ad;
14844 + dwc_otg_dev_in_ep_regs_t *in_regs =
14845 + core_if->dev_if->in_ep_regs[dwc_ep->num];
14846 + unsigned int frmnumber;
14847 + fifosize_data_t txfifosize,rxfifosize;
14849 + txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts);
14850 + rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
14853 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
14855 + dma_ad = dwc_ep->dma_addr0;
14857 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
14859 + sts.b_iso_in.bs = BS_HOST_READY;
14860 + sts.b_iso_in.txsts = 0;
14861 + sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0;
14862 + sts.b_iso_in.ioc = 0;
14863 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
14866 + frmnumber = dwc_ep->next_frame;
14868 + sts.b_iso_in.framenum = frmnumber;
14869 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
14870 + sts.b_iso_in.l = 0;
14872 + /** Buffer 0 descriptors setup */
14873 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
14875 + writel((uint32_t)dma_ad, &dma_desc->buf);
14876 + writel(sts.d32, &dma_desc->status);
14879 + //(uint32_t)dma_ad += dwc_ep->data_per_frame;
14880 + dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
14881 + sts.b_iso_in.framenum += dwc_ep->bInterval;
14884 + sts.b_iso_in.ioc = 1;
14885 + writel((uint32_t)dma_ad, &dma_desc->buf);
14886 + writel(sts.d32, &dma_desc->status);
14889 + /** Buffer 1 descriptors setup */
14890 + sts.b_iso_in.ioc = 0;
14891 + dma_ad = dwc_ep->dma_addr1;
14893 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14895 + writel((uint32_t)dma_ad, &dma_desc->buf);
14896 + writel(sts.d32, &dma_desc->status);
14899 + //(uint32_t)dma_ad += dwc_ep->data_per_frame;
14900 + dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
14901 + sts.b_iso_in.framenum += dwc_ep->bInterval;
14903 + sts.b_iso_in.ioc = 0;
14905 + sts.b_iso_in.ioc = 1;
14906 + sts.b_iso_in.l = 1;
14908 + writel((uint32_t)dma_ad, &dma_desc->buf);
14909 + writel(sts.d32, &dma_desc->status);
14911 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
14913 + /** Write dma_ad into diepdma register */
14914 + dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
14916 + /** Enable endpoint, clear nak */
14918 + depctl.b.epena = 1;
14919 + depctl.b.usbactep = 1;
14920 + depctl.b.cnak = 1;
14922 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
14923 + depctl.d32 = dwc_read_reg32(addr);
14927 + * This function initializes a descriptor chain for Isochronous transfer
14929 + * @param core_if Programming view of DWC_otg controller.
14930 + * @param ep The EP to start the transfer on.
14934 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
14936 + depctl_data_t depctl = { .d32 = 0 };
14937 + volatile uint32_t *addr;
14941 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
14943 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
14947 + if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) {
14950 + deptsiz_data_t deptsiz = { .d32 = 0 };
14952 + ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
14953 + ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) /
14955 + ep->xfer_count = 0;
14956 + ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
14957 + ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
14960 + /* Program the transfer size and packet count
14961 + * as follows: xfersize = N * maxpacket +
14962 + * short_packet pktcnt = N + (short_packet
14965 + deptsiz.b.mc = ep->pkt_per_frm;
14966 + deptsiz.b.xfersize = ep->xfer_len;
14967 + deptsiz.b.pktcnt =
14968 + (ep->xfer_len - 1 + ep->maxpacket) /
14970 + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
14972 + /* Write the DMA register */
14973 + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
14976 + deptsiz.b.pktcnt =
14977 + (ep->xfer_len + (ep->maxpacket - 1)) /
14979 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
14981 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
14983 + /* Write the DMA register */
14984 + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr);
14987 + /** Enable endpoint, clear nak */
14989 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
14991 + depctl.b.epena = 1;
14992 + depctl.b.cnak = 1;
14994 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
15000 + * This function does the setup for a data transfer for an EP and
15001 + * starts the transfer. For an IN transfer, the packets will be
15002 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
15003 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
15005 + * @param core_if Programming view of DWC_otg controller.
15006 + * @param ep The EP to start the transfer on.
15009 +void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
15011 + if(core_if->dma_enable) {
15012 + if(core_if->dma_desc_enable) {
15014 + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
15016 + ep->desc_cnt = ep->pkt_cnt;
15018 + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
15020 + if(core_if->pti_enh_enable) {
15021 + dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
15023 + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
15024 + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
15025 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
15029 + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
15030 + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
15031 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
15036 + * This function does the setup for a data transfer for an EP and
15037 + * starts the transfer. For an IN transfer, the packets will be
15038 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
15039 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
15041 + * @param core_if Programming view of DWC_otg controller.
15042 + * @param ep The EP to start the transfer on.
15045 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
15047 + depctl_data_t depctl = { .d32 = 0 };
15048 + volatile uint32_t *addr;
15050 + if(ep->is_in == 1) {
15051 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
15054 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
15057 + /* disable the ep */
15058 + depctl.d32 = dwc_read_reg32(addr);
15060 + depctl.b.epdis = 1;
15061 + depctl.b.snak = 1;
15063 + dwc_write_reg32(addr, depctl.d32);
15065 + if(core_if->dma_desc_enable &&
15066 + ep->iso_desc_addr && ep->iso_dma_desc_addr) {
15067 + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2);
15070 + /* reset varibales */
15071 + ep->dma_addr0 = 0;
15072 + ep->dma_addr1 = 0;
15073 + ep->xfer_buff0 = 0;
15074 + ep->xfer_buff1 = 0;
15075 + ep->data_per_frame = 0;
15076 + ep->data_pattern_frame = 0;
15077 + ep->sync_frame = 0;
15078 + ep->buf_proc_intrvl = 0;
15079 + ep->bInterval = 0;
15080 + ep->proc_buf_num = 0;
15081 + ep->pkt_per_frm = 0;
15082 + ep->pkt_per_frm = 0;
15083 + ep->desc_cnt = 0;
15084 + ep->iso_desc_addr = 0;
15085 + ep->iso_dma_desc_addr = 0;
15090 + * This function is used to submit an ISOC Transfer Request to an EP.
15092 + * - Every time a sync period completes the request's completion callback
15093 + * is called to provide data to the gadget driver.
15094 + * - Once submitted the request cannot be modified.
15095 + * - Each request is turned into periodic data packets untill ISO
15096 + * Transfer is stopped..
15098 +static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
15101 + dwc_otg_pcd_ep_t *ep;
15102 + dwc_otg_pcd_t *pcd;
15103 + dwc_ep_t *dwc_ep;
15104 + unsigned long flags = 0;
15105 + int32_t frm_data;
15106 + dwc_otg_core_if_t *core_if;
15107 + dcfg_data_t dcfg;
15108 + dsts_data_t dsts;
15111 + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
15112 + DWC_WARN("%s, bad params\n", __func__);
15116 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
15118 + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
15119 + DWC_WARN("%s, bad ep\n", __func__);
15124 + core_if = GET_CORE_IF(pcd);
15126 + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
15128 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
15129 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
15130 + DWC_WARN("%s, bogus device state\n", __func__);
15131 + return -ESHUTDOWN;
15134 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
15136 + dwc_ep = &ep->dwc_ep;
15138 + if(ep->iso_req) {
15139 + DWC_WARN("%s, iso request in progress\n", __func__);
15141 + req->status = -EINPROGRESS;
15143 + dwc_ep->dma_addr0 = req->dma0;
15144 + dwc_ep->dma_addr1 = req->dma1;
15146 + dwc_ep->xfer_buff0 = req->buf0;
15147 + dwc_ep->xfer_buff1 = req->buf1;
15149 + ep->iso_req = req;
15151 + dwc_ep->data_per_frame = req->data_per_frame;
15153 + /** @todo - pattern data support is to be implemented in the future */
15154 + dwc_ep->data_pattern_frame = req->data_pattern_frame;
15155 + dwc_ep->sync_frame = req->sync_frame;
15157 + dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl;
15159 + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
15161 + dwc_ep->proc_buf_num = 0;
15163 + dwc_ep->pkt_per_frm = 0;
15164 + frm_data = ep->dwc_ep.data_per_frame;
15165 + while(frm_data > 0) {
15166 + dwc_ep->pkt_per_frm++;
15167 + frm_data -= ep->dwc_ep.maxpacket;
15170 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
15172 + if(req->flags & USB_REQ_ISO_ASAP) {
15173 + dwc_ep->next_frame = dsts.b.soffn + 1;
15174 + if(dwc_ep->bInterval != 1){
15175 + dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval);
15178 + dwc_ep->next_frame = req->start_frame;
15182 + if(!core_if->pti_enh_enable) {
15183 + dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
15185 + dwc_ep->pkt_cnt =
15186 + (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
15187 + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
15190 + if(core_if->dma_desc_enable) {
15191 + dwc_ep->desc_cnt =
15192 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
15195 + dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL);
15196 + if(!dwc_ep->pkt_info) {
15199 + if(core_if->pti_enh_enable) {
15200 + memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
15203 + dwc_ep->cur_pkt = 0;
15205 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15207 + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
15213 + * This function stops ISO EP Periodic Data Transfer.
15215 +static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
15217 + dwc_otg_pcd_ep_t *ep;
15218 + dwc_otg_pcd_t *pcd;
15219 + dwc_ep_t *dwc_ep;
15220 + unsigned long flags;
15222 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
15224 + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
15225 + DWC_WARN("%s, bad ep\n", __func__);
15231 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
15232 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
15233 + DWC_WARN("%s, bogus device state\n", __func__);
15234 + return -ESHUTDOWN;
15237 + dwc_ep = &ep->dwc_ep;
15239 + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
15241 + kfree(dwc_ep->pkt_info);
15243 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
15245 + if(ep->iso_req != req) {
15249 + req->status = -ECONNRESET;
15251 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15260 + * This function is used for perodical data exchnage between PCD and gadget drivers.
15261 + * for Isochronous EPs
15263 + * - Every time a sync period completes this function is called to
15264 + * perform data exchange between PCD and gadget
15266 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req)
15269 + struct usb_gadget_iso_packet_descriptor *iso_packet;
15270 + dwc_ep_t *dwc_ep;
15272 + dwc_ep = &ep->dwc_ep;
15274 + if(ep->iso_req->status == -ECONNRESET) {
15275 + DWC_PRINT("Device has already disconnected\n");
15276 + /*Device has been disconnected*/
15280 + if(dwc_ep->proc_buf_num != 0) {
15281 + iso_packet = ep->iso_req->iso_packet_desc0;
15285 + iso_packet = ep->iso_req->iso_packet_desc1;
15288 + /* Fill in ISOC packets descriptors & pass to gadget driver*/
15290 + for(i = 0; i < dwc_ep->pkt_cnt; ++i) {
15291 + iso_packet[i].status = dwc_ep->pkt_info[i].status;
15292 + iso_packet[i].offset = dwc_ep->pkt_info[i].offset;
15293 + iso_packet[i].actual_length = dwc_ep->pkt_info[i].length;
15294 + dwc_ep->pkt_info[i].status = 0;
15295 + dwc_ep->pkt_info[i].offset = 0;
15296 + dwc_ep->pkt_info[i].length = 0;
15299 + /* Call callback function to process data buffer */
15300 + ep->iso_req->status = 0;/* success */
15302 + SPIN_UNLOCK(&ep->pcd->lock);
15303 + ep->iso_req->process_buffer(&ep->ep, ep->iso_req);
15304 + SPIN_LOCK(&ep->pcd->lock);
15308 +static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets,
15311 + struct usb_iso_request *pReq = NULL;
15312 + uint32_t req_size;
15315 + req_size = sizeof(struct usb_iso_request);
15316 + req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
15319 + pReq = kmalloc(req_size, gfp_flags);
15321 + DWC_WARN("%s, can't allocate Iso Request\n", __func__);
15324 + pReq->iso_packet_desc0 = (void*) (pReq + 1);
15326 + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
15331 +static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
15336 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops =
15340 + .enable = dwc_otg_pcd_ep_enable,
15341 + .disable = dwc_otg_pcd_ep_disable,
15343 + .alloc_request = dwc_otg_pcd_alloc_request,
15344 + .free_request = dwc_otg_pcd_free_request,
15346 + //.alloc_buffer = dwc_otg_pcd_alloc_buffer,
15347 + //.free_buffer = dwc_otg_pcd_free_buffer,
15349 + .queue = dwc_otg_pcd_ep_queue,
15350 + .dequeue = dwc_otg_pcd_ep_dequeue,
15352 + .set_halt = dwc_otg_pcd_ep_set_halt,
15353 + .fifo_status = 0,
15356 + .iso_ep_start = dwc_otg_pcd_iso_ep_start,
15357 + .iso_ep_stop = dwc_otg_pcd_iso_ep_stop,
15358 + .alloc_iso_request = dwc_otg_pcd_alloc_iso_request,
15359 + .free_iso_request = dwc_otg_pcd_free_iso_request,
15365 +static struct usb_ep_ops dwc_otg_pcd_ep_ops =
15367 + .enable = dwc_otg_pcd_ep_enable,
15368 + .disable = dwc_otg_pcd_ep_disable,
15370 + .alloc_request = dwc_otg_pcd_alloc_request,
15371 + .free_request = dwc_otg_pcd_free_request,
15373 +// .alloc_buffer = dwc_otg_pcd_alloc_buffer,
15374 +// .free_buffer = dwc_otg_pcd_free_buffer,
15376 + .queue = dwc_otg_pcd_ep_queue,
15377 + .dequeue = dwc_otg_pcd_ep_dequeue,
15379 + .set_halt = dwc_otg_pcd_ep_set_halt,
15380 + .fifo_status = 0,
15386 +#endif /* DWC_EN_ISOC */
15387 +/* Gadget Operations */
15389 + * The following gadget operations will be implemented in the DWC_otg
15390 + * PCD. Functions in the API that are not described below are not
15393 + * The Gadget API provides wrapper functions for each of the function
15394 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
15395 + * wrapper function, which then calls the underlying PCD function. The
15396 + * following sections are named according to the wrapper functions
15397 + * (except for ioctl, which doesn't have a wrapper function). Within
15398 + * each section, the corresponding DWC_otg PCD function name is
15404 + *Gets the USB Frame number of the last SOF.
15406 +static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget)
15408 + dwc_otg_pcd_t *pcd;
15410 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
15412 + if (gadget == 0) {
15416 + pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
15417 + dwc_otg_get_frame_number(GET_CORE_IF(pcd));
15423 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd)
15425 + uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl);
15426 + gotgctl_data_t mem;
15427 + gotgctl_data_t val;
15429 + val.d32 = dwc_read_reg32(addr);
15430 + if (val.b.sesreq) {
15431 + DWC_ERROR("Session Request Already active!\n");
15435 + DWC_NOTICE("Session Request Initated\n");
15436 + mem.d32 = dwc_read_reg32(addr);
15437 + mem.b.sesreq = 1;
15438 + dwc_write_reg32(addr, mem.d32);
15440 + /* Start the SRP timer */
15441 + dwc_otg_pcd_start_srp_timer(pcd);
15445 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set)
15447 + dctl_data_t dctl = {.d32=0};
15448 + volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl);
15450 + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
15451 + if (pcd->remote_wakeup_enable) {
15453 + dctl.b.rmtwkupsig = 1;
15454 + dwc_modify_reg32(addr, 0, dctl.d32);
15455 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
15457 + dwc_modify_reg32(addr, dctl.d32, 0);
15458 + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
15464 + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
15471 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
15472 + * session is in progress. If a session is already in progress, but
15473 + * the device is suspended, remote wakeup signaling is started.
15476 +static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget)
15478 + unsigned long flags;
15479 + dwc_otg_pcd_t *pcd;
15480 + dsts_data_t dsts;
15481 + gotgctl_data_t gotgctl;
15483 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
15485 + if (gadget == 0) {
15489 + pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
15491 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
15494 + * This function starts the Protocol if no session is in progress. If
15495 + * a session is already in progress, but the device is suspended,
15496 + * remote wakeup signaling is started.
15499 + /* Check if valid session */
15500 + gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
15501 + if (gotgctl.b.bsesvld) {
15502 + /* Check if suspend state */
15503 + dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts));
15504 + if (dsts.b.suspsts) {
15505 + dwc_otg_pcd_remote_wakeup(pcd, 1);
15509 + dwc_otg_pcd_initiate_srp(pcd);
15512 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15516 +static const struct usb_gadget_ops dwc_otg_pcd_ops =
15518 + .get_frame = dwc_otg_pcd_get_frame,
15519 + .wakeup = dwc_otg_pcd_wakeup,
15520 + // current versions must always be self-powered
15524 + * This function updates the otg values in the gadget structure.
15526 +void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
15529 + if (!pcd->gadget.is_otg)
15533 + pcd->b_hnp_enable = 0;
15534 + pcd->a_hnp_support = 0;
15535 + pcd->a_alt_hnp_support = 0;
15538 + pcd->gadget.b_hnp_enable = pcd->b_hnp_enable;
15539 + pcd->gadget.a_hnp_support = pcd->a_hnp_support;
15540 + pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support;
15544 + * This function is the top level PCD interrupt handler.
15546 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
15548 + dwc_otg_pcd_t *pcd = dev;
15549 + int32_t retval = IRQ_NONE;
15551 + retval = dwc_otg_pcd_handle_intr(pcd);
15552 + return IRQ_RETVAL(retval);
15556 + * PCD Callback function for initializing the PCD when switching to
15559 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15561 +static int32_t dwc_otg_pcd_start_cb(void *p)
15563 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15566 + * Initialized the Core for Device mode.
15568 + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
15569 + dwc_otg_core_dev_init(GET_CORE_IF(pcd));
15575 + * PCD Callback function for stopping the PCD when switching to Host
15578 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15580 +static int32_t dwc_otg_pcd_stop_cb(void *p)
15582 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15583 + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd);
15585 + dwc_otg_pcd_stop(pcd);
15591 + * PCD Callback function for notifying the PCD when resuming from
15594 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15596 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
15598 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15600 + if (pcd->driver && pcd->driver->resume) {
15601 + SPIN_UNLOCK(&pcd->lock);
15602 + pcd->driver->suspend(&pcd->gadget);
15603 + SPIN_LOCK(&pcd->lock);
15611 + * PCD Callback function for notifying the PCD when resuming from
15614 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15616 +static int32_t dwc_otg_pcd_resume_cb(void *p)
15618 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15620 + if (pcd->driver && pcd->driver->resume) {
15621 + SPIN_UNLOCK(&pcd->lock);
15622 + pcd->driver->resume(&pcd->gadget);
15623 + SPIN_LOCK(&pcd->lock);
15626 + /* Stop the SRP timeout timer. */
15627 + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ||
15628 + (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
15629 + if (GET_CORE_IF(pcd)->srp_timer_started) {
15630 + GET_CORE_IF(pcd)->srp_timer_started = 0;
15631 + del_timer(&pcd->srp_timer);
15639 + * PCD Callback structure for handling mode switching.
15641 +static dwc_otg_cil_callbacks_t pcd_callbacks =
15643 + .start = dwc_otg_pcd_start_cb,
15644 + .stop = dwc_otg_pcd_stop_cb,
15645 + .suspend = dwc_otg_pcd_suspend_cb,
15646 + .resume_wakeup = dwc_otg_pcd_resume_cb,
15647 + .p = 0, /* Set at registration */
15651 + * This function is called when the SRP timer expires. The SRP should
15652 + * complete within 6 seconds.
15654 +static void srp_timeout(unsigned long ptr)
15656 + gotgctl_data_t gotgctl;
15657 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr;
15658 + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
15660 + gotgctl.d32 = dwc_read_reg32(addr);
15662 + core_if->srp_timer_started = 0;
15664 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
15665 + (core_if->core_params->i2c_enable)) {
15666 + DWC_PRINT("SRP Timeout\n");
15668 + if ((core_if->srp_success) &&
15669 + (gotgctl.b.bsesvld)) {
15670 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
15671 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
15674 + /* Clear Session Request */
15676 + gotgctl.b.sesreq = 1;
15677 + dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
15680 + core_if->srp_success = 0;
15683 + DWC_ERROR("Device not connected/responding\n");
15684 + gotgctl.b.sesreq = 0;
15685 + dwc_write_reg32(addr, gotgctl.d32);
15688 + else if (gotgctl.b.sesreq) {
15689 + DWC_PRINT("SRP Timeout\n");
15691 + DWC_ERROR("Device not connected/responding\n");
15692 + gotgctl.b.sesreq = 0;
15693 + dwc_write_reg32(addr, gotgctl.d32);
15696 + DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32);
15701 + * Start the SRP timer to detect when the SRP does not complete within
15704 + * @param pcd the pcd structure.
15706 +void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd)
15708 + struct timer_list *srp_timer = &pcd->srp_timer;
15709 + GET_CORE_IF(pcd)->srp_timer_started = 1;
15710 + init_timer(srp_timer);
15711 + srp_timer->function = srp_timeout;
15712 + srp_timer->data = (unsigned long)GET_CORE_IF(pcd);
15713 + srp_timer->expires = jiffies + (HZ*6);
15714 + add_timer(srp_timer);
15721 +extern void start_next_request(dwc_otg_pcd_ep_t *ep);
15723 +static void start_xfer_tasklet_func (unsigned long data)
15725 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data;
15726 + dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if;
15729 + depctl_data_t diepctl;
15731 + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
15733 + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
15735 + if (pcd->ep0.queue_sof) {
15736 + pcd->ep0.queue_sof = 0;
15737 + start_next_request (&pcd->ep0);
15741 + for (i=0; i<core_if->dev_if->num_in_eps; i++)
15743 + depctl_data_t diepctl;
15744 + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
15746 + if (pcd->in_ep[i].queue_sof) {
15747 + pcd->in_ep[i].queue_sof = 0;
15748 + start_next_request (&pcd->in_ep[i]);
15762 +static struct tasklet_struct start_xfer_tasklet = {
15765 + .count = ATOMIC_INIT(0),
15766 + .func = start_xfer_tasklet_func,
15770 + * This function initialized the pcd Dp structures to there default
15773 + * @param pcd the pcd structure.
15775 +void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd)
15777 + static const char * names[] =
15815 + int in_ep_cntr, out_ep_cntr;
15817 + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
15818 + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
15819 + dwc_otg_pcd_ep_t *ep;
15821 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
15823 + INIT_LIST_HEAD (&pcd->gadget.ep_list);
15824 + pcd->gadget.ep0 = &pcd->ep0.ep;
15825 + pcd->gadget.speed = USB_SPEED_UNKNOWN;
15827 + INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list);
15830 + * Initialize the EP0 structure.
15834 + /* Init EP structure */
15839 + /* Init DWC ep structure */
15840 + ep->dwc_ep.num = 0;
15841 + ep->dwc_ep.active = 0;
15842 + ep->dwc_ep.tx_fifo_num = 0;
15843 + /* Control until ep is actvated */
15844 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
15845 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
15846 + ep->dwc_ep.dma_addr = 0;
15847 + ep->dwc_ep.start_xfer_buff = 0;
15848 + ep->dwc_ep.xfer_buff = 0;
15849 + ep->dwc_ep.xfer_len = 0;
15850 + ep->dwc_ep.xfer_count = 0;
15851 + ep->dwc_ep.sent_zlp = 0;
15852 + ep->dwc_ep.total_len = 0;
15853 + ep->queue_sof = 0;
15854 + ep->dwc_ep.desc_addr = 0;
15855 + ep->dwc_ep.dma_desc_addr = 0;
15857 + ep->dwc_ep.aligned_buf=NULL;
15858 + ep->dwc_ep.aligned_buf_size=0;
15859 + ep->dwc_ep.aligned_dma_addr=0;
15862 + /* Init the usb_ep structure. */
15863 + ep->ep.name = names[0];
15864 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
15867 + * @todo NGS: What should the max packet size be set to
15868 + * here? Before EP type is set?
15870 + ep->ep.maxpacket = MAX_PACKET_SIZE;
15872 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
15874 + INIT_LIST_HEAD (&ep->queue);
15876 + * Initialize the EP structures.
15879 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
15881 + for (i = 1; in_ep_cntr < num_in_eps; i++)
15883 + if((hwcfg1 & 0x1) == 0) {
15884 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
15887 + /* Init EP structure */
15892 + /* Init DWC ep structure */
15893 + ep->dwc_ep.is_in = 1;
15894 + ep->dwc_ep.num = i;
15895 + ep->dwc_ep.active = 0;
15896 + ep->dwc_ep.tx_fifo_num = 0;
15898 + /* Control until ep is actvated */
15899 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
15900 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
15901 + ep->dwc_ep.dma_addr = 0;
15902 + ep->dwc_ep.start_xfer_buff = 0;
15903 + ep->dwc_ep.xfer_buff = 0;
15904 + ep->dwc_ep.xfer_len = 0;
15905 + ep->dwc_ep.xfer_count = 0;
15906 + ep->dwc_ep.sent_zlp = 0;
15907 + ep->dwc_ep.total_len = 0;
15908 + ep->queue_sof = 0;
15909 + ep->dwc_ep.desc_addr = 0;
15910 + ep->dwc_ep.dma_desc_addr = 0;
15912 + /* Init the usb_ep structure. */
15913 + ep->ep.name = names[i];
15914 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
15917 + * @todo NGS: What should the max packet size be set to
15918 + * here? Before EP type is set?
15920 + ep->ep.maxpacket = MAX_PACKET_SIZE;
15922 + //add only even number ep as in
15924 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
15926 + INIT_LIST_HEAD (&ep->queue);
15932 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
15934 + for (i = 1; out_ep_cntr < num_out_eps; i++)
15936 + if((hwcfg1 & 0x1) == 0) {
15937 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
15940 + /* Init EP structure */
15945 + /* Init DWC ep structure */
15946 + ep->dwc_ep.is_in = 0;
15947 + ep->dwc_ep.num = i;
15948 + ep->dwc_ep.active = 0;
15949 + ep->dwc_ep.tx_fifo_num = 0;
15950 + /* Control until ep is actvated */
15951 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
15952 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
15953 + ep->dwc_ep.dma_addr = 0;
15954 + ep->dwc_ep.start_xfer_buff = 0;
15955 + ep->dwc_ep.xfer_buff = 0;
15956 + ep->dwc_ep.xfer_len = 0;
15957 + ep->dwc_ep.xfer_count = 0;
15958 + ep->dwc_ep.sent_zlp = 0;
15959 + ep->dwc_ep.total_len = 0;
15960 + ep->queue_sof = 0;
15962 + /* Init the usb_ep structure. */
15963 + ep->ep.name = names[15 + i];
15964 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
15966 + * @todo NGS: What should the max packet size be set to
15967 + * here? Before EP type is set?
15969 + ep->ep.maxpacket = MAX_PACKET_SIZE;
15971 + //add only odd number ep as out
15973 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
15975 + INIT_LIST_HEAD (&ep->queue);
15980 + /* remove ep0 from the list. There is a ep0 pointer.*/
15981 + list_del_init (&pcd->ep0.ep.ep_list);
15983 + pcd->ep0state = EP0_DISCONNECT;
15984 + pcd->ep0.ep.maxpacket = MAX_EP0_SIZE;
15985 + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
15986 + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
15990 + * This function releases the Gadget device.
15991 + * required by device_unregister().
15993 + * @todo Should this do something? Should it free the PCD?
15995 +static void dwc_otg_pcd_gadget_release(struct device *dev)
15997 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev);
16003 + * This function initialized the PCD portion of the driver.
16006 +u8 dev_id[]="gadget";
16007 +int dwc_otg_pcd_init(struct platform_device *pdev)
16009 + static char pcd_name[] = "dwc_otg_pcd";
16010 + dwc_otg_pcd_t *pcd;
16011 + dwc_otg_core_if_t* core_if;
16012 + dwc_otg_dev_if_t* dev_if;
16013 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
16017 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, pdev);
16019 + * Allocate PCD structure
16021 + pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL);
16027 + memset(pcd, 0, sizeof(dwc_otg_pcd_t));
16028 + spin_lock_init(&pcd->lock);
16030 + otg_dev->pcd = pcd;
16032 + pcd->gadget.name = pcd_name;
16034 + pcd->gadget.dev.init_name = dev_id;
16035 + pcd->otg_dev = platform_get_drvdata(pdev);
16037 + pcd->gadget.dev.parent = &pdev->dev;
16038 + pcd->gadget.dev.release = dwc_otg_pcd_gadget_release;
16039 + pcd->gadget.ops = &dwc_otg_pcd_ops;
16041 + core_if = GET_CORE_IF(pcd);
16042 + dev_if = core_if->dev_if;
16044 + if(core_if->hwcfg4.b.ded_fifo_en) {
16045 + DWC_PRINT("Dedicated Tx FIFOs mode\n");
16048 + DWC_PRINT("Shared Tx FIFO mode\n");
16051 + /* If the module is set to FS or if the PHY_TYPE is FS then the gadget
16052 + * should not report as dual-speed capable. replace the following line
16053 + * with the block of code below it once the software is debugged for
16054 + * this. If is_dualspeed = 0 then the gadget driver should not report
16055 + * a device qualifier descriptor when queried. */
16056 + if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) ||
16057 + ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) &&
16058 + (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) &&
16059 + (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) {
16060 + pcd->gadget.max_speed = USB_SPEED_FULL;
16063 + pcd->gadget.max_speed = USB_SPEED_HIGH;
16066 + if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) ||
16067 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) ||
16068 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
16069 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
16070 + pcd->gadget.is_otg = 0;
16073 + pcd->gadget.is_otg = 1;
16078 + /* Register the gadget device */
16079 +printk("%s: 1\n",__func__);
16080 + retval = device_register(&pcd->gadget.dev);
16081 + if (retval != 0) {
16083 +printk("%s: 2\n",__func__);
16089 + * Initialized the Core for Device mode.
16091 + if (dwc_otg_is_device_mode(core_if)) {
16092 + dwc_otg_core_dev_init(core_if);
16096 + * Initialize EP structures
16098 + dwc_otg_pcd_reinit(pcd);
16101 + * Register the PCD Callbacks.
16103 + dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks,
16106 + * Setup interupt handler
16108 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq);
16109 + retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq,
16110 + IRQF_SHARED, pcd->gadget.name, pcd);
16111 + if (retval != 0) {
16112 + DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
16113 + device_unregister(&pcd->gadget.dev);
16119 + * Initialize the DMA buffer for SETUP packets
16121 + if (GET_CORE_IF(pcd)->dma_enable) {
16122 + pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0);
16123 + if (pcd->setup_pkt == 0) {
16124 + free_irq(otg_dev->irq, pcd);
16125 + device_unregister(&pcd->gadget.dev);
16130 + pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0);
16131 + if (pcd->status_buf == 0) {
16132 + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16133 + free_irq(otg_dev->irq, pcd);
16134 + device_unregister(&pcd->gadget.dev);
16139 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
16140 + dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1);
16141 + dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1);
16142 + dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1);
16143 + dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1);
16145 + if(dev_if->setup_desc_addr[0] == 0
16146 + || dev_if->setup_desc_addr[1] == 0
16147 + || dev_if->in_desc_addr == 0
16148 + || dev_if->out_desc_addr == 0 ) {
16150 + if(dev_if->out_desc_addr)
16151 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
16152 + if(dev_if->in_desc_addr)
16153 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
16154 + if(dev_if->setup_desc_addr[1])
16155 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
16156 + if(dev_if->setup_desc_addr[0])
16157 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
16160 + dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle);
16161 + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16163 + free_irq(otg_dev->irq, pcd);
16164 + device_unregister(&pcd->gadget.dev);
16172 + pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL);
16173 + if (pcd->setup_pkt == 0) {
16174 + free_irq(otg_dev->irq, pcd);
16175 + device_unregister(&pcd->gadget.dev);
16180 + pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL);
16181 + if (pcd->status_buf == 0) {
16182 + kfree(pcd->setup_pkt);
16183 + free_irq(otg_dev->irq, pcd);
16184 + device_unregister(&pcd->gadget.dev);
16191 + /* Initialize tasklet */
16192 + start_xfer_tasklet.data = (unsigned long)pcd;
16193 + pcd->start_xfer_tasklet = &start_xfer_tasklet;
16199 + * Cleanup the PCD.
16201 +void dwc_otg_pcd_remove(struct platform_device *pdev)
16203 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
16204 + dwc_otg_pcd_t *pcd = otg_dev->pcd;
16205 + dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if;
16207 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pdev);
16212 + free_irq(otg_dev->irq, pcd);
16214 + /* start with the driver above us */
16215 + if (pcd->driver) {
16216 + /* should have been done already by driver model core */
16217 + DWC_WARN("driver '%s' is still registered\n",
16218 + pcd->driver->driver.name);
16219 + usb_gadget_unregister_driver(pcd->driver);
16221 + device_unregister(&pcd->gadget.dev);
16223 + if (GET_CORE_IF(pcd)->dma_enable) {
16224 + dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16225 + dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle);
16226 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
16227 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
16228 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
16229 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
16230 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
16234 + kfree (pcd->setup_pkt);
16235 + kfree (pcd->status_buf);
16239 + otg_dev->pcd = 0;
16243 + * This function registers a gadget driver with the PCD.
16245 + * When a driver is successfully registered, it will receive control
16246 + * requests including set_configuration(), which enables non-control
16247 + * requests. then usb traffic follows until a disconnect is reported.
16248 + * then a host may connect again, or the driver might get unbound.
16250 + * @param driver The driver being registered
16252 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
16253 + int (*bind)(struct usb_gadget *))
16257 + DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name);
16259 + if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
16261 + !driver->unbind ||
16262 + !driver->disconnect ||
16263 + !driver->setup) {
16264 + DWC_DEBUGPL(DBG_PCDV,"EINVAL\n");
16267 + if (s_pcd == 0) {
16268 + DWC_DEBUGPL(DBG_PCDV,"ENODEV\n");
16271 + if (s_pcd->driver != 0) {
16272 + DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver);
16276 + /* hook up the driver */
16277 + s_pcd->driver = driver;
16278 + s_pcd->gadget.dev.driver = &driver->driver;
16280 + DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
16281 + retval = bind(&s_pcd->gadget);
16283 + DWC_ERROR("bind to driver %s --> error %d\n",
16284 + driver->driver.name, retval);
16285 + s_pcd->driver = 0;
16286 + s_pcd->gadget.dev.driver = 0;
16289 + DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
16290 + driver->driver.name);
16294 +EXPORT_SYMBOL(usb_gadget_probe_driver);
16297 + * This function unregisters a gadget driver
16299 + * @param driver The driver being unregistered
16301 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
16303 + //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
16305 + if (s_pcd == 0) {
16306 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
16310 + if (driver == 0 || driver != s_pcd->driver) {
16311 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
16316 + driver->unbind(&s_pcd->gadget);
16317 + s_pcd->driver = 0;
16319 + DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n",
16320 + driver->driver.name);
16323 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
16325 +#endif /* DWC_HOST_ONLY */
16327 +++ b/drivers/usb/dwc/otg_pcd.h
16329 +/* ==========================================================================
16330 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
16331 + * $Revision: #36 $
16332 + * $Date: 2008/09/26 $
16333 + * $Change: 1103515 $
16335 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16336 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16337 + * otherwise expressly agreed to in writing between Synopsys and you.
16339 + * The Software IS NOT an item of Licensed Software or Licensed Product under
16340 + * any End User Software License Agreement or Agreement for Licensed Product
16341 + * with Synopsys or any supplement thereto. You are permitted to use and
16342 + * redistribute this Software in source and binary forms, with or without
16343 + * modification, provided that redistributions of source code must retain this
16344 + * notice. You may not view, use, disclose, copy or distribute this file or
16345 + * any information contained herein except pursuant to this license grant from
16346 + * Synopsys. If you do not agree with this notice, including the disclaimer
16347 + * below, then you are not authorized to use the Software.
16349 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16350 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16351 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16352 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16353 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16354 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16355 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16356 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16357 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16358 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16360 + * ========================================================================== */
16361 +#ifndef DWC_HOST_ONLY
16362 +#if !defined(__DWC_PCD_H__)
16363 +#define __DWC_PCD_H__
16365 +#include <linux/types.h>
16366 +#include <linux/list.h>
16367 +#include <linux/errno.h>
16368 +#include <linux/device.h>
16369 +#include <linux/platform_device.h>
16371 +#include <linux/usb/ch9.h>
16372 +#include <linux/usb/gadget.h>
16374 +#include <linux/interrupt.h>
16375 +#include <linux/dma-mapping.h>
16377 +struct dwc_otg_device;
16379 +#include "otg_cil.h"
16384 + * This file contains the structures, constants, and interfaces for
16385 + * the Perpherial Contoller Driver (PCD).
16387 + * The Peripheral Controller Driver (PCD) for Linux will implement the
16388 + * Gadget API, so that the existing Gadget drivers can be used. For
16389 + * the Mass Storage Function driver the File-backed USB Storage Gadget
16390 + * (FBS) driver will be used. The FBS driver supports the
16391 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
16396 +/** Invalid DMA Address */
16397 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
16398 +/** Maxpacket size for EP0 */
16399 +#define MAX_EP0_SIZE 64
16400 +/** Maxpacket size for any EP */
16401 +#define MAX_PACKET_SIZE 1024
16403 +/** Max Transfer size for any EP */
16404 +#define MAX_TRANSFER_SIZE 65535
16406 +/** Max DMA Descriptor count for any EP */
16407 +#define MAX_DMA_DESC_CNT 64
16410 + * Get the pointer to the core_if from the pcd pointer.
16412 +#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if)
16417 +typedef enum ep0_state
16419 + EP0_DISCONNECT, /* no host */
16421 + EP0_IN_DATA_PHASE,
16422 + EP0_OUT_DATA_PHASE,
16423 + EP0_IN_STATUS_PHASE,
16424 + EP0_OUT_STATUS_PHASE,
16428 +/** Fordward declaration.*/
16429 +struct dwc_otg_pcd;
16431 +/** DWC_otg iso request structure.
16434 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
16436 +/** PCD EP structure.
16437 + * This structure describes an EP, there is an array of EPs in the PCD
16440 +typedef struct dwc_otg_pcd_ep
16442 + /** USB EP data */
16443 + struct usb_ep ep;
16444 + /** USB EP Descriptor */
16445 + const struct usb_endpoint_descriptor *desc;
16447 + /** queue of dwc_otg_pcd_requests. */
16448 + struct list_head queue;
16449 + unsigned stopped : 1;
16450 + unsigned disabling : 1;
16451 + unsigned dma : 1;
16452 + unsigned queue_sof : 1;
16454 +#ifdef DWC_EN_ISOC
16455 + /** DWC_otg Isochronous Transfer */
16456 + struct usb_iso_request* iso_req;
16457 +#endif //DWC_EN_ISOC
16459 + /** DWC_otg ep data. */
16462 + /** Pointer to PCD */
16463 + struct dwc_otg_pcd *pcd;
16464 +}dwc_otg_pcd_ep_t;
16468 +/** DWC_otg PCD Structure.
16469 + * This structure encapsulates the data for the dwc_otg PCD.
16471 +typedef struct dwc_otg_pcd
16473 + /** USB gadget */
16474 + struct usb_gadget gadget;
16475 + /** USB gadget driver pointer*/
16476 + struct usb_gadget_driver *driver;
16477 + /** The DWC otg device pointer. */
16478 + struct dwc_otg_device *otg_dev;
16480 + /** State of EP0 */
16481 + ep0state_e ep0state;
16482 + /** EP0 Request is pending */
16483 + unsigned ep0_pending : 1;
16484 + /** Indicates when SET CONFIGURATION Request is in process */
16485 + unsigned request_config : 1;
16486 + /** The state of the Remote Wakeup Enable. */
16487 + unsigned remote_wakeup_enable : 1;
16488 + /** The state of the B-Device HNP Enable. */
16489 + unsigned b_hnp_enable : 1;
16490 + /** The state of A-Device HNP Support. */
16491 + unsigned a_hnp_support : 1;
16492 + /** The state of the A-Device Alt HNP support. */
16493 + unsigned a_alt_hnp_support : 1;
16494 + /** Count of pending Requests */
16495 + unsigned request_pending;
16497 + /** SETUP packet for EP0
16498 + * This structure is allocated as a DMA buffer on PCD initialization
16499 + * with enough space for up to 3 setup packets.
16503 + struct usb_ctrlrequest req;
16507 + dma_addr_t setup_pkt_dma_handle;
16509 + /** 2-byte dma buffer used to return status from GET_STATUS */
16510 + uint16_t *status_buf;
16511 + dma_addr_t status_buf_dma_handle;
16514 + dwc_otg_pcd_ep_t ep0;
16516 + /** Array of IN EPs. */
16517 + dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1];
16518 + /** Array of OUT EPs. */
16519 + dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1];
16520 + /** number of valid EPs in the above array. */
16521 +// unsigned num_eps : 4;
16523 + /** Timer for SRP. If it expires before SRP is successful
16524 + * clear the SRP. */
16525 + struct timer_list srp_timer;
16527 + /** Tasklet to defer starting of TEST mode transmissions until
16528 + * Status Phase has been completed.
16530 + struct tasklet_struct test_mode_tasklet;
16532 + /** Tasklet to delay starting of xfer in DMA mode */
16533 + struct tasklet_struct *start_xfer_tasklet;
16535 + /** The test mode to enter when the tasklet is executed. */
16536 + unsigned test_mode;
16541 +/** DWC_otg request structure.
16542 + * This structure is a list of requests.
16546 + struct usb_request req; /**< USB Request. */
16547 + struct list_head queue; /**< queue of these requests. */
16548 +} dwc_otg_pcd_request_t;
16551 +extern int dwc_otg_pcd_init(struct platform_device *pdev);
16553 +//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev );
16554 +extern void dwc_otg_pcd_remove( struct platform_device *pdev );
16555 +extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd );
16556 +extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd );
16558 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd);
16559 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set);
16561 +extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req);
16562 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req,
16564 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep);
16565 +extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd,
16566 + const unsigned reset);
16568 +#define VERIFY_PCD_DMA_ADDR(_addr_) BUG_ON(((_addr_)==DMA_ADDR_INVALID)||\
16572 +#define VERIFY_PCD_DMA_ADDR(_addr_) {\
16573 + if(((_addr_)==DMA_ADDR_INVALID)||\
16575 + ((_addr_)&0x3)) {\
16576 + printk("%s: Invalid DMA address "#_addr_"(%.8x)\n",__func__,_addr_);\
16583 +static inline void ep_check_and_patch_dma_addr(dwc_otg_pcd_ep_t *ep){
16584 +//void ep_check_and_patch_dma_addr(dwc_otg_pcd_ep_t *ep){
16585 + dwc_ep_t *dwc_ep=&ep->dwc_ep;
16587 +DWC_DEBUGPL(DBG_PCDV,"%s: dwc_ep xfer_buf=%.8x, total_len=%d, dma_addr=%.8x\n",__func__,(u32)dwc_ep->xfer_buff,(dwc_ep->total_len),dwc_ep->dma_addr);
16588 + if (/*(core_if->dma_enable)&&*/(dwc_ep->dma_addr==DMA_ADDR_INVALID)) {
16589 + if((((u32)dwc_ep->xfer_buff)&0x3)==0){
16590 + dwc_ep->dma_addr=dma_map_single(NULL,(void *)(dwc_ep->start_xfer_buff),(dwc_ep->total_len), DMA_TO_DEVICE);
16591 +DWC_DEBUGPL(DBG_PCDV," got dma_addr=%.8x\n",dwc_ep->dma_addr);
16593 +DWC_DEBUGPL(DBG_PCDV," buf not aligned, use aligned_buf instead. xfer_buf=%.8x, total_len=%d, aligned_buf_size=%d\n",(u32)dwc_ep->xfer_buff,(dwc_ep->total_len),dwc_ep->aligned_buf_size);
16594 + if(dwc_ep->aligned_buf_size<dwc_ep->total_len){
16595 + if(dwc_ep->aligned_buf){
16596 +//printk(" free buff dwc_ep aligned_buf_size=%d, aligned_buf(%.8x), aligned_dma_addr(%.8x));\n",dwc_ep->aligned_buf_size,dwc_ep->aligned_buf,dwc_ep->aligned_dma_addr);
16597 + //dma_free_coherent(NULL,dwc_ep->aligned_buf_size,dwc_ep->aligned_buf,dwc_ep->aligned_dma_addr);
16598 + kfree(dwc_ep->aligned_buf);
16600 + dwc_ep->aligned_buf_size=((1<<20)>(dwc_ep->total_len<<1))?(dwc_ep->total_len<<1):(1<<20);
16601 + //dwc_ep->aligned_buf = dma_alloc_coherent (NULL, dwc_ep->aligned_buf_size, &dwc_ep->aligned_dma_addr, GFP_KERNEL|GFP_DMA);
16602 + dwc_ep->aligned_buf=kmalloc(dwc_ep->aligned_buf_size,GFP_KERNEL|GFP_DMA|GFP_ATOMIC);
16603 + dwc_ep->aligned_dma_addr=dma_map_single(NULL,(void *)(dwc_ep->aligned_buf),(dwc_ep->aligned_buf_size),DMA_FROM_DEVICE);
16604 + if(!dwc_ep->aligned_buf){
16605 + DWC_ERROR("Cannot alloc required buffer!!\n");
16608 +DWC_DEBUGPL(DBG_PCDV," dwc_ep allocated aligned buf=%.8x, dma_addr=%.8x, size=%d(0x%x)\n", (u32)dwc_ep->aligned_buf, dwc_ep->aligned_dma_addr, dwc_ep->aligned_buf_size, dwc_ep->aligned_buf_size);
16610 + dwc_ep->dma_addr=dwc_ep->aligned_dma_addr;
16611 + if(dwc_ep->is_in) {
16612 + memcpy(dwc_ep->aligned_buf,dwc_ep->xfer_buff,dwc_ep->total_len);
16613 + dma_sync_single_for_device(NULL,dwc_ep->dma_addr,dwc_ep->total_len,DMA_TO_DEVICE);
16620 +#endif /* DWC_HOST_ONLY */
16622 +++ b/drivers/usb/dwc/otg_pcd_intr.c
16624 +/* ==========================================================================
16625 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
16626 + * $Revision: #83 $
16627 + * $Date: 2008/10/14 $
16628 + * $Change: 1115682 $
16630 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16631 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16632 + * otherwise expressly agreed to in writing between Synopsys and you.
16634 + * The Software IS NOT an item of Licensed Software or Licensed Product under
16635 + * any End User Software License Agreement or Agreement for Licensed Product
16636 + * with Synopsys or any supplement thereto. You are permitted to use and
16637 + * redistribute this Software in source and binary forms, with or without
16638 + * modification, provided that redistributions of source code must retain this
16639 + * notice. You may not view, use, disclose, copy or distribute this file or
16640 + * any information contained herein except pursuant to this license grant from
16641 + * Synopsys. If you do not agree with this notice, including the disclaimer
16642 + * below, then you are not authorized to use the Software.
16644 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16645 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16646 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16647 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16648 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16649 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16650 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16651 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16652 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16653 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16655 + * ========================================================================== */
16656 +#ifndef DWC_HOST_ONLY
16657 +#include <linux/interrupt.h>
16658 +#include <linux/dma-mapping.h>
16659 +#include <linux/version.h>
16660 +#include <linux/pci.h>
16662 +#include "otg_driver.h"
16663 +#include "otg_pcd.h"
16669 +/* request functions defined in "dwc_otg_pcd.c" */
16672 + * This file contains the implementation of the PCD Interrupt handlers.
16674 + * The PCD handles the device interrupts. Many conditions can cause a
16675 + * device interrupt. When an interrupt occurs, the device interrupt
16676 + * service routine determines the cause of the interrupt and
16677 + * dispatches handling to the appropriate function. These interrupt
16678 + * handling functions are described below.
16679 + * All interrupt registers are processed from LSB to MSB.
16684 + * This function prints the ep0 state for debug purposes.
16686 +static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
16691 + switch (pcd->ep0state) {
16692 + case EP0_DISCONNECT:
16693 + strcpy(str, "EP0_DISCONNECT");
16696 + strcpy(str, "EP0_IDLE");
16698 + case EP0_IN_DATA_PHASE:
16699 + strcpy(str, "EP0_IN_DATA_PHASE");
16701 + case EP0_OUT_DATA_PHASE:
16702 + strcpy(str, "EP0_OUT_DATA_PHASE");
16704 + case EP0_IN_STATUS_PHASE:
16705 + strcpy(str,"EP0_IN_STATUS_PHASE");
16707 + case EP0_OUT_STATUS_PHASE:
16708 + strcpy(str,"EP0_OUT_STATUS_PHASE");
16711 + strcpy(str,"EP0_STALL");
16714 + strcpy(str,"EP0_INVALID");
16717 + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
16722 + * This function returns pointer to in ep struct with number ep_num
16724 +static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
16727 + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
16728 + if(ep_num == 0) {
16729 + return &pcd->ep0;
16732 + for(i = 0; i < num_in_eps; ++i)
16734 + if(pcd->in_ep[i].dwc_ep.num == ep_num)
16735 + return &pcd->in_ep[i];
16741 + * This function returns pointer to out ep struct with number ep_num
16743 +static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
16746 + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
16747 + if(ep_num == 0) {
16748 + return &pcd->ep0;
16751 + for(i = 0; i < num_out_eps; ++i)
16753 + if(pcd->out_ep[i].dwc_ep.num == ep_num)
16754 + return &pcd->out_ep[i];
16760 + * This functions gets a pointer to an EP from the wIndex address
16761 + * value of the control request.
16763 +static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
16765 + dwc_otg_pcd_ep_t *ep;
16767 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
16768 + return &pcd->ep0;
16769 + list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list)
16771 + u8 bEndpointAddress;
16776 + bEndpointAddress = ep->desc->bEndpointAddress;
16777 + if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))
16778 + == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)))
16785 + * This function checks the EP request queue, if the queue is not
16786 + * empty the next request is started.
16788 +void start_next_request(dwc_otg_pcd_ep_t *ep)
16790 + dwc_otg_pcd_request_t *req = 0;
16791 + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
16792 + if (!list_empty(&ep->queue)) {
16793 + req = list_entry(ep->queue.next,
16794 + dwc_otg_pcd_request_t, queue);
16796 + /* Setup and start the Transfer */
16797 + ep->dwc_ep.dma_addr = req->req.dma;
16798 + ep->dwc_ep.start_xfer_buff = req->req.buf;
16799 + ep->dwc_ep.xfer_buff = req->req.buf;
16800 + ep->dwc_ep.sent_zlp = 0;
16801 + ep->dwc_ep.total_len = req->req.length;
16802 + ep->dwc_ep.xfer_len = 0;
16803 + ep->dwc_ep.xfer_count = 0;
16805 + if(max_transfer > MAX_TRANSFER_SIZE) {
16806 + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
16808 + ep->dwc_ep.maxxfer = max_transfer;
16811 + if(req->req.zero) {
16812 + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
16813 + && (ep->dwc_ep.total_len != 0)) {
16814 + ep->dwc_ep.sent_zlp = 1;
16818 + ep_check_and_patch_dma_addr(ep);
16819 + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
16824 + * This function handles the SOF Interrupts. At this time the SOF
16825 + * Interrupt is disabled.
16827 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
16829 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
16831 + gintsts_data_t gintsts;
16833 + DWC_DEBUGPL(DBG_PCD, "SOF\n");
16835 + /* Clear interrupt */
16837 + gintsts.b.sofintr = 1;
16838 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
16845 + * This function handles the Rx Status Queue Level Interrupt, which
16846 + * indicates that there is a least one packet in the Rx FIFO. The
16847 + * packets are moved from the FIFO to memory, where they will be
16848 + * processed when the Endpoint Interrupt Register indicates Transfer
16849 + * Complete or SETUP Phase Done.
16851 + * Repeat the following until the Rx Status Queue is empty:
16852 + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
16854 + * -# If Receive FIFO is empty then skip to step Clear the interrupt
16856 + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
16857 + * SETUP data to the buffer
16858 + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
16859 + * to the destination buffer
16861 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
16863 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
16864 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
16865 + gintmsk_data_t gintmask = {.d32=0};
16866 + device_grxsts_data_t status;
16867 + dwc_otg_pcd_ep_t *ep;
16868 + gintsts_data_t gintsts;
16870 + static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" };
16873 + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
16874 + /* Disable the Rx Status Queue Level interrupt */
16875 + gintmask.b.rxstsqlvl= 1;
16876 + dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
16878 + /* Get the Status from the top of the FIFO */
16879 + status.d32 = dwc_read_reg32(&global_regs->grxstsp);
16881 + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
16882 + "pktsts:%x Frame:%d(0x%0x)\n",
16883 + status.b.epnum, status.b.bcnt,
16884 + dpid_str[status.b.dpid],
16885 + status.b.pktsts, status.b.fn, status.b.fn);
16886 + /* Get pointer to EP structure */
16887 + ep = get_out_ep(pcd, status.b.epnum);
16889 + switch (status.b.pktsts) {
16890 + case DWC_DSTS_GOUT_NAK:
16891 + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
16893 + case DWC_STS_DATA_UPDT:
16894 + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
16895 + if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
16896 + /** @todo NGS Check for buffer overflow? */
16897 + dwc_otg_read_packet(core_if,
16898 + ep->dwc_ep.xfer_buff,
16900 + ep->dwc_ep.xfer_count += status.b.bcnt;
16901 + ep->dwc_ep.xfer_buff += status.b.bcnt;
16904 + case DWC_STS_XFER_COMP:
16905 + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
16907 + case DWC_DSTS_SETUP_COMP:
16909 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
16912 +case DWC_DSTS_SETUP_UPDT:
16913 + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
16915 + DWC_DEBUGPL(DBG_PCD,
16916 + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
16917 + pcd->setup_pkt->req.bRequestType,
16918 + pcd->setup_pkt->req.bRequest,
16919 + pcd->setup_pkt->req.wValue,
16920 + pcd->setup_pkt->req.wIndex,
16921 + pcd->setup_pkt->req.wLength);
16923 + ep->dwc_ep.xfer_count += status.b.bcnt;
16926 + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
16927 + status.b.pktsts);
16931 + /* Enable the Rx Status Queue Level interrupt */
16932 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
16933 + /* Clear interrupt */
16935 + gintsts.b.rxstsqlvl = 1;
16936 + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
16938 + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
16942 + * This function examines the Device IN Token Learning Queue to
16943 + * determine the EP number of the last IN token received. This
16944 + * implementation is for the Mass Storage device where there are only
16945 + * 2 IN EPs (Control-IN and BULK-IN).
16947 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
16948 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
16950 + * @param core_if Programming view of DWC_otg controller.
16953 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
16955 + dwc_otg_device_global_regs_t *dev_global_regs =
16956 + core_if->dev_if->dev_global_regs;
16957 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
16958 + /* Number of Token Queue Registers */
16959 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
16960 + dtknq1_data_t dtknqr1;
16961 + uint32_t in_tkn_epnums[4];
16964 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
16967 + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
16969 + /* Read the DTKNQ Registers */
16970 + for (i = 0; i < DTKNQ_REG_CNT; i++)
16972 + in_tkn_epnums[ i ] = dwc_read_reg32(addr);
16973 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1,
16974 + in_tkn_epnums[i]);
16975 + if (addr == &dev_global_regs->dvbusdis) {
16976 + addr = &dev_global_regs->dtknqr3_dthrctl;
16983 + /* Copy the DTKNQR1 data to the bit field. */
16984 + dtknqr1.d32 = in_tkn_epnums[0];
16985 + /* Get the EP numbers */
16986 + in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
16987 + ndx = dtknqr1.b.intknwptr - 1;
16989 + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
16991 + /** @todo Find a simpler way to calculate the max
16992 + * queue position.*/
16993 + int cnt = TOKEN_Q_DEPTH;
16994 + if (TOKEN_Q_DEPTH <= 6) {
16995 + cnt = TOKEN_Q_DEPTH - 1;
16997 + else if (TOKEN_Q_DEPTH <= 14) {
16998 + cnt = TOKEN_Q_DEPTH - 7;
17000 + else if (TOKEN_Q_DEPTH <= 22) {
17001 + cnt = TOKEN_Q_DEPTH - 15;
17004 + cnt = TOKEN_Q_DEPTH - 23;
17006 + epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF;
17010 + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
17012 + else if (ndx <= 13) {
17014 + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
17016 + else if (ndx <= 21) {
17018 + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
17020 + else if (ndx <= 29) {
17022 + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
17025 + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
17030 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
17031 + * The active request is checked for the next packet to be loaded into
17032 + * the non-periodic Tx FIFO.
17034 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
17036 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17037 + dwc_otg_core_global_regs_t *global_regs =
17038 + core_if->core_global_regs;
17039 + dwc_otg_dev_in_ep_regs_t *ep_regs;
17040 + gnptxsts_data_t txstatus = {.d32 = 0};
17041 + gintsts_data_t gintsts;
17044 + dwc_otg_pcd_ep_t *ep = 0;
17045 + uint32_t len = 0;
17048 + /* Get the epnum from the IN Token Learning Queue. */
17049 + epnum = get_ep_of_last_in_token(core_if);
17050 + ep = get_in_ep(pcd, epnum);
17052 + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
17053 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
17055 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17056 + if (len > ep->dwc_ep.maxpacket) {
17057 + len = ep->dwc_ep.maxpacket;
17059 + dwords = (len + 3)/4;
17061 + /* While there is space in the queue and space in the FIFO and
17062 + * More data to tranfer, Write packets to the Tx FIFO */
17063 + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
17064 + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32);
17066 + while (txstatus.b.nptxqspcavail > 0 &&
17067 + txstatus.b.nptxfspcavail > dwords &&
17068 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
17069 + /* Write the FIFO */
17070 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
17071 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17073 + if (len > ep->dwc_ep.maxpacket) {
17074 + len = ep->dwc_ep.maxpacket;
17077 + dwords = (len + 3)/4;
17078 + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
17079 + DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32);
17082 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
17083 + dwc_read_reg32(&global_regs->gnptxsts));
17085 + /* Clear interrupt */
17087 + gintsts.b.nptxfempty = 1;
17088 + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
17094 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
17095 + * The active request is checked for the next packet to be loaded into
17096 + * apropriate Tx FIFO.
17098 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
17100 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17101 + dwc_otg_dev_if_t* dev_if = core_if->dev_if;
17102 + dwc_otg_dev_in_ep_regs_t *ep_regs;
17103 + dtxfsts_data_t txstatus = {.d32 = 0};
17104 + dwc_otg_pcd_ep_t *ep = 0;
17105 + uint32_t len = 0;
17108 + ep = get_in_ep(pcd, epnum);
17110 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
17112 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
17114 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17116 + if (len > ep->dwc_ep.maxpacket) {
17117 + len = ep->dwc_ep.maxpacket;
17120 + dwords = (len + 3)/4;
17122 + /* While there is space in the queue and space in the FIFO and
17123 + * More data to tranfer, Write packets to the Tx FIFO */
17124 + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
17125 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32);
17127 + while (txstatus.b.txfspcavail > dwords &&
17128 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
17129 + ep->dwc_ep.xfer_len != 0) {
17130 + /* Write the FIFO */
17131 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
17133 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17134 + if (len > ep->dwc_ep.maxpacket) {
17135 + len = ep->dwc_ep.maxpacket;
17138 + dwords = (len + 3)/4;
17139 + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
17140 + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
17143 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
17149 + * This function is called when the Device is disconnected. It stops
17150 + * any active requests and informs the Gadget driver of the
17153 +void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
17155 + int i, num_in_eps, num_out_eps;
17156 + dwc_otg_pcd_ep_t *ep;
17158 + gintmsk_data_t intr_mask = {.d32 = 0};
17160 + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
17161 + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
17163 + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
17164 + /* don't disconnect drivers more than once */
17165 + if (pcd->ep0state == EP0_DISCONNECT) {
17166 + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
17169 + pcd->ep0state = EP0_DISCONNECT;
17171 + /* Reset the OTG state. */
17172 + dwc_otg_pcd_update_otg(pcd, 1);
17174 + /* Disable the NP Tx Fifo Empty Interrupt. */
17175 + intr_mask.b.nptxfempty = 1;
17176 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17177 + intr_mask.d32, 0);
17179 + /* Flush the FIFOs */
17180 + /**@todo NGS Flush Periodic FIFOs */
17181 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
17182 + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
17184 + /* prevent new request submissions, kill any outstanding requests */
17186 + dwc_otg_request_nuke(ep);
17187 + /* prevent new request submissions, kill any outstanding requests */
17188 + for (i = 0; i < num_in_eps; i++)
17190 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
17191 + dwc_otg_request_nuke(ep);
17193 + /* prevent new request submissions, kill any outstanding requests */
17194 + for (i = 0; i < num_out_eps; i++)
17196 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
17197 + dwc_otg_request_nuke(ep);
17200 + /* report disconnect; the driver is already quiesced */
17201 + if (pcd->driver && pcd->driver->disconnect) {
17202 + SPIN_UNLOCK(&pcd->lock);
17203 + pcd->driver->disconnect(&pcd->gadget);
17204 + SPIN_LOCK(&pcd->lock);
17209 + * This interrupt indicates that ...
17211 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
17213 + gintmsk_data_t intr_mask = { .d32 = 0};
17214 + gintsts_data_t gintsts;
17216 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr");
17217 + intr_mask.b.i2cintr = 1;
17218 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17219 + intr_mask.d32, 0);
17221 + /* Clear interrupt */
17223 + gintsts.b.i2cintr = 1;
17224 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17231 + * This interrupt indicates that ...
17233 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
17235 + gintsts_data_t gintsts;
17236 +#if defined(VERBOSE)
17237 + DWC_PRINT("Early Suspend Detected\n");
17239 + /* Clear interrupt */
17241 + gintsts.b.erlysuspend = 1;
17242 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17248 + * This function configures EPO to receive SETUP packets.
17250 + * @todo NGS: Update the comments from the HW FS.
17252 + * -# Program the following fields in the endpoint specific registers
17253 + * for Control OUT EP 0, in order to receive a setup packet
17254 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
17256 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
17257 + * to back setup packets)
17258 + * - In DMA mode, DOEPDMA0 Register with a memory address to
17259 + * store any setup packets received
17261 + * @param core_if Programming view of DWC_otg controller.
17262 + * @param pcd Programming view of the PCD.
17264 +static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
17266 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
17267 + deptsiz0_data_t doeptsize0 = { .d32 = 0};
17268 + dwc_otg_dma_desc_t* dma_desc;
17269 + depctl_data_t doepctl = { .d32 = 0 };
17272 + DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__,
17273 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
17276 + doeptsize0.b.supcnt = 3;
17277 + doeptsize0.b.pktcnt = 1;
17278 + doeptsize0.b.xfersize = 8*3;
17280 + if (core_if->dma_enable) {
17281 + if (!core_if->dma_desc_enable) {
17282 + /** put here as for Hermes mode deptisz register should not be written */
17283 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
17286 + /** @todo dma needs to handle multiple setup packets (up to 3) */
17287 + VERIFY_PCD_DMA_ADDR(pcd->setup_pkt_dma_handle);
17289 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
17290 + pcd->setup_pkt_dma_handle);
17292 + dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1;
17293 + dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index];
17295 + /** DMA Descriptor Setup */
17296 + dma_desc->status.b.bs = BS_HOST_BUSY;
17297 + dma_desc->status.b.l = 1;
17298 + dma_desc->status.b.ioc = 1;
17299 + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
17300 + dma_desc->buf = pcd->setup_pkt_dma_handle;
17301 + dma_desc->status.b.bs = BS_HOST_READY;
17303 + /** DOEPDMA0 Register write */
17304 + VERIFY_PCD_DMA_ADDR(dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
17305 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
17309 + /** put here as for Hermes mode deptisz register should not be written */
17310 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
17314 + /** DOEPCTL0 Register write */
17315 + doepctl.b.epena = 1;
17316 + doepctl.b.cnak = 1;
17317 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
17320 + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
17321 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
17322 + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
17323 + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
17328 + * This interrupt occurs when a USB Reset is detected. When the USB
17329 + * Reset Interrupt occurs the device state is set to DEFAULT and the
17330 + * EP0 state is set to IDLE.
17331 + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
17332 + * -# Unmask the following interrupt bits
17333 + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
17334 + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
17335 + * - DOEPMSK.SETUP = 1
17336 + * - DOEPMSK.XferCompl = 1
17337 + * - DIEPMSK.XferCompl = 1
17338 + * - DIEPMSK.TimeOut = 1
17339 + * -# Program the following fields in the endpoint specific registers
17340 + * for Control OUT EP 0, in order to receive a setup packet
17341 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
17343 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
17344 + * to back setup packets)
17345 + * - In DMA mode, DOEPDMA0 Register with a memory address to
17346 + * store any setup packets received
17347 + * At this point, all the required initialization, except for enabling
17348 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
17350 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
17352 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17353 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
17354 + depctl_data_t doepctl = { .d32 = 0};
17356 + daint_data_t daintmsk = { .d32 = 0};
17357 + doepmsk_data_t doepmsk = { .d32 = 0};
17358 + diepmsk_data_t diepmsk = { .d32 = 0};
17360 + dcfg_data_t dcfg = { .d32=0 };
17361 + grstctl_t resetctl = { .d32=0 };
17362 + dctl_data_t dctl = {.d32=0};
17364 + gintsts_data_t gintsts;
17366 + DWC_PRINT("USB RESET\n");
17367 +#ifdef DWC_EN_ISOC
17368 + for(i = 1;i < 16; ++i)
17370 + dwc_otg_pcd_ep_t *ep;
17371 + dwc_ep_t *dwc_ep;
17372 + ep = get_in_ep(pcd,i);
17374 + dwc_ep = &ep->dwc_ep;
17375 + dwc_ep->next_frame = 0xffffffff;
17378 +#endif /* DWC_EN_ISOC */
17380 + /* reset the HNP settings */
17381 + dwc_otg_pcd_update_otg(pcd, 1);
17383 + /* Clear the Remote Wakeup Signalling */
17384 + dctl.b.rmtwkupsig = 1;
17385 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
17388 + /* Set NAK for all OUT EPs */
17389 + doepctl.b.snak = 1;
17390 + for (i=0; i <= dev_if->num_out_eps; i++)
17392 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl,
17396 + /* Flush the NP Tx FIFO */
17397 + dwc_otg_flush_tx_fifo(core_if, 0x10);
17398 + /* Flush the Learning Queue */
17399 + resetctl.b.intknqflsh = 1;
17400 + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
17402 + if(core_if->multiproc_int_enable) {
17403 + daintmsk.b.inep0 = 1;
17404 + daintmsk.b.outep0 = 1;
17405 + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32);
17407 + doepmsk.b.setup = 1;
17408 + doepmsk.b.xfercompl = 1;
17409 + doepmsk.b.ahberr = 1;
17410 + doepmsk.b.epdisabled = 1;
17412 + if(core_if->dma_desc_enable) {
17413 + doepmsk.b.stsphsercvd = 1;
17414 + doepmsk.b.bna = 1;
17417 + doepmsk.b.babble = 1;
17418 + doepmsk.b.nyet = 1;
17420 + if(core_if->dma_enable) {
17421 + doepmsk.b.nak = 1;
17424 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32);
17426 + diepmsk.b.xfercompl = 1;
17427 + diepmsk.b.timeout = 1;
17428 + diepmsk.b.epdisabled = 1;
17429 + diepmsk.b.ahberr = 1;
17430 + diepmsk.b.intknepmis = 1;
17432 + if(core_if->dma_desc_enable) {
17433 + diepmsk.b.bna = 1;
17436 + if(core_if->dma_enable) {
17437 + diepmsk.b.nak = 1;
17440 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32);
17442 + daintmsk.b.inep0 = 1;
17443 + daintmsk.b.outep0 = 1;
17444 + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32);
17446 + doepmsk.b.setup = 1;
17447 + doepmsk.b.xfercompl = 1;
17448 + doepmsk.b.ahberr = 1;
17449 + doepmsk.b.epdisabled = 1;
17451 + if(core_if->dma_desc_enable) {
17452 + doepmsk.b.stsphsercvd = 1;
17453 + doepmsk.b.bna = 1;
17456 + doepmsk.b.babble = 1;
17457 + doepmsk.b.nyet = 1;
17458 + doepmsk.b.nak = 1;
17460 + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
17462 + diepmsk.b.xfercompl = 1;
17463 + diepmsk.b.timeout = 1;
17464 + diepmsk.b.epdisabled = 1;
17465 + diepmsk.b.ahberr = 1;
17466 + diepmsk.b.intknepmis = 1;
17468 + if(core_if->dma_desc_enable) {
17469 + diepmsk.b.bna = 1;
17472 +// diepmsk.b.nak = 1;
17474 + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
17477 + /* Reset Device Address */
17478 + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
17479 + dcfg.b.devaddr = 0;
17480 + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
17482 + /* setup EP0 to receive SETUP packets */
17483 + ep0_out_start(core_if, pcd);
17485 + /* Clear interrupt */
17487 + gintsts.b.usbreset = 1;
17488 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
17494 + * Get the device speed from the device status register and convert it
17495 + * to USB speed constant.
17497 + * @param core_if Programming view of DWC_otg controller.
17499 +static int get_device_speed(dwc_otg_core_if_t *core_if)
17501 + dsts_data_t dsts;
17502 + enum usb_device_speed speed = USB_SPEED_UNKNOWN;
17503 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
17505 + switch (dsts.b.enumspd) {
17506 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
17507 + speed = USB_SPEED_HIGH;
17509 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
17510 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
17511 + speed = USB_SPEED_FULL;
17514 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
17515 + speed = USB_SPEED_LOW;
17523 + * Read the device status register and set the device speed in the
17524 + * data structure.
17525 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
17527 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
17529 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17530 + gintsts_data_t gintsts;
17531 + gusbcfg_data_t gusbcfg;
17532 + dwc_otg_core_global_regs_t *global_regs =
17533 + GET_CORE_IF(pcd)->core_global_regs;
17534 + uint8_t utmi16b, utmi8b;
17535 +// DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
17536 + DWC_PRINT("SPEED ENUM\n");
17538 + if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) {
17545 + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
17548 + print_ep0_state(pcd);
17551 + if (pcd->ep0state == EP0_DISCONNECT) {
17552 + pcd->ep0state = EP0_IDLE;
17554 + else if (pcd->ep0state == EP0_STALL) {
17555 + pcd->ep0state = EP0_IDLE;
17558 + pcd->ep0state = EP0_IDLE;
17560 + ep0->stopped = 0;
17562 + pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd));
17564 + /* Set USB turnaround time based on device speed and PHY interface. */
17565 + gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
17566 + if (pcd->gadget.speed == USB_SPEED_HIGH) {
17567 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
17568 + /* ULPI interface */
17569 + gusbcfg.b.usbtrdtim = 9;
17571 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
17572 + /* UTMI+ interface */
17573 + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
17574 + gusbcfg.b.usbtrdtim = utmi8b;
17576 + else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) {
17577 + gusbcfg.b.usbtrdtim = utmi16b;
17579 + else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) {
17580 + gusbcfg.b.usbtrdtim = utmi8b;
17583 + gusbcfg.b.usbtrdtim = utmi16b;
17586 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
17587 + /* UTMI+ OR ULPI interface */
17588 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
17589 + /* ULPI interface */
17590 + gusbcfg.b.usbtrdtim = 9;
17593 + /* UTMI+ interface */
17594 + if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) {
17595 + gusbcfg.b.usbtrdtim = utmi16b;
17598 + gusbcfg.b.usbtrdtim = utmi8b;
17604 + /* Full or low speed */
17605 + gusbcfg.b.usbtrdtim = 9;
17607 + dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
17609 + /* Clear interrupt */
17611 + gintsts.b.enumdone = 1;
17612 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17618 + * This interrupt indicates that the ISO OUT Packet was dropped due to
17619 + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
17620 + * read all the data from the Rx FIFO.
17622 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
17624 + gintmsk_data_t intr_mask = { .d32 = 0};
17625 + gintsts_data_t gintsts;
17627 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
17628 + "ISOC Out Dropped");
17630 + intr_mask.b.isooutdrop = 1;
17631 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17632 + intr_mask.d32, 0);
17634 + /* Clear interrupt */
17637 + gintsts.b.isooutdrop = 1;
17638 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17645 + * This interrupt indicates the end of the portion of the micro-frame
17646 + * for periodic transactions. If there is a periodic transaction for
17647 + * the next frame, load the packets into the EP periodic Tx FIFO.
17649 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
17651 + gintmsk_data_t intr_mask = { .d32 = 0};
17652 + gintsts_data_t gintsts;
17653 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP");
17655 + intr_mask.b.eopframe = 1;
17656 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17657 + intr_mask.d32, 0);
17659 + /* Clear interrupt */
17661 + gintsts.b.eopframe = 1;
17662 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32);
17668 + * This interrupt indicates that EP of the packet on the top of the
17669 + * non-periodic Tx FIFO does not match EP of the IN Token received.
17671 + * The "Device IN Token Queue" Registers are read to determine the
17672 + * order the IN Tokens have been received. The non-periodic Tx FIFO
17673 + * is flushed, so it can be reloaded in the order seen in the IN Token
17676 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if)
17678 + gintsts_data_t gintsts;
17679 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
17681 + /* Clear interrupt */
17683 + gintsts.b.epmismatch = 1;
17684 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
17690 + * This funcion stalls EP0.
17692 +static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
17694 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17695 + struct usb_ctrlrequest *ctrl = &pcd->setup_pkt->req;
17696 + DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
17697 + ctrl->bRequestType, ctrl->bRequest, err_val);
17699 + ep0->dwc_ep.is_in = 1;
17700 + dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep);
17701 + pcd->ep0.stopped = 1;
17702 + pcd->ep0state = EP0_IDLE;
17703 + ep0_out_start(GET_CORE_IF(pcd), pcd);
17707 + * This functions delegates the setup command to the gadget driver.
17709 +static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
17710 + struct usb_ctrlrequest * ctrl)
17713 + if (pcd->driver && pcd->driver->setup) {
17714 + SPIN_UNLOCK(&pcd->lock);
17715 + ret = pcd->driver->setup(&pcd->gadget, ctrl);
17716 + SPIN_LOCK(&pcd->lock);
17718 + ep0_do_stall(pcd, ret);
17721 + /** @todo This is a g_file_storage gadget driver specific
17722 + * workaround: a DELAYED_STATUS result from the fsg_setup
17723 + * routine will result in the gadget queueing a EP0 IN status
17724 + * phase for a two-stage control transfer. Exactly the same as
17725 + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
17726 + * specific request. Need a generic way to know when the gadget
17727 + * driver will queue the status phase. Can we assume when we
17728 + * call the gadget driver setup() function that it will always
17729 + * queue and require the following flag? Need to look into
17733 + if (ret == 256 + 999) {
17734 + pcd->request_config = 1;
17740 + * This function starts the Zero-Length Packet for the IN status phase
17741 + * of a 2 stage control transfer.
17743 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
17745 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17746 + if (pcd->ep0state == EP0_STALL) {
17750 + pcd->ep0state = EP0_IN_STATUS_PHASE;
17752 + /* Prepare for more SETUP Packets */
17753 + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
17754 + ep0->dwc_ep.xfer_len = 0;
17755 + ep0->dwc_ep.xfer_count = 0;
17756 + ep0->dwc_ep.is_in = 1;
17757 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
17758 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
17760 + /* Prepare for more SETUP Packets */
17761 +// if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd);
17765 + * This function starts the Zero-Length Packet for the OUT status phase
17766 + * of a 2 stage control transfer.
17768 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
17770 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17771 + if (pcd->ep0state == EP0_STALL) {
17772 + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
17775 + pcd->ep0state = EP0_OUT_STATUS_PHASE;
17777 + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
17778 + ep0->dwc_ep.xfer_len = 0;
17779 + ep0->dwc_ep.xfer_count = 0;
17780 + ep0->dwc_ep.is_in = 0;
17781 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
17782 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
17784 + /* Prepare for more SETUP Packets */
17785 + if(GET_CORE_IF(pcd)->dma_enable == 0) {
17786 + ep0_out_start(GET_CORE_IF(pcd), pcd);
17791 + * Clear the EP halt (STALL) and if pending requests start the
17794 +static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
17796 + if(ep->dwc_ep.stall_clear_flag == 0)
17797 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
17799 + /* Reactive the EP */
17800 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
17801 + if (ep->stopped) {
17803 + /* If there is a request in the EP queue start it */
17805 + /** @todo FIXME: this causes an EP mismatch in DMA mode.
17806 + * epmismatch not yet implemented. */
17809 + * Above fixme is solved by implmenting a tasklet to call the
17810 + * start_next_request(), outside of interrupt context at some
17811 + * time after the current time, after a clear-halt setup packet.
17812 + * Still need to implement ep mismatch in the future if a gadget
17813 + * ever uses more than one endpoint at once
17815 + ep->queue_sof = 1;
17816 + tasklet_schedule (pcd->start_xfer_tasklet);
17818 + /* Start Control Status Phase */
17819 + do_setup_in_status_phase(pcd);
17823 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
17824 + * is sent from the host. The Device Control register is written with
17825 + * the Test Mode bits set to the specified Test Mode. This is done as
17826 + * a tasklet so that the "Status" phase of the control transfer
17827 + * completes before transmitting the TEST packets.
17829 + * @todo This has not been tested since the tasklet struct was put
17830 + * into the PCD struct!
17833 +static void do_test_mode(unsigned long data)
17835 + dctl_data_t dctl;
17836 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data;
17837 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17838 + int test_mode = pcd->test_mode;
17841 +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
17843 + dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
17844 + switch (test_mode) {
17845 + case 1: // TEST_J
17846 + dctl.b.tstctl = 1;
17849 + case 2: // TEST_K
17850 + dctl.b.tstctl = 2;
17853 + case 3: // TEST_SE0_NAK
17854 + dctl.b.tstctl = 3;
17857 + case 4: // TEST_PACKET
17858 + dctl.b.tstctl = 4;
17861 + case 5: // TEST_FORCE_ENABLE
17862 + dctl.b.tstctl = 5;
17865 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
17869 + * This function process the GET_STATUS Setup Commands.
17871 +static inline void do_get_status(dwc_otg_pcd_t *pcd)
17873 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
17874 + dwc_otg_pcd_ep_t *ep;
17875 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17876 + uint16_t *status = pcd->status_buf;
17879 + DWC_DEBUGPL(DBG_PCD,
17880 + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
17881 + ctrl.bRequestType, ctrl.bRequest,
17882 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
17885 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
17886 + case USB_RECIP_DEVICE:
17887 + *status = 0x1; /* Self powered */
17888 + *status |= pcd->remote_wakeup_enable << 1;
17891 + case USB_RECIP_INTERFACE:
17895 + case USB_RECIP_ENDPOINT:
17896 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
17897 + if (ep == 0 || ctrl.wLength > 2) {
17898 + ep0_do_stall(pcd, -EOPNOTSUPP);
17901 + /** @todo check for EP stall */
17902 + *status = ep->stopped;
17905 + pcd->ep0_pending = 1;
17906 + ep0->dwc_ep.start_xfer_buff = (uint8_t *)status;
17907 + ep0->dwc_ep.xfer_buff = (uint8_t *)status;
17908 + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
17909 + ep0->dwc_ep.xfer_len = 2;
17910 + ep0->dwc_ep.xfer_count = 0;
17911 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
17912 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
17915 + * This function process the SET_FEATURE Setup Commands.
17917 +static inline void do_set_feature(dwc_otg_pcd_t *pcd)
17919 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17920 + dwc_otg_core_global_regs_t *global_regs =
17921 + core_if->core_global_regs;
17922 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
17923 + dwc_otg_pcd_ep_t *ep = 0;
17924 + int32_t otg_cap_param = core_if->core_params->otg_cap;
17925 + gotgctl_data_t gotgctl = { .d32 = 0 };
17927 + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
17928 + ctrl.bRequestType, ctrl.bRequest,
17929 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
17930 + DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param);
17933 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
17934 + case USB_RECIP_DEVICE:
17935 + switch (ctrl.wValue) {
17936 + case USB_DEVICE_REMOTE_WAKEUP:
17937 + pcd->remote_wakeup_enable = 1;
17940 + case USB_DEVICE_TEST_MODE:
17941 + /* Setup the Test Mode tasklet to do the Test
17942 + * Packet generation after the SETUP Status
17943 + * phase has completed. */
17945 + /** @todo This has not been tested since the
17946 + * tasklet struct was put into the PCD
17948 + pcd->test_mode_tasklet.next = 0;
17949 + pcd->test_mode_tasklet.state = 0;
17950 + atomic_set(&pcd->test_mode_tasklet.count, 0);
17951 + pcd->test_mode_tasklet.func = do_test_mode;
17952 + pcd->test_mode_tasklet.data = (unsigned long)pcd;
17953 + pcd->test_mode = ctrl.wIndex >> 8;
17954 + tasklet_schedule(&pcd->test_mode_tasklet);
17957 + case USB_DEVICE_B_HNP_ENABLE:
17958 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
17960 + /* dev may initiate HNP */
17961 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
17962 + pcd->b_hnp_enable = 1;
17963 + dwc_otg_pcd_update_otg(pcd, 0);
17964 + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
17965 + /**@todo Is the gotgctl.devhnpen cleared
17966 + * by a USB Reset? */
17967 + gotgctl.b.devhnpen = 1;
17968 + gotgctl.b.hnpreq = 1;
17969 + dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32);
17972 + ep0_do_stall(pcd, -EOPNOTSUPP);
17976 + case USB_DEVICE_A_HNP_SUPPORT:
17977 + /* RH port supports HNP */
17978 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
17979 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
17980 + pcd->a_hnp_support = 1;
17981 + dwc_otg_pcd_update_otg(pcd, 0);
17984 + ep0_do_stall(pcd, -EOPNOTSUPP);
17988 + case USB_DEVICE_A_ALT_HNP_SUPPORT:
17989 + /* other RH port does */
17990 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
17991 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
17992 + pcd->a_alt_hnp_support = 1;
17993 + dwc_otg_pcd_update_otg(pcd, 0);
17996 + ep0_do_stall(pcd, -EOPNOTSUPP);
18000 + do_setup_in_status_phase(pcd);
18003 + case USB_RECIP_INTERFACE:
18004 + do_gadget_setup(pcd, &ctrl);
18007 + case USB_RECIP_ENDPOINT:
18008 + if (ctrl.wValue == USB_ENDPOINT_HALT) {
18009 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
18011 + ep0_do_stall(pcd, -EOPNOTSUPP);
18015 + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
18017 + do_setup_in_status_phase(pcd);
18023 + * This function process the CLEAR_FEATURE Setup Commands.
18025 +static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
18027 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18028 + dwc_otg_pcd_ep_t *ep = 0;
18030 + DWC_DEBUGPL(DBG_PCD,
18031 + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
18032 + ctrl.bRequestType, ctrl.bRequest,
18033 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
18035 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
18036 + case USB_RECIP_DEVICE:
18037 + switch (ctrl.wValue) {
18038 + case USB_DEVICE_REMOTE_WAKEUP:
18039 + pcd->remote_wakeup_enable = 0;
18042 + case USB_DEVICE_TEST_MODE:
18043 + /** @todo Add CLEAR_FEATURE for TEST modes. */
18046 + do_setup_in_status_phase(pcd);
18049 + case USB_RECIP_ENDPOINT:
18050 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
18052 + ep0_do_stall(pcd, -EOPNOTSUPP);
18056 + pcd_clear_halt(pcd, ep);
18063 + * This function process the SET_ADDRESS Setup Commands.
18065 +static inline void do_set_address(dwc_otg_pcd_t *pcd)
18067 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
18068 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18070 + if (ctrl.bRequestType == USB_RECIP_DEVICE) {
18071 + dcfg_data_t dcfg = {.d32=0};
18074 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
18076 + dcfg.b.devaddr = ctrl.wValue;
18077 + dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
18078 + do_setup_in_status_phase(pcd);
18083 + * This function processes SETUP commands. In Linux, the USB Command
18084 + * processing is done in two places - the first being the PCD and the
18085 + * second in the Gadget Driver (for example, the File-Backed Storage
18086 + * Gadget Driver).
18089 + * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
18091 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
18092 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
18095 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
18096 + * requests are the ENDPOINT_HALT feature is procesed, all others the
18097 + * interface requests are ignored.</td></tr>
18099 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
18100 + * requests are processed by the PCD. Interface requests are passed
18101 + * to the Gadget Driver.</td></tr>
18103 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
18104 + * with device address received </td></tr>
18106 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
18107 + * requested descriptor</td></tr>
18109 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
18110 + * not implemented by any of the existing Gadget Drivers.</td></tr>
18112 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
18113 + * all EPs and enable EPs for new configuration.</td></tr>
18115 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
18116 + * the current configuration</td></tr>
18118 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
18119 + * EPs and enable EPs for new configuration.</td></tr>
18121 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
18122 + * current interface.</td></tr>
18124 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
18125 + * message.</td></tr>
18128 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
18129 + * processed by pcd_setup. Calling the Function Driver's setup function from
18130 + * pcd_setup processes the gadget SETUP commands.
18132 +static inline void pcd_setup(dwc_otg_pcd_t *pcd)
18134 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18135 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18136 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18137 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
18139 + deptsiz0_data_t doeptsize0 = { .d32 = 0};
18142 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
18143 + ctrl.bRequestType, ctrl.bRequest,
18144 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
18147 + doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
18149 + /** @todo handle > 1 setup packet , assert error for now */
18151 + if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) {
18152 + DWC_ERROR ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
18155 + /* Clean up the request queue */
18156 + dwc_otg_request_nuke(ep0);
18157 + ep0->stopped = 0;
18159 + if (ctrl.bRequestType & USB_DIR_IN) {
18160 + ep0->dwc_ep.is_in = 1;
18161 + pcd->ep0state = EP0_IN_DATA_PHASE;
18164 + ep0->dwc_ep.is_in = 0;
18165 + pcd->ep0state = EP0_OUT_DATA_PHASE;
18168 + if(ctrl.wLength == 0) {
18169 + ep0->dwc_ep.is_in = 1;
18170 + pcd->ep0state = EP0_IN_STATUS_PHASE;
18173 + if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) {
18174 + /* handle non-standard (class/vendor) requests in the gadget driver */
18175 + do_gadget_setup(pcd, &ctrl);
18179 + /** @todo NGS: Handle bad setup packet? */
18181 +///////////////////////////////////////////
18182 +//// --- Standard Request handling --- ////
18184 + switch (ctrl.bRequest) {
18185 + case USB_REQ_GET_STATUS:
18186 + do_get_status(pcd);
18189 + case USB_REQ_CLEAR_FEATURE:
18190 + do_clear_feature(pcd);
18193 + case USB_REQ_SET_FEATURE:
18194 + do_set_feature(pcd);
18197 + case USB_REQ_SET_ADDRESS:
18198 + do_set_address(pcd);
18201 + case USB_REQ_SET_INTERFACE:
18202 + case USB_REQ_SET_CONFIGURATION:
18203 +// _pcd->request_config = 1; /* Configuration changed */
18204 + do_gadget_setup(pcd, &ctrl);
18207 + case USB_REQ_SYNCH_FRAME:
18208 + do_gadget_setup(pcd, &ctrl);
18212 + /* Call the Gadget Driver's setup functions */
18213 + do_gadget_setup(pcd, &ctrl);
18219 + * This function completes the ep0 control transfer.
18221 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
18223 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
18224 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18225 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
18226 + dev_if->in_ep_regs[ep->dwc_ep.num];
18228 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
18229 + dev_if->out_ep_regs[ep->dwc_ep.num];
18231 + deptsiz0_data_t deptsiz;
18232 + desc_sts_data_t desc_sts;
18233 + dwc_otg_pcd_request_t *req;
18235 + dwc_otg_pcd_t *pcd = ep->pcd;
18237 + //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name);
18239 + if (pcd->ep0_pending && list_empty(&ep->queue)) {
18240 + if (ep->dwc_ep.is_in) {
18242 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
18244 + do_setup_out_status_phase(pcd);
18248 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
18250 + do_setup_in_status_phase(pcd);
18252 + pcd->ep0_pending = 0;
18256 + if (list_empty(&ep->queue)) {
18259 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue);
18262 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
18265 + else if (ep->dwc_ep.is_in) {
18266 + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
18267 + if(core_if->dma_desc_enable != 0)
18268 + desc_sts.d32 = readl(dev_if->in_desc_addr);
18270 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18271 + ep->ep.name, ep->dwc_ep.xfer_len,
18272 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
18275 + if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) ||
18276 + ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) {
18277 + req->req.actual = ep->dwc_ep.xfer_count;
18278 + /* Is a Zero Len Packet needed? */
18279 + if (req->req.zero) {
18281 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
18283 + req->req.zero = 0;
18285 + do_setup_out_status_phase(pcd);
18291 + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
18292 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n",
18293 + ep->ep.name, ep->dwc_ep.xfer_len,
18294 + deptsiz.b.xfersize,
18295 + deptsiz.b.pktcnt);
18297 + req->req.actual = ep->dwc_ep.xfer_count;
18298 + /* Is a Zero Len Packet needed? */
18299 + if (req->req.zero) {
18301 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
18303 + req->req.zero = 0;
18305 + if(core_if->dma_desc_enable == 0)
18306 + do_setup_in_status_phase(pcd);
18309 + /* Complete the request */
18311 + dwc_otg_request_done(ep, req, 0);
18312 + ep->dwc_ep.start_xfer_buff = 0;
18313 + ep->dwc_ep.xfer_buff = 0;
18314 + ep->dwc_ep.xfer_len = 0;
18320 +inline void aligned_buf_patch_on_buf_dma_oep_completion(dwc_otg_pcd_ep_t *ep, uint32_t byte_count)
18322 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
18323 + if(byte_count && dwc_ep->aligned_buf &&
18324 + dwc_ep->dma_addr>=dwc_ep->aligned_dma_addr &&
18325 + dwc_ep->dma_addr<=(dwc_ep->aligned_dma_addr+dwc_ep->aligned_buf_size))\
18327 + //aligned buf used, apply complete patch
18328 + u32 offset=(dwc_ep->dma_addr-dwc_ep->aligned_dma_addr);
18329 + memcpy(dwc_ep->start_xfer_buff+offset, dwc_ep->aligned_buf+offset, byte_count);
18334 + * This function completes the request for the EP. If there are
18335 + * additional requests for the EP in the queue they will be started.
18337 +static void complete_ep(dwc_otg_pcd_ep_t *ep)
18339 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
18340 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18341 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
18342 + dev_if->in_ep_regs[ep->dwc_ep.num];
18343 + deptsiz_data_t deptsiz;
18344 + desc_sts_data_t desc_sts;
18345 + dwc_otg_pcd_request_t *req = 0;
18346 + dwc_otg_dma_desc_t* dma_desc;
18347 + uint32_t byte_count = 0;
18351 + DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name,
18352 + (ep->dwc_ep.is_in?"IN":"OUT"));
18354 + /* Get any pending requests */
18355 + if (!list_empty(&ep->queue)) {
18356 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
18359 + printk("complete_ep 0x%p, req = NULL!\n", ep);
18364 + printk("complete_ep 0x%p, ep->queue empty!\n", ep);
18367 + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
18369 + if (ep->dwc_ep.is_in) {
18370 + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
18372 + if (core_if->dma_enable) {
18373 + //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_NONE);
18374 + if(core_if->dma_desc_enable == 0) {
18375 + //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_NONE);
18376 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
18377 + byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
18378 +DWC_DEBUGPL(DBG_PCDV,"byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x)\n", byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count );
18380 + ep->dwc_ep.xfer_buff += byte_count;
18381 + ep->dwc_ep.dma_addr += byte_count;
18382 + ep->dwc_ep.xfer_count += byte_count;
18384 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18385 + ep->ep.name, ep->dwc_ep.xfer_len,
18386 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
18388 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18389 + //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18390 +printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18391 + } else if(ep->dwc_ep.sent_zlp) {
18393 + * This fragment of code should initiate 0
18394 + * length trasfer in case if it is queued
18395 + * a trasfer with size divisible to EPs max
18396 + * packet size and with usb_request zero field
18397 + * is set, which means that after data is transfered,
18398 + * it is also should be transfered
18399 + * a 0 length packet at the end. For Slave and
18400 + * Buffer DMA modes in this case SW has
18401 + * to initiate 2 transfers one with transfer size,
18402 + * and the second with 0 size. For Desriptor
18403 + * DMA mode SW is able to initiate a transfer,
18404 + * which will handle all the packets including
18405 + * the last 0 legth.
18407 + ep->dwc_ep.sent_zlp = 0;
18408 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18413 + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
18414 + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
18415 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
18419 + dma_desc = ep->dwc_ep.desc_addr;
18421 + ep->dwc_ep.sent_zlp = 0;
18423 + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
18424 + desc_sts.d32 = readl(dma_desc);
18425 + byte_count += desc_sts.b.bytes;
18429 + if(byte_count == 0) {
18430 + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len;
18433 + DWC_WARN("Incomplete transfer\n");
18437 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
18438 + /* Check if the whole transfer was completed,
18439 + * if no, setup transfer for next portion of data
18441 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18442 + ep->ep.name, ep->dwc_ep.xfer_len,
18443 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
18444 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18445 + //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18446 +printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, ep->dwc_ep.xfer_len(%.8x) \n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, ep->dwc_ep.xfer_len );
18447 + } else if(ep->dwc_ep.sent_zlp) {
18449 + * This fragment of code should initiate 0
18450 + * length trasfer in case if it is queued
18451 + * a trasfer with size divisible to EPs max
18452 + * packet size and with usb_request zero field
18453 + * is set, which means that after data is transfered,
18454 + * it is also should be transfered
18455 + * a 0 length packet at the end. For Slave and
18456 + * Buffer DMA modes in this case SW has
18457 + * to initiate 2 transfers one with transfer size,
18458 + * and the second with 0 size. For Desriptor
18459 + * DMA mode SW is able to initiate a transfer,
18460 + * which will handle all the packets including
18461 + * the last 0 legth.
18463 + ep->dwc_ep.sent_zlp = 0;
18464 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18470 + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
18471 + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
18472 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
18476 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
18477 + dev_if->out_ep_regs[ep->dwc_ep.num];
18478 + desc_sts.d32 = 0;
18479 + if(core_if->dma_enable) {
18480 + //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_FROM_DEVICE);
18481 + if(core_if->dma_desc_enable) {
18482 + DWC_WARN("\n\n%s: we need a cache invalidation here!!\n\n",__func__);
18483 + dma_desc = ep->dwc_ep.desc_addr;
18485 + ep->dwc_ep.sent_zlp = 0;
18486 + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
18487 + desc_sts.d32 = readl(dma_desc);
18488 + byte_count += desc_sts.b.bytes;
18492 + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
18493 + - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
18495 + //todo: invalidate cache & aligned buf patch on completion
18501 + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
18503 + byte_count = (ep->dwc_ep.xfer_len -
18504 + ep->dwc_ep.xfer_count - deptsiz.b.xfersize);
18506 +// dma_sync_single_for_device(NULL,ep->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
18508 +DWC_DEBUGPL(DBG_PCDV,"ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18509 + //todo: invalidate cache & aligned buf patch on completion
18510 + dma_sync_single_for_device(NULL,ep->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
18511 + aligned_buf_patch_on_buf_dma_oep_completion(ep,byte_count);
18513 + ep->dwc_ep.xfer_buff += byte_count;
18514 + ep->dwc_ep.dma_addr += byte_count;
18515 + ep->dwc_ep.xfer_count += byte_count;
18517 + /* Check if the whole transfer was completed,
18518 + * if no, setup transfer for next portion of data
18520 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18521 + //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18522 +printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18524 + else if(ep->dwc_ep.sent_zlp) {
18526 + * This fragment of code should initiate 0
18527 + * length trasfer in case if it is queued
18528 + * a trasfer with size divisible to EPs max
18529 + * packet size and with usb_request zero field
18530 + * is set, which means that after data is transfered,
18531 + * it is also should be transfered
18532 + * a 0 length packet at the end. For Slave and
18533 + * Buffer DMA modes in this case SW has
18534 + * to initiate 2 transfers one with transfer size,
18535 + * and the second with 0 size. For Desriptor
18536 + * DMA mode SW is able to initiate a transfer,
18537 + * which will handle all the packets including
18538 + * the last 0 legth.
18540 + ep->dwc_ep.sent_zlp = 0;
18541 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18547 + /* Check if the whole transfer was completed,
18548 + * if no, setup transfer for next portion of data
18550 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18551 + //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18552 +printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, ep->dwc_ep.xfer_len(%.8x) \n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, ep->dwc_ep.xfer_len );
18554 + else if(ep->dwc_ep.sent_zlp) {
18556 + * This fragment of code should initiate 0
18557 + * length trasfer in case if it is queued
18558 + * a trasfer with size divisible to EPs max
18559 + * packet size and with usb_request zero field
18560 + * is set, which means that after data is transfered,
18561 + * it is also should be transfered
18562 + * a 0 length packet at the end. For Slave and
18563 + * Buffer DMA modes in this case SW has
18564 + * to initiate 2 transfers one with transfer size,
18565 + * and the second with 0 size. For Desriptor
18566 + * DMA mode SW is able to initiate a transfer,
18567 + * which will handle all the packets including
18568 + * the last 0 legth.
18570 + ep->dwc_ep.sent_zlp = 0;
18571 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18579 + DWC_DEBUGPL(DBG_PCDV, "addr %p, %s len=%d cnt=%d xsize=%d pktcnt=%d\n",
18580 + &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len,
18581 + ep->dwc_ep.xfer_count,
18582 + deptsiz.b.xfersize,
18583 + deptsiz.b.pktcnt);
18587 + /* Complete the request */
18589 + req->req.actual = ep->dwc_ep.xfer_count;
18591 + dwc_otg_request_done(ep, req, 0);
18593 + ep->dwc_ep.start_xfer_buff = 0;
18594 + ep->dwc_ep.xfer_buff = 0;
18595 + ep->dwc_ep.xfer_len = 0;
18597 + /* If there is a request in the queue start it.*/
18598 + start_next_request(ep);
18603 +#ifdef DWC_EN_ISOC
18606 + * This function BNA interrupt for Isochronous EPs
18609 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
18611 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
18612 + volatile uint32_t *addr;
18613 + depctl_data_t depctl = {.d32 = 0};
18614 + dwc_otg_pcd_t *pcd = ep->pcd;
18615 + dwc_otg_dma_desc_t *dma_desc;
18618 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
18620 + if(dwc_ep->is_in) {
18621 + desc_sts_data_t sts = {.d32 = 0};
18622 + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
18624 + sts.d32 = readl(&dma_desc->status);
18625 + sts.b_iso_in.bs = BS_HOST_READY;
18626 + writel(sts.d32,&dma_desc->status);
18630 + desc_sts_data_t sts = {.d32 = 0};
18631 + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
18633 + sts.d32 = readl(&dma_desc->status);
18634 + sts.b_iso_out.bs = BS_HOST_READY;
18635 + writel(sts.d32,&dma_desc->status);
18639 + if(dwc_ep->is_in == 0){
18640 + addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
18643 + addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
18645 + depctl.b.epena = 1;
18646 + dwc_modify_reg32(addr,depctl.d32,depctl.d32);
18650 + * This function sets latest iso packet information(non-PTI mode)
18652 + * @param core_if Programming view of DWC_otg controller.
18653 + * @param ep The EP to start the transfer on.
18656 +void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
18658 + deptsiz_data_t deptsiz = { .d32 = 0 };
18659 + dma_addr_t dma_addr;
18662 + if(ep->proc_buf_num)
18663 + dma_addr = ep->dma_addr1;
18665 + dma_addr = ep->dma_addr0;
18668 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
18669 + offset = ep->data_per_frame;
18671 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
18672 + offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
18675 + if(!deptsiz.b.xfersize) {
18676 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
18677 + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
18678 + ep->pkt_info[ep->cur_pkt].status = 0;
18680 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
18681 + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
18682 + ep->pkt_info[ep->cur_pkt].status = -ENODATA;
18684 + ep->cur_pkt_addr += offset;
18685 + ep->cur_pkt_dma_addr += offset;
18690 + * This function sets latest iso packet information(DDMA mode)
18692 + * @param core_if Programming view of DWC_otg controller.
18693 + * @param dwc_ep The EP to start the transfer on.
18696 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
18698 + dwc_otg_dma_desc_t* dma_desc;
18699 + desc_sts_data_t sts = {.d32 = 0};
18700 + iso_pkt_info_t *iso_packet;
18701 + uint32_t data_per_desc;
18705 + iso_packet = dwc_ep->pkt_info;
18707 + /** Reinit closed DMA Descriptors*/
18708 + /** ISO OUT EP */
18709 + if(dwc_ep->is_in == 0) {
18710 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18713 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
18715 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
18717 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18718 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18719 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18721 + sts.d32 = readl(&dma_desc->status);
18723 + /* Write status in iso_packet_decsriptor */
18724 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18725 + if(iso_packet->status) {
18726 + iso_packet->status = -ENODATA;
18729 + /* Received data length */
18730 + if(!sts.b_iso_out.rxbytes){
18731 + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes;
18733 + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes +
18734 + (4 - dwc_ep->data_per_frame % 4);
18737 + iso_packet->offset = offset;
18739 + offset += data_per_desc;
18745 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
18747 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18748 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18749 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18751 + sts.d32 = readl(&dma_desc->status);
18753 + /* Write status in iso_packet_decsriptor */
18754 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18755 + if(iso_packet->status) {
18756 + iso_packet->status = -ENODATA;
18759 + /* Received data length */
18760 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
18762 + iso_packet->offset = offset;
18764 + offset += data_per_desc;
18769 + sts.d32 = readl(&dma_desc->status);
18771 + /* Write status in iso_packet_decsriptor */
18772 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18773 + if(iso_packet->status) {
18774 + iso_packet->status = -ENODATA;
18776 + /* Received data length */
18777 + if(!sts.b_iso_out.rxbytes){
18778 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
18780 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
18781 + (4 - dwc_ep->data_per_frame % 4);
18784 + iso_packet->offset = offset;
18786 + else /** ISO IN EP */
18788 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18790 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
18792 + sts.d32 = readl(&dma_desc->status);
18794 + /* Write status in iso packet descriptor */
18795 + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
18796 + if(iso_packet->status != 0) {
18797 + iso_packet->status = -ENODATA;
18800 + /* Bytes has been transfered */
18801 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
18807 + sts.d32 = readl(&dma_desc->status);
18808 + while(sts.b_iso_in.bs == BS_DMA_BUSY) {
18809 + sts.d32 = readl(&dma_desc->status);
18812 + /* Write status in iso packet descriptor ??? do be done with ERROR codes*/
18813 + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
18814 + if(iso_packet->status != 0) {
18815 + iso_packet->status = -ENODATA;
18818 + /* Bytes has been transfered */
18819 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
18824 + * This function reinitialize DMA Descriptors for Isochronous transfer
18826 + * @param core_if Programming view of DWC_otg controller.
18827 + * @param dwc_ep The EP to start the transfer on.
18830 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
18833 + dwc_otg_dma_desc_t* dma_desc;
18834 + dma_addr_t dma_ad;
18835 + volatile uint32_t *addr;
18836 + desc_sts_data_t sts = { .d32 =0 };
18837 + uint32_t data_per_desc;
18839 + if(dwc_ep->is_in == 0) {
18840 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
18843 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
18847 + if(dwc_ep->proc_buf_num == 0) {
18848 + /** Buffer 0 descriptors setup */
18849 + dma_ad = dwc_ep->dma_addr0;
18852 + /** Buffer 1 descriptors setup */
18853 + dma_ad = dwc_ep->dma_addr1;
18856 + /** Reinit closed DMA Descriptors*/
18857 + /** ISO OUT EP */
18858 + if(dwc_ep->is_in == 0) {
18859 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18861 + sts.b_iso_out.bs = BS_HOST_READY;
18862 + sts.b_iso_out.rxsts = 0;
18863 + sts.b_iso_out.l = 0;
18864 + sts.b_iso_out.sp = 0;
18865 + sts.b_iso_out.ioc = 0;
18866 + sts.b_iso_out.pid = 0;
18867 + sts.b_iso_out.framenum = 0;
18869 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
18871 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
18873 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18874 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18875 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18876 + sts.b_iso_out.rxbytes = data_per_desc;
18877 + writel((uint32_t)dma_ad, &dma_desc->buf);
18878 + writel(sts.d32, &dma_desc->status);
18880 + //(uint32_t)dma_ad += data_per_desc;
18881 + dma_ad = (uint32_t)dma_ad + data_per_desc;
18886 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
18889 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18890 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18891 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18892 + sts.b_iso_out.rxbytes = data_per_desc;
18894 + writel((uint32_t)dma_ad, &dma_desc->buf);
18895 + writel(sts.d32, &dma_desc->status);
18898 + //(uint32_t)dma_ad += data_per_desc;
18899 + dma_ad = (uint32_t)dma_ad + data_per_desc;
18902 + sts.b_iso_out.ioc = 1;
18903 + sts.b_iso_out.l = dwc_ep->proc_buf_num;
18905 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18906 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18907 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18908 + sts.b_iso_out.rxbytes = data_per_desc;
18910 + writel((uint32_t)dma_ad, &dma_desc->buf);
18911 + writel(sts.d32, &dma_desc->status);
18913 + else /** ISO IN EP */
18915 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18917 + sts.b_iso_in.bs = BS_HOST_READY;
18918 + sts.b_iso_in.txsts = 0;
18919 + sts.b_iso_in.sp = 0;
18920 + sts.b_iso_in.ioc = 0;
18921 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
18922 + sts.b_iso_in.framenum = dwc_ep->next_frame;
18923 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
18924 + sts.b_iso_in.l = 0;
18926 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
18928 + writel((uint32_t)dma_ad, &dma_desc->buf);
18929 + writel(sts.d32, &dma_desc->status);
18931 + sts.b_iso_in.framenum += dwc_ep->bInterval;
18932 + //(uint32_t)dma_ad += dwc_ep->data_per_frame;
18933 + dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
18937 + sts.b_iso_in.ioc = 1;
18938 + sts.b_iso_in.l = dwc_ep->proc_buf_num;
18940 + writel((uint32_t)dma_ad, &dma_desc->buf);
18941 + writel(sts.d32, &dma_desc->status);
18943 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
18945 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
18950 + * This function is to handle Iso EP transfer complete interrupt
18951 + * in case Iso out packet was dropped
18953 + * @param core_if Programming view of DWC_otg controller.
18954 + * @param dwc_ep The EP for wihich transfer complete was asserted
18957 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
18959 + uint32_t dma_addr;
18960 + uint32_t drp_pkt;
18961 + uint32_t drp_pkt_cnt;
18962 + deptsiz_data_t deptsiz = { .d32 = 0 };
18963 + depctl_data_t depctl = { .d32 = 0 };
18966 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
18968 + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
18969 + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
18971 + /* Setting dropped packets status */
18972 + for(i = 0; i < drp_pkt_cnt; ++i) {
18973 + dwc_ep->pkt_info[drp_pkt].status = -ENODATA;
18975 + deptsiz.b.pktcnt--;
18979 + if(deptsiz.b.pktcnt > 0) {
18980 + deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket;
18982 + deptsiz.b.xfersize = 0;
18983 + deptsiz.b.pktcnt = 0;
18986 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32);
18988 + if(deptsiz.b.pktcnt > 0) {
18989 + if(dwc_ep->proc_buf_num) {
18990 + dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize;
18992 + dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;;
18995 + VERIFY_PCD_DMA_ADDR(dma_addr);
18996 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
18998 + /** Re-enable endpoint, clear nak */
19000 + depctl.b.epena = 1;
19001 + depctl.b.cnak = 1;
19003 + dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
19004 + depctl.d32,depctl.d32);
19012 + * This function sets iso packets information(PTI mode)
19014 + * @param core_if Programming view of DWC_otg controller.
19015 + * @param ep The EP to start the transfer on.
19018 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
19021 + dma_addr_t dma_ad;
19022 + iso_pkt_info_t *packet_info = ep->pkt_info;
19024 + uint32_t frame_data;
19025 + deptsiz_data_t deptsiz;
19027 + if(ep->proc_buf_num == 0) {
19028 + /** Buffer 0 descriptors setup */
19029 + dma_ad = ep->dma_addr0;
19032 + /** Buffer 1 descriptors setup */
19033 + dma_ad = ep->dma_addr1;
19037 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
19039 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
19042 + if(!deptsiz.b.xfersize) {
19044 + for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm)
19046 + frame_data = ep->data_per_frame;
19047 + for(j = 0; j < ep->pkt_per_frm; ++j) {
19049 + /* Packet status - is not set as initially
19050 + * it is set to 0 and if packet was sent
19051 + successfully, status field will remain 0*/
19053 + /* Bytes has been transfered */
19054 + packet_info->length = (ep->maxpacket < frame_data) ?
19055 + ep->maxpacket : frame_data;
19057 + /* Received packet offset */
19058 + packet_info->offset = offset;
19059 + offset += packet_info->length;
19060 + frame_data -= packet_info->length;
19067 + /* This is a workaround for in case of Transfer Complete with
19068 + * PktDrpSts interrupts merging - in this case Transfer complete
19069 + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
19070 + * set and with DOEPTSIZ register non zero. Investigations showed,
19071 + * that this happens when Out packet is dropped, but because of
19072 + * interrupts merging during first interrupt handling PktDrpSts
19073 + * bit is cleared and for next merged interrupts it is not reset.
19074 + * In this case SW hadles the interrupt as if PktDrpSts bit is set.
19079 + return handle_iso_out_pkt_dropped(core_if, ep);
19085 + * This function is to handle Iso EP transfer complete interrupt
19087 + * @param ep The EP for which transfer complete was asserted
19090 +static void complete_iso_ep(dwc_otg_pcd_ep_t *ep)
19092 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
19093 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
19094 + uint8_t is_last = 0;
19096 + if(core_if->dma_enable) {
19097 + if(core_if->dma_desc_enable) {
19098 + set_ddma_iso_pkts_info(core_if, dwc_ep);
19099 + reinit_ddma_iso_xfer(core_if, dwc_ep);
19102 + if(core_if->pti_enh_enable) {
19103 + if(set_iso_pkts_info(core_if, dwc_ep)) {
19104 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19105 + dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep);
19109 + set_current_pkt_info(core_if, dwc_ep);
19110 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
19112 + dwc_ep->cur_pkt = 0;
19113 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19114 + if(dwc_ep->proc_buf_num) {
19115 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
19116 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
19118 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
19119 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
19122 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
19126 + set_current_pkt_info(core_if, dwc_ep);
19127 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
19129 + dwc_ep->cur_pkt = 0;
19130 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19131 + if(dwc_ep->proc_buf_num) {
19132 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
19133 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
19135 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
19136 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
19139 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
19142 + dwc_otg_iso_buffer_done(ep, ep->iso_req);
19145 +#endif //DWC_EN_ISOC
19149 + * This function handles EP0 Control transfers.
19151 + * The state of the control tranfers are tracked in
19152 + * <code>ep0state</code>.
19154 +static void handle_ep0(dwc_otg_pcd_t *pcd)
19156 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19157 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19158 + desc_sts_data_t desc_sts;
19159 + deptsiz0_data_t deptsiz;
19160 + uint32_t byte_count;
19163 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
19164 + print_ep0_state(pcd);
19167 + switch (pcd->ep0state) {
19168 + case EP0_DISCONNECT:
19172 + pcd->request_config = 0;
19177 + case EP0_IN_DATA_PHASE:
19179 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
19180 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
19181 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
19184 + if (core_if->dma_enable != 0) {
19186 + * For EP0 we can only program 1 packet at a time so we
19187 + * need to do the make calculations after each complete.
19188 + * Call write_packet to make the calculations, as in
19189 + * slave mode, and use those values to determine if we
19192 + if(core_if->dma_desc_enable == 0) {
19193 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz);
19194 + byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
19197 + desc_sts.d32 = readl(core_if->dev_if->in_desc_addr);
19198 + byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
19201 + ep0->dwc_ep.xfer_count += byte_count;
19202 + ep0->dwc_ep.xfer_buff += byte_count;
19203 + ep0->dwc_ep.dma_addr += byte_count;
19205 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
19206 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19207 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19209 + else if(ep0->dwc_ep.sent_zlp) {
19210 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19211 + ep0->dwc_ep.sent_zlp = 0;
19212 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19215 + ep0_complete_request(ep0);
19216 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
19219 + case EP0_OUT_DATA_PHASE:
19221 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
19222 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
19223 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
19225 + if (core_if->dma_enable != 0) {
19226 + if(core_if->dma_desc_enable == 0) {
19227 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz);
19228 + byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
19230 + //todo: invalidate cache & aligned buf patch on completion
19231 + dma_sync_single_for_device(NULL,ep0->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
19232 + aligned_buf_patch_on_buf_dma_oep_completion(ep0,byte_count);
19235 + desc_sts.d32 = readl(core_if->dev_if->out_desc_addr);
19236 + byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
19238 + //todo: invalidate cache & aligned buf patch on completion
19242 + ep0->dwc_ep.xfer_count += byte_count;
19243 + ep0->dwc_ep.xfer_buff += byte_count;
19244 + ep0->dwc_ep.dma_addr += byte_count;
19246 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
19247 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19248 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19250 + else if(ep0->dwc_ep.sent_zlp) {
19251 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19252 + ep0->dwc_ep.sent_zlp = 0;
19253 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19256 + ep0_complete_request(ep0);
19257 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
19261 + case EP0_IN_STATUS_PHASE:
19262 + case EP0_OUT_STATUS_PHASE:
19263 + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
19264 + ep0_complete_request(ep0);
19265 + pcd->ep0state = EP0_IDLE;
19266 + ep0->stopped = 1;
19267 + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
19269 + /* Prepare for more SETUP Packets */
19270 + if(core_if->dma_enable) {
19271 + ep0_out_start(core_if, pcd);
19276 + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
19280 + print_ep0_state(pcd);
19286 + * Restart transfer
19288 +static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
19290 + dwc_otg_core_if_t *core_if;
19291 + dwc_otg_dev_if_t *dev_if;
19292 + deptsiz_data_t dieptsiz = {.d32=0};
19293 + dwc_otg_pcd_ep_t *ep;
19295 + ep = get_in_ep(pcd, epnum);
19297 +#ifdef DWC_EN_ISOC
19298 + if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
19301 +#endif /* DWC_EN_ISOC */
19303 + core_if = GET_CORE_IF(pcd);
19304 + dev_if = core_if->dev_if;
19306 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
19308 + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x"
19309 + " stopped=%d\n", ep->dwc_ep.xfer_buff,
19310 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
19313 + * If xfersize is 0 and pktcnt in not 0, resend the last packet.
19315 + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
19316 + ep->dwc_ep.start_xfer_buff != 0) {
19317 + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
19318 + ep->dwc_ep.xfer_count = 0;
19319 + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
19320 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
19323 + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
19324 + /* convert packet size to dwords. */
19325 + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
19326 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
19329 + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x "
19330 + "xfer_len=%0x stopped=%d\n",
19331 + ep->dwc_ep.xfer_buff,
19332 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
19335 + if (epnum == 0) {
19336 + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
19339 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
19346 + * handle the IN EP disable interrupt.
19348 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
19349 + const uint32_t epnum)
19351 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19352 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19353 + deptsiz_data_t dieptsiz = {.d32=0};
19354 + dctl_data_t dctl = {.d32=0};
19355 + dwc_otg_pcd_ep_t *ep;
19356 + dwc_ep_t *dwc_ep;
19358 + ep = get_in_ep(pcd, epnum);
19359 + dwc_ep = &ep->dwc_ep;
19361 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19362 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
19366 + DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum,
19367 + dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
19368 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
19370 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
19371 + dieptsiz.b.pktcnt,
19372 + dieptsiz.b.xfersize);
19374 + if (ep->stopped) {
19375 + /* Flush the Tx FIFO */
19376 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
19377 + /* Clear the Global IN NP NAK */
19379 + dctl.b.cgnpinnak = 1;
19380 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
19382 + /* Restart the transaction */
19383 + if (dieptsiz.b.pktcnt != 0 ||
19384 + dieptsiz.b.xfersize != 0) {
19385 + restart_transfer(pcd, epnum);
19389 + /* Restart the transaction */
19390 + if (dieptsiz.b.pktcnt != 0 ||
19391 + dieptsiz.b.xfersize != 0) {
19392 + restart_transfer(pcd, epnum);
19394 + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
19399 + * Handler for the IN EP timeout handshake interrupt.
19401 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
19402 + const uint32_t epnum)
19404 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19405 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19408 + deptsiz_data_t dieptsiz = {.d32=0};
19409 + uint32_t num = 0;
19411 + dctl_data_t dctl = {.d32=0};
19412 + dwc_otg_pcd_ep_t *ep;
19414 + gintmsk_data_t intr_mask = {.d32 = 0};
19416 + ep = get_in_ep(pcd, epnum);
19418 + /* Disable the NP Tx Fifo Empty Interrrupt */
19419 + if (!core_if->dma_enable) {
19420 + intr_mask.b.nptxfempty = 1;
19421 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
19423 + /** @todo NGS Check EP type.
19424 + * Implement for Periodic EPs */
19426 + * Non-periodic EP
19428 + /* Enable the Global IN NAK Effective Interrupt */
19429 + intr_mask.b.ginnakeff = 1;
19430 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
19431 + 0, intr_mask.d32);
19433 + /* Set Global IN NAK */
19434 + dctl.b.sgnpinnak = 1;
19435 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
19436 + dctl.d32, dctl.d32);
19441 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
19442 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
19443 + dieptsiz.b.pktcnt,
19444 + dieptsiz.b.xfersize);
19447 +#ifdef DISABLE_PERIODIC_EP
19449 + * Set the NAK bit for this EP to
19450 + * start the disable process.
19453 + diepctl.b.snak = 1;
19454 + dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32);
19455 + ep->disabling = 1;
19461 + * Handler for the IN EP NAK interrupt.
19463 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
19464 + const uint32_t epnum)
19466 + /** @todo implement ISR */
19467 + dwc_otg_core_if_t* core_if;
19468 + diepmsk_data_t intr_mask = { .d32 = 0};
19470 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
19471 + core_if = GET_CORE_IF(pcd);
19472 + intr_mask.b.nak = 1;
19474 + if(core_if->multiproc_int_enable) {
19475 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum],
19476 + intr_mask.d32, 0);
19478 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
19479 + intr_mask.d32, 0);
19486 + * Handler for the OUT EP Babble interrupt.
19488 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
19489 + const uint32_t epnum)
19491 + /** @todo implement ISR */
19492 + dwc_otg_core_if_t* core_if;
19493 + doepmsk_data_t intr_mask = { .d32 = 0};
19495 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble");
19496 + core_if = GET_CORE_IF(pcd);
19497 + intr_mask.b.babble = 1;
19499 + if(core_if->multiproc_int_enable) {
19500 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19501 + intr_mask.d32, 0);
19503 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19504 + intr_mask.d32, 0);
19511 + * Handler for the OUT EP NAK interrupt.
19513 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
19514 + const uint32_t epnum)
19516 + /** @todo implement ISR */
19517 + dwc_otg_core_if_t* core_if;
19518 + doepmsk_data_t intr_mask = { .d32 = 0};
19520 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
19521 + core_if = GET_CORE_IF(pcd);
19522 + intr_mask.b.nak = 1;
19524 + if(core_if->multiproc_int_enable) {
19525 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19526 + intr_mask.d32, 0);
19528 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19529 + intr_mask.d32, 0);
19536 + * Handler for the OUT EP NYET interrupt.
19538 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
19539 + const uint32_t epnum)
19541 + /** @todo implement ISR */
19542 + dwc_otg_core_if_t* core_if;
19543 + doepmsk_data_t intr_mask = { .d32 = 0};
19545 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
19546 + core_if = GET_CORE_IF(pcd);
19547 + intr_mask.b.nyet = 1;
19549 + if(core_if->multiproc_int_enable) {
19550 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19551 + intr_mask.d32, 0);
19553 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19554 + intr_mask.d32, 0);
19561 + * This interrupt indicates that an IN EP has a pending Interrupt.
19562 + * The sequence for handling the IN EP interrupt is shown below:
19563 + * -# Read the Device All Endpoint Interrupt register
19564 + * -# Repeat the following for each IN EP interrupt bit set (from
19566 + * -# Read the Device Endpoint Interrupt (DIEPINTn) register
19567 + * -# If "Transfer Complete" call the request complete function
19568 + * -# If "Endpoint Disabled" complete the EP disable procedure.
19569 + * -# If "AHB Error Interrupt" log error
19570 + * -# If "Time-out Handshake" log error
19571 + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
19573 + * -# If "IN Token EP Mismatch" (disable, this is handled by EP
19574 + * Mismatch Interrupt)
19576 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
19578 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
19580 + diepint_data_t diepint = {.d32=0}; \
19581 + diepint.b.__intr = 1; \
19582 + dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
19586 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19587 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19588 + diepint_data_t diepint = {.d32=0};
19589 + dctl_data_t dctl = {.d32=0};
19590 + depctl_data_t depctl = {.d32=0};
19591 + uint32_t ep_intr;
19592 + uint32_t epnum = 0;
19593 + dwc_otg_pcd_ep_t *ep;
19594 + dwc_ep_t *dwc_ep;
19595 + gintmsk_data_t intr_mask = {.d32 = 0};
19597 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
19599 + /* Read in the device interrupt bits */
19600 + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
19602 + /* Service the Device IN interrupts for each endpoint */
19604 + if (ep_intr&0x1) {
19605 + uint32_t empty_msk;
19606 + /* Get EP pointer */
19607 + ep = get_in_ep(pcd, epnum);
19608 + dwc_ep = &ep->dwc_ep;
19610 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
19611 + empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
19613 + DWC_DEBUGPL(DBG_PCDV,
19614 + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
19619 + DWC_DEBUGPL(DBG_PCD,
19620 + "EP%d-%s: type=%d, mps=%d\n",
19621 + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
19622 + dwc_ep->type, dwc_ep->maxpacket);
19624 + diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
19626 + DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32);
19627 + /* Transfer complete */
19628 + if (diepint.b.xfercompl) {
19629 + /* Disable the NP Tx FIFO Empty
19631 + if(core_if->en_multiple_tx_fifo == 0) {
19632 + intr_mask.b.nptxfempty = 1;
19633 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
19636 + /* Disable the Tx FIFO Empty Interrupt for this EP */
19637 + uint32_t fifoemptymsk = 0x1 << dwc_ep->num;
19638 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
19639 + fifoemptymsk, 0);
19641 + /* Clear the bit in DIEPINTn for this interrupt */
19642 + CLEAR_IN_EP_INTR(core_if,epnum,xfercompl);
19644 + /* Complete the transfer */
19645 + if (epnum == 0) {
19648 +#ifdef DWC_EN_ISOC
19649 + else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19651 + complete_iso_ep(ep);
19653 +#endif //DWC_EN_ISOC
19659 + /* Endpoint disable */
19660 + if (diepint.b.epdisabled) {
19661 + DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum);
19662 + handle_in_ep_disable_intr(pcd, epnum);
19664 + /* Clear the bit in DIEPINTn for this interrupt */
19665 + CLEAR_IN_EP_INTR(core_if,epnum,epdisabled);
19668 + if (diepint.b.ahberr) {
19669 + DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum);
19670 + /* Clear the bit in DIEPINTn for this interrupt */
19671 + CLEAR_IN_EP_INTR(core_if,epnum,ahberr);
19673 + /* TimeOUT Handshake (non-ISOC IN EPs) */
19674 + if (diepint.b.timeout) {
19675 + DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum);
19676 + handle_in_ep_timeout_intr(pcd, epnum);
19678 + CLEAR_IN_EP_INTR(core_if,epnum,timeout);
19680 + /** IN Token received with TxF Empty */
19681 + if (diepint.b.intktxfemp) {
19682 + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n",
19684 + if (!ep->stopped && epnum != 0) {
19686 + diepmsk_data_t diepmsk = { .d32 = 0};
19687 + diepmsk.b.intktxfemp = 1;
19689 + if(core_if->multiproc_int_enable) {
19690 + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum],
19693 + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0);
19695 + start_next_request(ep);
19697 + else if(core_if->dma_desc_enable && epnum == 0 &&
19698 + pcd->ep0state == EP0_OUT_STATUS_PHASE) {
19699 + // EP0 IN set STALL
19700 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
19702 + /* set the disable and stall bits */
19703 + if (depctl.b.epena) {
19704 + depctl.b.epdis = 1;
19706 + depctl.b.stall = 1;
19707 + dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
19709 + CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp);
19711 + /** IN Token Received with EP mismatch */
19712 + if (diepint.b.intknepmis) {
19713 + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum);
19714 + CLEAR_IN_EP_INTR(core_if,epnum,intknepmis);
19716 + /** IN Endpoint NAK Effective */
19717 + if (diepint.b.inepnakeff) {
19718 + DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum);
19719 + /* Periodic EP */
19720 + if (ep->disabling) {
19722 + depctl.b.snak = 1;
19723 + depctl.b.epdis = 1;
19724 + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
19726 + CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff);
19730 + /** IN EP Tx FIFO Empty Intr */
19731 + if (diepint.b.emptyintr) {
19732 + DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum);
19733 + write_empty_tx_fifo(pcd, epnum);
19735 + CLEAR_IN_EP_INTR(core_if,epnum,emptyintr);
19738 + /** IN EP BNA Intr */
19739 + if (diepint.b.bna) {
19740 + CLEAR_IN_EP_INTR(core_if,epnum,bna);
19741 + if(core_if->dma_desc_enable) {
19742 +#ifdef DWC_EN_ISOC
19743 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19745 + * This checking is performed to prevent first "false" BNA
19746 + * handling occuring right after reconnect
19748 + if(dwc_ep->next_frame != 0xffffffff)
19749 + dwc_otg_pcd_handle_iso_bna(ep);
19752 +#endif //DWC_EN_ISOC
19754 + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
19756 + /* If Global Continue on BNA is disabled - disable EP */
19757 + if(!dctl.b.gcontbna) {
19759 + depctl.b.snak = 1;
19760 + depctl.b.epdis = 1;
19761 + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
19763 + start_next_request(ep);
19768 + /* NAK Interrutp */
19769 + if (diepint.b.nak) {
19770 + DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum);
19771 + handle_in_ep_nak_intr(pcd, epnum);
19773 + CLEAR_IN_EP_INTR(core_if,epnum,nak);
19781 +#undef CLEAR_IN_EP_INTR
19785 + * This interrupt indicates that an OUT EP has a pending Interrupt.
19786 + * The sequence for handling the OUT EP interrupt is shown below:
19787 + * -# Read the Device All Endpoint Interrupt register
19788 + * -# Repeat the following for each OUT EP interrupt bit set (from
19790 + * -# Read the Device Endpoint Interrupt (DOEPINTn) register
19791 + * -# If "Transfer Complete" call the request complete function
19792 + * -# If "Endpoint Disabled" complete the EP disable procedure.
19793 + * -# If "AHB Error Interrupt" log error
19794 + * -# If "Setup Phase Done" process Setup Packet (See Standard USB
19795 + * Command Processing)
19797 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
19799 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
19801 + doepint_data_t doepint = {.d32=0}; \
19802 + doepint.b.__intr = 1; \
19803 + dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
19807 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19808 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19809 + uint32_t ep_intr;
19810 + doepint_data_t doepint = {.d32=0};
19811 + dctl_data_t dctl = {.d32=0};
19812 + depctl_data_t doepctl = {.d32=0};
19813 + uint32_t epnum = 0;
19814 + dwc_otg_pcd_ep_t *ep;
19815 + dwc_ep_t *dwc_ep;
19817 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
19819 + /* Read in the device interrupt bits */
19820 + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
19823 + if (ep_intr&0x1) {
19824 + /* Get EP pointer */
19825 + ep = get_out_ep(pcd, epnum);
19826 + dwc_ep = &ep->dwc_ep;
19829 + DWC_DEBUGPL(DBG_PCDV,
19830 + "EP%d-%s: type=%d, mps=%d\n",
19831 + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
19832 + dwc_ep->type, dwc_ep->maxpacket);
19834 + doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
19836 + /* Transfer complete */
19837 + if (doepint.b.xfercompl) {
19838 + if (epnum == 0) {
19839 + /* Clear the bit in DOEPINTn for this interrupt */
19840 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19841 + if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE)
19843 +#ifdef DWC_EN_ISOC
19844 + } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19845 + if (doepint.b.pktdrpsts == 0) {
19846 + /* Clear the bit in DOEPINTn for this interrupt */
19847 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19848 + complete_iso_ep(ep);
19850 + doepint_data_t doepint = {.d32=0};
19851 + doepint.b.xfercompl = 1;
19852 + doepint.b.pktdrpsts = 1;
19853 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint,
19855 + if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) {
19856 + complete_iso_ep(ep);
19859 +#endif //DWC_EN_ISOC
19861 + /* Clear the bit in DOEPINTn for this interrupt */
19862 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19868 + /* Endpoint disable */
19869 + if (doepint.b.epdisabled) {
19870 + /* Clear the bit in DOEPINTn for this interrupt */
19871 + CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled);
19874 + if (doepint.b.ahberr) {
19875 + DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum);
19876 + DWC_DEBUGPL(DBG_PCD,"EP DMA REG %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma);
19877 + CLEAR_OUT_EP_INTR(core_if,epnum,ahberr);
19879 + /* Setup Phase Done (contorl EPs) */
19880 + if (doepint.b.setup) {
19882 + DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n",
19885 + CLEAR_OUT_EP_INTR(core_if,epnum,setup);
19889 + /** OUT EP BNA Intr */
19890 + if (doepint.b.bna) {
19891 + CLEAR_OUT_EP_INTR(core_if,epnum,bna);
19892 + if(core_if->dma_desc_enable) {
19893 +#ifdef DWC_EN_ISOC
19894 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19896 + * This checking is performed to prevent first "false" BNA
19897 + * handling occuring right after reconnect
19899 + if(dwc_ep->next_frame != 0xffffffff)
19900 + dwc_otg_pcd_handle_iso_bna(ep);
19903 +#endif //DWC_EN_ISOC
19905 + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
19907 + /* If Global Continue on BNA is disabled - disable EP*/
19908 + if(!dctl.b.gcontbna) {
19910 + doepctl.b.snak = 1;
19911 + doepctl.b.epdis = 1;
19912 + dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32);
19914 + start_next_request(ep);
19919 + if (doepint.b.stsphsercvd) {
19920 + CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd);
19921 + if(core_if->dma_desc_enable) {
19922 + do_setup_in_status_phase(pcd);
19925 + /* Babble Interrutp */
19926 + if (doepint.b.babble) {
19927 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum);
19928 + handle_out_ep_babble_intr(pcd, epnum);
19930 + CLEAR_OUT_EP_INTR(core_if,epnum,babble);
19932 + /* NAK Interrutp */
19933 + if (doepint.b.nak) {
19934 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum);
19935 + handle_out_ep_nak_intr(pcd, epnum);
19937 + CLEAR_OUT_EP_INTR(core_if,epnum,nak);
19939 + /* NYET Interrutp */
19940 + if (doepint.b.nyet) {
19941 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum);
19942 + handle_out_ep_nyet_intr(pcd, epnum);
19944 + CLEAR_OUT_EP_INTR(core_if,epnum,nyet);
19954 +#undef CLEAR_OUT_EP_INTR
19959 + * Incomplete ISO IN Transfer Interrupt.
19960 + * This interrupt indicates one of the following conditions occurred
19961 + * while transmitting an ISOC transaction.
19962 + * - Corrupted IN Token for ISOC EP.
19963 + * - Packet not complete in FIFO.
19964 + * The follow actions will be taken:
19965 + * -# Determine the EP
19966 + * -# Set incomplete flag in dwc_ep structure
19967 + * -# Disable EP; when "Endpoint Disabled" interrupt is received
19970 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
19972 + gintsts_data_t gintsts;
19975 +#ifdef DWC_EN_ISOC
19976 + dwc_otg_dev_if_t *dev_if;
19977 + deptsiz_data_t deptsiz = { .d32 = 0};
19978 + depctl_data_t depctl = { .d32 = 0};
19979 + dsts_data_t dsts = { .d32 = 0};
19980 + dwc_ep_t *dwc_ep;
19983 + dev_if = GET_CORE_IF(pcd)->dev_if;
19985 + for(i = 1; i <= dev_if->num_in_eps; ++i) {
19986 + dwc_ep = &pcd->in_ep[i].dwc_ep;
19987 + if(dwc_ep->active &&
19988 + dwc_ep->type == USB_ENDPOINT_XFER_ISOC)
19990 + deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
19991 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
19993 + if(depctl.b.epdis && deptsiz.d32) {
19994 + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
19995 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
19996 + dwc_ep->cur_pkt = 0;
19997 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19999 + if(dwc_ep->proc_buf_num) {
20000 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
20001 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
20003 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
20004 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
20008 + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
20009 + dwc_ep->next_frame = dsts.b.soffn;
20011 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
20017 + gintmsk_data_t intr_mask = { .d32 = 0};
20018 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20019 + "IN ISOC Incomplete");
20021 + intr_mask.b.incomplisoin = 1;
20022 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20023 + intr_mask.d32, 0);
20024 +#endif //DWC_EN_ISOC
20026 + /* Clear interrupt */
20028 + gintsts.b.incomplisoin = 1;
20029 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20036 + * Incomplete ISO OUT Transfer Interrupt.
20038 + * This interrupt indicates that the core has dropped an ISO OUT
20039 + * packet. The following conditions can be the cause:
20040 + * - FIFO Full, the entire packet would not fit in the FIFO.
20042 + * - Corrupted Token
20043 + * The follow actions will be taken:
20044 + * -# Determine the EP
20045 + * -# Set incomplete flag in dwc_ep structure
20046 + * -# Read any data from the FIFO
20047 + * -# Disable EP. when "Endpoint Disabled" interrupt is received
20050 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
20052 + /* @todo implement ISR */
20053 + gintsts_data_t gintsts;
20055 +#ifdef DWC_EN_ISOC
20056 + dwc_otg_dev_if_t *dev_if;
20057 + deptsiz_data_t deptsiz = { .d32 = 0};
20058 + depctl_data_t depctl = { .d32 = 0};
20059 + dsts_data_t dsts = { .d32 = 0};
20060 + dwc_ep_t *dwc_ep;
20063 + dev_if = GET_CORE_IF(pcd)->dev_if;
20065 + for(i = 1; i <= dev_if->num_out_eps; ++i) {
20066 + dwc_ep = &pcd->in_ep[i].dwc_ep;
20067 + if(pcd->out_ep[i].dwc_ep.active &&
20068 + pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC)
20070 + deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
20071 + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
20073 + if(depctl.b.epdis && deptsiz.d32) {
20074 + set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep);
20075 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
20076 + dwc_ep->cur_pkt = 0;
20077 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20079 + if(dwc_ep->proc_buf_num) {
20080 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
20081 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
20083 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
20084 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
20088 + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
20089 + dwc_ep->next_frame = dsts.b.soffn;
20091 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
20096 + /** @todo implement ISR */
20097 + gintmsk_data_t intr_mask = { .d32 = 0};
20099 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20100 + "OUT ISOC Incomplete");
20102 + intr_mask.b.incomplisoout = 1;
20103 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20104 + intr_mask.d32, 0);
20106 +#endif // DWC_EN_ISOC
20108 + /* Clear interrupt */
20110 + gintsts.b.incomplisoout = 1;
20111 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20118 + * This function handles the Global IN NAK Effective interrupt.
20121 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
20123 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
20124 + depctl_data_t diepctl = { .d32 = 0};
20125 + depctl_data_t diepctl_rd = { .d32 = 0};
20126 + gintmsk_data_t intr_mask = { .d32 = 0};
20127 + gintsts_data_t gintsts;
20130 + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
20132 + /* Disable all active IN EPs */
20133 + diepctl.b.epdis = 1;
20134 + diepctl.b.snak = 1;
20136 + for (i=0; i <= dev_if->num_in_eps; i++)
20138 + diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
20139 + if (diepctl_rd.b.epena) {
20140 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
20144 + /* Disable the Global IN NAK Effective Interrupt */
20145 + intr_mask.b.ginnakeff = 1;
20146 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20147 + intr_mask.d32, 0);
20149 + /* Clear interrupt */
20151 + gintsts.b.ginnakeff = 1;
20152 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20159 + * OUT NAK Effective.
20162 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
20164 + gintmsk_data_t intr_mask = { .d32 = 0};
20165 + gintsts_data_t gintsts;
20167 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20168 + "Global IN NAK Effective\n");
20169 + /* Disable the Global IN NAK Effective Interrupt */
20170 + intr_mask.b.goutnakeff = 1;
20171 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20172 + intr_mask.d32, 0);
20174 + /* Clear interrupt */
20176 + gintsts.b.goutnakeff = 1;
20177 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20185 + * PCD interrupt handler.
20187 + * The PCD handles the device interrupts. Many conditions can cause a
20188 + * device interrupt. When an interrupt occurs, the device interrupt
20189 + * service routine determines the cause of the interrupt and
20190 + * dispatches handling to the appropriate function. These interrupt
20191 + * handling functions are described below.
20193 + * All interrupt registers are processed from LSB to MSB.
20196 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
20198 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20200 + dwc_otg_core_global_regs_t *global_regs =
20201 + core_if->core_global_regs;
20203 + gintsts_data_t gintr_status;
20204 + int32_t retval = 0;
20208 + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
20210 + dwc_read_reg32(&global_regs->gintsts),
20211 + dwc_read_reg32(&global_regs->gintmsk));
20214 + if (dwc_otg_is_device_mode(core_if)) {
20215 + SPIN_LOCK(&pcd->lock);
20217 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
20219 + dwc_read_reg32(&global_regs->gintsts),
20220 + dwc_read_reg32(&global_regs->gintmsk));
20223 + gintr_status.d32 = dwc_otg_read_core_intr(core_if);
20225 + if (!gintr_status.d32) {
20226 + SPIN_UNLOCK(&pcd->lock);
20230 + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
20231 + __func__, gintr_status.d32);
20233 + if (gintr_status.b.sofintr) {
20234 + retval |= dwc_otg_pcd_handle_sof_intr(pcd);
20236 + if (gintr_status.b.rxstsqlvl) {
20237 + retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
20239 + if (gintr_status.b.nptxfempty) {
20240 + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
20242 + if (gintr_status.b.ginnakeff) {
20243 + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
20245 + if (gintr_status.b.goutnakeff) {
20246 + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
20248 + if (gintr_status.b.i2cintr) {
20249 + retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
20251 + if (gintr_status.b.erlysuspend) {
20252 + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
20254 + if (gintr_status.b.usbreset) {
20255 + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
20257 + if (gintr_status.b.enumdone) {
20258 + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
20260 + if (gintr_status.b.isooutdrop) {
20261 + retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd);
20263 + if (gintr_status.b.eopframe) {
20264 + retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
20266 + if (gintr_status.b.epmismatch) {
20267 + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
20269 + if (gintr_status.b.inepint) {
20270 + if(!core_if->multiproc_int_enable) {
20271 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
20274 + if (gintr_status.b.outepintr) {
20275 + if(!core_if->multiproc_int_enable) {
20276 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
20279 + if (gintr_status.b.incomplisoin) {
20280 + retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
20282 + if (gintr_status.b.incomplisoout) {
20283 + retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
20286 + /* In MPI mode De vice Endpoints intterrupts are asserted
20287 + * without setting outepintr and inepint bits set, so these
20288 + * Interrupt handlers are called without checking these bit-fields
20290 + if(core_if->multiproc_int_enable) {
20291 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
20292 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
20295 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
20296 + dwc_read_reg32(&global_regs->gintsts));
20298 + SPIN_UNLOCK(&pcd->lock);
20300 + S3C2410X_CLEAR_EINTPEND();
20305 +#endif /* DWC_HOST_ONLY */
20307 +++ b/drivers/usb/dwc/otg_plat.h
20309 +/* ==========================================================================
20310 + * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $
20311 + * $Revision: #23 $
20312 + * $Date: 2008/07/15 $
20313 + * $Change: 1064915 $
20315 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
20316 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
20317 + * otherwise expressly agreed to in writing between Synopsys and you.
20319 + * The Software IS NOT an item of Licensed Software or Licensed Product under
20320 + * any End User Software License Agreement or Agreement for Licensed Product
20321 + * with Synopsys or any supplement thereto. You are permitted to use and
20322 + * redistribute this Software in source and binary forms, with or without
20323 + * modification, provided that redistributions of source code must retain this
20324 + * notice. You may not view, use, disclose, copy or distribute this file or
20325 + * any information contained herein except pursuant to this license grant from
20326 + * Synopsys. If you do not agree with this notice, including the disclaimer
20327 + * below, then you are not authorized to use the Software.
20329 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
20330 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20331 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20332 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
20333 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20334 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20335 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20336 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20337 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
20338 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
20340 + * ========================================================================== */
20342 +#if !defined(__DWC_OTG_PLAT_H__)
20343 +#define __DWC_OTG_PLAT_H__
20345 +#include <linux/types.h>
20346 +#include <linux/slab.h>
20347 +#include <linux/list.h>
20348 +#include <linux/delay.h>
20349 +#include <asm/io.h>
20351 +/* Changed all readl and writel to __raw_readl, __raw_writel */
20356 + * This file contains the Platform Specific constants, interfaces
20357 + * (functions and macros) for Linux.
20360 +//#if !defined(__LINUX_ARM_ARCH__)
20361 +//#error "The contents of this file is Linux specific!!!"
20365 + * Reads the content of a register.
20367 + * @param reg address of register to read.
20368 + * @return contents of the register.
20372 + * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
20374 +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg)
20376 + return __raw_readl(reg);
20377 + // return readl(reg);
20381 + * Writes a register with a 32 bit value.
20383 + * @param reg address of register to read.
20384 + * @param value to write to _reg.
20387 + * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
20389 +static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value)
20391 + // writel( value, reg );
20392 + __raw_writel(value, reg);
20397 + * This function modifies bit values in a register. Using the
20398 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
20400 + * @param reg address of register to read.
20401 + * @param clear_mask bit mask to be cleared.
20402 + * @param set_mask bit mask to be set.
20405 + * <code> // Clear the SOF Interrupt Mask bit and <br>
20406 + * // set the OTG Interrupt mask bit, leaving all others as they were.
20407 + * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
20410 + void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask)
20412 + // writel( (readl(reg) & ~clear_mask) | set_mask, reg );
20413 + __raw_writel( (__raw_readl(reg) & ~clear_mask) | set_mask, reg );
20418 + * Wrapper for the OS micro-second delay function.
20419 + * @param[in] usecs Microseconds of delay
20421 +static __inline__ void UDELAY( const uint32_t usecs )
20427 + * Wrapper for the OS milli-second delay function.
20428 + * @param[in] msecs milliseconds of delay
20430 +static __inline__ void MDELAY( const uint32_t msecs )
20436 + * Wrapper for the Linux spin_lock. On the ARM (Integrator)
20437 + * spin_lock() is a nop.
20439 + * @param lock Pointer to the spinlock.
20441 +static __inline__ void SPIN_LOCK( spinlock_t *lock )
20447 + * Wrapper for the Linux spin_unlock. On the ARM (Integrator)
20448 + * spin_lock() is a nop.
20450 + * @param lock Pointer to the spinlock.
20452 +static __inline__ void SPIN_UNLOCK( spinlock_t *lock )
20454 + spin_unlock(lock);
20458 + * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
20459 + * (Integrator) spin_lock() is a nop.
20461 + * @param l Pointer to the spinlock.
20462 + * @param f unsigned long for irq flags storage.
20464 +#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f);
20467 + * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
20468 + * (Integrator) spin_lock() is a nop.
20470 + * @param l Pointer to the spinlock.
20471 + * @param f unsigned long for irq flags storage.
20473 +#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f);
20476 + * Debugging support vanishes in non-debug builds.
20481 + * The Debug Level bit-mask variable.
20483 +extern uint32_t g_dbg_lvl;
20485 + * Set the Debug Level variable.
20487 +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new )
20489 + uint32_t old = g_dbg_lvl;
20494 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
20495 +#define DBG_CIL (0x2)
20496 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
20498 +#define DBG_CILV (0x20)
20499 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
20501 +#define DBG_PCD (0x4)
20502 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
20504 +#define DBG_PCDV (0x40)
20505 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
20506 +#define DBG_HCD (0x8)
20507 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
20509 +#define DBG_HCDV (0x80)
20510 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
20512 +#define DBG_HCD_URB (0x800)
20514 +/** When debug level has any bit set, display debug messages */
20515 +#define DBG_ANY (0xFF)
20517 +/** All debug messages off */
20520 +/** Prefix string for DWC_DEBUG print macros. */
20521 +#define USB_DWC "DWC_otg: "
20524 + * Print a debug message when the Global debug level variable contains
20525 + * the bit defined in <code>lvl</code>.
20527 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
20528 + * @param[in] x - like printf
20532 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
20535 + * results in:<br>
20537 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
20542 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
20543 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
20545 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
20549 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
20550 +# define DWC_DEBUGP(x...)
20552 +# define CHK_DEBUG_LEVEL(level) (0)
20557 + * Print an Error message.
20559 +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
20561 + * Print a Warning message.
20563 +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
20565 + * Print a notice (normal but significant message).
20567 +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
20569 + * Basic message printing.
20571 +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
20576 +++ b/drivers/usb/dwc/otg_regs.h
20578 +/* ==========================================================================
20579 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
20580 + * $Revision: #72 $
20581 + * $Date: 2008/09/19 $
20582 + * $Change: 1099526 $
20584 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
20585 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
20586 + * otherwise expressly agreed to in writing between Synopsys and you.
20588 + * The Software IS NOT an item of Licensed Software or Licensed Product under
20589 + * any End User Software License Agreement or Agreement for Licensed Product
20590 + * with Synopsys or any supplement thereto. You are permitted to use and
20591 + * redistribute this Software in source and binary forms, with or without
20592 + * modification, provided that redistributions of source code must retain this
20593 + * notice. You may not view, use, disclose, copy or distribute this file or
20594 + * any information contained herein except pursuant to this license grant from
20595 + * Synopsys. If you do not agree with this notice, including the disclaimer
20596 + * below, then you are not authorized to use the Software.
20598 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
20599 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20600 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20601 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
20602 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20603 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20604 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20605 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20606 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
20607 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
20609 + * ========================================================================== */
20611 +#ifndef __DWC_OTG_REGS_H__
20612 +#define __DWC_OTG_REGS_H__
20617 + * This file contains the data structures for accessing the DWC_otg core registers.
20619 + * The application interfaces with the HS OTG core by reading from and
20620 + * writing to the Control and Status Register (CSR) space through the
20621 + * AHB Slave interface. These registers are 32 bits wide, and the
20622 + * addresses are 32-bit-block aligned.
20623 + * CSRs are classified as follows:
20624 + * - Core Global Registers
20625 + * - Device Mode Registers
20626 + * - Device Global Registers
20627 + * - Device Endpoint Specific Registers
20628 + * - Host Mode Registers
20629 + * - Host Global Registers
20630 + * - Host Port CSRs
20631 + * - Host Channel Specific Registers
20633 + * Only the Core Global registers can be accessed in both Device and
20634 + * Host modes. When the HS OTG core is operating in one mode, either
20635 + * Device or Host, the application must not access registers from the
20636 + * other mode. When the core switches from one mode to another, the
20637 + * registers in the new mode of operation must be reprogrammed as they
20638 + * would be after a power-on reset.
20641 +/** Maximum number of Periodic FIFOs */
20642 +#define MAX_PERIO_FIFOS 15
20643 +/** Maximum number of Transmit FIFOs */
20644 +#define MAX_TX_FIFOS 15
20646 +/** Maximum number of Endpoints/HostChannels */
20647 +#define MAX_EPS_CHANNELS 16
20649 +/****************************************************************************/
20650 +/** DWC_otg Core registers .
20651 + * The dwc_otg_core_global_regs structure defines the size
20652 + * and relative field offsets for the Core Global registers.
20654 +typedef struct dwc_otg_core_global_regs
20656 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
20657 + volatile uint32_t gotgctl;
20658 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
20659 + volatile uint32_t gotgint;
20660 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
20661 + volatile uint32_t gahbcfg;
20663 +#define DWC_GLBINTRMASK 0x0001
20664 +#define DWC_DMAENABLE 0x0020
20665 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
20666 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
20667 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
20668 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
20670 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
20671 + volatile uint32_t gusbcfg;
20672 + /**Core Reset Register. <i>Offset: 010h</i> */
20673 + volatile uint32_t grstctl;
20674 + /**Core Interrupt Register. <i>Offset: 014h</i> */
20675 + volatile uint32_t gintsts;
20676 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
20677 + volatile uint32_t gintmsk;
20678 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
20679 + volatile uint32_t grxstsr;
20680 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
20681 + volatile uint32_t grxstsp;
20682 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
20683 + volatile uint32_t grxfsiz;
20684 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
20685 + volatile uint32_t gnptxfsiz;
20686 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
20687 + * Only). <i>Offset: 02Ch</i> */
20688 + volatile uint32_t gnptxsts;
20689 + /**I2C Access Register. <i>Offset: 030h</i> */
20690 + volatile uint32_t gi2cctl;
20691 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
20692 + volatile uint32_t gpvndctl;
20693 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
20694 + volatile uint32_t ggpio;
20695 + /**User ID Register. <i>Offset: 03Ch</i> */
20696 + volatile uint32_t guid;
20697 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
20698 + volatile uint32_t gsnpsid;
20699 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
20700 + volatile uint32_t ghwcfg1;
20701 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
20702 + volatile uint32_t ghwcfg2;
20703 +#define DWC_SLAVE_ONLY_ARCH 0
20704 +#define DWC_EXT_DMA_ARCH 1
20705 +#define DWC_INT_DMA_ARCH 2
20707 +#define DWC_MODE_HNP_SRP_CAPABLE 0
20708 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
20709 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
20710 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
20711 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
20712 +#define DWC_MODE_SRP_CAPABLE_HOST 5
20713 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
20715 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
20716 + volatile uint32_t ghwcfg3;
20717 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
20718 + volatile uint32_t ghwcfg4;
20719 + /** Reserved <i>Offset: 054h-0FFh</i> */
20720 + volatile uint32_t reserved[43];
20721 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
20722 + volatile uint32_t hptxfsiz;
20723 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
20724 + otherwise Device Transmit FIFO#n Register.
20725 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
20726 + volatile uint32_t dptxfsiz_dieptxf[15];
20727 +} dwc_otg_core_global_regs_t;
20730 + * This union represents the bit fields of the Core OTG Control
20731 + * and Status Register (GOTGCTL). Set the bits using the bit
20732 + * fields then write the <i>d32</i> value to the register.
20734 +typedef union gotgctl_data
20736 + /** raw register data */
20738 + /** register bits */
20741 + unsigned sesreqscs : 1;
20742 + unsigned sesreq : 1;
20743 + unsigned reserved2_7 : 6;
20744 + unsigned hstnegscs : 1;
20745 + unsigned hnpreq : 1;
20746 + unsigned hstsethnpen : 1;
20747 + unsigned devhnpen : 1;
20748 + unsigned reserved12_15 : 4;
20749 + unsigned conidsts : 1;
20750 + unsigned reserved17 : 1;
20751 + unsigned asesvld : 1;
20752 + unsigned bsesvld : 1;
20753 + unsigned currmod : 1;
20754 + unsigned reserved21_31 : 11;
20759 + * This union represents the bit fields of the Core OTG Interrupt Register
20760 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
20761 + * value to the register.
20763 +typedef union gotgint_data
20765 + /** raw register data */
20767 + /** register bits */
20770 + /** Current Mode */
20771 + unsigned reserved0_1 : 2;
20773 + /** Session End Detected */
20774 + unsigned sesenddet : 1;
20776 + unsigned reserved3_7 : 5;
20778 + /** Session Request Success Status Change */
20779 + unsigned sesreqsucstschng : 1;
20780 + /** Host Negotiation Success Status Change */
20781 + unsigned hstnegsucstschng : 1;
20783 + unsigned reserver10_16 : 7;
20785 + /** Host Negotiation Detected */
20786 + unsigned hstnegdet : 1;
20787 + /** A-Device Timeout Change */
20788 + unsigned adevtoutchng : 1;
20789 + /** Debounce Done */
20790 + unsigned debdone : 1;
20792 + unsigned reserved31_20 : 12;
20799 + * This union represents the bit fields of the Core AHB Configuration
20800 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
20801 + * write the <i>d32</i> value to the register.
20803 +typedef union gahbcfg_data
20805 + /** raw register data */
20807 + /** register bits */
20810 + unsigned glblintrmsk : 1;
20811 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
20813 + unsigned hburstlen : 4;
20814 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
20815 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
20816 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
20817 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
20818 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
20820 + unsigned dmaenable : 1;
20821 +#define DWC_GAHBCFG_DMAENABLE 1
20822 + unsigned reserved : 1;
20823 + unsigned nptxfemplvl_txfemplvl : 1;
20824 + unsigned ptxfemplvl : 1;
20825 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
20826 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
20827 + unsigned reserved9_31 : 23;
20832 + * This union represents the bit fields of the Core USB Configuration
20833 + * Register (GUSBCFG). Set the bits using the bit fields then write
20834 + * the <i>d32</i> value to the register.
20836 +typedef union gusbcfg_data
20838 + /** raw register data */
20840 + /** register bits */
20843 + unsigned toutcal : 3;
20844 + unsigned phyif : 1;
20845 + unsigned ulpi_utmi_sel : 1;
20846 + unsigned fsintf : 1;
20847 + unsigned physel : 1;
20848 + unsigned ddrsel : 1;
20849 + unsigned srpcap : 1;
20850 + unsigned hnpcap : 1;
20851 + unsigned usbtrdtim : 4;
20852 + unsigned nptxfrwnden : 1;
20853 + unsigned phylpwrclksel : 1;
20854 + unsigned otgutmifssel : 1;
20855 + unsigned ulpi_fsls : 1;
20856 + unsigned ulpi_auto_res : 1;
20857 + unsigned ulpi_clk_sus_m : 1;
20858 + unsigned ulpi_ext_vbus_drv : 1;
20859 + unsigned ulpi_int_vbus_indicator : 1;
20860 + unsigned term_sel_dl_pulse : 1;
20861 + unsigned reserved23_27 : 5;
20862 + unsigned tx_end_delay : 1;
20863 + unsigned reserved29_31 : 3;
20868 + * This union represents the bit fields of the Core Reset Register
20869 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
20870 + * <i>d32</i> value to the register.
20872 +typedef union grstctl_data
20874 + /** raw register data */
20876 + /** register bits */
20879 + /** Core Soft Reset (CSftRst) (Device and Host)
20881 + * The application can flush the control logic in the
20882 + * entire core using this bit. This bit resets the
20883 + * pipelines in the AHB Clock domain as well as the
20884 + * PHY Clock domain.
20886 + * The state machines are reset to an IDLE state, the
20887 + * control bits in the CSRs are cleared, all the
20888 + * transmit FIFOs and the receive FIFO are flushed.
20890 + * The status mask bits that control the generation of
20891 + * the interrupt, are cleared, to clear the
20892 + * interrupt. The interrupt status bits are not
20893 + * cleared, so the application can get the status of
20894 + * any events that occurred in the core after it has
20897 + * Any transactions on the AHB are terminated as soon
20898 + * as possible following the protocol. Any
20899 + * transactions on the USB are terminated immediately.
20901 + * The configuration settings in the CSRs are
20902 + * unchanged, so the software doesn't have to
20903 + * reprogram these registers (Device
20904 + * Configuration/Host Configuration/Core System
20905 + * Configuration/Core PHY Configuration).
20907 + * The application can write to this bit, any time it
20908 + * wants to reset the core. This is a self clearing
20909 + * bit and the core clears this bit after all the
20910 + * necessary logic is reset in the core, which may
20911 + * take several clocks, depending on the current state
20914 + unsigned csftrst : 1;
20915 + /** Hclk Soft Reset
20917 + * The application uses this bit to reset the control logic in
20918 + * the AHB clock domain. Only AHB clock domain pipelines are
20921 + unsigned hsftrst : 1;
20922 + /** Host Frame Counter Reset (Host Only)<br>
20924 + * The application can reset the (micro)frame number
20925 + * counter inside the core, using this bit. When the
20926 + * (micro)frame counter is reset, the subsequent SOF
20927 + * sent out by the core, will have a (micro)frame
20930 + unsigned hstfrm : 1;
20931 + /** In Token Sequence Learning Queue Flush
20932 + * (INTknQFlsh) (Device Only)
20934 + unsigned intknqflsh : 1;
20935 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
20937 + * The application can flush the entire Receive FIFO
20938 + * using this bit. <p>The application must first
20939 + * ensure that the core is not in the middle of a
20940 + * transaction. <p>The application should write into
20941 + * this bit, only after making sure that neither the
20942 + * DMA engine is reading from the RxFIFO nor the MAC
20943 + * is writing the data in to the FIFO. <p>The
20944 + * application should wait until the bit is cleared
20945 + * before performing any other operations. This bit
20946 + * will takes 8 clocks (slowest of PHY or AHB clock)
20949 + unsigned rxfflsh : 1;
20950 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
20952 + * This bit is used to selectively flush a single or
20953 + * all transmit FIFOs. The application must first
20954 + * ensure that the core is not in the middle of a
20955 + * transaction. <p>The application should write into
20956 + * this bit, only after making sure that neither the
20957 + * DMA engine is writing into the TxFIFO nor the MAC
20958 + * is reading the data out of the FIFO. <p>The
20959 + * application should wait until the core clears this
20960 + * bit, before performing any operations. This bit
20961 + * will takes 8 clocks (slowest of PHY or AHB clock)
20964 + unsigned txfflsh : 1;
20965 + /** TxFIFO Number (TxFNum) (Device and Host).
20967 + * This is the FIFO number which needs to be flushed,
20968 + * using the TxFIFO Flush bit. This field should not
20969 + * be changed until the TxFIFO Flush bit is cleared by
20971 + * - 0x0 : Non Periodic TxFIFO Flush
20972 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
20973 + * or Periodic TxFIFO in host mode
20974 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
20976 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
20977 + * - 0x10: Flush all the Transmit NonPeriodic and
20978 + * Transmit Periodic FIFOs in the core
20980 + unsigned txfnum : 5;
20982 + unsigned reserved11_29 : 19;
20983 + /** DMA Request Signal. Indicated DMA request is in
20984 + * probress. Used for debug purpose. */
20985 + unsigned dmareq : 1;
20986 + /** AHB Master Idle. Indicates the AHB Master State
20987 + * Machine is in IDLE condition. */
20988 + unsigned ahbidle : 1;
20994 + * This union represents the bit fields of the Core Interrupt Mask
20995 + * Register (GINTMSK). Set/clear the bits using the bit fields then
20996 + * write the <i>d32</i> value to the register.
20998 +typedef union gintmsk_data
21000 + /** raw register data */
21002 + /** register bits */
21005 + unsigned reserved0 : 1;
21006 + unsigned modemismatch : 1;
21007 + unsigned otgintr : 1;
21008 + unsigned sofintr : 1;
21009 + unsigned rxstsqlvl : 1;
21010 + unsigned nptxfempty : 1;
21011 + unsigned ginnakeff : 1;
21012 + unsigned goutnakeff : 1;
21013 + unsigned reserved8 : 1;
21014 + unsigned i2cintr : 1;
21015 + unsigned erlysuspend : 1;
21016 + unsigned usbsuspend : 1;
21017 + unsigned usbreset : 1;
21018 + unsigned enumdone : 1;
21019 + unsigned isooutdrop : 1;
21020 + unsigned eopframe : 1;
21021 + unsigned reserved16 : 1;
21022 + unsigned epmismatch : 1;
21023 + unsigned inepintr : 1;
21024 + unsigned outepintr : 1;
21025 + unsigned incomplisoin : 1;
21026 + unsigned incomplisoout : 1;
21027 + unsigned reserved22_23 : 2;
21028 + unsigned portintr : 1;
21029 + unsigned hcintr : 1;
21030 + unsigned ptxfempty : 1;
21031 + unsigned reserved27 : 1;
21032 + unsigned conidstschng : 1;
21033 + unsigned disconnect : 1;
21034 + unsigned sessreqintr : 1;
21035 + unsigned wkupintr : 1;
21039 + * This union represents the bit fields of the Core Interrupt Register
21040 + * (GINTSTS). Set/clear the bits using the bit fields then write the
21041 + * <i>d32</i> value to the register.
21043 +typedef union gintsts_data
21045 + /** raw register data */
21047 +#define DWC_SOF_INTR_MASK 0x0008
21048 + /** register bits */
21051 +#define DWC_HOST_MODE 1
21052 + unsigned curmode : 1;
21053 + unsigned modemismatch : 1;
21054 + unsigned otgintr : 1;
21055 + unsigned sofintr : 1;
21056 + unsigned rxstsqlvl : 1;
21057 + unsigned nptxfempty : 1;
21058 + unsigned ginnakeff : 1;
21059 + unsigned goutnakeff : 1;
21060 + unsigned reserved8 : 1;
21061 + unsigned i2cintr : 1;
21062 + unsigned erlysuspend : 1;
21063 + unsigned usbsuspend : 1;
21064 + unsigned usbreset : 1;
21065 + unsigned enumdone : 1;
21066 + unsigned isooutdrop : 1;
21067 + unsigned eopframe : 1;
21068 + unsigned intokenrx : 1;
21069 + unsigned epmismatch : 1;
21070 + unsigned inepint: 1;
21071 + unsigned outepintr : 1;
21072 + unsigned incomplisoin : 1;
21073 + unsigned incomplisoout : 1;
21074 + unsigned reserved22_23 : 2;
21075 + unsigned portintr : 1;
21076 + unsigned hcintr : 1;
21077 + unsigned ptxfempty : 1;
21078 + unsigned reserved27 : 1;
21079 + unsigned conidstschng : 1;
21080 + unsigned disconnect : 1;
21081 + unsigned sessreqintr : 1;
21082 + unsigned wkupintr : 1;
21088 + * This union represents the bit fields in the Device Receive Status Read and
21089 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
21090 + * element then read out the bits using the <i>b</i>it elements.
21092 +typedef union device_grxsts_data
21094 + /** raw register data */
21096 + /** register bits */
21099 + unsigned epnum : 4;
21100 + unsigned bcnt : 11;
21101 + unsigned dpid : 2;
21102 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
21103 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
21105 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
21106 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
21107 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
21108 + unsigned pktsts : 4;
21110 + unsigned reserved : 7;
21112 +} device_grxsts_data_t;
21115 + * This union represents the bit fields in the Host Receive Status Read and
21116 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
21117 + * element then read out the bits using the <i>b</i>it elements.
21119 +typedef union host_grxsts_data
21121 + /** raw register data */
21123 + /** register bits */
21126 + unsigned chnum : 4;
21127 + unsigned bcnt : 11;
21128 + unsigned dpid : 2;
21129 + unsigned pktsts : 4;
21130 +#define DWC_GRXSTS_PKTSTS_IN 0x2
21131 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
21132 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
21133 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
21134 + unsigned reserved : 11;
21136 +} host_grxsts_data_t;
21139 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
21140 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
21141 + * read out the bits using the <i>b</i>it elements.
21143 +typedef union fifosize_data
21145 + /** raw register data */
21147 + /** register bits */
21150 + unsigned startaddr : 16;
21151 + unsigned depth : 16;
21153 +} fifosize_data_t;
21156 + * This union represents the bit fields in the Non-Periodic Transmit
21157 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
21158 + * <i>d32</i> element then read out the bits using the <i>b</i>it
21161 +typedef union gnptxsts_data
21163 + /** raw register data */
21165 + /** register bits */
21168 + unsigned nptxfspcavail : 16;
21169 + unsigned nptxqspcavail : 8;
21170 + /** Top of the Non-Periodic Transmit Request Queue
21171 + * - bit 24 - Terminate (Last entry for the selected
21173 + * - bits 26:25 - Token Type
21174 + * - 2'b00 - IN/OUT
21175 + * - 2'b01 - Zero Length OUT
21176 + * - 2'b10 - PING/Complete Split
21177 + * - 2'b11 - Channel Halt
21178 + * - bits 30:27 - Channel/EP Number
21180 + unsigned nptxqtop_terminate : 1;
21181 + unsigned nptxqtop_token : 2;
21182 + unsigned nptxqtop_chnep : 4;
21183 + unsigned reserved : 1;
21185 +} gnptxsts_data_t;
21188 + * This union represents the bit fields in the Transmit
21189 + * FIFO Status Register (DTXFSTS). Read the register into the
21190 + * <i>d32</i> element then read out the bits using the <i>b</i>it
21193 +typedef union dtxfsts_data
21195 + /** raw register data */
21197 + /** register bits */
21200 + unsigned txfspcavail : 16;
21201 + unsigned reserved : 16;
21206 + * This union represents the bit fields in the I2C Control Register
21207 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
21208 + * bits using the <i>b</i>it elements.
21210 +typedef union gi2cctl_data
21212 + /** raw register data */
21214 + /** register bits */
21217 + unsigned rwdata : 8;
21218 + unsigned regaddr : 8;
21219 + unsigned addr : 7;
21220 + unsigned i2cen : 1;
21221 + unsigned ack : 1;
21222 + unsigned i2csuspctl : 1;
21223 + unsigned i2cdevaddr : 2;
21224 + unsigned reserved : 2;
21226 + unsigned bsydne : 1;
21231 + * This union represents the bit fields in the User HW Config1
21232 + * Register. Read the register into the <i>d32</i> element then read
21233 + * out the bits using the <i>b</i>it elements.
21235 +typedef union hwcfg1_data
21237 + /** raw register data */
21239 + /** register bits */
21242 + unsigned ep_dir0 : 2;
21243 + unsigned ep_dir1 : 2;
21244 + unsigned ep_dir2 : 2;
21245 + unsigned ep_dir3 : 2;
21246 + unsigned ep_dir4 : 2;
21247 + unsigned ep_dir5 : 2;
21248 + unsigned ep_dir6 : 2;
21249 + unsigned ep_dir7 : 2;
21250 + unsigned ep_dir8 : 2;
21251 + unsigned ep_dir9 : 2;
21252 + unsigned ep_dir10 : 2;
21253 + unsigned ep_dir11 : 2;
21254 + unsigned ep_dir12 : 2;
21255 + unsigned ep_dir13 : 2;
21256 + unsigned ep_dir14 : 2;
21257 + unsigned ep_dir15 : 2;
21262 + * This union represents the bit fields in the User HW Config2
21263 + * Register. Read the register into the <i>d32</i> element then read
21264 + * out the bits using the <i>b</i>it elements.
21266 +typedef union hwcfg2_data
21268 + /** raw register data */
21270 + /** register bits */
21274 + unsigned op_mode : 3;
21275 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
21276 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
21277 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
21278 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
21279 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
21280 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
21281 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
21283 + unsigned architecture : 2;
21284 + unsigned point2point : 1;
21285 + unsigned hs_phy_type : 2;
21286 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
21287 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
21288 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
21289 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
21291 + unsigned fs_phy_type : 2;
21292 + unsigned num_dev_ep : 4;
21293 + unsigned num_host_chan : 4;
21294 + unsigned perio_ep_supported : 1;
21295 + unsigned dynamic_fifo : 1;
21296 + unsigned multi_proc_int : 1;
21297 + unsigned reserved21 : 1;
21298 + unsigned nonperio_tx_q_depth : 2;
21299 + unsigned host_perio_tx_q_depth : 2;
21300 + unsigned dev_token_q_depth : 5;
21301 + unsigned reserved31 : 1;
21306 + * This union represents the bit fields in the User HW Config3
21307 + * Register. Read the register into the <i>d32</i> element then read
21308 + * out the bits using the <i>b</i>it elements.
21310 +typedef union hwcfg3_data
21312 + /** raw register data */
21314 + /** register bits */
21318 + unsigned xfer_size_cntr_width : 4;
21319 + unsigned packet_size_cntr_width : 3;
21320 + unsigned otg_func : 1;
21321 + unsigned i2c : 1;
21322 + unsigned vendor_ctrl_if : 1;
21323 + unsigned optional_features : 1;
21324 + unsigned synch_reset_type : 1;
21325 + unsigned ahb_phy_clock_synch : 1;
21326 + unsigned reserved15_13 : 3;
21327 + unsigned dfifo_depth : 16;
21332 + * This union represents the bit fields in the User HW Config4
21333 + * Register. Read the register into the <i>d32</i> element then read
21334 + * out the bits using the <i>b</i>it elements.
21336 +typedef union hwcfg4_data
21338 + /** raw register data */
21340 + /** register bits */
21343 + unsigned num_dev_perio_in_ep : 4;
21344 + unsigned power_optimiz : 1;
21345 + unsigned min_ahb_freq : 9;
21346 + unsigned utmi_phy_data_width : 2;
21347 + unsigned num_dev_mode_ctrl_ep : 4;
21348 + unsigned iddig_filt_en : 1;
21349 + unsigned vbus_valid_filt_en : 1;
21350 + unsigned a_valid_filt_en : 1;
21351 + unsigned b_valid_filt_en : 1;
21352 + unsigned session_end_filt_en : 1;
21353 + unsigned ded_fifo_en : 1;
21354 + unsigned num_in_eps : 4;
21355 + unsigned desc_dma : 1;
21356 + unsigned desc_dma_dyn : 1;
21360 +////////////////////////////////////////////
21361 +// Device Registers
21363 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
21365 + * The following structures define the size and relative field offsets
21366 + * for the Device Mode Registers.
21368 + * <i>These registers are visible only in Device mode and must not be
21369 + * accessed in Host mode, as the results are unknown.</i>
21371 +typedef struct dwc_otg_dev_global_regs
21373 + /** Device Configuration Register. <i>Offset 800h</i> */
21374 + volatile uint32_t dcfg;
21375 + /** Device Control Register. <i>Offset: 804h</i> */
21376 + volatile uint32_t dctl;
21377 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
21378 + volatile uint32_t dsts;
21379 + /** Reserved. <i>Offset: 80Ch</i> */
21381 + /** Device IN Endpoint Common Interrupt Mask
21382 + * Register. <i>Offset: 810h</i> */
21383 + volatile uint32_t diepmsk;
21384 + /** Device OUT Endpoint Common Interrupt Mask
21385 + * Register. <i>Offset: 814h</i> */
21386 + volatile uint32_t doepmsk;
21387 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
21388 + volatile uint32_t daint;
21389 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
21391 + volatile uint32_t daintmsk;
21392 + /** Device IN Token Queue Read Register-1 (Read Only).
21393 + * <i>Offset: 820h</i> */
21394 + volatile uint32_t dtknqr1;
21395 + /** Device IN Token Queue Read Register-2 (Read Only).
21396 + * <i>Offset: 824h</i> */
21397 + volatile uint32_t dtknqr2;
21398 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
21399 + volatile uint32_t dvbusdis;
21400 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
21401 + volatile uint32_t dvbuspulse;
21402 + /** Device IN Token Queue Read Register-3 (Read Only). /
21403 + * Device Thresholding control register (Read/Write)
21404 + * <i>Offset: 830h</i> */
21405 + volatile uint32_t dtknqr3_dthrctl;
21406 + /** Device IN Token Queue Read Register-4 (Read Only). /
21407 + * Device IN EPs empty Inr. Mask Register (Read/Write)
21408 + * <i>Offset: 834h</i> */
21409 + volatile uint32_t dtknqr4_fifoemptymsk;
21410 + /** Device Each Endpoint Interrupt Register (Read Only). /
21411 + * <i>Offset: 838h</i> */
21412 + volatile uint32_t deachint;
21413 + /** Device Each Endpoint Interrupt mask Register (Read/Write). /
21414 + * <i>Offset: 83Ch</i> */
21415 + volatile uint32_t deachintmsk;
21416 + /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
21417 + * <i>Offset: 840h</i> */
21418 + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
21419 + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
21420 + * <i>Offset: 880h</i> */
21421 + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
21422 +} dwc_otg_device_global_regs_t;
21425 + * This union represents the bit fields in the Device Configuration
21426 + * Register. Read the register into the <i>d32</i> member then
21427 + * set/clear the bits using the <i>b</i>it elements. Write the
21428 + * <i>d32</i> member to the dcfg register.
21430 +typedef union dcfg_data
21432 + /** raw register data */
21434 + /** register bits */
21437 + /** Device Speed */
21438 + unsigned devspd : 2;
21439 + /** Non Zero Length Status OUT Handshake */
21440 + unsigned nzstsouthshk : 1;
21441 +#define DWC_DCFG_SEND_STALL 1
21443 + unsigned reserved3 : 1;
21444 + /** Device Addresses */
21445 + unsigned devaddr : 7;
21446 + /** Periodic Frame Interval */
21447 + unsigned perfrint : 2;
21448 +#define DWC_DCFG_FRAME_INTERVAL_80 0
21449 +#define DWC_DCFG_FRAME_INTERVAL_85 1
21450 +#define DWC_DCFG_FRAME_INTERVAL_90 2
21451 +#define DWC_DCFG_FRAME_INTERVAL_95 3
21453 + unsigned reserved13_17 : 5;
21454 + /** In Endpoint Mis-match count */
21455 + unsigned epmscnt : 5;
21456 + /** Enable Descriptor DMA in Device mode */
21457 + unsigned descdma : 1;
21462 + * This union represents the bit fields in the Device Control
21463 + * Register. Read the register into the <i>d32</i> member then
21464 + * set/clear the bits using the <i>b</i>it elements.
21466 +typedef union dctl_data
21468 + /** raw register data */
21470 + /** register bits */
21473 + /** Remote Wakeup */
21474 + unsigned rmtwkupsig : 1;
21475 + /** Soft Disconnect */
21476 + unsigned sftdiscon : 1;
21477 + /** Global Non-Periodic IN NAK Status */
21478 + unsigned gnpinnaksts : 1;
21479 + /** Global OUT NAK Status */
21480 + unsigned goutnaksts : 1;
21481 + /** Test Control */
21482 + unsigned tstctl : 3;
21483 + /** Set Global Non-Periodic IN NAK */
21484 + unsigned sgnpinnak : 1;
21485 + /** Clear Global Non-Periodic IN NAK */
21486 + unsigned cgnpinnak : 1;
21487 + /** Set Global OUT NAK */
21488 + unsigned sgoutnak : 1;
21489 + /** Clear Global OUT NAK */
21490 + unsigned cgoutnak : 1;
21492 + /** Power-On Programming Done */
21493 + unsigned pwronprgdone : 1;
21494 + /** Global Continue on BNA */
21495 + unsigned gcontbna : 1;
21496 + /** Global Multi Count */
21497 + unsigned gmc : 2;
21498 + /** Ignore Frame Number for ISOC EPs */
21499 + unsigned ifrmnum : 1;
21500 + /** NAK on Babble */
21501 + unsigned nakonbble : 1;
21503 + unsigned reserved16_31 : 16;
21508 + * This union represents the bit fields in the Device Status
21509 + * Register. Read the register into the <i>d32</i> member then
21510 + * set/clear the bits using the <i>b</i>it elements.
21512 +typedef union dsts_data
21514 + /** raw register data */
21516 + /** register bits */
21519 + /** Suspend Status */
21520 + unsigned suspsts : 1;
21521 + /** Enumerated Speed */
21522 + unsigned enumspd : 2;
21523 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
21524 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
21525 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
21526 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
21527 + /** Erratic Error */
21528 + unsigned errticerr : 1;
21529 + unsigned reserved4_7: 4;
21530 + /** Frame or Microframe Number of the received SOF */
21531 + unsigned soffn : 14;
21532 + unsigned reserved22_31 : 10;
21538 + * This union represents the bit fields in the Device IN EP Interrupt
21539 + * Register and the Device IN EP Common Mask Register.
21541 + * - Read the register into the <i>d32</i> member then set/clear the
21542 + * bits using the <i>b</i>it elements.
21544 +typedef union diepint_data
21546 + /** raw register data */
21548 + /** register bits */
21551 + /** Transfer complete mask */
21552 + unsigned xfercompl : 1;
21553 + /** Endpoint disable mask */
21554 + unsigned epdisabled : 1;
21555 + /** AHB Error mask */
21556 + unsigned ahberr : 1;
21557 + /** TimeOUT Handshake mask (non-ISOC EPs) */
21558 + unsigned timeout : 1;
21559 + /** IN Token received with TxF Empty mask */
21560 + unsigned intktxfemp : 1;
21561 + /** IN Token Received with EP mismatch mask */
21562 + unsigned intknepmis : 1;
21563 + /** IN Endpoint HAK Effective mask */
21564 + unsigned inepnakeff : 1;
21565 + /** IN Endpoint HAK Effective mask */
21566 + unsigned emptyintr : 1;
21567 + unsigned txfifoundrn : 1;
21569 + /** BNA Interrupt mask */
21570 + unsigned bna : 1;
21571 + unsigned reserved10_12 : 3;
21572 + /** BNA Interrupt mask */
21573 + unsigned nak : 1;
21574 + unsigned reserved14_31 : 18;
21579 + * This union represents the bit fields in the Device IN EP
21580 + * Common/Dedicated Interrupt Mask Register.
21582 +typedef union diepint_data diepmsk_data_t;
21585 + * This union represents the bit fields in the Device OUT EP Interrupt
21586 + * Registerand Device OUT EP Common Interrupt Mask Register.
21588 + * - Read the register into the <i>d32</i> member then set/clear the
21589 + * bits using the <i>b</i>it elements.
21591 +typedef union doepint_data
21593 + /** raw register data */
21595 + /** register bits */
21598 + /** Transfer complete */
21599 + unsigned xfercompl : 1;
21600 + /** Endpoint disable */
21601 + unsigned epdisabled : 1;
21603 + unsigned ahberr : 1;
21604 + /** Setup Phase Done (contorl EPs) */
21605 + unsigned setup : 1;
21606 + /** OUT Token Received when Endpoint Disabled */
21607 + unsigned outtknepdis : 1;
21608 + unsigned stsphsercvd : 1;
21609 + /** Back-to-Back SETUP Packets Received */
21610 + unsigned back2backsetup : 1;
21611 + unsigned reserved7 : 1;
21612 + /** OUT packet Error */
21613 + unsigned outpkterr : 1;
21614 + /** BNA Interrupt */
21615 + unsigned bna : 1;
21616 + unsigned reserved10 : 1;
21617 + /** Packet Drop Status */
21618 + unsigned pktdrpsts : 1;
21619 + /** Babble Interrupt */
21620 + unsigned babble : 1;
21621 + /** NAK Interrupt */
21622 + unsigned nak : 1;
21623 + /** NYET Interrupt */
21624 + unsigned nyet : 1;
21626 + unsigned reserved15_31 : 17;
21631 + * This union represents the bit fields in the Device OUT EP
21632 + * Common/Dedicated Interrupt Mask Register.
21634 +typedef union doepint_data doepmsk_data_t;
21637 + * This union represents the bit fields in the Device All EP Interrupt
21638 + * and Mask Registers.
21639 + * - Read the register into the <i>d32</i> member then set/clear the
21640 + * bits using the <i>b</i>it elements.
21642 +typedef union daint_data
21644 + /** raw register data */
21646 + /** register bits */
21649 + /** IN Endpoint bits */
21650 + unsigned in : 16;
21651 + /** OUT Endpoint bits */
21652 + unsigned out : 16;
21656 + /** IN Endpoint bits */
21657 + unsigned inep0 : 1;
21658 + unsigned inep1 : 1;
21659 + unsigned inep2 : 1;
21660 + unsigned inep3 : 1;
21661 + unsigned inep4 : 1;
21662 + unsigned inep5 : 1;
21663 + unsigned inep6 : 1;
21664 + unsigned inep7 : 1;
21665 + unsigned inep8 : 1;
21666 + unsigned inep9 : 1;
21667 + unsigned inep10 : 1;
21668 + unsigned inep11 : 1;
21669 + unsigned inep12 : 1;
21670 + unsigned inep13 : 1;
21671 + unsigned inep14 : 1;
21672 + unsigned inep15 : 1;
21673 + /** OUT Endpoint bits */
21674 + unsigned outep0 : 1;
21675 + unsigned outep1 : 1;
21676 + unsigned outep2 : 1;
21677 + unsigned outep3 : 1;
21678 + unsigned outep4 : 1;
21679 + unsigned outep5 : 1;
21680 + unsigned outep6 : 1;
21681 + unsigned outep7 : 1;
21682 + unsigned outep8 : 1;
21683 + unsigned outep9 : 1;
21684 + unsigned outep10 : 1;
21685 + unsigned outep11 : 1;
21686 + unsigned outep12 : 1;
21687 + unsigned outep13 : 1;
21688 + unsigned outep14 : 1;
21689 + unsigned outep15 : 1;
21694 + * This union represents the bit fields in the Device IN Token Queue
21695 + * Read Registers.
21696 + * - Read the register into the <i>d32</i> member.
21697 + * - READ-ONLY Register
21699 +typedef union dtknq1_data
21701 + /** raw register data */
21703 + /** register bits */
21706 + /** In Token Queue Write Pointer */
21707 + unsigned intknwptr : 5;
21709 + unsigned reserved05_06 : 2;
21710 + /** write pointer has wrapped. */
21711 + unsigned wrap_bit : 1;
21712 + /** EP Numbers of IN Tokens 0 ... 4 */
21713 + unsigned epnums0_5 : 24;
21718 + * This union represents Threshold control Register
21719 + * - Read and write the register into the <i>d32</i> member.
21720 + * - READ-WRITABLE Register
21722 +typedef union dthrctl_data
21724 + /** raw register data */
21726 + /** register bits */
21729 + /** non ISO Tx Thr. Enable */
21730 + unsigned non_iso_thr_en : 1;
21731 + /** ISO Tx Thr. Enable */
21732 + unsigned iso_thr_en : 1;
21733 + /** Tx Thr. Length */
21734 + unsigned tx_thr_len : 9;
21736 + unsigned reserved11_15 : 5;
21737 + /** Rx Thr. Enable */
21738 + unsigned rx_thr_en : 1;
21739 + /** Rx Thr. Length */
21740 + unsigned rx_thr_len : 9;
21742 + unsigned reserved26_31 : 6;
21748 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
21751 + * There will be one set of endpoint registers per logical endpoint
21754 + * <i>These registers are visible only in Device mode and must not be
21755 + * accessed in Host mode, as the results are unknown.</i>
21757 +typedef struct dwc_otg_dev_in_ep_regs
21759 + /** Device IN Endpoint Control Register. <i>Offset:900h +
21760 + * (ep_num * 20h) + 00h</i> */
21761 + volatile uint32_t diepctl;
21762 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
21763 + uint32_t reserved04;
21764 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
21765 + * (ep_num * 20h) + 08h</i> */
21766 + volatile uint32_t diepint;
21767 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
21768 + uint32_t reserved0C;
21769 + /** Device IN Endpoint Transfer Size
21770 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
21771 + volatile uint32_t dieptsiz;
21772 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
21773 + * (ep_num * 20h) + 14h</i> */
21774 + volatile uint32_t diepdma;
21775 + /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
21776 + * (ep_num * 20h) + 18h</i> */
21777 + volatile uint32_t dtxfsts;
21778 + /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
21779 + * (ep_num * 20h) + 1Ch</i> */
21780 + volatile uint32_t diepdmab;
21781 +} dwc_otg_dev_in_ep_regs_t;
21784 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
21787 + * There will be one set of endpoint registers per logical endpoint
21790 + * <i>These registers are visible only in Device mode and must not be
21791 + * accessed in Host mode, as the results are unknown.</i>
21793 +typedef struct dwc_otg_dev_out_ep_regs
21795 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
21796 + * (ep_num * 20h) + 00h</i> */
21797 + volatile uint32_t doepctl;
21798 + /** Device OUT Endpoint Frame number Register. <i>Offset:
21799 + * B00h + (ep_num * 20h) + 04h</i> */
21800 + volatile uint32_t doepfn;
21801 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
21802 + * (ep_num * 20h) + 08h</i> */
21803 + volatile uint32_t doepint;
21804 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
21805 + uint32_t reserved0C;
21806 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
21807 + * B00h + (ep_num * 20h) + 10h</i> */
21808 + volatile uint32_t doeptsiz;
21809 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
21810 + * + (ep_num * 20h) + 14h</i> */
21811 + volatile uint32_t doepdma;
21812 + /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 1Ch</i> */
21814 + /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
21815 + * + (ep_num * 20h) + 1Ch</i> */
21816 + uint32_t doepdmab;
21817 +} dwc_otg_dev_out_ep_regs_t;
21820 + * This union represents the bit fields in the Device EP Control
21821 + * Register. Read the register into the <i>d32</i> member then
21822 + * set/clear the bits using the <i>b</i>it elements.
21824 +typedef union depctl_data
21826 + /** raw register data */
21828 + /** register bits */
21831 + /** Maximum Packet Size
21833 + * IN/OUT EP0 - 2 bits
21834 + * 2'b00: 64 Bytes
21838 + unsigned mps : 11;
21839 +#define DWC_DEP0CTL_MPS_64 0
21840 +#define DWC_DEP0CTL_MPS_32 1
21841 +#define DWC_DEP0CTL_MPS_16 2
21842 +#define DWC_DEP0CTL_MPS_8 3
21844 + /** Next Endpoint
21846 + * OUT EPn/OUT EP0 - reserved */
21847 + unsigned nextep : 4;
21849 + /** USB Active Endpoint */
21850 + unsigned usbactep : 1;
21852 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
21853 + * This field contains the PID of the packet going to
21854 + * be received or transmitted on this endpoint. The
21855 + * application should program the PID of the first
21856 + * packet going to be received or transmitted on this
21857 + * endpoint , after the endpoint is
21858 + * activated. Application use the SetD1PID and
21859 + * SetD0PID fields of this register to program either
21862 + * The encoding for this field is
21866 + unsigned dpid : 1;
21868 + /** NAK Status */
21869 + unsigned naksts : 1;
21871 + /** Endpoint Type
21873 + * 2'b01: Isochronous
21875 + * 2'b11: Interrupt */
21876 + unsigned eptype : 2;
21879 + * OUT EPn/OUT EP0
21880 + * IN EPn/IN EP0 - reserved */
21881 + unsigned snp : 1;
21883 + /** Stall Handshake */
21884 + unsigned stall : 1;
21886 + /** Tx Fifo Number
21888 + * OUT EPn/OUT EP0 - reserved */
21889 + unsigned txfnum : 4;
21892 + unsigned cnak : 1;
21894 + unsigned snak : 1;
21895 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
21896 + * Writing to this field sets the Endpoint DPID (DPID)
21897 + * field in this register to DATA0. Set Even
21898 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
21899 + * Writing to this field sets the Even/Odd
21900 + * (micro)frame (EO_FrNum) field to even (micro)
21903 + unsigned setd0pid : 1;
21904 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
21905 + * Writing to this field sets the Endpoint DPID (DPID)
21906 + * field in this register to DATA1 Set Odd
21907 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
21908 + * Writing to this field sets the Even/Odd
21909 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
21911 + unsigned setd1pid : 1;
21912 + /** Endpoint Disable */
21913 + unsigned epdis : 1;
21914 + /** Endpoint Enable */
21915 + unsigned epena : 1;
21920 + * This union represents the bit fields in the Device EP Transfer
21921 + * Size Register. Read the register into the <i>d32</i> member then
21922 + * set/clear the bits using the <i>b</i>it elements.
21924 +typedef union deptsiz_data
21926 + /** raw register data */
21928 + /** register bits */
21930 + /** Transfer size */
21931 + unsigned xfersize : 19;
21932 + /** Packet Count */
21933 + unsigned pktcnt : 10;
21934 + /** Multi Count - Periodic IN endpoints */
21936 + unsigned reserved : 1;
21941 + * This union represents the bit fields in the Device EP 0 Transfer
21942 + * Size Register. Read the register into the <i>d32</i> member then
21943 + * set/clear the bits using the <i>b</i>it elements.
21945 +typedef union deptsiz0_data
21947 + /** raw register data */
21949 + /** register bits */
21951 + /** Transfer size */
21952 + unsigned xfersize : 7;
21954 + unsigned reserved7_18 : 12;
21955 + /** Packet Count */
21956 + unsigned pktcnt : 1;
21958 + unsigned reserved20_28 : 9;
21959 + /**Setup Packet Count (DOEPTSIZ0 Only) */
21960 + unsigned supcnt : 2;
21961 + unsigned reserved31;
21963 +} deptsiz0_data_t;
21966 +/////////////////////////////////////////////////
21967 +// DMA Descriptor Specific Structures
21970 +/** Buffer status definitions */
21972 +#define BS_HOST_READY 0x0
21973 +#define BS_DMA_BUSY 0x1
21974 +#define BS_DMA_DONE 0x2
21975 +#define BS_HOST_BUSY 0x3
21977 +/** Receive/Transmit status definitions */
21979 +#define RTS_SUCCESS 0x0
21980 +#define RTS_BUFFLUSH 0x1
21981 +#define RTS_RESERVED 0x2
21982 +#define RTS_BUFERR 0x3
21986 + * This union represents the bit fields in the DMA Descriptor
21987 + * status quadlet. Read the quadlet into the <i>d32</i> member then
21988 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
21989 + * <i>b_iso_in</i> elements.
21991 +typedef union desc_sts_data
21993 + /** raw register data */
21995 + /** quadlet bits */
21997 + /** Received number of bytes */
21998 + unsigned bytes : 16;
22000 + unsigned reserved16_22 : 7;
22001 + /** Multiple Transfer - only for OUT EPs */
22002 + unsigned mtrf : 1;
22003 + /** Setup Packet received - only for OUT EPs */
22005 + /** Interrupt On Complete */
22006 + unsigned ioc : 1;
22007 + /** Short Packet */
22011 + /** Receive Status */
22012 + unsigned sts : 2;
22013 + /** Buffer Status */
22017 +#ifdef DWC_EN_ISOC
22018 + /** iso out quadlet bits */
22020 + /** Received number of bytes */
22021 + unsigned rxbytes : 11;
22023 + unsigned reserved11 : 1;
22024 + /** Frame Number */
22025 + unsigned framenum : 11;
22026 + /** Received ISO Data PID */
22027 + unsigned pid : 2;
22028 + /** Interrupt On Complete */
22029 + unsigned ioc : 1;
22030 + /** Short Packet */
22034 + /** Receive Status */
22035 + unsigned rxsts : 2;
22036 + /** Buffer Status */
22040 + /** iso in quadlet bits */
22042 + /** Transmited number of bytes */
22043 + unsigned txbytes : 12;
22044 + /** Frame Number */
22045 + unsigned framenum : 11;
22046 + /** Transmited ISO Data PID */
22047 + unsigned pid : 2;
22048 + /** Interrupt On Complete */
22049 + unsigned ioc : 1;
22050 + /** Short Packet */
22054 + /** Transmit Status */
22055 + unsigned txsts : 2;
22056 + /** Buffer Status */
22059 +#endif //DWC_EN_ISOC
22060 +} desc_sts_data_t;
22063 + * DMA Descriptor structure
22065 + * DMA Descriptor structure contains two quadlets:
22066 + * Status quadlet and Data buffer pointer.
22068 +typedef struct dwc_otg_dma_desc
22070 + /** DMA Descriptor status quadlet */
22071 + desc_sts_data_t status;
22072 + /** DMA Descriptor data buffer pointer */
22074 +} dwc_otg_dma_desc_t;
22077 + * The dwc_otg_dev_if structure contains information needed to manage
22078 + * the DWC_otg controller acting in device mode. It represents the
22079 + * programming view of the device-specific aspects of the controller.
22081 +typedef struct dwc_otg_dev_if
22083 + /** Pointer to device Global registers.
22084 + * Device Global Registers starting at offset 800h
22086 + dwc_otg_device_global_regs_t *dev_global_regs;
22087 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
22090 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
22092 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
22093 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
22094 +#define DWC_EP_REG_OFFSET 0x20
22096 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
22097 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
22098 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
22100 + /* Device configuration information*/
22101 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
22102 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
22103 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
22105 + /** Size of periodic FIFOs (Bytes) */
22106 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
22108 + /** Size of Tx FIFOs (Bytes) */
22109 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
22111 + /** Thresholding enable flags and length varaiables **/
22112 + uint16_t rx_thr_en;
22113 + uint16_t iso_tx_thr_en;
22114 + uint16_t non_iso_tx_thr_en;
22116 + uint16_t rx_thr_length;
22117 + uint16_t tx_thr_length;
22120 + * Pointers to the DMA Descriptors for EP0 Control
22121 + * transfers (virtual and physical)
22123 + /** 2 descriptors for SETUP packets */
22124 + uint32_t dma_setup_desc_addr[2];
22125 + dwc_otg_dma_desc_t* setup_desc_addr[2];
22127 + /** Pointer to Descriptor with latest SETUP packet */
22128 + dwc_otg_dma_desc_t* psetup;
22130 + /** Index of current SETUP handler descriptor */
22131 + uint32_t setup_desc_index;
22133 + /** Descriptor for Data In or Status In phases */
22134 + uint32_t dma_in_desc_addr;
22135 + dwc_otg_dma_desc_t* in_desc_addr;;
22137 + /** Descriptor for Data Out or Status Out phases */
22138 + uint32_t dma_out_desc_addr;
22139 + dwc_otg_dma_desc_t* out_desc_addr;
22140 +} dwc_otg_dev_if_t;
22145 +/////////////////////////////////////////////////
22146 +// Host Mode Register Structures
22149 + * The Host Global Registers structure defines the size and relative
22150 + * field offsets for the Host Mode Global Registers. Host Global
22151 + * Registers offsets 400h-7FFh.
22153 +typedef struct dwc_otg_host_global_regs
22155 + /** Host Configuration Register. <i>Offset: 400h</i> */
22156 + volatile uint32_t hcfg;
22157 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
22158 + volatile uint32_t hfir;
22159 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
22160 + volatile uint32_t hfnum;
22161 + /** Reserved. <i>Offset: 40Ch</i> */
22162 + uint32_t reserved40C;
22163 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
22164 + volatile uint32_t hptxsts;
22165 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
22166 + volatile uint32_t haint;
22167 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
22168 + volatile uint32_t haintmsk;
22169 +} dwc_otg_host_global_regs_t;
22172 + * This union represents the bit fields in the Host Configuration Register.
22173 + * Read the register into the <i>d32</i> member then set/clear the bits using
22174 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
22176 +typedef union hcfg_data
22178 + /** raw register data */
22181 + /** register bits */
22184 + /** FS/LS Phy Clock Select */
22185 + unsigned fslspclksel : 2;
22186 +#define DWC_HCFG_30_60_MHZ 0
22187 +#define DWC_HCFG_48_MHZ 1
22188 +#define DWC_HCFG_6_MHZ 2
22190 + /** FS/LS Only Support */
22191 + unsigned fslssupp : 1;
22196 + * This union represents the bit fields in the Host Frame Remaing/Number
22199 +typedef union hfir_data
22201 + /** raw register data */
22204 + /** register bits */
22207 + unsigned frint : 16;
22208 + unsigned reserved : 16;
22213 + * This union represents the bit fields in the Host Frame Remaing/Number
22216 +typedef union hfnum_data
22218 + /** raw register data */
22221 + /** register bits */
22224 + unsigned frnum : 16;
22225 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
22226 + unsigned frrem : 16;
22230 +typedef union hptxsts_data
22232 + /** raw register data */
22235 + /** register bits */
22238 + unsigned ptxfspcavail : 16;
22239 + unsigned ptxqspcavail : 8;
22240 + /** Top of the Periodic Transmit Request Queue
22241 + * - bit 24 - Terminate (last entry for the selected channel)
22242 + * - bits 26:25 - Token Type
22243 + * - 2'b00 - Zero length
22245 + * - 2'b10 - Disable
22246 + * - bits 30:27 - Channel Number
22247 + * - bit 31 - Odd/even microframe
22249 + unsigned ptxqtop_terminate : 1;
22250 + unsigned ptxqtop_token : 2;
22251 + unsigned ptxqtop_chnum : 4;
22252 + unsigned ptxqtop_odd : 1;
22257 + * This union represents the bit fields in the Host Port Control and Status
22258 + * Register. Read the register into the <i>d32</i> member then set/clear the
22259 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22260 + * hprt0 register.
22262 +typedef union hprt0_data
22264 + /** raw register data */
22266 + /** register bits */
22269 + unsigned prtconnsts : 1;
22270 + unsigned prtconndet : 1;
22271 + unsigned prtena : 1;
22272 + unsigned prtenchng : 1;
22273 + unsigned prtovrcurract : 1;
22274 + unsigned prtovrcurrchng : 1;
22275 + unsigned prtres : 1;
22276 + unsigned prtsusp : 1;
22277 + unsigned prtrst : 1;
22278 + unsigned reserved9 : 1;
22279 + unsigned prtlnsts : 2;
22280 + unsigned prtpwr : 1;
22281 + unsigned prttstctl : 4;
22282 + unsigned prtspd : 2;
22283 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
22284 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
22285 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
22286 + unsigned reserved19_31 : 13;
22291 + * This union represents the bit fields in the Host All Interrupt
22294 +typedef union haint_data
22296 + /** raw register data */
22298 + /** register bits */
22301 + unsigned ch0 : 1;
22302 + unsigned ch1 : 1;
22303 + unsigned ch2 : 1;
22304 + unsigned ch3 : 1;
22305 + unsigned ch4 : 1;
22306 + unsigned ch5 : 1;
22307 + unsigned ch6 : 1;
22308 + unsigned ch7 : 1;
22309 + unsigned ch8 : 1;
22310 + unsigned ch9 : 1;
22311 + unsigned ch10 : 1;
22312 + unsigned ch11 : 1;
22313 + unsigned ch12 : 1;
22314 + unsigned ch13 : 1;
22315 + unsigned ch14 : 1;
22316 + unsigned ch15 : 1;
22317 + unsigned reserved : 16;
22322 + unsigned chint : 16;
22323 + unsigned reserved : 16;
22328 + * This union represents the bit fields in the Host All Interrupt
22331 +typedef union haintmsk_data
22333 + /** raw register data */
22335 + /** register bits */
22338 + unsigned ch0 : 1;
22339 + unsigned ch1 : 1;
22340 + unsigned ch2 : 1;
22341 + unsigned ch3 : 1;
22342 + unsigned ch4 : 1;
22343 + unsigned ch5 : 1;
22344 + unsigned ch6 : 1;
22345 + unsigned ch7 : 1;
22346 + unsigned ch8 : 1;
22347 + unsigned ch9 : 1;
22348 + unsigned ch10 : 1;
22349 + unsigned ch11 : 1;
22350 + unsigned ch12 : 1;
22351 + unsigned ch13 : 1;
22352 + unsigned ch14 : 1;
22353 + unsigned ch15 : 1;
22354 + unsigned reserved : 16;
22359 + unsigned chint : 16;
22360 + unsigned reserved : 16;
22362 +} haintmsk_data_t;
22365 + * Host Channel Specific Registers. <i>500h-5FCh</i>
22367 +typedef struct dwc_otg_hc_regs
22369 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
22370 + volatile uint32_t hcchar;
22371 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
22372 + volatile uint32_t hcsplt;
22373 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
22374 + volatile uint32_t hcint;
22375 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
22376 + volatile uint32_t hcintmsk;
22377 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
22378 + volatile uint32_t hctsiz;
22379 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
22380 + volatile uint32_t hcdma;
22381 + /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
22382 + uint32_t reserved[2];
22383 +} dwc_otg_hc_regs_t;
22386 + * This union represents the bit fields in the Host Channel Characteristics
22387 + * Register. Read the register into the <i>d32</i> member then set/clear the
22388 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22389 + * hcchar register.
22391 +typedef union hcchar_data
22393 + /** raw register data */
22396 + /** register bits */
22399 + /** Maximum packet size in bytes */
22400 + unsigned mps : 11;
22402 + /** Endpoint number */
22403 + unsigned epnum : 4;
22405 + /** 0: OUT, 1: IN */
22406 + unsigned epdir : 1;
22408 + unsigned reserved : 1;
22410 + /** 0: Full/high speed device, 1: Low speed device */
22411 + unsigned lspddev : 1;
22413 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
22414 + unsigned eptype : 2;
22416 + /** Packets per frame for periodic transfers. 0 is reserved. */
22417 + unsigned multicnt : 2;
22419 + /** Device address */
22420 + unsigned devaddr : 7;
22423 + * Frame to transmit periodic transaction.
22424 + * 0: even, 1: odd
22426 + unsigned oddfrm : 1;
22428 + /** Channel disable */
22429 + unsigned chdis : 1;
22431 + /** Channel enable */
22432 + unsigned chen : 1;
22436 +typedef union hcsplt_data
22438 + /** raw register data */
22441 + /** register bits */
22444 + /** Port Address */
22445 + unsigned prtaddr : 7;
22447 + /** Hub Address */
22448 + unsigned hubaddr : 7;
22450 + /** Transaction Position */
22451 + unsigned xactpos : 2;
22452 +#define DWC_HCSPLIT_XACTPOS_MID 0
22453 +#define DWC_HCSPLIT_XACTPOS_END 1
22454 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
22455 +#define DWC_HCSPLIT_XACTPOS_ALL 3
22457 + /** Do Complete Split */
22458 + unsigned compsplt : 1;
22461 + unsigned reserved : 14;
22463 + /** Split Enble */
22464 + unsigned spltena : 1;
22470 + * This union represents the bit fields in the Host All Interrupt
22473 +typedef union hcint_data
22475 + /** raw register data */
22477 + /** register bits */
22480 + /** Transfer Complete */
22481 + unsigned xfercomp : 1;
22482 + /** Channel Halted */
22483 + unsigned chhltd : 1;
22485 + unsigned ahberr : 1;
22486 + /** STALL Response Received */
22487 + unsigned stall : 1;
22488 + /** NAK Response Received */
22489 + unsigned nak : 1;
22490 + /** ACK Response Received */
22491 + unsigned ack : 1;
22492 + /** NYET Response Received */
22493 + unsigned nyet : 1;
22494 + /** Transaction Err */
22495 + unsigned xacterr : 1;
22496 + /** Babble Error */
22497 + unsigned bblerr : 1;
22498 + /** Frame Overrun */
22499 + unsigned frmovrun : 1;
22500 + /** Data Toggle Error */
22501 + unsigned datatglerr : 1;
22503 + unsigned reserved : 21;
22508 + * This union represents the bit fields in the Host Channel Transfer Size
22509 + * Register. Read the register into the <i>d32</i> member then set/clear the
22510 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22511 + * hcchar register.
22513 +typedef union hctsiz_data
22515 + /** raw register data */
22518 + /** register bits */
22521 + /** Total transfer size in bytes */
22522 + unsigned xfersize : 19;
22524 + /** Data packets to transfer */
22525 + unsigned pktcnt : 10;
22528 + * Packet ID for next data packet
22532 + * 3: MDATA (non-Control), SETUP (Control)
22534 + unsigned pid : 2;
22535 +#define DWC_HCTSIZ_DATA0 0
22536 +#define DWC_HCTSIZ_DATA1 2
22537 +#define DWC_HCTSIZ_DATA2 1
22538 +#define DWC_HCTSIZ_MDATA 3
22539 +#define DWC_HCTSIZ_SETUP 3
22541 + /** Do PING protocol when 1 */
22542 + unsigned dopng : 1;
22547 + * This union represents the bit fields in the Host Channel Interrupt Mask
22548 + * Register. Read the register into the <i>d32</i> member then set/clear the
22549 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22550 + * hcintmsk register.
22552 +typedef union hcintmsk_data
22554 + /** raw register data */
22557 + /** register bits */
22560 + unsigned xfercompl : 1;
22561 + unsigned chhltd : 1;
22562 + unsigned ahberr : 1;
22563 + unsigned stall : 1;
22564 + unsigned nak : 1;
22565 + unsigned ack : 1;
22566 + unsigned nyet : 1;
22567 + unsigned xacterr : 1;
22568 + unsigned bblerr : 1;
22569 + unsigned frmovrun : 1;
22570 + unsigned datatglerr : 1;
22571 + unsigned reserved : 21;
22573 +} hcintmsk_data_t;
22575 +/** OTG Host Interface Structure.
22577 + * The OTG Host Interface Structure structure contains information
22578 + * needed to manage the DWC_otg controller acting in host mode. It
22579 + * represents the programming view of the host-specific aspects of the
22582 +typedef struct dwc_otg_host_if
22584 + /** Host Global Registers starting at offset 400h.*/
22585 + dwc_otg_host_global_regs_t *host_global_regs;
22586 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
22588 + /** Host Port 0 Control and Status Register */
22589 + volatile uint32_t *hprt0;
22590 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
22592 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
22593 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
22594 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
22595 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
22598 + /* Host configuration information */
22599 + /** Number of Host Channels (range: 1-16) */
22600 + uint8_t num_host_channels;
22601 + /** Periodic EPs supported (0: no, 1: yes) */
22602 + uint8_t perio_eps_supported;
22603 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
22604 + uint16_t perio_tx_fifo_size;
22605 +} dwc_otg_host_if_t;
22609 + * This union represents the bit fields in the Power and Clock Gating Control
22610 + * Register. Read the register into the <i>d32</i> member then set/clear the
22611 + * bits using the <i>b</i>it elements.
22613 +typedef union pcgcctl_data
22615 + /** raw register data */
22618 + /** register bits */
22622 + unsigned stoppclk : 1;
22624 + unsigned gatehclk : 1;
22625 + /** Power Clamp */
22626 + unsigned pwrclmp : 1;
22627 + /** Reset Power Down Modules */
22628 + unsigned rstpdwnmodule : 1;
22629 + /** PHY Suspended */
22630 + unsigned physuspended : 1;
22631 + unsigned reserved : 27;
22637 --- a/drivers/usb/core/urb.c
22638 +++ b/drivers/usb/core/urb.c
22639 @@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre
22641 if (urb->transfer_flags & URB_FREE_BUFFER)
22642 kfree(urb->transfer_buffer);
22644 + if (urb->aligned_transfer_buffer) {
22645 + kfree(urb->aligned_transfer_buffer);
22646 + urb->aligned_transfer_buffer = 0;
22647 + urb->aligned_transfer_dma = 0;
22652 --- a/include/linux/usb.h
22653 +++ b/include/linux/usb.h
22654 @@ -1234,6 +1234,9 @@ struct urb {
22655 unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/
22656 void *transfer_buffer; /* (in) associated data buffer */
22657 dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */
22658 + void *aligned_transfer_buffer; /* (in) associeated data buffer */
22659 + dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */
22660 + u32 aligned_transfer_buffer_length; /* (in) data buffer length */
22661 struct scatterlist *sg; /* (in) scatter gather buffer list */
22662 int num_mapped_sgs; /* (internal) mapped sg entries */
22663 int num_sgs; /* (in) number of entries in the sg list */
22664 --- a/drivers/usb/gadget/Kconfig
22665 +++ b/drivers/usb/gadget/Kconfig
22666 @@ -125,6 +125,7 @@ config USB_GADGET_STORAGE_NUM_BUFFERS
22669 prompt "USB Peripheral Controller"
22670 + depends on !USB_DWC_OTG
22672 A USB device uses a controller to talk to its host.
22673 Systems should have only one such upstream link.
22674 @@ -616,7 +617,7 @@ config USB_ETH
22676 This driver implements Ethernet style communication, in one of
22680 - The "Communication Device Class" (CDC) Ethernet Control Model.
22681 That protocol is often avoided with pure Ethernet adapters, in
22682 favor of simpler vendor-specific hardware, but is widely
22683 @@ -656,7 +657,7 @@ config USB_ETH_RNDIS
22684 If you say "y" here, the Ethernet gadget driver will try to provide
22685 a second device configuration, supporting RNDIS to talk to such
22686 Microsoft USB hosts.
22689 To make MS-Windows work with this, use Documentation/usb/linux.inf
22690 as the "driver info file". For versions of MS-Windows older than
22691 XP, you'll need to download drivers from Microsoft's website; a URL
22692 --- a/drivers/usb/gadget/Makefile
22693 +++ b/drivers/usb/gadget/Makefile
22696 ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG
22698 -obj-$(CONFIG_USB_GADGET) += udc-core.o
22699 +#obj-$(CONFIG_USB_GADGET) += udc-core.o
22700 obj-$(CONFIG_USB_DUMMY_HCD) += dummy_hcd.o
22701 obj-$(CONFIG_USB_NET2272) += net2272.o
22702 obj-$(CONFIG_USB_NET2280) += net2280.o