target/linux/cns3xxx/patches-2.6.31/203-cns3xxx_i2c_support.patch

   1 --- /dev/null
   2 +++ b/drivers/i2c/busses/i2c-cns3xxx.c
   3 @@ -0,0 +1,388 @@
   4 +#include <linux/kernel.h>
   5 +#include <linux/module.h>
   6 +#include <linux/init.h>
   7 +#include <linux/platform_device.h>
   8 +#include <asm/io.h>
   9 +#include <linux/wait.h>
  10 +#include <linux/interrupt.h>
  11 +#include <linux/delay.h>
  12 +#include <linux/i2c.h>
  13 +#include <mach/pm.h>
  14 +
  15 +/*
  16 + * We need the memory map
  17 + */
  18 +
  19 +#include <mach/board.h>
  20 +
  21 +#define MISC_MEM_MAP_VALUE(reg_offset) (*((uint32_t volatile *)(CNS3XXX_MISC_BASE_VIRT + reg_offset)))
  22 +#define MISC_IOCDB_CTRL                                MISC_MEM_MAP_VALUE(0x020)
  23 +
  24 +#define I2C_MEM_MAP_ADDR(x)         (CNS3XXX_SSP_BASE_VIRT + x)
  25 +#define I2C_MEM_MAP_VALUE(x)        (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
  26 +
  27 +#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x20)
  28 +#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x24)
  29 +#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x28)
  30 +#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x2C)
  31 +#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x30)
  32 +#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x34)
  33 +#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x38)
  34 +#define I2C_TWI_OUT_DLY_REG                                                    I2C_MEM_MAP_VALUE(0x3C)
  35 +
  36 +#define I2C_BUS_ERROR_FLAG     (0x1)
  37 +#define I2C_ACTION_DONE_FLAG   (0x2)
  38 +
  39 +#define CNS3xxx_I2C_ENABLE()          (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31)
  40 +#define CNS3xxx_I2C_DISABLE()         (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31)
  41 +#define CNS3xxx_I2C_ENABLE_INTR()     (I2C_INTERRUPT_ENABLE_REG) |= 0x03
  42 +#define CNS3xxx_I2C_DISABLE_INTR()    (I2C_INTERRUPT_ENABLE_REG) &= 0xfc
  43 +
  44 +#define TWI_TIMEOUT         (10*HZ)
  45 +#define I2C_100KHZ          100000
  46 +#define I2C_200KHZ          200000
  47 +#define I2C_300KHZ          300000
  48 +#define I2C_400KHZ          400000
  49 +
  50 +#define CNS3xxx_I2C_CLK     I2C_100KHZ
  51 +
  52 +#define STATE_DONE             1
  53 +#define STATE_ERROR            2
  54 +
  55 +struct cns3xxx_i2c {
  56 +       void __iomem *base;
  57 +       wait_queue_head_t wait;
  58 +       struct i2c_adapter adap;
  59 +       struct i2c_msg *msg;
  60 +       int state;              /* see STATE_ */
  61 +       int rd_wr_len;
  62 +       u8 *buf;
  63 +};
  64 +
  65 +static u32 cns3xxx_i2c_func(struct i2c_adapter *adap)
  66 +{
  67 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  68 +}
  69 +
  70 +static int
  71 +cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg)
  72 +{
  73 +       struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap);
  74 +       int i, j;
  75 +       u8 buf[1] = { 0 };
  76 +
  77 +       if (msg->len == 0) {
  78 +               /*
  79 +                *      We are probably doing a probe for a device here,
  80 +                *      so set the length to one, and data to 0
  81 +                */
  82 +               msg->len = 1;
  83 +               i2c->buf = buf;
  84 +       } else {
  85 +               i2c->buf = msg->buf;
  86 +       }
  87 +
  88 +       if (msg->flags & I2C_M_TEN) {
  89 +               printk
  90 +                       ("%s:%d: Presently the driver does not handle extended addressing\n",
  91 +                               __FUNCTION__, __LINE__);
  92 +               return -EINVAL;
  93 +       }
  94 +       i2c->msg = msg;
  95 +
  96 +       for (i = 0; i < msg->len; i++) {
  97 +               if (msg->len - i >= 4)
  98 +                       i2c->rd_wr_len = 3;
  99 +               else
 100 +                       i2c->rd_wr_len = msg->len - i - 1;
 101 +
 102 +               // Set Data Width       and TWI_EN
 103 +               I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
 104 +
 105 +               // Clear Write Reg
 106 +               I2C_WRITE_DATA_REG = 0;
 107 +
 108 +               // Set the slave address
 109 +               I2C_SLAVE_ADDRESS_REG = (msg->addr << 1);
 110 +
 111 +               // Are we Writing
 112 +               if (!(msg->flags & I2C_M_RD)) {
 113 +                       I2C_CONTROLLER_REG |= (1 << 4);
 114 +                       if (i != 0) {
 115 +                               /*
 116 +                                * We need to set the address in the first byte.
 117 +                                * The base address is going to be in buf[0] and then
 118 +                                * it needs to be incremented by i - 1.
 119 +                                */
 120 +                               i2c->buf--;
 121 +                               *i2c->buf = buf[0] + i - 1;
 122 +
 123 +                               if (i2c->rd_wr_len < 3) {
 124 +                                       i += i2c->rd_wr_len;
 125 +                                       i2c->rd_wr_len++;
 126 +                                       I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
 127 +                               } else {
 128 +                                       i += i2c->rd_wr_len - 1;
 129 +                               }
 130 +                       } else {
 131 +                               i += i2c->rd_wr_len;
 132 +                               buf[0] = *i2c->buf;
 133 +                       }
 134 +                       for (j = 0; j <= i2c->rd_wr_len; j++) {
 135 +                               I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j));
 136 +                       }
 137 +               } else {
 138 +                       i += i2c->rd_wr_len;
 139 +               }
 140 +
 141 +               // Start the Transfer
 142 +               i2c->state = 0;         // Clear out the State
 143 +               I2C_CONTROLLER_REG |= (1 << 6);
 144 +
 145 +               if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 146 +                               (i2c->state == STATE_DONE), TWI_TIMEOUT)) {
 147 +                       if (i2c->state == STATE_ERROR) {
 148 +                               return -EIO;
 149 +                       }
 150 +               } else {
 151 +                       return -ETIMEDOUT;
 152 +               }
 153 +       }
 154 +       return 0;
 155 +}
 156 +
 157 +static int
 158 +cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 159 +{
 160 +       int i;
 161 +       int ret;
 162 +       for (i = 0; i < num; i++)
 163 +       {
 164 +               ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]);
 165 +               if (ret < 0) {
 166 +                       return ret;
 167 +               }
 168 +       }
 169 +       return num;
 170 +}
 171 +
 172 +
 173 +static struct i2c_algorithm cns3xxx_i2c_algo = {
 174 +       .master_xfer = cns3xxx_i2c_xfer,
 175 +       .functionality = cns3xxx_i2c_func,
 176 +};
 177 +
 178 +static struct i2c_adapter cns3xxx_i2c_adapter = {
 179 +       .owner = THIS_MODULE,
 180 +       .algo = &cns3xxx_i2c_algo,
 181 +       .algo_data = NULL,
 182 +       .nr = 0,
 183 +       .name = "CNS3xxx I2C 0",
 184 +       .retries = 5,
 185 +};
 186 +
 187 +static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
 188 +{
 189 +
 190 +       /* Steps
 191 +        * 1. Check if the power is enabled to the module (PMU_BASE + 0x010)
 192 +        * 2. Enable the clock (Enabled by default (PMU doc
 193 +        *    but check clk status anyway PMU_BASE + 0X00C)
 194 +        * 3. Configure the registers of i2c
 195 +        */
 196 +
 197 +       //   if (!CNS3xxx_I2C_POWER_ON())
 198 +//        CNS3xxx_I2C_POWER_ENABLE();
 199 +
 200 +       //  if (!CNS3xxx_I2C_CLOCK())
 201 +       //      CNS3xxx_I2C_CLOCK_ENABLE();
 202 +
 203 +        cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
 204 +        cns3xxx_pwr_power_up(0x1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
 205 +        cns3xxx_pwr_soft_rst(0x1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
 206 +
 207 +       /* Disable the I2C */
 208 +       I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
 209 +
 210 +       //enable SCL and SDA which share pin with GPIOB_PIN_EN(0x18)
 211 +       //GPIOB[12]: SCL
 212 +       //GPIOB[13]: SDA
 213 +       (*(u32*)(CNS3XXX_MISC_BASE_VIRT+0x18)) |= ((1<<12)|(1<<13));
 214 +
 215 +       MISC_IOCDB_CTRL &= ~0x300;
 216 +       MISC_IOCDB_CTRL |= 0x300; //21mA...
 217 +
 218 +       /* Check the Reg Dump when testing */
 219 +       I2C_TIME_OUT_REG =
 220 +           ((((((cns3xxx_cpu_clock()*(1000000/8)) / (2 * CNS3xxx_I2C_CLK)) -
 221 +               1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
 222 +       I2C_TWI_OUT_DLY_REG |= 0x3;
 223 +
 224 +       /* Enable The Interrupt */
 225 +       CNS3xxx_I2C_ENABLE_INTR();
 226 +
 227 +       /* Clear Interrupt Status (0x2 | 0x1) */
 228 +       I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
 229 +
 230 +       /* Enable the I2C Controller */
 231 +       CNS3xxx_I2C_ENABLE();
 232 +}
 233 +
 234 +static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id)
 235 +{
 236 +       struct cns3xxx_i2c *i2c = dev_id;
 237 +       int i;
 238 +       uint32_t stat = I2C_INTERRUPT_STATUS_REG;
 239 +
 240 +       /* Clear Interrupt */
 241 +       I2C_INTERRUPT_STATUS_REG |= 0x1;
 242 +
 243 +       if (stat & I2C_BUS_ERROR_FLAG) {
 244 +               i2c->state = STATE_ERROR;
 245 +       } else {
 246 +               if (i2c->msg->flags & I2C_M_RD) {
 247 +                       for (i = 0; i <= i2c->rd_wr_len; i++)
 248 +                       {
 249 +                               *i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff);
 250 +                       }
 251 +               }
 252 +               i2c->state = STATE_DONE;
 253 +       }
 254 +       wake_up(&i2c->wait);
 255 +       return IRQ_HANDLED;
 256 +}
 257 +
 258 +static int __devinit cns3xxx_i2c_probe(struct platform_device *pdev)
 259 +{
 260 +       struct cns3xxx_i2c *i2c;
 261 +       struct resource *res, *res2;
 262 +       int ret;
 263 +
 264 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265 +       if (!res) {
 266 +               printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__);
 267 +               return -ENODEV;
 268 +       }
 269 +
 270 +       res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 271 +       if (!res2) {
 272 +               printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__);
 273 +               return -ENODEV;
 274 +       }
 275 +
 276 +       i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 277 +       if (!i2c)
 278 +               return -ENOMEM;
 279 +
 280 +       if (!request_mem_region(res->start, res->end - res->start + 1,
 281 +                               pdev->name)) {
 282 +               dev_err(&pdev->dev, "Memory region busy\n");
 283 +               ret = -EBUSY;
 284 +               goto request_mem_failed;
 285 +       }
 286 +
 287 +       i2c->base = ioremap(res->start, res->end - res->start + 1);
 288 +       if (!i2c->base) {
 289 +               dev_err(&pdev->dev, "Unable to map registers\n");
 290 +               ret = -EIO;
 291 +               goto map_failed;
 292 +       }
 293 +
 294 +       cns3xxx_i2c_adapter_init(i2c);
 295 +
 296 +       init_waitqueue_head(&i2c->wait);
 297 +       ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c);
 298 +       if (ret) {
 299 +               dev_err(&pdev->dev, "Cannot claim IRQ\n");
 300 +               goto request_irq_failed;
 301 +       }
 302 +
 303 +       platform_set_drvdata(pdev, i2c);
 304 +       i2c->adap = cns3xxx_i2c_adapter;
 305 +       i2c_set_adapdata(&i2c->adap, i2c);
 306 +       i2c->adap.dev.parent = &pdev->dev;
 307 +
 308 +       /* add i2c adapter to i2c tree */
 309 +       ret = i2c_add_numbered_adapter(&i2c->adap);
 310 +       if (ret) {
 311 +               dev_err(&pdev->dev, "Failed to add adapter\n");
 312 +               goto add_adapter_failed;
 313 +       }
 314 +
 315 +       return 0;
 316 +
 317 +      add_adapter_failed:
 318 +       free_irq(res2->start, i2c);
 319 +      request_irq_failed:
 320 +       iounmap(i2c->base);
 321 +      map_failed:
 322 +       release_mem_region(res->start, res->end - res->start + 1);
 323 +      request_mem_failed:
 324 +       kfree(i2c);
 325 +
 326 +       return ret;
 327 +}
 328 +
 329 +static int __devexit cns3xxx_i2c_remove(struct platform_device *pdev)
 330 +{
 331 +       struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev);
 332 +       struct resource *res;
 333 +
 334 +       /* disable i2c logic */
 335 +       CNS3xxx_I2C_DISABLE_INTR();
 336 +       CNS3xxx_I2C_DISABLE();
 337 +       /* remove adapter & data */
 338 +       i2c_del_adapter(&i2c->adap);
 339 +       platform_set_drvdata(pdev, NULL);
 340 +
 341 +       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 342 +       if (res)
 343 +               free_irq(res->start, i2c);
 344 +
 345 +       iounmap(i2c->base);
 346 +
 347 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 348 +       if (res)
 349 +               release_mem_region(res->start, res->end - res->start + 1);
 350 +
 351 +       kfree(i2c);
 352 +
 353 +       return 0;
 354 +}
 355 +
 356 +#ifdef CONFIG_PM
 357 +#warning "CONFIG_PM defined: suspend and resume not implemented"
 358 +#define cns3xxx_i2c_suspend    NULL
 359 +#define cns3xxx_i2c_resume     NULL
 360 +#else
 361 +#define cns3xxx_i2c_suspend    NULL
 362 +#define cns3xxx_i2c_resume     NULL
 363 +#endif
 364 +
 365 +static struct platform_driver cns3xxx_i2c_driver = {
 366 +       .probe = cns3xxx_i2c_probe,
 367 +       .remove = cns3xxx_i2c_remove,
 368 +       .suspend = cns3xxx_i2c_suspend,
 369 +       .resume = cns3xxx_i2c_resume,
 370 +       .driver = {
 371 +                  .owner = THIS_MODULE,
 372 +                  .name = "cns3xxx-i2c",
 373 +                  },
 374 +};
 375 +
 376 +static int __init cns3xxx_i2c_init(void)
 377 +{
 378 +       return platform_driver_register(&cns3xxx_i2c_driver);
 379 +}
 380 +
 381 +static void __exit cns3xxx_i2c_exit(void)
 382 +{
 383 +       platform_driver_unregister(&cns3xxx_i2c_driver);
 384 +}
 385 +
 386 +module_init(cns3xxx_i2c_init);
 387 +module_exit(cns3xxx_i2c_exit);
 388 +
 389 +MODULE_AUTHOR("Cavium Networks");
 390 +MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller");
 391 +MODULE_LICENSE("GPL");
 392 --- a/drivers/i2c/busses/Kconfig
 393 +++ b/drivers/i2c/busses/Kconfig
 394 @@ -422,6 +422,12 @@ config I2C_MV64XXX
 395           This driver can also be built as a module.  If so, the module
 396           will be called i2c-mv64xxx.
 397
 398 +config I2C_CNS3XXX
 399 +       tristate "Cavium Networks CNS3XXX I2C Controller"
 400 +       depends on ARCH_CNS3XXX
 401 +       help
 402 +         Supports the Cavium Networks CNS3XXX on-chip I2C interfaces
 403 +
 404  config I2C_OCORES
 405         tristate "OpenCores I2C Controller"
 406         depends on EXPERIMENTAL
 407 --- a/drivers/i2c/busses/Makefile
 408 +++ b/drivers/i2c/busses/Makefile
 409 @@ -39,6 +39,7 @@ obj-$(CONFIG_I2C_IOP3XX)      += i2c-iop3xx.o
 410  obj-$(CONFIG_I2C_IXP2000)      += i2c-ixp2000.o
 411  obj-$(CONFIG_I2C_MPC)          += i2c-mpc.o
 412  obj-$(CONFIG_I2C_MV64XXX)      += i2c-mv64xxx.o
 413 +obj-$(CONFIG_I2C_CNS3XXX)      += i2c-cns3xxx.o
 414  obj-$(CONFIG_I2C_OCORES)       += i2c-ocores.o
 415  obj-$(CONFIG_I2C_OMAP)         += i2c-omap.o
 416  obj-$(CONFIG_I2C_PASEMI)       += i2c-pasemi.o