1 /*******************************************************************************
3 * CNS3XXX SPI controller driver (master mode only)
5 * Copyright (c) 2008 Cavium Networks
6 * Copyright 2011 Gateworks Corporation
7 * Chris Lang <clang@gateworks.com>
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful,
14 * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this file; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
21 * visit http://www.gnu.org/licenses/.
23 * This file may also be available under a different license from Cavium.
24 * Contact Cavium Networks for more information
26 ******************************************************************************/
28 #include <linux/init.h>
29 #include <linux/spinlock.h>
30 #include <linux/workqueue.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/platform_device.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/spi_bitbang.h>
40 #include <linux/mtd/partitions.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
45 #include <asm/memory.h>
47 #include <asm/delay.h>
48 #include <mach/cns3xxx.h>
49 #include <linux/module.h>
53 * define access macros
55 #define SPI_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)(CNS3XXX_SSP_BASE_VIRT + reg_offset)))
57 #define SPI_CONFIGURATION_REG SPI_MEM_MAP_VALUE(0x40)
58 #define SPI_SERVICE_STATUS_REG SPI_MEM_MAP_VALUE(0x44)
59 #define SPI_BIT_RATE_CONTROL_REG SPI_MEM_MAP_VALUE(0x48)
60 #define SPI_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x4C)
61 #define SPI_TRANSMIT_BUFFER_REG SPI_MEM_MAP_VALUE(0x50)
62 #define SPI_RECEIVE_CONTROL_REG SPI_MEM_MAP_VALUE(0x54)
63 #define SPI_RECEIVE_BUFFER_REG SPI_MEM_MAP_VALUE(0x58)
64 #define SPI_FIFO_TRANSMIT_CONFIG_REG SPI_MEM_MAP_VALUE(0x5C)
65 #define SPI_FIFO_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x60)
66 #define SPI_FIFO_RECEIVE_CONFIG_REG SPI_MEM_MAP_VALUE(0x64)
67 #define SPI_INTERRUPT_STATUS_REG SPI_MEM_MAP_VALUE(0x68)
68 #define SPI_INTERRUPT_ENABLE_REG SPI_MEM_MAP_VALUE(0x6C)
70 #define SPI_TRANSMIT_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x50)
71 #define SPI_RECEIVE_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x58)
73 /* Structure for SPI controller of CNS3XXX SOCs */
75 /* bitbang has to be first */
76 struct spi_bitbang bitbang;
77 struct completion done;
78 wait_queue_head_t wait;
82 int last_in_message_list;
85 const unsigned char *tx;
88 struct spi_master *master;
89 struct platform_device *pdev;
93 static inline u8 cns3xxx_spi_bus_idle(void)
95 return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
98 static inline u8 cns3xxx_spi_tx_buffer_empty(void)
100 return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
103 static inline u8 cns3xxx_spi_rx_buffer_full(void)
105 return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
108 u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
114 while (!cns3xxx_spi_bus_idle()) ; // do nothing
116 while (!cns3xxx_spi_tx_buffer_empty()) ; // do nothing
118 SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
119 SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
121 SPI_TRANSMIT_BUFFER_REG = tx_data;
123 while (!cns3xxx_spi_rx_buffer_full()) ; // do nothing
125 rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
126 rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
128 *rx_data = SPI_RECEIVE_BUFFER_REG;
130 if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) {
137 u8 cns3xxx_spi_tx(u8 tx_channel, u8 tx_eof, u32 tx_data)
140 while (!cns3xxx_spi_bus_idle()) ; // do nothing
142 while (!cns3xxx_spi_tx_buffer_empty()) ; // do nothing
144 SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
145 SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
147 SPI_TRANSMIT_BUFFER_REG = tx_data;
152 static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev)
154 return spi_master_get_devdata(sdev->master);
157 static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
158 struct spi_transfer *t)
163 static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
165 unsigned int spi_config;
168 case BITBANG_CS_INACTIVE:
171 case BITBANG_CS_ACTIVE:
172 spi_config = SPI_CONFIGURATION_REG;
174 if (spi->mode & SPI_CPHA)
175 spi_config |= (0x1 << 13);
177 spi_config &= ~(0x1 << 13);
179 if (spi->mode & SPI_CPOL)
180 spi_config |= (0x1 << 14);
182 spi_config &= ~(0x1 << 14);
184 /* write new configration */
185 SPI_CONFIGURATION_REG = spi_config;
187 SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
188 SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3);
194 static int cns3xxx_spi_setup(struct spi_device *spi)
196 if (!spi->bits_per_word)
197 spi->bits_per_word = 8;
202 static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
204 struct cns3xxx_spi *hw = to_hw(spi);
206 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf,
213 hw->last_in_message_list = t->last_in_message_list;
215 init_completion(&hw->done);
220 for (i = 0; i < (hw->len - 1); i++) {
222 "[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
224 cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
229 "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
234 if (t->last_in_message_list) {
235 cns3xxx_spi_tx_rx(spi->chip_select, 1, hw->tx[i],
240 "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
244 cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
253 for (i = 0; i < (hw->len - 1); i++) {
254 cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
257 "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
261 if (t->last_in_message_list) {
262 cns3xxx_spi_tx_rx(spi->chip_select, 1, 0xff, &rx_data);
264 cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
267 dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
274 static void __init cns3xxx_spi_initial(void)
276 u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
277 u32 gpiob_pins = __raw_readl(gpiob);
279 /* MMC/SD pins share with GPIOA */
281 __raw_writel(gpiob_pins, gpiob);
283 /* share pin config. */
284 //PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
285 //HAL_MISC_ENABLE_SPI_PINS();
286 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
287 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
289 SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */
290 (0x0 << 9) | /* SPI mode */
291 (0x0 << 10) | /* disable FIFO */
292 (0x1 << 11) | /* SPI master mode */
293 (0x0 << 12) | /* disable SPI loopback mode */
294 (0x1 << 13) | /* clock phase */
295 (0x1 << 14) | /* clock polarity */
296 (0x0 << 24) | /* disable - SPI data swap */
297 (0x1 << 29) | /* enable - 2IO Read mode */
298 (0x0 << 30) | /* disable - SPI high speed read for system boot up */
299 (0x0 << 31)); /* disable - SPI */
301 /* Set SPI bit rate PCLK/2 */
302 SPI_BIT_RATE_CONTROL_REG = 0x1;
304 /* Set SPI Tx channel 0 */
305 SPI_TRANSMIT_CONTROL_REG = 0x0;
307 /* Set Tx FIFO Threshold, Tx FIFO has 2 words */
308 SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
309 SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
311 /* Set Rx FIFO Threshold, Rx FIFO has 2 words */
312 SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
313 SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
315 /* Disable all interrupt */
316 SPI_INTERRUPT_ENABLE_REG = 0x0;
318 /* Clear spurious interrupt sources */
319 SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
322 SPI_CONFIGURATION_REG |= (0x1 << 31);
327 static int cns3xxx_spi_probe(struct platform_device *pdev)
329 struct spi_master *master;
330 struct cns3xxx_spi *hw;
333 printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__);
335 /* Allocate master with space for cns3xxx_spi */
336 master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
337 if (master == NULL) {
338 dev_err(&pdev->dev, "No memory for spi_master\n");
343 hw = spi_master_get_devdata(master);
344 memset(hw, 0, sizeof(struct cns3xxx_spi));
346 hw->master = spi_master_get(master);
347 hw->dev = &pdev->dev;
349 platform_set_drvdata(pdev, hw);
350 init_completion(&hw->done);
352 /* setup the master state. */
354 master->num_chipselect = 4;
357 /* setup the state for the bitbang driver */
359 hw->bitbang.master = hw->master;
360 hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer;
361 hw->bitbang.chipselect = cns3xxx_spi_chipselect;
362 hw->bitbang.txrx_bufs = cns3xxx_spi_txrx;
363 hw->bitbang.master->setup = cns3xxx_spi_setup;
365 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
367 /* SPI controller initializations */
368 cns3xxx_spi_initial();
370 /* register SPI controller */
372 err = spi_bitbang_start(&hw->bitbang);
374 dev_err(&pdev->dev, "Failed to register SPI master\n");
381 spi_master_put(hw->master);;
387 static int cns3xxx_spi_remove(struct platform_device *dev)
389 struct cns3xxx_spi *hw = platform_get_drvdata(dev);
391 platform_set_drvdata(dev, NULL);
393 spi_unregister_master(hw->master);
395 spi_master_put(hw->master);
401 static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
403 struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
408 static int cns3xxx_spi_resume(struct platform_device *pdev)
410 struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
416 #define cns3xxx_spi_suspend NULL
417 #define cns3xxx_spi_resume NULL
420 static struct platform_driver cns3xxx_spi_driver = {
421 .probe = cns3xxx_spi_probe,
422 .remove = cns3xxx_spi_remove,
423 .suspend = cns3xxx_spi_suspend,
424 .resume = cns3xxx_spi_resume,
426 .name = "cns3xxx_spi",
427 .owner = THIS_MODULE,
431 static int __init cns3xxx_spi_init(void)
433 return platform_driver_register(&cns3xxx_spi_driver);
436 static void __exit cns3xxx_spi_exit(void)
438 platform_driver_unregister(&cns3xxx_spi_driver);
441 module_init(cns3xxx_spi_init);
442 module_exit(cns3xxx_spi_exit);
444 MODULE_AUTHOR("Cavium Networks");
445 MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver");
446 MODULE_LICENSE("GPL");
447 MODULE_ALIAS("platform:cns3xxx_spi");
449 EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx);