2 * Cavium CNS3xxx Gigabit driver for Linux
4 * Copyright 2011 Gateworks Corporation
5 * Chris Lang <clang@gateworks.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/cns3xxx.h>
24 #include <linux/skbuff.h>
26 #define DRV_NAME "cns3xxx_eth"
30 #define TX_DESC_RESERVE 20
32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
36 #define RX_BUFFER_ALIGN 64
37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
40 #define RX_SEGMENT_ALLOC_SIZE 2048
41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
45 #define NAPI_WEIGHT 64
48 #define MDIO_CMD_COMPLETE 0x00008000
49 #define MDIO_WRITE_COMMAND 0x00002000
50 #define MDIO_READ_COMMAND 0x00004000
51 #define MDIO_REG_OFFSET 8
52 #define MDIO_VALUE_OFFSET 16
54 /* Descritor Defines */
55 #define END_OF_RING 0x40000000
56 #define FIRST_SEGMENT 0x20000000
57 #define LAST_SEGMENT 0x10000000
58 #define FORCE_ROUTE 0x04000000
59 #define IP_CHECKSUM 0x00040000
60 #define UDP_CHECKSUM 0x00020000
61 #define TCP_CHECKSUM 0x00010000
63 /* Port Config Defines */
64 #define PORT_BP_ENABLE 0x00020000
65 #define PORT_DISABLE 0x00040000
66 #define PORT_LEARN_DIS 0x00080000
67 #define PORT_BLOCK_STATE 0x00100000
68 #define PORT_BLOCK_MODE 0x00200000
70 #define PROMISC_OFFSET 29
72 /* Global Config Defines */
73 #define UNKNOWN_VLAN_TO_CPU 0x02000000
74 #define ACCEPT_CRC_PACKET 0x00200000
75 #define CRC_STRIPPING 0x00100000
77 /* VLAN Config Defines */
78 #define NIC_MODE 0x00008000
79 #define VLAN_UNAWARE 0x00000001
81 /* DMA AUTO Poll Defines */
82 #define TS_POLL_EN 0x00000020
83 #define TS_SUSPEND 0x00000010
84 #define FS_POLL_EN 0x00000002
85 #define FS_SUSPEND 0x00000001
87 /* DMA Ring Control Defines */
88 #define QUEUE_THRESHOLD 0x000000f0
89 #define CLR_FS_STATE 0x80000000
91 /* Interrupt Status Defines */
92 #define MAC0_STATUS_CHANGE 0x00004000
93 #define MAC1_STATUS_CHANGE 0x00008000
94 #define MAC2_STATUS_CHANGE 0x00010000
95 #define MAC0_RX_ERROR 0x00100000
96 #define MAC1_RX_ERROR 0x00200000
97 #define MAC2_RX_ERROR 0x00400000
101 u32 sdp; /* segment data pointer */
105 u32 sdl:16; /* segment data length */
109 u32 rsv_1:3; /* reserve */
111 u32 fp:1; /* force priority */
151 u8 alignment[16]; /* for 32 byte */
156 u32 sdp; /* segment data pointer */
160 u32 sdl:16; /* segment data length */
205 u8 alignment[16]; /* for 32 byte alignment */
214 u32 mac_pri_ctrl[5], __res;
236 u32 fc_input_thrs, __res1[2];
238 u32 mac_glob_cfg_ext, __res2[2];
240 u32 dma_auto_poll_cfg;
241 u32 delay_intr_cfg, __res3;
244 u32 ts_desc_base_addr0, __res4;
247 u32 fs_desc_base_addr0, __res5;
250 u32 ts_desc_base_addr1, __res6;
253 u32 fs_desc_base_addr1;
255 u32 mac_counter0[13];
259 struct tx_desc *desc;
260 dma_addr_t phys_addr;
261 struct tx_desc *cur_addr;
262 struct sk_buff *buff_tab[TX_DESCS];
263 unsigned int phys_tab[TX_DESCS];
273 struct rx_desc *desc;
274 dma_addr_t phys_addr;
275 struct rx_desc *cur_addr;
276 void *buff_tab[RX_DESCS];
277 unsigned int phys_tab[RX_DESCS];
284 struct switch_regs __iomem *regs;
285 struct napi_struct napi;
286 struct cns3xxx_plat_info *plat;
287 struct _tx_ring tx_ring;
288 struct _rx_ring rx_ring;
289 struct sk_buff *frag_first;
290 struct sk_buff *frag_last;
296 struct net_device *netdev;
297 struct phy_device *phydev;
299 int id; /* logical port ID */
303 static spinlock_t mdio_lock;
304 static DEFINE_SPINLOCK(tx_lock);
305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
306 struct mii_bus *mdio_bus;
307 static int ports_open;
308 static struct port *switch_port_tab[4];
309 static struct dma_pool *rx_dma_pool;
310 static struct dma_pool *tx_dma_pool;
311 struct net_device *napi_dev;
313 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
319 temp = __raw_readl(&mdio_regs->phy_control);
320 temp |= MDIO_CMD_COMPLETE;
321 __raw_writel(temp, &mdio_regs->phy_control);
325 temp = (cmd << MDIO_VALUE_OFFSET);
326 temp |= MDIO_WRITE_COMMAND;
328 temp = MDIO_READ_COMMAND;
330 temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
331 temp |= (phy_id & 0x1f);
333 __raw_writel(temp, &mdio_regs->phy_control);
335 while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
341 if (cycles == 5000) {
342 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
347 temp = __raw_readl(&mdio_regs->phy_control);
348 temp |= MDIO_CMD_COMPLETE;
349 __raw_writel(temp, &mdio_regs->phy_control);
354 return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
357 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
362 spin_lock_irqsave(&mdio_lock, flags);
363 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
364 spin_unlock_irqrestore(&mdio_lock, flags);
368 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
374 spin_lock_irqsave(&mdio_lock, flags);
375 ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
376 spin_unlock_irqrestore(&mdio_lock, flags);
380 static int cns3xxx_mdio_register(void __iomem *base)
384 if (!(mdio_bus = mdiobus_alloc()))
389 spin_lock_init(&mdio_lock);
390 mdio_bus->name = "CNS3xxx MII Bus";
391 mdio_bus->read = &cns3xxx_mdio_read;
392 mdio_bus->write = &cns3xxx_mdio_write;
393 strcpy(mdio_bus->id, "0");
395 if ((err = mdiobus_register(mdio_bus)))
396 mdiobus_free(mdio_bus);
400 static void cns3xxx_mdio_remove(void)
402 mdiobus_unregister(mdio_bus);
403 mdiobus_free(mdio_bus);
406 static void enable_tx_dma(struct sw *sw)
408 __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
411 static void enable_rx_dma(struct sw *sw)
413 __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
416 static void cns3xxx_adjust_link(struct net_device *dev)
418 struct port *port = netdev_priv(dev);
419 struct phy_device *phydev = port->phydev;
424 printk(KERN_INFO "%s: link down\n", dev->name);
429 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
432 port->speed = phydev->speed;
433 port->duplex = phydev->duplex;
435 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
436 dev->name, port->speed, port->duplex ? "full" : "half");
439 static void eth_schedule_poll(struct sw *sw)
441 if (unlikely(!napi_schedule_prep(&sw->napi)))
444 disable_irq_nosync(sw->rx_irq);
445 __napi_schedule(&sw->napi);
448 irqreturn_t eth_rx_irq(int irq, void *pdev)
450 struct net_device *dev = pdev;
451 struct sw *sw = netdev_priv(dev);
452 eth_schedule_poll(sw);
453 return (IRQ_HANDLED);
456 irqreturn_t eth_stat_irq(int irq, void *pdev)
458 struct net_device *dev = pdev;
459 struct sw *sw = netdev_priv(dev);
461 u32 stat = __raw_readl(&sw->regs->intr_stat);
462 __raw_writel(0xffffffff, &sw->regs->intr_stat);
464 if (stat & MAC2_RX_ERROR)
465 switch_port_tab[3]->netdev->stats.rx_dropped++;
466 if (stat & MAC1_RX_ERROR)
467 switch_port_tab[1]->netdev->stats.rx_dropped++;
468 if (stat & MAC0_RX_ERROR)
469 switch_port_tab[0]->netdev->stats.rx_dropped++;
471 if (stat & MAC0_STATUS_CHANGE) {
472 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
473 switch_port_tab[0]->phydev->link = (cfg & 0x1);
474 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
475 if (((cfg >> 2) & 0x3) == 2)
476 switch_port_tab[0]->phydev->speed = 1000;
477 else if (((cfg >> 2) & 0x3) == 1)
478 switch_port_tab[0]->phydev->speed = 100;
480 switch_port_tab[0]->phydev->speed = 10;
481 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
484 if (stat & MAC1_STATUS_CHANGE) {
485 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
486 switch_port_tab[1]->phydev->link = (cfg & 0x1);
487 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
488 if (((cfg >> 2) & 0x3) == 2)
489 switch_port_tab[1]->phydev->speed = 1000;
490 else if (((cfg >> 2) & 0x3) == 1)
491 switch_port_tab[1]->phydev->speed = 100;
493 switch_port_tab[1]->phydev->speed = 10;
494 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
497 if (stat & MAC2_STATUS_CHANGE) {
498 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
499 switch_port_tab[3]->phydev->link = (cfg & 0x1);
500 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
501 if (((cfg >> 2) & 0x3) == 2)
502 switch_port_tab[3]->phydev->speed = 1000;
503 else if (((cfg >> 2) & 0x3) == 1)
504 switch_port_tab[3]->phydev->speed = 100;
506 switch_port_tab[3]->phydev->speed = 10;
507 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
510 return (IRQ_HANDLED);
514 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
516 struct _rx_ring *rx_ring = &sw->rx_ring;
517 unsigned int i = rx_ring->alloc_index;
518 struct rx_desc *desc = &(rx_ring)->desc[i];
522 for (received += rx_ring->alloc_count; received > 0; received--) {
523 buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC);
527 phys = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
528 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
529 if (dma_mapping_error(NULL, phys)) {
534 desc->sdl = RX_SEGMENT_MRU;
539 /* put the new buffer on RX-free queue */
540 rx_ring->buff_tab[i] = buf;
541 rx_ring->phys_tab[i] = phys;
542 if (i == RX_DESCS - 1) {
544 desc->config0 = END_OF_RING | FIRST_SEGMENT |
545 LAST_SEGMENT | RX_SEGMENT_MRU;
546 desc = &(rx_ring)->desc[i];
548 desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
555 rx_ring->alloc_count = received;
556 rx_ring->alloc_index = i;
559 static void eth_check_num_used(struct _tx_ring *tx_ring)
564 if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
567 if (tx_ring->stopped == stop)
570 tx_ring->stopped = stop;
571 for (i = 0; i < 4; i++) {
572 struct port *port = switch_port_tab[i];
573 struct net_device *dev;
580 netif_stop_queue(dev);
582 netif_wake_queue(dev);
586 static void eth_complete_tx(struct sw *sw)
588 struct _tx_ring *tx_ring = &sw->tx_ring;
589 struct tx_desc *desc;
592 int num_used = tx_ring->num_used;
595 index = tx_ring->free_index;
596 desc = &(tx_ring)->desc[index];
597 for (i = 0; i < num_used; i++) {
599 skb = tx_ring->buff_tab[index];
600 tx_ring->buff_tab[index] = 0;
602 dev_kfree_skb_any(skb);
603 dma_unmap_single(NULL, tx_ring->phys_tab[index],
604 desc->sdl, DMA_TO_DEVICE);
605 if (++index == TX_DESCS) {
607 desc = &(tx_ring)->desc[index];
615 tx_ring->free_index = index;
616 tx_ring->num_used -= i;
617 eth_check_num_used(tx_ring);
620 static int eth_poll(struct napi_struct *napi, int budget)
622 struct sw *sw = container_of(napi, struct sw, napi);
623 struct _rx_ring *rx_ring = &sw->rx_ring;
626 unsigned int i = rx_ring->cur_index;
627 struct rx_desc *desc = &(rx_ring)->desc[i];
628 unsigned int alloc_count = rx_ring->alloc_count;
630 while (desc->cown && alloc_count + received < RX_DESCS - 1) {
632 int reserve = SKB_HEAD_ALIGN;
634 if (received >= budget)
637 /* process received frame */
638 dma_unmap_single(NULL, rx_ring->phys_tab[i],
639 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
641 skb = build_skb(rx_ring->buff_tab[i], 0);
645 skb->dev = switch_port_tab[desc->sp]->netdev;
648 if (desc->fsd && !desc->lsd)
649 length = RX_SEGMENT_MRU;
652 reserve -= NET_IP_ALIGN;
654 length += NET_IP_ALIGN;
657 skb_reserve(skb, reserve);
658 skb_put(skb, length);
661 sw->frag_first = skb;
663 if (sw->frag_first == sw->frag_last)
664 skb_frag_add_head(sw->frag_first, skb);
666 sw->frag_last->next = skb;
667 sw->frag_first->len += skb->len;
668 sw->frag_first->data_len += skb->len;
669 sw->frag_first->truesize += skb->truesize;
674 struct net_device *dev;
676 skb = sw->frag_first;
678 skb->protocol = eth_type_trans(skb, dev);
680 dev->stats.rx_packets++;
681 dev->stats.rx_bytes += skb->len;
683 /* RX Hardware checksum offload */
684 skb->ip_summed = CHECKSUM_NONE;
685 switch (desc->prot) {
693 skb->ip_summed = CHECKSUM_UNNECESSARY;
694 napi_gro_receive(napi, skb);
699 netif_receive_skb(skb);
703 sw->frag_first = NULL;
704 sw->frag_last = NULL;
708 if (++i == RX_DESCS) {
710 desc = &(rx_ring)->desc[i];
716 rx_ring->cur_index = i;
719 enable_irq(sw->rx_irq);
721 /* if rx descriptors are full schedule another poll */
722 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
723 eth_schedule_poll(sw);
726 spin_lock_bh(&tx_lock);
728 spin_unlock_bh(&tx_lock);
730 cns3xxx_alloc_rx_buf(sw, received);
738 static void eth_set_desc(struct _tx_ring *tx_ring, int index, int index_last,
739 void *data, int len, u32 config0, u32 pmap)
741 struct tx_desc *tx_desc = &(tx_ring)->desc[index];
744 phys = dma_map_single(NULL, data, len, DMA_TO_DEVICE);
746 tx_desc->pmap = pmap;
747 tx_ring->phys_tab[index] = phys;
750 if (index == TX_DESCS - 1)
751 config0 |= END_OF_RING;
752 if (index == index_last)
753 config0 |= LAST_SEGMENT;
756 tx_desc->config0 = config0;
759 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
761 struct port *port = netdev_priv(dev);
762 struct sw *sw = port->sw;
763 struct _tx_ring *tx_ring = &sw->tx_ring;
764 struct sk_buff *skb1;
765 char pmap = (1 << port->id);
766 int nr_frags = skb_shinfo(skb)->nr_frags;
767 int nr_desc = nr_frags;
768 int index0, index, index_last;
776 skb_walk_frags(skb, skb1)
779 eth_schedule_poll(sw);
780 spin_lock_bh(&tx_lock);
781 if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
782 spin_unlock_bh(&tx_lock);
783 return NETDEV_TX_BUSY;
786 index = index0 = tx_ring->cur_index;
787 index_last = (index0 + nr_desc) % TX_DESCS;
788 tx_ring->cur_index = (index_last + 1) % TX_DESCS;
790 spin_unlock_bh(&tx_lock);
792 config0 = FORCE_ROUTE;
793 if (skb->ip_summed == CHECKSUM_PARTIAL)
794 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
799 for (i = 0; i < nr_frags; i++) {
800 struct skb_frag_struct *frag;
803 index = (index + 1) % TX_DESCS;
805 frag = &skb_shinfo(skb)->frags[i];
806 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
808 eth_set_desc(tx_ring, index, index_last, addr, frag->size,
813 len0 = skb->len - skb->data_len;
815 skb_walk_frags(skb, skb1) {
816 index = (index + 1) % TX_DESCS;
819 eth_set_desc(tx_ring, index, index_last, skb1->data, skb1->len,
823 tx_ring->buff_tab[index0] = skb;
824 eth_set_desc(tx_ring, index0, index_last, skb->data, len0,
825 config0 | FIRST_SEGMENT, pmap);
830 tx_ring->num_used += nr_desc + 1;
831 spin_unlock(&tx_lock);
833 dev->stats.tx_packets++;
834 dev->stats.tx_bytes += skb->len;
841 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
843 struct port *port = netdev_priv(dev);
845 if (!netif_running(dev))
847 return phy_mii_ioctl(port->phydev, req, cmd);
850 /* ethtool support */
852 static void cns3xxx_get_drvinfo(struct net_device *dev,
853 struct ethtool_drvinfo *info)
855 strcpy(info->driver, DRV_NAME);
856 strcpy(info->bus_info, "internal");
859 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
861 struct port *port = netdev_priv(dev);
862 return phy_ethtool_gset(port->phydev, cmd);
865 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
867 struct port *port = netdev_priv(dev);
868 return phy_ethtool_sset(port->phydev, cmd);
871 static int cns3xxx_nway_reset(struct net_device *dev)
873 struct port *port = netdev_priv(dev);
874 return phy_start_aneg(port->phydev);
877 static struct ethtool_ops cns3xxx_ethtool_ops = {
878 .get_drvinfo = cns3xxx_get_drvinfo,
879 .get_settings = cns3xxx_get_settings,
880 .set_settings = cns3xxx_set_settings,
881 .nway_reset = cns3xxx_nway_reset,
882 .get_link = ethtool_op_get_link,
886 static int init_rings(struct sw *sw)
889 struct _rx_ring *rx_ring = &sw->rx_ring;
890 struct _tx_ring *tx_ring = &sw->tx_ring;
892 __raw_writel(0, &sw->regs->fs_dma_ctrl0);
893 __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
894 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
895 __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
897 __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
899 if (!(rx_dma_pool = dma_pool_create(DRV_NAME, NULL,
900 RX_POOL_ALLOC_SIZE, 32, 0)))
903 if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL,
904 &rx_ring->phys_addr)))
906 memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
908 /* Setup RX buffers */
909 for (i = 0; i < RX_DESCS; i++) {
910 struct rx_desc *desc = &(rx_ring)->desc[i];
913 buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL);
917 desc->sdl = RX_SEGMENT_MRU;
918 if (i == (RX_DESCS - 1))
923 desc->sdp = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
924 RX_SEGMENT_MRU, DMA_FROM_DEVICE);
925 if (dma_mapping_error(NULL, desc->sdp))
928 rx_ring->buff_tab[i] = buf;
929 rx_ring->phys_tab[i] = desc->sdp;
932 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
933 __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
935 if (!(tx_dma_pool = dma_pool_create(DRV_NAME, NULL,
936 TX_POOL_ALLOC_SIZE, 32, 0)))
939 if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL,
940 &tx_ring->phys_addr)))
942 memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
944 /* Setup TX buffers */
945 for (i = 0; i < TX_DESCS; i++) {
946 struct tx_desc *desc = &(tx_ring)->desc[i];
947 tx_ring->buff_tab[i] = 0;
949 if (i == (TX_DESCS - 1))
953 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
954 __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
959 static void destroy_rings(struct sw *sw)
962 if (sw->rx_ring.desc) {
963 for (i = 0; i < RX_DESCS; i++) {
964 struct _rx_ring *rx_ring = &sw->rx_ring;
965 struct rx_desc *desc = &(rx_ring)->desc[i];
966 struct sk_buff *skb = sw->rx_ring.buff_tab[i];
971 dma_unmap_single(NULL, desc->sdp, RX_SEGMENT_MRU,
975 dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr);
976 dma_pool_destroy(rx_dma_pool);
978 sw->rx_ring.desc = 0;
980 if (sw->tx_ring.desc) {
981 for (i = 0; i < TX_DESCS; i++) {
982 struct _tx_ring *tx_ring = &sw->tx_ring;
983 struct tx_desc *desc = &(tx_ring)->desc[i];
984 struct sk_buff *skb = sw->tx_ring.buff_tab[i];
986 dma_unmap_single(NULL, desc->sdp,
987 skb->len, DMA_TO_DEVICE);
991 dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr);
992 dma_pool_destroy(tx_dma_pool);
994 sw->tx_ring.desc = 0;
998 static int eth_open(struct net_device *dev)
1000 struct port *port = netdev_priv(dev);
1001 struct sw *sw = port->sw;
1004 port->speed = 0; /* force "link up" message */
1005 phy_start(port->phydev);
1007 netif_start_queue(dev);
1010 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
1011 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
1012 napi_enable(&sw->napi);
1013 netif_start_queue(napi_dev);
1015 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1016 MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1018 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1019 temp &= ~(PORT_DISABLE);
1020 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1022 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1023 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1024 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1028 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1029 temp &= ~(PORT_DISABLE);
1030 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1033 netif_carrier_on(dev);
1038 static int eth_close(struct net_device *dev)
1040 struct port *port = netdev_priv(dev);
1041 struct sw *sw = port->sw;
1046 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1047 temp |= (PORT_DISABLE);
1048 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1050 netif_stop_queue(dev);
1052 phy_stop(port->phydev);
1055 disable_irq(sw->rx_irq);
1056 free_irq(sw->rx_irq, napi_dev);
1057 disable_irq(sw->stat_irq);
1058 free_irq(sw->stat_irq, napi_dev);
1059 napi_disable(&sw->napi);
1060 netif_stop_queue(napi_dev);
1061 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1062 temp |= (PORT_DISABLE);
1063 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1065 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1066 &sw->regs->dma_auto_poll_cfg);
1069 netif_carrier_off(dev);
1073 static void eth_rx_mode(struct net_device *dev)
1075 struct port *port = netdev_priv(dev);
1076 struct sw *sw = port->sw;
1079 temp = __raw_readl(&sw->regs->mac_glob_cfg);
1081 if (dev->flags & IFF_PROMISC) {
1083 temp |= ((1 << 2) << PROMISC_OFFSET);
1085 temp |= ((1 << port->id) << PROMISC_OFFSET);
1088 temp &= ~((1 << 2) << PROMISC_OFFSET);
1090 temp &= ~((1 << port->id) << PROMISC_OFFSET);
1092 __raw_writel(temp, &sw->regs->mac_glob_cfg);
1095 static int eth_set_mac(struct net_device *netdev, void *p)
1097 struct port *port = netdev_priv(netdev);
1098 struct sw *sw = port->sw;
1099 struct sockaddr *addr = p;
1102 if (!is_valid_ether_addr(addr->sa_data))
1103 return -EADDRNOTAVAIL;
1105 /* Invalidate old ARL Entry */
1107 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1109 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1110 __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1111 (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1112 &sw->regs->arl_ctrl[1]);
1114 __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1116 &sw->regs->arl_ctrl[2]);
1117 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1119 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1126 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1129 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1131 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1132 __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1133 (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1134 &sw->regs->arl_ctrl[1]);
1136 __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1137 (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1138 __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1140 while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1148 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1150 if (new_mtu > MAX_MTU)
1157 static const struct net_device_ops cns3xxx_netdev_ops = {
1158 .ndo_open = eth_open,
1159 .ndo_stop = eth_close,
1160 .ndo_start_xmit = eth_xmit,
1161 .ndo_set_rx_mode = eth_rx_mode,
1162 .ndo_do_ioctl = eth_ioctl,
1163 .ndo_change_mtu = cns3xxx_change_mtu,
1164 .ndo_set_mac_address = eth_set_mac,
1165 .ndo_validate_addr = eth_validate_addr,
1168 static int eth_init_one(struct platform_device *pdev)
1173 struct net_device *dev;
1174 struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1175 char phy_id[MII_BUS_ID_SIZE + 3];
1178 struct resource *res;
1181 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182 regs = devm_ioremap_resource(&pdev->dev, res);
1184 return PTR_ERR(regs);
1186 err = cns3xxx_mdio_register(regs);
1190 if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1192 goto err_remove_mdio;
1195 strcpy(napi_dev->name, "switch%d");
1196 napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1198 SET_NETDEV_DEV(napi_dev, &pdev->dev);
1199 sw = netdev_priv(napi_dev);
1200 memset(sw, 0, sizeof(struct sw));
1203 sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1204 sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1206 temp = __raw_readl(&sw->regs->phy_auto_addr);
1207 temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1208 __raw_writel(temp, &sw->regs->phy_auto_addr);
1210 for (i = 0; i < 4; i++) {
1211 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1212 temp |= (PORT_DISABLE);
1213 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1216 temp = PORT_DISABLE;
1217 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1219 temp = __raw_readl(&sw->regs->vlan_cfg);
1220 temp |= NIC_MODE | VLAN_UNAWARE;
1221 __raw_writel(temp, &sw->regs->vlan_cfg);
1223 __raw_writel(UNKNOWN_VLAN_TO_CPU |
1224 CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1226 if ((err = init_rings(sw)) != 0) {
1231 platform_set_drvdata(pdev, napi_dev);
1233 netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1235 for (i = 0; i < 3; i++) {
1236 if (!(plat->ports & (1 << i))) {
1240 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1244 port = netdev_priv(dev);
1252 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1253 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1254 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1256 dev->netdev_ops = &cns3xxx_netdev_ops;
1257 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1258 dev->tx_queue_len = 1000;
1259 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1261 switch_port_tab[port->id] = port;
1262 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1264 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1265 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1266 PHY_INTERFACE_MODE_RGMII);
1267 if ((err = IS_ERR(port->phydev))) {
1268 switch_port_tab[port->id] = 0;
1273 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1275 if ((err = register_netdev(dev))) {
1276 phy_disconnect(port->phydev);
1277 switch_port_tab[port->id] = 0;
1282 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1283 netif_carrier_off(dev);
1291 for (--i; i >= 0; i--) {
1292 if (switch_port_tab[i]) {
1293 port = switch_port_tab[i];
1295 unregister_netdev(dev);
1296 phy_disconnect(port->phydev);
1297 switch_port_tab[i] = 0;
1302 free_netdev(napi_dev);
1304 cns3xxx_mdio_remove();
1308 static int eth_remove_one(struct platform_device *pdev)
1310 struct net_device *dev = platform_get_drvdata(pdev);
1311 struct sw *sw = netdev_priv(dev);
1315 for (i = 3; i >= 0; i--) {
1316 if (switch_port_tab[i]) {
1317 struct port *port = switch_port_tab[i];
1318 struct net_device *dev = port->netdev;
1319 unregister_netdev(dev);
1320 phy_disconnect(port->phydev);
1321 switch_port_tab[i] = 0;
1326 free_netdev(napi_dev);
1327 cns3xxx_mdio_remove();
1332 static struct platform_driver cns3xxx_eth_driver = {
1333 .driver.name = DRV_NAME,
1334 .probe = eth_init_one,
1335 .remove = eth_remove_one,
1338 static int __init eth_init_module(void)
1340 return platform_driver_register(&cns3xxx_eth_driver);
1343 static void __exit eth_cleanup_module(void)
1345 platform_driver_unregister(&cns3xxx_eth_driver);
1348 module_init(eth_init_module);
1349 module_exit(eth_cleanup_module);
1351 MODULE_AUTHOR("Chris Lang");
1352 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1353 MODULE_LICENSE("GPL v2");
1354 MODULE_ALIAS("platform:cns3xxx_eth");