target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c

   1 /*
   2  * Cavium CNS3xxx Gigabit driver for Linux
   3  *
   4  * Copyright 2011 Gateworks Corporation
   5  *                Chris Lang <clang@gateworks.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of version 2 of the GNU General Public License
   9  * as published by the Free Software Foundation.
  10  *
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/module.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmapool.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/platform_data/cns3xxx.h>
  24 #include <linux/skbuff.h>
  25
  26 #define DRV_NAME "cns3xxx_eth"
  27
  28 #define RX_DESCS 256
  29 #define TX_DESCS 128
  30 #define TX_DESC_RESERVE 20
  31
  32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
  33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
  34 #define REGS_SIZE 336
  35
  36 #define RX_BUFFER_ALIGN 64
  37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
  38
  39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
  40 #define RX_SEGMENT_ALLOC_SIZE 2048
  41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
  42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
  43 #define MAX_MTU 9500
  44
  45 #define NAPI_WEIGHT 64
  46
  47 /* MDIO Defines */
  48 #define MDIO_CMD_COMPLETE 0x00008000
  49 #define MDIO_WRITE_COMMAND 0x00002000
  50 #define MDIO_READ_COMMAND 0x00004000
  51 #define MDIO_REG_OFFSET 8
  52 #define MDIO_VALUE_OFFSET 16
  53
  54 /* Descritor Defines */
  55 #define END_OF_RING 0x40000000
  56 #define FIRST_SEGMENT 0x20000000
  57 #define LAST_SEGMENT 0x10000000
  58 #define FORCE_ROUTE 0x04000000
  59 #define IP_CHECKSUM 0x00040000
  60 #define UDP_CHECKSUM 0x00020000
  61 #define TCP_CHECKSUM 0x00010000
  62
  63 /* Port Config Defines */
  64 #define PORT_BP_ENABLE 0x00020000
  65 #define PORT_DISABLE 0x00040000
  66 #define PORT_LEARN_DIS 0x00080000
  67 #define PORT_BLOCK_STATE 0x00100000
  68 #define PORT_BLOCK_MODE 0x00200000
  69
  70 #define PROMISC_OFFSET 29
  71
  72 /* Global Config Defines */
  73 #define UNKNOWN_VLAN_TO_CPU 0x02000000
  74 #define ACCEPT_CRC_PACKET 0x00200000
  75 #define CRC_STRIPPING 0x00100000
  76
  77 /* VLAN Config Defines */
  78 #define NIC_MODE 0x00008000
  79 #define VLAN_UNAWARE 0x00000001
  80
  81 /* DMA AUTO Poll Defines */
  82 #define TS_POLL_EN 0x00000020
  83 #define TS_SUSPEND 0x00000010
  84 #define FS_POLL_EN 0x00000002
  85 #define FS_SUSPEND 0x00000001
  86
  87 /* DMA Ring Control Defines */
  88 #define QUEUE_THRESHOLD 0x000000f0
  89 #define CLR_FS_STATE 0x80000000
  90
  91 /* Interrupt Status Defines */
  92 #define MAC0_STATUS_CHANGE 0x00004000
  93 #define MAC1_STATUS_CHANGE 0x00008000
  94 #define MAC2_STATUS_CHANGE 0x00010000
  95 #define MAC0_RX_ERROR 0x00100000
  96 #define MAC1_RX_ERROR 0x00200000
  97 #define MAC2_RX_ERROR 0x00400000
  98
  99 struct tx_desc
 100 {
 101         u32 sdp; /* segment data pointer */
 102
 103         union {
 104                 struct {
 105                         u32 sdl:16; /* segment data length */
 106                         u32 tco:1;
 107                         u32 uco:1;
 108                         u32 ico:1;
 109                         u32 rsv_1:3; /* reserve */
 110                         u32 pri:3;
 111                         u32 fp:1; /* force priority */
 112                         u32 fr:1;
 113                         u32 interrupt:1;
 114                         u32 lsd:1;
 115                         u32 fsd:1;
 116                         u32 eor:1;
 117                         u32 cown:1;
 118                 };
 119                 u32 config0;
 120         };
 121
 122         union {
 123                 struct {
 124                         u32 ctv:1;
 125                         u32 stv:1;
 126                         u32 sid:4;
 127                         u32 inss:1;
 128                         u32 dels:1;
 129                         u32 rsv_2:9;
 130                         u32 pmap:5;
 131                         u32 mark:3;
 132                         u32 ewan:1;
 133                         u32 fewan:1;
 134                         u32 rsv_3:5;
 135                 };
 136                 u32 config1;
 137         };
 138
 139         union {
 140                 struct {
 141                         u32 c_vid:12;
 142                         u32 c_cfs:1;
 143                         u32 c_pri:3;
 144                         u32 s_vid:12;
 145                         u32 s_dei:1;
 146                         u32 s_pri:3;
 147                 };
 148                 u32 config2;
 149         };
 150
 151         u8 alignment[16]; /* for 32 byte */
 152 };
 153
 154 struct rx_desc
 155 {
 156         u32 sdp; /* segment data pointer */
 157
 158         union {
 159                 struct {
 160                         u32 sdl:16; /* segment data length */
 161                         u32 l4f:1;
 162                         u32 ipf:1;
 163                         u32 prot:4;
 164                         u32 hr:6;
 165                         u32 lsd:1;
 166                         u32 fsd:1;
 167                         u32 eor:1;
 168                         u32 cown:1;
 169                 };
 170                 u32 config0;
 171         };
 172
 173         union {
 174                 struct {
 175                         u32 ctv:1;
 176                         u32 stv:1;
 177                         u32 unv:1;
 178                         u32 iwan:1;
 179                         u32 exdv:1;
 180                         u32 e_wan:1;
 181                         u32 rsv_1:2;
 182                         u32 sp:3;
 183                         u32 crc_err:1;
 184                         u32 un_eth:1;
 185                         u32 tc:2;
 186                         u32 rsv_2:1;
 187                         u32 ip_offset:5;
 188                         u32 rsv_3:11;
 189                 };
 190                 u32 config1;
 191         };
 192
 193         union {
 194                 struct {
 195                         u32 c_vid:12;
 196                         u32 c_cfs:1;
 197                         u32 c_pri:3;
 198                         u32 s_vid:12;
 199                         u32 s_dei:1;
 200                         u32 s_pri:3;
 201                 };
 202                 u32 config2;
 203         };
 204
 205         u8 alignment[16]; /* for 32 byte alignment */
 206 };
 207
 208
 209 struct switch_regs {
 210         u32 phy_control;
 211         u32 phy_auto_addr;
 212         u32 mac_glob_cfg;
 213         u32 mac_cfg[4];
 214         u32 mac_pri_ctrl[5], __res;
 215         u32 etype[2];
 216         u32 udp_range[4];
 217         u32 prio_etype_udp;
 218         u32 prio_ipdscp[8];
 219         u32 tc_ctrl;
 220         u32 rate_ctrl;
 221         u32 fc_glob_thrs;
 222         u32 fc_port_thrs;
 223         u32 mc_fc_glob_thrs;
 224         u32 dc_glob_thrs;
 225         u32 arl_vlan_cmd;
 226         u32 arl_ctrl[3];
 227         u32 vlan_cfg;
 228         u32 pvid[2];
 229         u32 vlan_ctrl[3];
 230         u32 session_id[8];
 231         u32 intr_stat;
 232         u32 intr_mask;
 233         u32 sram_test;
 234         u32 mem_queue;
 235         u32 farl_ctrl;
 236         u32 fc_input_thrs, __res1[2];
 237         u32 clk_skew_ctrl;
 238         u32 mac_glob_cfg_ext, __res2[2];
 239         u32 dma_ring_ctrl;
 240         u32 dma_auto_poll_cfg;
 241         u32 delay_intr_cfg, __res3;
 242         u32 ts_dma_ctrl0;
 243         u32 ts_desc_ptr0;
 244         u32 ts_desc_base_addr0, __res4;
 245         u32 fs_dma_ctrl0;
 246         u32 fs_desc_ptr0;
 247         u32 fs_desc_base_addr0, __res5;
 248         u32 ts_dma_ctrl1;
 249         u32 ts_desc_ptr1;
 250         u32 ts_desc_base_addr1, __res6;
 251         u32 fs_dma_ctrl1;
 252         u32 fs_desc_ptr1;
 253         u32 fs_desc_base_addr1;
 254         u32 __res7[109];
 255         u32 mac_counter0[13];
 256 };
 257
 258 struct _tx_ring {
 259         struct tx_desc *desc;
 260         dma_addr_t phys_addr;
 261         struct tx_desc *cur_addr;
 262         struct sk_buff *buff_tab[TX_DESCS];
 263         unsigned int phys_tab[TX_DESCS];
 264         u32 free_index;
 265         u32 count_index;
 266         u32 cur_index;
 267         int num_used;
 268         int num_count;
 269         bool stopped;
 270 };
 271
 272 struct _rx_ring {
 273         struct rx_desc *desc;
 274         dma_addr_t phys_addr;
 275         struct rx_desc *cur_addr;
 276         void *buff_tab[RX_DESCS];
 277         unsigned int phys_tab[RX_DESCS];
 278         u32 cur_index;
 279         u32 alloc_index;
 280         int alloc_count;
 281 };
 282
 283 struct sw {
 284         struct switch_regs __iomem *regs;
 285         struct napi_struct napi;
 286         struct cns3xxx_plat_info *plat;
 287         struct _tx_ring tx_ring;
 288         struct _rx_ring rx_ring;
 289         struct sk_buff *frag_first;
 290         struct sk_buff *frag_last;
 291         int rx_irq;
 292         int stat_irq;
 293 };
 294
 295 struct port {
 296         struct net_device *netdev;
 297         struct phy_device *phydev;
 298         struct sw *sw;
 299         int id;                 /* logical port ID */
 300         int speed, duplex;
 301 };
 302
 303 static spinlock_t mdio_lock;
 304 static DEFINE_SPINLOCK(tx_lock);
 305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
 306 struct mii_bus *mdio_bus;
 307 static int ports_open;
 308 static struct port *switch_port_tab[4];
 309 static struct dma_pool *rx_dma_pool;
 310 static struct dma_pool *tx_dma_pool;
 311 struct net_device *napi_dev;
 312
 313 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 314                            int write, u16 cmd)
 315 {
 316         int cycles = 0;
 317         u32 temp = 0;
 318
 319         temp = __raw_readl(&mdio_regs->phy_control);
 320         temp |= MDIO_CMD_COMPLETE;
 321         __raw_writel(temp, &mdio_regs->phy_control);
 322         udelay(10);
 323
 324         if (write) {
 325                 temp = (cmd << MDIO_VALUE_OFFSET);
 326                 temp |= MDIO_WRITE_COMMAND;
 327         } else {
 328                 temp = MDIO_READ_COMMAND;
 329         }
 330         temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
 331         temp |= (phy_id & 0x1f);
 332
 333         __raw_writel(temp, &mdio_regs->phy_control);
 334
 335         while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
 336                         && cycles < 5000) {
 337                 udelay(1);
 338                 cycles++;
 339         }
 340
 341         if (cycles == 5000) {
 342                 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
 343                        phy_id);
 344                 return -1;
 345         }
 346
 347         temp = __raw_readl(&mdio_regs->phy_control);
 348         temp |= MDIO_CMD_COMPLETE;
 349         __raw_writel(temp, &mdio_regs->phy_control);
 350
 351         if (write)
 352                 return 0;
 353
 354         return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
 355 }
 356
 357 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 358 {
 359         unsigned long flags;
 360         int ret;
 361
 362         spin_lock_irqsave(&mdio_lock, flags);
 363         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
 364         spin_unlock_irqrestore(&mdio_lock, flags);
 365         return ret;
 366 }
 367
 368 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 369                              u16 val)
 370 {
 371         unsigned long flags;
 372         int ret;
 373
 374         spin_lock_irqsave(&mdio_lock, flags);
 375         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
 376         spin_unlock_irqrestore(&mdio_lock, flags);
 377         return ret;
 378 }
 379
 380 static int cns3xxx_mdio_register(void __iomem *base)
 381 {
 382         int err;
 383
 384         if (!(mdio_bus = mdiobus_alloc()))
 385                 return -ENOMEM;
 386
 387         mdio_regs = base;
 388
 389         spin_lock_init(&mdio_lock);
 390         mdio_bus->name = "CNS3xxx MII Bus";
 391         mdio_bus->read = &cns3xxx_mdio_read;
 392         mdio_bus->write = &cns3xxx_mdio_write;
 393         strcpy(mdio_bus->id, "0");
 394
 395         if ((err = mdiobus_register(mdio_bus)))
 396                 mdiobus_free(mdio_bus);
 397         return err;
 398 }
 399
 400 static void cns3xxx_mdio_remove(void)
 401 {
 402         mdiobus_unregister(mdio_bus);
 403         mdiobus_free(mdio_bus);
 404 }
 405
 406 static void enable_tx_dma(struct sw *sw)
 407 {
 408         __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
 409 }
 410
 411 static void enable_rx_dma(struct sw *sw)
 412 {
 413         __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
 414 }
 415
 416 static void cns3xxx_adjust_link(struct net_device *dev)
 417 {
 418         struct port *port = netdev_priv(dev);
 419         struct phy_device *phydev = port->phydev;
 420
 421         if (!phydev->link) {
 422                 if (port->speed) {
 423                         port->speed = 0;
 424                         printk(KERN_INFO "%s: link down\n", dev->name);
 425                 }
 426                 return;
 427         }
 428
 429         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 430                 return;
 431
 432         port->speed = phydev->speed;
 433         port->duplex = phydev->duplex;
 434
 435         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
 436                dev->name, port->speed, port->duplex ? "full" : "half");
 437 }
 438
 439 static void eth_schedule_poll(struct sw *sw)
 440 {
 441         if (unlikely(!napi_schedule_prep(&sw->napi)))
 442                 return;
 443
 444         disable_irq_nosync(sw->rx_irq);
 445         __napi_schedule(&sw->napi);
 446 }
 447
 448 irqreturn_t eth_rx_irq(int irq, void *pdev)
 449 {
 450         struct net_device *dev = pdev;
 451         struct sw *sw = netdev_priv(dev);
 452         eth_schedule_poll(sw);
 453         return (IRQ_HANDLED);
 454 }
 455
 456 irqreturn_t eth_stat_irq(int irq, void *pdev)
 457 {
 458         struct net_device *dev = pdev;
 459         struct sw *sw = netdev_priv(dev);
 460         u32 cfg;
 461         u32 stat = __raw_readl(&sw->regs->intr_stat);
 462         __raw_writel(0xffffffff, &sw->regs->intr_stat);
 463
 464         if (stat & MAC2_RX_ERROR)
 465                 switch_port_tab[3]->netdev->stats.rx_dropped++;
 466         if (stat & MAC1_RX_ERROR)
 467                 switch_port_tab[1]->netdev->stats.rx_dropped++;
 468         if (stat & MAC0_RX_ERROR)
 469                 switch_port_tab[0]->netdev->stats.rx_dropped++;
 470
 471         if (stat & MAC0_STATUS_CHANGE) {
 472                 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
 473                 switch_port_tab[0]->phydev->link = (cfg & 0x1);
 474                 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
 475                 if (((cfg >> 2) & 0x3) == 2)
 476                         switch_port_tab[0]->phydev->speed = 1000;
 477                 else if (((cfg >> 2) & 0x3) == 1)
 478                         switch_port_tab[0]->phydev->speed = 100;
 479                 else
 480                         switch_port_tab[0]->phydev->speed = 10;
 481                 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
 482         }
 483
 484         if (stat & MAC1_STATUS_CHANGE) {
 485                 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
 486                 switch_port_tab[1]->phydev->link = (cfg & 0x1);
 487                 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
 488                 if (((cfg >> 2) & 0x3) == 2)
 489                         switch_port_tab[1]->phydev->speed = 1000;
 490                 else if (((cfg >> 2) & 0x3) == 1)
 491                         switch_port_tab[1]->phydev->speed = 100;
 492                 else
 493                         switch_port_tab[1]->phydev->speed = 10;
 494                 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
 495         }
 496
 497         if (stat & MAC2_STATUS_CHANGE) {
 498                 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
 499                 switch_port_tab[3]->phydev->link = (cfg & 0x1);
 500                 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
 501                 if (((cfg >> 2) & 0x3) == 2)
 502                         switch_port_tab[3]->phydev->speed = 1000;
 503                 else if (((cfg >> 2) & 0x3) == 1)
 504                         switch_port_tab[3]->phydev->speed = 100;
 505                 else
 506                         switch_port_tab[3]->phydev->speed = 10;
 507                 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
 508         }
 509
 510         return (IRQ_HANDLED);
 511 }
 512
 513
 514 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
 515 {
 516         struct _rx_ring *rx_ring = &sw->rx_ring;
 517         unsigned int i = rx_ring->alloc_index;
 518         struct rx_desc *desc = &(rx_ring)->desc[i];
 519         void *buf;
 520         unsigned int phys;
 521
 522         for (received += rx_ring->alloc_count; received > 0; received--) {
 523                 buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC);
 524                 if (!buf)
 525                         break;
 526
 527                 phys = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
 528                                       RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 529                 if (dma_mapping_error(NULL, phys)) {
 530                         kfree(buf);
 531                         break;
 532                 }
 533
 534                 desc->sdl = RX_SEGMENT_MRU;
 535                 desc->sdp = phys;
 536
 537                 wmb();
 538
 539                 /* put the new buffer on RX-free queue */
 540                 rx_ring->buff_tab[i] = buf;
 541                 rx_ring->phys_tab[i] = phys;
 542                 if (i == RX_DESCS - 1) {
 543                         i = 0;
 544                         desc->config0 = END_OF_RING | FIRST_SEGMENT |
 545                                         LAST_SEGMENT | RX_SEGMENT_MRU;
 546                         desc = &(rx_ring)->desc[i];
 547                 } else {
 548                         desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
 549                                         RX_SEGMENT_MRU;
 550                         i++;
 551                         desc++;
 552                 }
 553         }
 554
 555         rx_ring->alloc_count = received;
 556         rx_ring->alloc_index = i;
 557 }
 558
 559 static void eth_check_num_used(struct _tx_ring *tx_ring)
 560 {
 561         bool stop = false;
 562         int i;
 563
 564         if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
 565                 stop = true;
 566
 567         if (tx_ring->stopped == stop)
 568                 return;
 569
 570         tx_ring->stopped = stop;
 571         for (i = 0; i < 4; i++) {
 572                 struct port *port = switch_port_tab[i];
 573                 struct net_device *dev;
 574
 575                 if (!port)
 576                         continue;
 577
 578                 dev = port->netdev;
 579                 if (stop)
 580                         netif_stop_queue(dev);
 581                 else
 582                         netif_wake_queue(dev);
 583         }
 584 }
 585
 586 static void eth_complete_tx(struct sw *sw)
 587 {
 588         struct _tx_ring *tx_ring = &sw->tx_ring;
 589         struct tx_desc *desc;
 590         int i;
 591         int index;
 592         int num_used = tx_ring->num_used;
 593         struct sk_buff *skb;
 594
 595         index = tx_ring->free_index;
 596         desc = &(tx_ring)->desc[index];
 597         for (i = 0; i < num_used; i++) {
 598                 if (desc->cown) {
 599                         skb = tx_ring->buff_tab[index];
 600                         tx_ring->buff_tab[index] = 0;
 601                         if (skb)
 602                                 dev_kfree_skb_any(skb);
 603                         dma_unmap_single(NULL, tx_ring->phys_tab[index],
 604                                 desc->sdl, DMA_TO_DEVICE);
 605                         if (++index == TX_DESCS) {
 606                                 index = 0;
 607                                 desc = &(tx_ring)->desc[index];
 608                         } else {
 609                                 desc++;
 610                         }
 611                 } else {
 612                         break;
 613                 }
 614         }
 615         tx_ring->free_index = index;
 616         tx_ring->num_used -= i;
 617         eth_check_num_used(tx_ring);
 618 }
 619
 620 static int eth_poll(struct napi_struct *napi, int budget)
 621 {
 622         struct sw *sw = container_of(napi, struct sw, napi);
 623         struct _rx_ring *rx_ring = &sw->rx_ring;
 624         int received = 0;
 625         unsigned int length;
 626         unsigned int i = rx_ring->cur_index;
 627         struct rx_desc *desc = &(rx_ring)->desc[i];
 628         unsigned int alloc_count = rx_ring->alloc_count;
 629
 630         while (desc->cown && alloc_count + received < RX_DESCS - 1) {
 631                 struct sk_buff *skb;
 632                 int reserve = SKB_HEAD_ALIGN;
 633
 634                 if (received >= budget)
 635                         break;
 636
 637                 /* process received frame */
 638                 dma_unmap_single(NULL, rx_ring->phys_tab[i],
 639                                  RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 640
 641                 skb = build_skb(rx_ring->buff_tab[i], 0);
 642                 if (!skb)
 643                         break;
 644
 645                 skb->dev = switch_port_tab[desc->sp]->netdev;
 646
 647                 length = desc->sdl;
 648                 if (desc->fsd && !desc->lsd)
 649                         length = RX_SEGMENT_MRU;
 650
 651                 if (!desc->fsd) {
 652                         reserve -= NET_IP_ALIGN;
 653                         if (!desc->lsd)
 654                                 length += NET_IP_ALIGN;
 655                 }
 656
 657                 skb_reserve(skb, reserve);
 658                 skb_put(skb, length);
 659
 660                 if (!sw->frag_first)
 661                         sw->frag_first = skb;
 662                 else {
 663                         if (sw->frag_first == sw->frag_last)
 664                                 skb_frag_add_head(sw->frag_first, skb);
 665                         else
 666                                 sw->frag_last->next = skb;
 667                         sw->frag_first->len += skb->len;
 668                         sw->frag_first->data_len += skb->len;
 669                         sw->frag_first->truesize += skb->truesize;
 670                 }
 671                 sw->frag_last = skb;
 672
 673                 if (desc->lsd) {
 674                         struct net_device *dev;
 675
 676                         skb = sw->frag_first;
 677                         dev = skb->dev;
 678                         skb->protocol = eth_type_trans(skb, dev);
 679
 680                         dev->stats.rx_packets++;
 681                         dev->stats.rx_bytes += skb->len;
 682
 683                         /* RX Hardware checksum offload */
 684                         skb->ip_summed = CHECKSUM_NONE;
 685                         switch (desc->prot) {
 686                                 case 1:
 687                                 case 2:
 688                                 case 5:
 689                                 case 6:
 690                                 case 13:
 691                                 case 14:
 692                                         if (!desc->l4f) {
 693                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 694                                                 napi_gro_receive(napi, skb);
 695                                                 break;
 696                                         }
 697                                         /* fall through */
 698                                 default:
 699                                         netif_receive_skb(skb);
 700                                         break;
 701                         }
 702
 703                         sw->frag_first = NULL;
 704                         sw->frag_last = NULL;
 705                 }
 706
 707                 received++;
 708                 if (++i == RX_DESCS) {
 709                         i = 0;
 710                         desc = &(rx_ring)->desc[i];
 711                 } else {
 712                         desc++;
 713                 }
 714         }
 715
 716         rx_ring->cur_index = i;
 717         if (!received) {
 718                 napi_complete(napi);
 719                 enable_irq(sw->rx_irq);
 720
 721                 /* if rx descriptors are full schedule another poll */
 722                 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
 723                         eth_schedule_poll(sw);
 724         }
 725
 726         spin_lock_bh(&tx_lock);
 727         eth_complete_tx(sw);
 728         spin_unlock_bh(&tx_lock);
 729
 730         cns3xxx_alloc_rx_buf(sw, received);
 731
 732         wmb();
 733         enable_rx_dma(sw);
 734
 735         return received;
 736 }
 737
 738 static void eth_set_desc(struct _tx_ring *tx_ring, int index, int index_last,
 739                          void *data, int len, u32 config0, u32 pmap)
 740 {
 741         struct tx_desc *tx_desc = &(tx_ring)->desc[index];
 742         unsigned int phys;
 743
 744         phys = dma_map_single(NULL, data, len, DMA_TO_DEVICE);
 745         tx_desc->sdp = phys;
 746         tx_desc->pmap = pmap;
 747         tx_ring->phys_tab[index] = phys;
 748
 749         config0 |= len;
 750         if (index == TX_DESCS - 1)
 751                 config0 |= END_OF_RING;
 752         if (index == index_last)
 753                 config0 |= LAST_SEGMENT;
 754
 755         wmb();
 756         tx_desc->config0 = config0;
 757 }
 758
 759 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 760 {
 761         struct port *port = netdev_priv(dev);
 762         struct sw *sw = port->sw;
 763         struct _tx_ring *tx_ring = &sw->tx_ring;
 764         struct sk_buff *skb1;
 765         char pmap = (1 << port->id);
 766         int nr_frags = skb_shinfo(skb)->nr_frags;
 767         int nr_desc = nr_frags;
 768         int index0, index, index_last;
 769         int len0;
 770         unsigned int i;
 771         u32 config0;
 772
 773         if (pmap == 8)
 774                 pmap = (1 << 4);
 775
 776         skb_walk_frags(skb, skb1)
 777                 nr_desc++;
 778
 779         eth_schedule_poll(sw);
 780         spin_lock_bh(&tx_lock);
 781         if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
 782                 spin_unlock_bh(&tx_lock);
 783                 return NETDEV_TX_BUSY;
 784         }
 785
 786         index = index0 = tx_ring->cur_index;
 787         index_last = (index0 + nr_desc) % TX_DESCS;
 788         tx_ring->cur_index = (index_last + 1) % TX_DESCS;
 789
 790         spin_unlock_bh(&tx_lock);
 791
 792         config0 = FORCE_ROUTE;
 793         if (skb->ip_summed == CHECKSUM_PARTIAL)
 794                 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
 795
 796         len0 = skb->len;
 797
 798         /* fragments */
 799         for (i = 0; i < nr_frags; i++) {
 800                 struct skb_frag_struct *frag;
 801                 void *addr;
 802
 803                 index = (index + 1) % TX_DESCS;
 804
 805                 frag = &skb_shinfo(skb)->frags[i];
 806                 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
 807
 808                 eth_set_desc(tx_ring, index, index_last, addr, frag->size,
 809                              config0, pmap);
 810         }
 811
 812         if (nr_frags)
 813                 len0 = skb->len - skb->data_len;
 814
 815         skb_walk_frags(skb, skb1) {
 816                 index = (index + 1) % TX_DESCS;
 817                 len0 -= skb1->len;
 818
 819                 eth_set_desc(tx_ring, index, index_last, skb1->data, skb1->len,
 820                              config0, pmap);
 821         }
 822
 823         tx_ring->buff_tab[index0] = skb;
 824         eth_set_desc(tx_ring, index0, index_last, skb->data, len0,
 825                      config0 | FIRST_SEGMENT, pmap);
 826
 827         wmb();
 828
 829         spin_lock(&tx_lock);
 830         tx_ring->num_used += nr_desc + 1;
 831         spin_unlock(&tx_lock);
 832
 833         dev->stats.tx_packets++;
 834         dev->stats.tx_bytes += skb->len;
 835
 836         enable_tx_dma(sw);
 837
 838         return NETDEV_TX_OK;
 839 }
 840
 841 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 842 {
 843         struct port *port = netdev_priv(dev);
 844
 845         if (!netif_running(dev))
 846                 return -EINVAL;
 847         return phy_mii_ioctl(port->phydev, req, cmd);
 848 }
 849
 850 /* ethtool support */
 851
 852 static void cns3xxx_get_drvinfo(struct net_device *dev,
 853                                struct ethtool_drvinfo *info)
 854 {
 855         strcpy(info->driver, DRV_NAME);
 856         strcpy(info->bus_info, "internal");
 857 }
 858
 859 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 860 {
 861         struct port *port = netdev_priv(dev);
 862         return phy_ethtool_gset(port->phydev, cmd);
 863 }
 864
 865 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 866 {
 867         struct port *port = netdev_priv(dev);
 868         return phy_ethtool_sset(port->phydev, cmd);
 869 }
 870
 871 static int cns3xxx_nway_reset(struct net_device *dev)
 872 {
 873         struct port *port = netdev_priv(dev);
 874         return phy_start_aneg(port->phydev);
 875 }
 876
 877 static struct ethtool_ops cns3xxx_ethtool_ops = {
 878         .get_drvinfo = cns3xxx_get_drvinfo,
 879         .get_settings = cns3xxx_get_settings,
 880         .set_settings = cns3xxx_set_settings,
 881         .nway_reset = cns3xxx_nway_reset,
 882         .get_link = ethtool_op_get_link,
 883 };
 884
 885
 886 static int init_rings(struct sw *sw)
 887 {
 888         int i;
 889         struct _rx_ring *rx_ring = &sw->rx_ring;
 890         struct _tx_ring *tx_ring = &sw->tx_ring;
 891
 892         __raw_writel(0, &sw->regs->fs_dma_ctrl0);
 893         __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
 894         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 895         __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 896
 897         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 898
 899         if (!(rx_dma_pool = dma_pool_create(DRV_NAME, NULL,
 900                                             RX_POOL_ALLOC_SIZE, 32, 0)))
 901                 return -ENOMEM;
 902
 903         if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL,
 904                                               &rx_ring->phys_addr)))
 905                 return -ENOMEM;
 906         memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
 907
 908         /* Setup RX buffers */
 909         for (i = 0; i < RX_DESCS; i++) {
 910                 struct rx_desc *desc = &(rx_ring)->desc[i];
 911                 void *buf;
 912
 913                 buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL);
 914                 if (!buf)
 915                         return -ENOMEM;
 916
 917                 desc->sdl = RX_SEGMENT_MRU;
 918                 if (i == (RX_DESCS - 1))
 919                         desc->eor = 1;
 920                 desc->fsd = 1;
 921                 desc->lsd = 1;
 922
 923                 desc->sdp = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
 924                                            RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 925                 if (dma_mapping_error(NULL, desc->sdp))
 926                         return -EIO;
 927
 928                 rx_ring->buff_tab[i] = buf;
 929                 rx_ring->phys_tab[i] = desc->sdp;
 930                 desc->cown = 0;
 931         }
 932         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
 933         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
 934
 935         if (!(tx_dma_pool = dma_pool_create(DRV_NAME, NULL,
 936                                             TX_POOL_ALLOC_SIZE, 32, 0)))
 937                 return -ENOMEM;
 938
 939         if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL,
 940                                               &tx_ring->phys_addr)))
 941                 return -ENOMEM;
 942         memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
 943
 944         /* Setup TX buffers */
 945         for (i = 0; i < TX_DESCS; i++) {
 946                 struct tx_desc *desc = &(tx_ring)->desc[i];
 947                 tx_ring->buff_tab[i] = 0;
 948
 949                 if (i == (TX_DESCS - 1))
 950                         desc->eor = 1;
 951                 desc->cown = 1;
 952         }
 953         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
 954         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
 955
 956         return 0;
 957 }
 958
 959 static void destroy_rings(struct sw *sw)
 960 {
 961         int i;
 962         if (sw->rx_ring.desc) {
 963                 for (i = 0; i < RX_DESCS; i++) {
 964                         struct _rx_ring *rx_ring = &sw->rx_ring;
 965                         struct rx_desc *desc = &(rx_ring)->desc[i];
 966                         struct sk_buff *skb = sw->rx_ring.buff_tab[i];
 967
 968                         if (!skb)
 969                                 continue;
 970
 971                         dma_unmap_single(NULL, desc->sdp, RX_SEGMENT_MRU,
 972                                          DMA_FROM_DEVICE);
 973                         dev_kfree_skb(skb);
 974                 }
 975                 dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr);
 976                 dma_pool_destroy(rx_dma_pool);
 977                 rx_dma_pool = 0;
 978                 sw->rx_ring.desc = 0;
 979         }
 980         if (sw->tx_ring.desc) {
 981                 for (i = 0; i < TX_DESCS; i++) {
 982                         struct _tx_ring *tx_ring = &sw->tx_ring;
 983                         struct tx_desc *desc = &(tx_ring)->desc[i];
 984                         struct sk_buff *skb = sw->tx_ring.buff_tab[i];
 985                         if (skb) {
 986                                 dma_unmap_single(NULL, desc->sdp,
 987                                         skb->len, DMA_TO_DEVICE);
 988                                 dev_kfree_skb(skb);
 989                         }
 990                 }
 991                 dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr);
 992                 dma_pool_destroy(tx_dma_pool);
 993                 tx_dma_pool = 0;
 994                 sw->tx_ring.desc = 0;
 995         }
 996 }
 997
 998 static int eth_open(struct net_device *dev)
 999 {
1000         struct port *port = netdev_priv(dev);
1001         struct sw *sw = port->sw;
1002         u32 temp;
1003
1004         port->speed = 0;        /* force "link up" message */
1005         phy_start(port->phydev);
1006
1007         netif_start_queue(dev);
1008
1009         if (!ports_open) {
1010                 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
1011                 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
1012                 napi_enable(&sw->napi);
1013                 netif_start_queue(napi_dev);
1014
1015                 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1016                                MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1017
1018                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1019                 temp &= ~(PORT_DISABLE);
1020                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1021
1022                 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1023                 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1024                 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1025
1026                 enable_rx_dma(sw);
1027         }
1028         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1029         temp &= ~(PORT_DISABLE);
1030         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1031
1032         ports_open++;
1033         netif_carrier_on(dev);
1034
1035         return 0;
1036 }
1037
1038 static int eth_close(struct net_device *dev)
1039 {
1040         struct port *port = netdev_priv(dev);
1041         struct sw *sw = port->sw;
1042         u32 temp;
1043
1044         ports_open--;
1045
1046         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1047         temp |= (PORT_DISABLE);
1048         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1049
1050         netif_stop_queue(dev);
1051
1052         phy_stop(port->phydev);
1053
1054         if (!ports_open) {
1055                 disable_irq(sw->rx_irq);
1056                 free_irq(sw->rx_irq, napi_dev);
1057                 disable_irq(sw->stat_irq);
1058                 free_irq(sw->stat_irq, napi_dev);
1059                 napi_disable(&sw->napi);
1060                 netif_stop_queue(napi_dev);
1061                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1062                 temp |= (PORT_DISABLE);
1063                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1064
1065                 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1066                              &sw->regs->dma_auto_poll_cfg);
1067         }
1068
1069         netif_carrier_off(dev);
1070         return 0;
1071 }
1072
1073 static void eth_rx_mode(struct net_device *dev)
1074 {
1075         struct port *port = netdev_priv(dev);
1076         struct sw *sw = port->sw;
1077         u32 temp;
1078
1079         temp = __raw_readl(&sw->regs->mac_glob_cfg);
1080
1081         if (dev->flags & IFF_PROMISC) {
1082                 if (port->id == 3)
1083                         temp |= ((1 << 2) << PROMISC_OFFSET);
1084                 else
1085                         temp |= ((1 << port->id) << PROMISC_OFFSET);
1086         } else {
1087                 if (port->id == 3)
1088                         temp &= ~((1 << 2) << PROMISC_OFFSET);
1089                 else
1090                         temp &= ~((1 << port->id) << PROMISC_OFFSET);
1091         }
1092         __raw_writel(temp, &sw->regs->mac_glob_cfg);
1093 }
1094
1095 static int eth_set_mac(struct net_device *netdev, void *p)
1096 {
1097         struct port *port = netdev_priv(netdev);
1098         struct sw *sw = port->sw;
1099         struct sockaddr *addr = p;
1100         u32 cycles = 0;
1101
1102         if (!is_valid_ether_addr(addr->sa_data))
1103                 return -EADDRNOTAVAIL;
1104
1105         /* Invalidate old ARL Entry */
1106         if (port->id == 3)
1107                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1108         else
1109                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1110         __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1111                         (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1112                         &sw->regs->arl_ctrl[1]);
1113
1114         __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1115                         (1 << 1)),
1116                         &sw->regs->arl_ctrl[2]);
1117         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1118
1119         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1120                         && cycles < 5000) {
1121                 udelay(1);
1122                 cycles++;
1123         }
1124
1125         cycles = 0;
1126         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1127
1128         if (port->id == 3)
1129                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1130         else
1131                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1132         __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1133                         (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1134                         &sw->regs->arl_ctrl[1]);
1135
1136         __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1137                         (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1138         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1139
1140         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1141                 && cycles < 5000) {
1142                 udelay(1);
1143                 cycles++;
1144         }
1145         return 0;
1146 }
1147
1148 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1149 {
1150         if (new_mtu > MAX_MTU)
1151                 return -EINVAL;
1152
1153         dev->mtu = new_mtu;
1154         return 0;
1155 }
1156
1157 static const struct net_device_ops cns3xxx_netdev_ops = {
1158         .ndo_open = eth_open,
1159         .ndo_stop = eth_close,
1160         .ndo_start_xmit = eth_xmit,
1161         .ndo_set_rx_mode = eth_rx_mode,
1162         .ndo_do_ioctl = eth_ioctl,
1163         .ndo_change_mtu = cns3xxx_change_mtu,
1164         .ndo_set_mac_address = eth_set_mac,
1165         .ndo_validate_addr = eth_validate_addr,
1166 };
1167
1168 static int eth_init_one(struct platform_device *pdev)
1169 {
1170         int i;
1171         struct port *port;
1172         struct sw *sw;
1173         struct net_device *dev;
1174         struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1175         char phy_id[MII_BUS_ID_SIZE + 3];
1176         int err;
1177         u32 temp;
1178         struct resource *res;
1179         void __iomem *regs;
1180
1181         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182         regs = devm_ioremap_resource(&pdev->dev, res);
1183         if (IS_ERR(regs))
1184                 return PTR_ERR(regs);
1185
1186         err = cns3xxx_mdio_register(regs);
1187         if (err)
1188                 return err;
1189
1190         if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1191                 err = -ENOMEM;
1192                 goto err_remove_mdio;
1193         }
1194
1195         strcpy(napi_dev->name, "switch%d");
1196         napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1197
1198         SET_NETDEV_DEV(napi_dev, &pdev->dev);
1199         sw = netdev_priv(napi_dev);
1200         memset(sw, 0, sizeof(struct sw));
1201         sw->regs = regs;
1202
1203         sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1204         sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1205
1206         temp = __raw_readl(&sw->regs->phy_auto_addr);
1207         temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1208         __raw_writel(temp, &sw->regs->phy_auto_addr);
1209
1210         for (i = 0; i < 4; i++) {
1211                 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1212                 temp |= (PORT_DISABLE);
1213                 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1214         }
1215
1216         temp = PORT_DISABLE;
1217         __raw_writel(temp, &sw->regs->mac_cfg[2]);
1218
1219         temp = __raw_readl(&sw->regs->vlan_cfg);
1220         temp |= NIC_MODE | VLAN_UNAWARE;
1221         __raw_writel(temp, &sw->regs->vlan_cfg);
1222
1223         __raw_writel(UNKNOWN_VLAN_TO_CPU |
1224                      CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1225
1226         if ((err = init_rings(sw)) != 0) {
1227                 destroy_rings(sw);
1228                 err = -ENOMEM;
1229                 goto err_free;
1230         }
1231         platform_set_drvdata(pdev, napi_dev);
1232
1233         netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1234
1235         for (i = 0; i < 3; i++) {
1236                 if (!(plat->ports & (1 << i))) {
1237                         continue;
1238                 }
1239
1240                 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1241                         goto free_ports;
1242                 }
1243
1244                 port = netdev_priv(dev);
1245                 port->netdev = dev;
1246                 if (i == 2)
1247                         port->id = 3;
1248                 else
1249                         port->id = i;
1250                 port->sw = sw;
1251
1252                 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1253                 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1254                 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1255
1256                 dev->netdev_ops = &cns3xxx_netdev_ops;
1257                 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1258                 dev->tx_queue_len = 1000;
1259                 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1260
1261                 switch_port_tab[port->id] = port;
1262                 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1263
1264                 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1265                 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1266                         PHY_INTERFACE_MODE_RGMII);
1267                 if ((err = IS_ERR(port->phydev))) {
1268                         switch_port_tab[port->id] = 0;
1269                         free_netdev(dev);
1270                         goto free_ports;
1271                 }
1272
1273                 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1274
1275                 if ((err = register_netdev(dev))) {
1276                         phy_disconnect(port->phydev);
1277                         switch_port_tab[port->id] = 0;
1278                         free_netdev(dev);
1279                         goto free_ports;
1280                 }
1281
1282                 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1283                 netif_carrier_off(dev);
1284                 dev = 0;
1285         }
1286
1287         return 0;
1288
1289 free_ports:
1290         err = -ENOMEM;
1291         for (--i; i >= 0; i--) {
1292                 if (switch_port_tab[i]) {
1293                         port = switch_port_tab[i];
1294                         dev = port->netdev;
1295                         unregister_netdev(dev);
1296                         phy_disconnect(port->phydev);
1297                         switch_port_tab[i] = 0;
1298                         free_netdev(dev);
1299                 }
1300         }
1301 err_free:
1302         free_netdev(napi_dev);
1303 err_remove_mdio:
1304         cns3xxx_mdio_remove();
1305         return err;
1306 }
1307
1308 static int eth_remove_one(struct platform_device *pdev)
1309 {
1310         struct net_device *dev = platform_get_drvdata(pdev);
1311         struct sw *sw = netdev_priv(dev);
1312         int i;
1313         destroy_rings(sw);
1314
1315         for (i = 3; i >= 0; i--) {
1316                 if (switch_port_tab[i]) {
1317                         struct port *port = switch_port_tab[i];
1318                         struct net_device *dev = port->netdev;
1319                         unregister_netdev(dev);
1320                         phy_disconnect(port->phydev);
1321                         switch_port_tab[i] = 0;
1322                         free_netdev(dev);
1323                 }
1324         }
1325
1326         free_netdev(napi_dev);
1327         cns3xxx_mdio_remove();
1328
1329         return 0;
1330 }
1331
1332 static struct platform_driver cns3xxx_eth_driver = {
1333         .driver.name    = DRV_NAME,
1334         .probe          = eth_init_one,
1335         .remove         = eth_remove_one,
1336 };
1337
1338 static int __init eth_init_module(void)
1339 {
1340         return platform_driver_register(&cns3xxx_eth_driver);
1341 }
1342
1343 static void __exit eth_cleanup_module(void)
1344 {
1345         platform_driver_unregister(&cns3xxx_eth_driver);
1346 }
1347
1348 module_init(eth_init_module);
1349 module_exit(eth_cleanup_module);
1350
1351 MODULE_AUTHOR("Chris Lang");
1352 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1353 MODULE_LICENSE("GPL v2");
1354 MODULE_ALIAS("platform:cns3xxx_eth");