2 * linux/arch/arm/mach-cns3xxx/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
5 * Copyright 2012 Gateworks Corporation
6 * Chris Lang <clang@gateworks.com>
7 * Tim Harvey <tharvey@gateworks.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/gic.h>
25 #include <asm/smp_scu.h>
26 #include <asm/unified.h>
29 #include <mach/cns3xxx.h>
31 static struct fiq_handler fh = {
35 static unsigned int fiq_buffer[8];
37 #define FIQ_ENABLED 0x80000000
38 #define FIQ_GENERATE 0x00010000
39 #define CNS3XXX_MAP_AREA 0x01000000
40 #define CNS3XXX_UNMAP_AREA 0x02000000
41 #define CNS3XXX_FLUSH_RANGE 0x03000000
43 extern void cns3xxx_secondary_startup(void);
44 extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
45 extern unsigned int fiq_number[2];
46 extern struct cpu_cache_fns cpu_cache;
47 struct cpu_cache_fns cpu_cache_save;
49 #define SCU_CPU_STATUS 0x08
50 static void __iomem *scu_base;
53 * control for which core is the next to come out of the secondary
56 volatile int __cpuinitdata pen_release = -1;
58 static void __init cns3xxx_set_fiq_regs(void)
60 struct pt_regs FIQ_regs;
61 unsigned int cpu = smp_processor_id();
64 FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
65 FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
67 FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
68 FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
70 set_fiq_regs(&FIQ_regs);
73 static void __init cns3xxx_init_fiq(void)
75 void *fiqhandler_start;
76 unsigned int fiqhandler_length;
79 fiqhandler_start = &cns3xxx_fiq_start;
80 fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
88 set_fiq_handler(fiqhandler_start, fiqhandler_length);
89 fiq_buffer[0] = (unsigned int)&fiq_number[0];
91 fiq_buffer[4] = (unsigned int)&fiq_number[1];
97 * Write pen_release in a way that is guaranteed to be visible to all
98 * observers, irrespective of whether they're taking part in coherency
99 * or not. This is necessary for the hotplug code to work reliably.
101 static void __cpuinit write_pen_release(int val)
105 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
106 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
109 static DEFINE_SPINLOCK(boot_lock);
111 void __cpuinit platform_secondary_init(unsigned int cpu)
114 * if any interrupts are already enabled for the primary
115 * core (e.g. timer irq), then they will not have been enabled
118 gic_secondary_init(0);
121 * Setup Secondary Core FIQ regs
123 cns3xxx_set_fiq_regs();
126 * let the primary processor know we're out of the
127 * pen, then head off into the C entry point
129 write_pen_release(-1);
132 * Fixup DMA Operations
135 cpu_cache.dma_map_area = (void *)smp_dma_map_area;
136 cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
137 cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
140 * Synchronise with the boot thread.
142 spin_lock(&boot_lock);
143 spin_unlock(&boot_lock);
146 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
148 unsigned long timeout;
151 * Set synchronisation state between this boot processor
152 * and the secondary one
154 spin_lock(&boot_lock);
157 * The secondary processor is waiting to be released from
158 * the holding pen - release it, then wait for it to flag
159 * that it has been released by resetting pen_release.
161 * Note that "pen_release" is the hardware CPU ID, whereas
162 * "cpu" is Linux's internal ID.
164 write_pen_release(cpu);
167 * Send the secondary CPU a soft interrupt, thereby causing
168 * the boot monitor to read the system wide flags register,
169 * and branch to the address found there.
171 gic_raise_softirq(cpumask_of(cpu), 1);
173 timeout = jiffies + (1 * HZ);
174 while (time_before(jiffies, timeout)) {
176 if (pen_release == -1)
183 * now the secondary core is starting up let it run its
184 * calibrations, then wait for it to finish
186 spin_unlock(&boot_lock);
188 return pen_release != -1 ? -ENOSYS : 0;
192 * Initialise the CPU possible map early - this describes the CPUs
193 * which may be present or become present in the system.
195 void __init smp_init_cpus(void)
197 unsigned int i, ncores;
200 scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
202 /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
203 * used in scu_get_core_count
205 status = __raw_readl(scu_base + SCU_CPU_STATUS);
206 for (i = 0; i < NR_CPUS+1; i++) {
207 if (((status >> (i*2)) & 0x3) == 0)
208 set_cpu_possible(i, true);
214 set_smp_cross_call(gic_raise_softirq);
217 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
222 * Initialise the present map, which describes the set of CPUs
223 * actually populated at the present time.
225 for (i = 0; i < max_cpus; i++) {
226 set_cpu_present(i, true);
232 scu_enable(scu_base);
235 * Write the address of secondary startup into the
236 * system-wide flags register. The boot monitor waits
237 * until it receives a soft interrupt, and then the
238 * secondary CPU branches to this address.
240 __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
241 (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
244 * Setup FIQ's for main cpu
247 cns3xxx_set_fiq_regs();
248 memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
252 static inline unsigned long cns3xxx_cpu_id(void)
257 " mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
258 : "=r" (cpu) : : "memory", "cc");
262 void smp_dma_map_area(const void *addr, size_t size, int dir)
266 raw_local_irq_save(flags);
267 cpu = cns3xxx_cpu_id();
269 fiq_buffer[1] = (unsigned int)addr;
270 fiq_buffer[2] = size;
271 fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
273 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
275 cpu_cache_save.dma_map_area(addr, size, dir);
276 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
279 fiq_buffer[5] = (unsigned int)addr;
280 fiq_buffer[6] = size;
281 fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
283 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
285 cpu_cache_save.dma_map_area(addr, size, dir);
286 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
288 raw_local_irq_restore(flags);
291 void smp_dma_unmap_area(const void *addr, size_t size, int dir)
296 raw_local_irq_save(flags);
297 cpu = cns3xxx_cpu_id();
300 fiq_buffer[1] = (unsigned int)addr;
301 fiq_buffer[2] = size;
302 fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
304 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
306 cpu_cache_save.dma_unmap_area(addr, size, dir);
307 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
310 fiq_buffer[5] = (unsigned int)addr;
311 fiq_buffer[6] = size;
312 fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
314 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
316 cpu_cache_save.dma_unmap_area(addr, size, dir);
317 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
319 raw_local_irq_restore(flags);
322 void smp_dma_flush_range(const void *start, const void *end)
326 raw_local_irq_save(flags);
327 cpu = cns3xxx_cpu_id();
330 fiq_buffer[1] = (unsigned int)start;
331 fiq_buffer[2] = (unsigned int)end;
332 fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
334 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
336 cpu_cache_save.dma_flush_range(start, end);
337 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
340 fiq_buffer[5] = (unsigned int)start;
341 fiq_buffer[6] = (unsigned int)end;
342 fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
344 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
346 cpu_cache_save.dma_flush_range(start, end);
347 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
349 raw_local_irq_restore(flags);