target/linux/brcm63xx/patches-4.9/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch

   1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sun, 3 Jul 2011 15:00:38 +0200
   4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/bcm63xx/dev-flash.c                     |   35 +++++++++++++++++++-
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +
  10  2 files changed, 33 insertions(+), 2 deletions(-)
  11
  12 --- a/arch/mips/bcm63xx/dev-flash.c
  13 +++ b/arch/mips/bcm63xx/dev-flash.c
  14 @@ -17,6 +17,9 @@
  15  #include <linux/mtd/partitions.h>
  16  #include <linux/mtd/physmap.h>
  17  #include <linux/mtd/spi-nor.h>
  18 +#include <linux/of.h>
  19 +#include <linux/spi/spi.h>
  20 +#include <linux/spi/flash.h>
  21
  22  #include <bcm63xx_cpu.h>
  23  #include <bcm63xx_dev_flash.h>
  24 @@ -66,6 +69,41 @@ void __init bcm63xx_flash_force_phys_bas
  25         mtd_resources[0].end = end;
  26  }
  27
  28 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
  29 +       {
  30 +               .bus_num        = 0,
  31 +               .chip_select    = 0,
  32 +               .mode           = 0,
  33 +               .max_speed_hz   = 781000,
  34 +               .modalias       = "m25p80",
  35 +       },
  36 +};
  37 +
  38 +static void bcm63xx_of_update_spi_flash_speed(struct device_node *np,
  39 +                                              unsigned int new_hz)
  40 +{
  41 +       struct property *max_hz;
  42 +       __be32 *hz;
  43 +
  44 +       max_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL);
  45 +       if (!max_hz)
  46 +               return;
  47 +
  48 +       max_hz->name = kstrdup("spi-max-frequency", GFP_KERNEL);
  49 +       if (!max_hz->name) {
  50 +               kfree(max_hz);
  51 +               return;
  52 +       }
  53 +
  54 +       max_hz->value = max_hz + 1;
  55 +       max_hz->length = sizeof(*hz);
  56 +
  57 +       hz = max_hz->value;
  58 +       *hz = cpu_to_be32(new_hz);
  59 +
  60 +       of_update_property(np, max_hz);
  61 +}
  62 +
  63  static int __init bcm63xx_detect_flash_type(void)
  64  {
  65         u32 val;
  66 @@ -73,9 +111,15 @@ static int __init bcm63xx_detect_flash_t
  67         switch (bcm63xx_get_cpu_id()) {
  68         case BCM6318_CPU_ID:
  69                 /* only support serial flash */
  70 +               bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
  71                 return BCM63XX_FLASH_TYPE_SERIAL;
  72         case BCM6328_CPU_ID:
  73                 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
  74 +               if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
  75 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
  76 +               else
  77 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
  78 +
  79                 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  80                         return BCM63XX_FLASH_TYPE_SERIAL;
  81                 else
  82 @@ -94,12 +138,20 @@ static int __init bcm63xx_detect_flash_t
  83                         return BCM63XX_FLASH_TYPE_SERIAL;
  84         case BCM6362_CPU_ID:
  85                 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
  86 +               if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
  87 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
  88 +               else
  89 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
  90 +
  91                 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
  92                         return BCM63XX_FLASH_TYPE_SERIAL;
  93                 else
  94                         return BCM63XX_FLASH_TYPE_NAND;
  95         case BCM6368_CPU_ID:
  96                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
  97 +               if (val & STRAPBUS_6368_SPI_CLK_FAST)
  98 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
  99 +
 100                 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
 101                 case STRAPBUS_6368_BOOT_SEL_NAND:
 102                         return BCM63XX_FLASH_TYPE_NAND;
 103 @@ -110,6 +162,11 @@ static int __init bcm63xx_detect_flash_t
 104                 }
 105         case BCM63268_CPU_ID:
 106                 val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
 107 +               if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
 108 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
 109 +               else
 110 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
 111 +
 112                 if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
 113                         return BCM63XX_FLASH_TYPE_SERIAL;
 114                 else
 115 @@ -176,6 +233,7 @@ void __init bcm63xx_flash_detect(void)
 116
 117  int __init bcm63xx_flash_register(void)
 118  {
 119 +       struct device_node *np;
 120         u32 val;
 121
 122         switch (flash_type) {
 123 @@ -195,8 +253,14 @@ int __init bcm63xx_flash_register(void)
 124
 125                 return platform_device_register(&mtd_dev);
 126         case BCM63XX_FLASH_TYPE_SERIAL:
 127 -               pr_warn("unsupported serial flash detected\n");
 128 -               return -ENODEV;
 129 +               np = of_find_compatible_node(NULL, NULL, "jedec,spi-nor");
 130 +               if (np) {
 131 +                       bcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz);
 132 +                       of_node_put(np);
 133 +                       return 0;
 134 +               } else {
 135 +                       return -ENODEV;
 136 +               }
 137         case BCM63XX_FLASH_TYPE_NAND:
 138                 pr_warn("unsupported NAND flash detected\n");
 139                 return -ENODEV;
 140 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 141 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 142 @@ -708,6 +708,7 @@
 143  #define GPIO_STRAPBUS_REG              0x40
 144  #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
 145  #define STRAPBUS_6358_BOOT_SEL_SERIAL  (0 << 1)
 146 +#define STRAPBUS_6368_SPI_CLK_FAST     (1 << 6)
 147  #define STRAPBUS_6368_BOOT_SEL_MASK    0x3
 148  #define STRAPBUS_6368_BOOT_SEL_NAND    0
 149  #define STRAPBUS_6368_BOOT_SEL_SERIAL  1
 150 @@ -1564,6 +1565,7 @@
 151  #define IDDQ_CTRL_63268_USBH           (1 << 4)
 152
 153  #define MISC_STRAPBUS_6328_REG         0x240
 154 +#define STRAPBUS_6328_HSSPI_CLK_FAST   (1 << 4)
 155  #define STRAPBUS_6328_FCVO_SHIFT       7
 156  #define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 157  #define STRAPBUS_6328_BOOT_SEL_SERIAL  (1 << 28)