target/linux/brcm63xx/patches-3.7/443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch

   1 From 1b0b5d325d0cc50cade62afd6a9416fb3cd1e658 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Mon, 7 Jan 2013 17:42:45 +0100
   4 Subject: [PATCH 69/72] 443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch
   5
   6 ---
   7  arch/mips/bcm63xx/dev-enet.c                       |   63 ++++++-
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h   |    3 +-
   9  .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h    |   88 +++++++++
  10  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   43 ++++-
  11  drivers/net/ethernet/broadcom/bcm63xx_enet.c       |  199 ++++++++++++--------
  12  drivers/net/ethernet/broadcom/bcm63xx_enet.h       |   15 ++
  13  6 files changed, 320 insertions(+), 91 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/dev-enet.c
  16 +++ b/arch/mips/bcm63xx/dev-enet.c
  17 @@ -9,10 +9,44 @@
  18  #include <linux/init.h>
  19  #include <linux/kernel.h>
  20  #include <linux/platform_device.h>
  21 +#include <linux/export.h>
  22  #include <bcm63xx_dev_enet.h>
  23  #include <bcm63xx_io.h>
  24  #include <bcm63xx_regs.h>
  25
  26 +#ifdef BCMCPU_RUNTIME_DETECT
  27 +static const unsigned long bcm6xxx_regs_enetdmac[] = {
  28 +       [ENETDMAC_CHANCFG]      = ENETDMAC_CHANCFG_REG,
  29 +       [ENETDMAC_IR]           = ENETDMAC_IR_REG,
  30 +       [ENETDMAC_IRMASK]       = ENETDMAC_IRMASK_REG,
  31 +       [ENETDMAC_MAXBURST]     = ENETDMAC_MAXBURST_REG,
  32 +};
  33 +
  34 +static const unsigned long bcm6345_regs_enetdmac[] = {
  35 +       [ENETDMAC_CHANCFG]      = ENETDMA_6345_CHANCFG_REG,
  36 +       [ENETDMAC_IR]           = ENETDMA_6345_IR_REG,
  37 +       [ENETDMAC_IRMASK]       = ENETDMA_6345_IRMASK_REG,
  38 +       [ENETDMAC_MAXBURST]     = ENETDMA_6345_MAXBURST_REG,
  39 +       [ENETDMAC_BUFALLOC]     = ENETDMA_6345_BUFALLOC_REG,
  40 +       [ENETDMAC_RSTART]       = ENETDMA_6345_RSTART_REG,
  41 +       [ENETDMAC_FC]           = ENETDMA_6345_FC_REG,
  42 +       [ENETDMAC_LEN]          = ENETDMA_6345_LEN_REG,
  43 +};
  44 +
  45 +const unsigned long *bcm63xx_regs_enetdmac;
  46 +EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
  47 +
  48 +static __init void bcm63xx_enetdmac_regs_init(void)
  49 +{
  50 +       if (BCMCPU_IS_6345())
  51 +               bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
  52 +       else
  53 +               bcm63xx_regs_enetdmac = bcm6xxx_regs_enetdmac;
  54 +}
  55 +#else
  56 +static __init void bcm63xx_enetdmac_regs_init(void) { }
  57 +#endif
  58 +
  59  static struct resource shared_res[] = {
  60         {
  61                 .start          = -1, /* filled at runtime */
  62 @@ -137,12 +171,19 @@ static int __init register_shared(void)
  63         if (shared_device_registered)
  64                 return 0;
  65
  66 +       bcm63xx_enetdmac_regs_init();
  67 +
  68         shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
  69         shared_res[0].end = shared_res[0].start;
  70 -       shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
  71 +       if (BCMCPU_IS_6345())
  72 +               shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
  73 +       else
  74 +               shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
  75
  76         if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
  77                 chan_count = 32;
  78 +       else if (BCMCPU_IS_6345())
  79 +               chan_count = 8;
  80         else
  81                 chan_count = 16;
  82
  83 @@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int uni
  84         if (unit > 1)
  85                 return -ENODEV;
  86
  87 -       if (unit == 1 && BCMCPU_IS_6338())
  88 +       if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
  89                 return -ENODEV;
  90
  91         ret = register_shared();
  92 @@ -213,6 +254,20 @@ int __init bcm63xx_enet_register(int uni
  93                 dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
  94         }
  95
  96 +       dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
  97 +       dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
  98 +       if (BCMCPU_IS_6345()) {
  99 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
 100 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
 101 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
 102 +               dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
 103 +               dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
 104 +               dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
 105 +               dpd->dma_no_sram = 1;
 106 +               dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
 107 +       } else
 108 +               dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
 109 +
 110         ret = platform_device_register(pdev);
 111         if (ret)
 112                 return ret;
 113 @@ -248,6 +303,10 @@ bcm63xx_enetsw_register(const struct bcm
 114         else if (BCMCPU_IS_6368())
 115                 enetsw_pd.num_ports = ENETSW_PORTS_6368;
 116
 117 +       enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
 118 +       enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
 119 +       enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
 120 +
 121         ret = platform_device_register(&bcm63xx_enetsw_device);
 122         if (ret)
 123                 return ret;
 124 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 125 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 126 @@ -175,6 +175,7 @@ enum bcm63xx_regs_set {
 127  #define BCM_6368_RSET_SPI_SIZE         1804
 128  #define RSET_ENET_SIZE                 2048
 129  #define RSET_ENETDMA_SIZE              256
 130 +#define RSET_6345_ENETDMA_SIZE         64
 131  #define RSET_ENETDMAC_SIZE(chans)      (16 * (chans))
 132  #define RSET_ENETDMAS_SIZE(chans)      (16 * (chans))
 133  #define RSET_ENETSW_SIZE               65536
 134 @@ -305,7 +306,7 @@ enum bcm63xx_regs_set {
 135  #define BCM_6345_USBDMA_BASE           (0xfffe2800)
 136  #define BCM_6345_ENET0_BASE            (0xfffe1800)
 137  #define BCM_6345_ENETDMA_BASE          (0xfffe2800)
 138 -#define BCM_6345_ENETDMAC_BASE         (0xfffe2900)
 139 +#define BCM_6345_ENETDMAC_BASE         (0xfffe2840)
 140  #define BCM_6345_ENETDMAS_BASE         (0xfffe2a00)
 141  #define BCM_6345_ENETSW_BASE           (0xdeadbeef)
 142  #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
 143 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 144 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 145 @@ -4,6 +4,8 @@
 146  #include <linux/if_ether.h>
 147  #include <linux/init.h>
 148
 149 +#include <bcm63xx_regs.h>
 150 +
 151  /*
 152   * on board ethernet platform data
 153   */
 154 @@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
 155                                           int phy_id, int reg),
 156                           void (*mii_write)(struct net_device *dev,
 157                                             int phy_id, int reg, int val));
 158 +
 159 +       /* DMA channel enable mask */
 160 +       u32 dma_chan_en_mask;
 161 +
 162 +       /* DMA channel interrupt mask */
 163 +       u32 dma_chan_int_mask;
 164 +
 165 +       /* Set to one if DMA engine has *no* SRAM */
 166 +       unsigned int dma_no_sram;
 167 +
 168 +       /* DMA channel register width */
 169 +       unsigned int dma_chan_width;
 170 +
 171 +       /* DMA descriptor shift */
 172 +       unsigned int dma_desc_shift;
 173  };
 174
 175  /*
 176 @@ -64,6 +81,15 @@ struct bcm63xx_enetsw_platform_data {
 177         char mac_addr[ETH_ALEN];
 178         int num_ports;
 179         struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
 180 +
 181 +       /* DMA channel enable mask */
 182 +       u32 dma_chan_en_mask;
 183 +
 184 +       /* DMA channel interrupt mask */
 185 +       u32 dma_chan_int_mask;
 186 +
 187 +       /* DMA channel register width */
 188 +       unsigned int dma_chan_width;
 189  };
 190
 191  int __init bcm63xx_enet_register(int unit,
 192 @@ -72,4 +98,66 @@ int __init bcm63xx_enet_register(int uni
 193  int __init
 194  bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
 195
 196 +enum bcm63xx_regs_enetdmac {
 197 +       ENETDMAC_CHANCFG,
 198 +       ENETDMAC_IR,
 199 +       ENETDMAC_IRMASK,
 200 +       ENETDMAC_MAXBURST,
 201 +       ENETDMAC_BUFALLOC,
 202 +       ENETDMAC_RSTART,
 203 +       ENETDMAC_FC,
 204 +       ENETDMAC_LEN,
 205 +};
 206 +
 207 +static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
 208 +{
 209 +#ifdef BCMCPU_RUNTIME_DETECT
 210 +       extern const unsigned long *bcm63xx_regs_enetdmac;
 211 +
 212 +       return bcm63xx_regs_enetdmac[reg];
 213 +#else
 214 +#ifdef CONFIG_BCM63XX_CPU_6345
 215 +       switch (reg) {
 216 +       case ENETDMAC_CHANCFG:
 217 +               return ENETDMA_6345_CHANCFG_REG;
 218 +       case ENETDMAC_IR:
 219 +               return ENETDMA_6345_IR_REG;
 220 +       case ENETDMAC_IRMASK:
 221 +               return ENETDMA_6345_IRMASK_REG;
 222 +       case ENETDMAC_MAXBURST:
 223 +               return ENETDMA_6345_MAXBURST_REG;
 224 +       case ENETDMAC_BUFALLOC:
 225 +               return ENETDMA_6345_BUFALLOC_REG;
 226 +       case ENETDMAC_RSTART:
 227 +               return ENETDMA_6345_RSTART_REG;
 228 +       case ENETDMAC_FC:
 229 +               return ENETDMA_6345_FC_REG;
 230 +       case ENETDMAC_LEN:
 231 +               return ENETDMA_6345_LEN_REG;
 232 +       }
 233 +#endif
 234 +#if defined(CONFIG_BCM6XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348) \
 235 +       defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) \
 236 +       defined(CONFIG_BCM63XX_CPU_6368)
 237 +       switch (reg) {
 238 +       case ENETDMAC_CHANCFG:
 239 +               return ENETDMAC_CHANCFG_REG;
 240 +       case ENETDMAC_IR:
 241 +               return ENETDMAC_IR_REG;
 242 +       case ENETDMAC_IRMASK:
 243 +               return ENETDMAC_IRMASK_REG;
 244 +       case ENETDMAC_MAXBURST:
 245 +               return ENETDMAC_MAXBURST_REG;
 246 +       case ENETDMAC_BUFALLOC:
 247 +       case ENETDMAC_RSTART:
 248 +       case ENETDMAC_FC:
 249 +       case ENETDMAC_LEN:
 250 +               return 0;
 251 +       }
 252 +#endif
 253 +#endif
 254 +       return 0;
 255 +}
 256 +
 257 +
 258  #endif /* ! BCM63XX_DEV_ENET_H_ */
 259 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 260 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 261 @@ -725,6 +725,8 @@
 262  /*************************************************************************
 263   * _REG relative to RSET_ENETDMA
 264   *************************************************************************/
 265 +#define ENETDMA_CHAN_WIDTH             0x10
 266 +#define ENETDMA_6345_CHAN_WIDTH                0x40
 267
 268  /* Controller Configuration Register */
 269  #define ENETDMA_CFG_REG                        (0x0)
 270 @@ -780,31 +782,56 @@
 271  /* State Ram Word 4 */
 272  #define ENETDMA_SRAM4_REG(x)           (0x20c + (x) * 0x10)
 273
 274 +/* Broadcom 6345 ENET DMA definitions */
 275 +#define ENETDMA_6345_CHANCFG_REG       (0x00)
 276 +
 277 +#define ENETDMA_6345_MAXBURST_REG      (0x40)
 278 +
 279 +#define ENETDMA_6345_RSTART_REG                (0x08)
 280 +
 281 +#define ENETDMA_6345_LEN_REG           (0x0C)
 282 +
 283 +#define ENETDMA_6345_IR_REG            (0x14)
 284 +
 285 +#define ENETDMA_6345_IRMASK_REG                (0x18)
 286 +
 287 +#define ENETDMA_6345_FC_REG            (0x1C)
 288 +
 289 +#define ENETDMA_6345_BUFALLOC_REG      (0x20)
 290 +
 291 +/* Shift down for EOP, SOP and WRAP bits */
 292 +#define ENETDMA_6345_DESC_SHIFT                (3)
 293
 294  /*************************************************************************
 295   * _REG relative to RSET_ENETDMAC
 296   *************************************************************************/
 297
 298  /* Channel Configuration register */
 299 -#define ENETDMAC_CHANCFG_REG(x)                ((x) * 0x10)
 300 +#define ENETDMAC_CHANCFG_REG           (0x0)
 301  #define ENETDMAC_CHANCFG_EN_SHIFT      0
 302  #define ENETDMAC_CHANCFG_EN_MASK       (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 303  #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
 304  #define ENETDMAC_CHANCFG_PKTHALT_MASK  (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 305  #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
 306  #define ENETDMAC_CHANCFG_BUFHALT_MASK  (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 307 +#define ENETDMAC_CHANCFG_CHAINING_SHIFT        2
 308 +#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
 309 +#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
 310 +#define ENETDMAC_CHANCFG_WRAP_EN_MASK  (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
 311 +#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT        4
 312 +#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 313
 314  /* Interrupt Control/Status register */
 315 -#define ENETDMAC_IR_REG(x)             (0x4 + (x) * 0x10)
 316 +#define ENETDMAC_IR_REG                        (0x4)
 317  #define ENETDMAC_IR_BUFDONE_MASK       (1 << 0)
 318  #define ENETDMAC_IR_PKTDONE_MASK       (1 << 1)
 319  #define ENETDMAC_IR_NOTOWNER_MASK      (1 << 2)
 320
 321  /* Interrupt Mask register */
 322 -#define ENETDMAC_IRMASK_REG(x)         (0x8 + (x) * 0x10)
 323 +#define ENETDMAC_IRMASK_REG            (0x8)
 324
 325  /* Maximum Burst Length */
 326 -#define ENETDMAC_MAXBURST_REG(x)       (0xc + (x) * 0x10)
 327 +#define ENETDMAC_MAXBURST_REG          (0xc)
 328
 329
 330  /*************************************************************************
 331 @@ -812,16 +839,16 @@
 332   *************************************************************************/
 333
 334  /* Ring Start Address register */
 335 -#define ENETDMAS_RSTART_REG(x)         ((x) * 0x10)
 336 +#define ENETDMAS_RSTART_REG            (0x0)
 337
 338  /* State Ram Word 2 */
 339 -#define ENETDMAS_SRAM2_REG(x)          (0x4 + (x) * 0x10)
 340 +#define ENETDMAS_SRAM2_REG             (0x4)
 341
 342  /* State Ram Word 3 */
 343 -#define ENETDMAS_SRAM3_REG(x)          (0x8 + (x) * 0x10)
 344 +#define ENETDMAS_SRAM3_REG             (0x8)
 345
 346  /* State Ram Word 4 */
 347 -#define ENETDMAS_SRAM4_REG(x)          (0xc + (x) * 0x10)
 348 +#define ENETDMAS_SRAM4_REG             (0xc)
 349
 350
 351  /*************************************************************************
 352 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 353 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 354 @@ -115,26 +115,28 @@ static inline void enet_dma_writel(struc
 355         bcm_writel(val, bcm_enet_shared_base[0] + off);
 356  }
 357
 358 -static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
 359 +static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 360  {
 361 -       return bcm_readl(bcm_enet_shared_base[1] + off);
 362 +       return bcm_readl(bcm_enet_shared_base[1] +
 363 +               (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
 364  }
 365
 366  static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 367 -                                      u32 val, u32 off)
 368 +                                      u32 val, u32 off, int chan)
 369  {
 370 -       bcm_writel(val, bcm_enet_shared_base[1] + off);
 371 +       bcm_writel(val, bcm_enet_shared_base[1] +
 372 +               (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
 373  }
 374
 375 -static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
 376 +static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 377  {
 378 -       return bcm_readl(bcm_enet_shared_base[2] + off);
 379 +       return bcm_readl(bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
 380  }
 381
 382  static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 383 -                                      u32 val, u32 off)
 384 +                                      u32 val, u32 off, int chan)
 385  {
 386 -       bcm_writel(val, bcm_enet_shared_base[2] + off);
 387 +       bcm_writel(val, bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
 388  }
 389
 390  /*
 391 @@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
 392                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 393                 len_stat |= DMADESC_OWNER_MASK;
 394                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 395 -                       len_stat |= DMADESC_WRAP_MASK;
 396 +                       len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 397                         priv->rx_dirty_desc = 0;
 398                 } else {
 399                         priv->rx_dirty_desc++;
 400 @@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
 401                 priv->rx_desc_count++;
 402
 403                 /* tell dma engine we allocated one buffer */
 404 -               enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 405 +               if (!priv->dma_no_sram)
 406 +                       enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 407 +               else
 408 +                       enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 409         }
 410
 411         /* If rx ring is still empty, set a timer to try allocating
 412 @@ -357,7 +362,8 @@ static int bcm_enet_receive_queue(struct
 413
 414                 /* if the packet does not have start of packet _and_
 415                  * end of packet flag set, then just recycle it */
 416 -               if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 417 +               if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 418 +                       (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 419                         dev->stats.rx_dropped++;
 420                         continue;
 421                 }
 422 @@ -418,8 +424,8 @@ static int bcm_enet_receive_queue(struct
 423                 bcm_enet_refill_rx(dev);
 424
 425                 /* kick rx dma */
 426 -               enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 427 -                                ENETDMAC_CHANCFG_REG(priv->rx_chan));
 428 +               enet_dmac_writel(priv, priv->dma_chan_en_mask,
 429 +                                        ENETDMAC_CHANCFG, priv->rx_chan);
 430         }
 431
 432         return processed;
 433 @@ -494,10 +500,10 @@ static int bcm_enet_poll(struct napi_str
 434         dev = priv->net_dev;
 435
 436         /* ack interrupts */
 437 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 438 -                        ENETDMAC_IR_REG(priv->rx_chan));
 439 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 440 -                        ENETDMAC_IR_REG(priv->tx_chan));
 441 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 442 +                        ENETDMAC_IR, priv->rx_chan);
 443 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 444 +                        ENETDMAC_IR, priv->tx_chan);
 445
 446         /* reclaim sent skb */
 447         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 448 @@ -516,10 +522,10 @@ static int bcm_enet_poll(struct napi_str
 449         napi_complete(napi);
 450
 451         /* restore rx/tx interrupt */
 452 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 453 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 454 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 455 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 456 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 457 +                        ENETDMAC_IRMASK, priv->rx_chan);
 458 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 459 +                        ENETDMAC_IRMASK, priv->tx_chan);
 460
 461         return rx_work_done;
 462  }
 463 @@ -562,8 +568,8 @@ static irqreturn_t bcm_enet_isr_dma(int
 464         priv = netdev_priv(dev);
 465
 466         /* mask rx/tx interrupts */
 467 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 468 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 469 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 470 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 471
 472         napi_schedule(&priv->napi);
 473
 474 @@ -624,14 +630,14 @@ static int bcm_enet_start_xmit(struct sk
 475                                        DMA_TO_DEVICE);
 476
 477         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 478 -       len_stat |= DMADESC_ESOP_MASK |
 479 +       len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 480                 DMADESC_APPEND_CRC |
 481                 DMADESC_OWNER_MASK;
 482
 483         priv->tx_curr_desc++;
 484         if (priv->tx_curr_desc == priv->tx_ring_size) {
 485                 priv->tx_curr_desc = 0;
 486 -               len_stat |= DMADESC_WRAP_MASK;
 487 +               len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 488         }
 489         priv->tx_desc_count--;
 490
 491 @@ -642,8 +648,8 @@ static int bcm_enet_start_xmit(struct sk
 492         wmb();
 493
 494         /* kick tx dma */
 495 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 496 -                        ENETDMAC_CHANCFG_REG(priv->tx_chan));
 497 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 498 +                                ENETDMAC_CHANCFG, priv->tx_chan);
 499
 500         /* stop queue if no more desc available */
 501         if (!priv->tx_desc_count)
 502 @@ -771,6 +777,9 @@ static void bcm_enet_set_flow(struct bcm
 503                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 504         enet_writel(priv, val, ENET_RXCFG_REG);
 505
 506 +       if (priv->dma_no_sram)
 507 +               return;
 508 +
 509         /* tx flow control (pause frame generation) */
 510         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 511         if (tx_en)
 512 @@ -886,8 +895,8 @@ static int bcm_enet_open(struct net_devi
 513
 514         /* mask all interrupts and request them */
 515         enet_writel(priv, 0, ENET_IRMASK_REG);
 516 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 517 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 518 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 519 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 520
 521         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 522         if (ret)
 523 @@ -966,8 +975,12 @@ static int bcm_enet_open(struct net_devi
 524         priv->rx_curr_desc = 0;
 525
 526         /* initialize flow control buffer allocation */
 527 -       enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 528 -                       ENETDMA_BUFALLOC_REG(priv->rx_chan));
 529 +       if (!priv->dma_no_sram)
 530 +               enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 531 +                               ENETDMA_BUFALLOC_REG(priv->rx_chan));
 532 +       else
 533 +               enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 534 +                               ENETDMAC_BUFALLOC, priv->rx_chan);
 535
 536         if (bcm_enet_refill_rx(dev)) {
 537                 dev_err(kdev, "cannot allocate rx skb queue\n");
 538 @@ -976,18 +989,30 @@ static int bcm_enet_open(struct net_devi
 539         }
 540
 541         /* write rx & tx ring addresses */
 542 -       enet_dmas_writel(priv, priv->rx_desc_dma,
 543 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 544 -       enet_dmas_writel(priv, priv->tx_desc_dma,
 545 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 546 +       if (!priv->dma_no_sram) {
 547 +               enet_dmas_writel(priv, priv->rx_desc_dma,
 548 +                                ENETDMAS_RSTART_REG, priv->rx_chan);
 549 +               enet_dmas_writel(priv, priv->tx_desc_dma,
 550 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 551 +       } else {
 552 +               enet_dmac_writel(priv, priv->rx_desc_dma,
 553 +                               ENETDMAC_RSTART, priv->rx_chan);
 554 +               enet_dmac_writel(priv, priv->tx_desc_dma,
 555 +                               ENETDMAC_RSTART, priv->tx_chan);
 556 +       }
 557
 558         /* clear remaining state ram for rx & tx channel */
 559 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 560 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 561 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 562 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 563 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 564 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 565 +       if (!priv->dma_no_sram) {
 566 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 567 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 568 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 569 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 570 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 571 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 572 +       } else {
 573 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
 574 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
 575 +       }
 576
 577         /* set max rx/tx length */
 578         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 579 @@ -995,18 +1020,24 @@ static int bcm_enet_open(struct net_devi
 580
 581         /* set dma maximum burst len */
 582         enet_dmac_writel(priv, priv->dma_maxburst,
 583 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 584 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 585         enet_dmac_writel(priv, priv->dma_maxburst,
 586 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 587 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 588
 589         /* set correct transmit fifo watermark */
 590         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 591
 592         /* set flow control low/high threshold to 1/3 / 2/3 */
 593 -       val = priv->rx_ring_size / 3;
 594 -       enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 595 -       val = (priv->rx_ring_size * 2) / 3;
 596 -       enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 597 +       if (!priv->dma_no_sram) {
 598 +               val = priv->rx_ring_size / 3;
 599 +               enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 600 +               val = (priv->rx_ring_size * 2) / 3;
 601 +               enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 602 +       } else {
 603 +               enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
 604 +               enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
 605 +               enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
 606 +       }
 607
 608         /* all set, enable mac and interrupts, start dma engine and
 609          * kick rx dma channel */
 610 @@ -1015,26 +1046,26 @@ static int bcm_enet_open(struct net_devi
 611         val |= ENET_CTL_ENABLE_MASK;
 612         enet_writel(priv, val, ENET_CTL_REG);
 613         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 614 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 615 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 616 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 617 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 618
 619         /* watch "mib counters about to overflow" interrupt */
 620         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 621         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 622
 623         /* watch "packet transferred" interrupt in rx and tx */
 624 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 625 -                        ENETDMAC_IR_REG(priv->rx_chan));
 626 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 627 -                        ENETDMAC_IR_REG(priv->tx_chan));
 628 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 629 +                        ENETDMAC_IR, priv->rx_chan);
 630 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 631 +                        ENETDMAC_IR, priv->tx_chan);
 632
 633         /* make sure we enable napi before rx interrupt  */
 634         napi_enable(&priv->napi);
 635
 636 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 637 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 638 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 639 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 640 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 641 +                        ENETDMAC_IRMASK, priv->rx_chan);
 642 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 643 +                        ENETDMAC_IRMASK, priv->tx_chan);
 644
 645         if (priv->has_phy)
 646                 phy_start(priv->phydev);
 647 @@ -1111,13 +1142,13 @@ static void bcm_enet_disable_dma(struct
 648  {
 649         int limit;
 650
 651 -       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
 652 +       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
 653
 654         limit = 1000;
 655         do {
 656                 u32 val;
 657
 658 -               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
 659 +               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
 660                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
 661                         break;
 662                 udelay(1);
 663 @@ -1144,8 +1175,8 @@ static int bcm_enet_stop(struct net_devi
 664
 665         /* mask all interrupts */
 666         enet_writel(priv, 0, ENET_IRMASK_REG);
 667 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 668 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 669 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 670 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 671
 672         /* make sure no mib update is scheduled */
 673         cancel_work_sync(&priv->mib_update_task);
 674 @@ -1757,6 +1788,11 @@ static int __devinit bcm_enet_probe(stru
 675                 priv->pause_tx = pd->pause_tx;
 676                 priv->force_duplex_full = pd->force_duplex_full;
 677                 priv->force_speed_100 = pd->force_speed_100;
 678 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 679 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 680 +               priv->dma_chan_width = pd->dma_chan_width;
 681 +               priv->dma_no_sram = pd->dma_no_sram;
 682 +               priv->dma_desc_shift = pd->dma_desc_shift;
 683         }
 684
 685         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
 686 @@ -2144,8 +2180,8 @@ static int bcm_enetsw_open(struct net_de
 687         kdev = &priv->pdev->dev;
 688
 689         /* mask all interrupts and request them */
 690 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 691 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 692 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 693 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 694
 695         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 696                           IRQF_DISABLED, dev->name, dev);
 697 @@ -2269,23 +2305,23 @@ static int bcm_enetsw_open(struct net_de
 698
 699         /* write rx & tx ring addresses */
 700         enet_dmas_writel(priv, priv->rx_desc_dma,
 701 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 702 +                        ENETDMAS_RSTART_REG, priv->rx_chan);
 703         enet_dmas_writel(priv, priv->tx_desc_dma,
 704 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 705 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 706
 707         /* clear remaining state ram for rx & tx channel */
 708 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 709 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 710 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 711 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 712 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 713 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 714 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 715 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 716 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 717 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 718 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 719 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 720
 721         /* set dma maximum burst len */
 722         enet_dmac_writel(priv, priv->dma_maxburst,
 723 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 724 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 725         enet_dmac_writel(priv, priv->dma_maxburst,
 726 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 727 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 728
 729         /* set flow control low/high threshold to 1/3 / 2/3 */
 730         val = priv->rx_ring_size / 3;
 731 @@ -2298,21 +2334,21 @@ static int bcm_enetsw_open(struct net_de
 732         wmb();
 733         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 734         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 735 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 736 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 737
 738         /* watch "packet transferred" interrupt in rx and tx */
 739         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 740 -                        ENETDMAC_IR_REG(priv->rx_chan));
 741 +                        ENETDMAC_IR, priv->rx_chan);
 742         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 743 -                        ENETDMAC_IR_REG(priv->tx_chan));
 744 +                        ENETDMAC_IR, priv->tx_chan);
 745
 746         /* make sure we enable napi before rx interrupt  */
 747         napi_enable(&priv->napi);
 748
 749         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 750 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 751 +                        ENETDMAC_IRMASK, priv->rx_chan);
 752         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 753 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 754 +                        ENETDMAC_IRMASK, priv->tx_chan);
 755
 756         netif_carrier_on(dev);
 757         netif_start_queue(dev);
 758 @@ -2419,8 +2455,8 @@ static int bcm_enetsw_stop(struct net_de
 759         del_timer_sync(&priv->rx_timeout);
 760
 761         /* mask all interrupts */
 762 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 763 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 764 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 765 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 766
 767         /* disable dma & mac */
 768         bcm_enet_disable_dma(priv, priv->tx_chan);
 769 @@ -2757,6 +2793,9 @@ static int __devinit bcm_enetsw_probe(st
 770                 memcpy(priv->used_ports, pd->used_ports,
 771                        sizeof (pd->used_ports));
 772                 priv->num_ports = pd->num_ports;
 773 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 774 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 775 +               priv->dma_chan_width = pd->dma_chan_width;
 776         }
 777
 778         ret = compute_hw_mtu(priv, dev->mtu);
 779 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 780 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 781 @@ -339,6 +339,21 @@ struct bcm_enet_priv {
 782         /* used to poll switch port state */
 783         struct timer_list swphy_poll;
 784         spinlock_t enetsw_mdio_lock;
 785 +
 786 +       /* dma channel enable mask */
 787 +       u32 dma_chan_en_mask;
 788 +
 789 +       /* dma channel interrupt mask */
 790 +       u32 dma_chan_int_mask;
 791 +
 792 +       /* dma engine has *no* internal SRAM */
 793 +       unsigned int dma_no_sram;
 794 +
 795 +       /* dma channel width */
 796 +       unsigned int dma_chan_width;
 797 +
 798 +       /* dma descriptor shift value */
 799 +       unsigned int dma_desc_shift;
 800  };
 801
 802  static inline int bcm_enet_port_is_rgmii(int portid)