1 From e9ad4456c6415b0d3adcbb41b8d34c9298dd28e4 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Mon, 21 Nov 2011 00:53:26 +0100
4 Subject: [PATCH 030/118] MIPS: BCM63XX: enable pcie for BCM6362
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
8 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 ++-
9 arch/mips/pci/pci-bcm63xx.c | 19 ++++++++++++++++---
10 2 files changed, 18 insertions(+), 4 deletions(-)
12 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
13 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
15 /*************************************************************************
16 * _REG relative to RSET_MISC
17 *************************************************************************/
18 -#define MISC_SERDES_CTRL_REG 0x0
19 +#define MISC_SERDES_CTRL_6328_REG 0x0
20 +#define MISC_SERDES_CTRL_6362_REG 0x4
21 #define SERDES_PCIE_EN (1 << 0)
22 #define SERDES_PCIE_EXD_EN (1 << 15)
24 --- a/arch/mips/pci/pci-bcm63xx.c
25 +++ b/arch/mips/pci/pci-bcm63xx.c
26 @@ -120,16 +120,28 @@ void __iomem *pci_iospace_start;
27 static void __init bcm63xx_reset_pcie(void)
34 + if (BCMCPU_IS_6328())
35 + mask = CKCTL_6328_PCIE_EN;
37 + mask = CKCTL_6362_PCIE_EN;
39 val = bcm_perf_readl(PERF_CKCTL_REG);
40 - val |= CKCTL_6328_PCIE_EN;
42 bcm_perf_writel(val, PERF_CKCTL_REG);
45 - val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
46 + if (BCMCPU_IS_6328())
47 + reg = MISC_SERDES_CTRL_6328_REG;
49 + reg = MISC_SERDES_CTRL_6362_REG;
51 + val = bcm_misc_readl(reg);
52 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
53 - bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
54 + bcm_misc_writel(val, reg);
56 /* reset the PCIe core */
57 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
58 @@ -325,6 +337,7 @@ static int __init bcm63xx_pci_init(void)
60 switch (bcm63xx_get_cpu_id()) {
62 + case BCM6362_CPU_ID:
63 return bcm63xx_register_pcie();