target/linux/brcm63xx/patches-3.7/312-MIPS-BCM63XX-add-basic-BCM6362-support.patch

   1 From 023660ed83daf4aebc54efd364906e5d641170a9 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Mon, 21 Nov 2011 00:48:52 +0100
   4 Subject: [PATCH 029/118] MIPS: BCM63XX: add basic BCM6362 support
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/bcm63xx/Kconfig                         |    4 +
   9  arch/mips/bcm63xx/boards/board_bcm963xx.c         |    2 +-
  10  arch/mips/bcm63xx/cpu.c                           |   52 +++++++-
  11  arch/mips/bcm63xx/irq.c                           |   19 +++
  12  arch/mips/bcm63xx/prom.c                          |    2 +
  13  arch/mips/bcm63xx/reset.c                         |   28 +++++
  14  arch/mips/bcm63xx/setup.c                         |    3 +
  15  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  139 +++++++++++++++++++++
  16  arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
  17  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   59 +++++++++
  18  arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    1 +
  19  11 files changed, 309 insertions(+), 2 deletions(-)
  20
  21 --- a/arch/mips/bcm63xx/Kconfig
  22 +++ b/arch/mips/bcm63xx/Kconfig
  23 @@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
  24         bool "support 6358 CPU"
  25         select HW_HAS_PCI
  26
  27 +config BCM63XX_CPU_6362
  28 +       bool "support 6362 CPU"
  29 +       select HW_HAS_PCI
  30 +
  31  config BCM63XX_CPU_6368
  32         bool "support 6368 CPU"
  33         select HW_HAS_PCI
  34 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
  35 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
  36 @@ -783,7 +783,7 @@ void __init board_prom_init(void)
  37         /* read base address of boot chip select (0)
  38          * 6328 does not have MPI but boots from a fixed address
  39          */
  40 -       if (BCMCPU_IS_6328())
  41 +       if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
  42                 val = 0x18000000;
  43         else {
  44                 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
  45 --- a/arch/mips/bcm63xx/cpu.c
  46 +++ b/arch/mips/bcm63xx/cpu.c
  47 @@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
  48
  49  };
  50
  51 +static const unsigned long bcm6362_regs_base[] = {
  52 +       __GEN_CPU_REGS_TABLE(6362)
  53 +};
  54 +
  55 +static const int bcm6362_irqs[] = {
  56 +       __GEN_CPU_IRQ_TABLE(6362)
  57 +
  58 +};
  59 +
  60  static const unsigned long bcm6368_regs_base[] = {
  61         __GEN_CPU_REGS_TABLE(6368)
  62  };
  63 @@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(voi
  64                 return (16 * 1000000 * n1 * n2) / m1;
  65         }
  66
  67 +       case BCM6362_CPU_ID:
  68 +       {
  69 +               unsigned int tmp, mips_pll_fcvo;
  70 +
  71 +               tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
  72 +               mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
  73 +                               >> STRAPBUS_6362_FCVO_SHIFT;
  74 +               switch (mips_pll_fcvo) {
  75 +               case 0x03:
  76 +               case 0x0b:
  77 +               case 0x13:
  78 +               case 0x1b:
  79 +                       return 240000000;
  80 +               case 0x04:
  81 +               case 0x0c:
  82 +               case 0x14:
  83 +               case 0x1c:
  84 +                       return 160000000;
  85 +               case 0x05:
  86 +               case 0x0e:
  87 +               case 0x16:
  88 +               case 0x1e:
  89 +               case 0x1f:
  90 +                       return 400000000;
  91 +               case 0x06:
  92 +                       return 440000000;
  93 +               case 0x07:
  94 +               case 0x17:
  95 +                       return 384000000;
  96 +               case 0x15:
  97 +               case 0x1d:
  98 +                       return 200000000;
  99 +               default:
 100 +                       return 320000000;
 101 +               }
 102 +       }
 103         case BCM6368_CPU_ID:
 104         {
 105                 unsigned int tmp, p1, p2, ndiv, m1;
 106 @@ -205,7 +250,7 @@ static unsigned int detect_memory_size(v
 107         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 108         u32 val;
 109
 110 -       if (BCMCPU_IS_6328())
 111 +       if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
 112                 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
 113
 114         if (BCMCPU_IS_6345()) {
 115 @@ -280,6 +325,11 @@ void __init bcm63xx_cpu_init(void)
 116                                 bcm63xx_regs_base = bcm6328_regs_base;
 117                                 bcm63xx_irqs = bcm6328_irqs;
 118                                 break;
 119 +                       case BCM6362_CPU_ID:
 120 +                               expected_cpu_id = BCM6362_CPU_ID;
 121 +                               bcm63xx_regs_base = bcm6362_regs_base;
 122 +                               bcm63xx_irqs = bcm6362_irqs;
 123 +                               break;
 124                         case BCM6368_CPU_ID:
 125                                 expected_cpu_id = BCM6368_CPU_ID;
 126                                 bcm63xx_regs_base = bcm6368_regs_base;
 127 --- a/arch/mips/bcm63xx/irq.c
 128 +++ b/arch/mips/bcm63xx/irq.c
 129 @@ -82,6 +82,14 @@ static void __internal_irq_unmask_64(uns
 130  #define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_6358
 131  #define ext_irq_cfg_reg2       0
 132  #endif
 133 +#ifdef CONFIG_BCM63XX_CPU_6362
 134 +#define irq_stat_reg           PERF_IRQSTAT_6362_REG
 135 +#define irq_mask_reg           PERF_IRQMASK_6362_REG
 136 +#define irq_bits               64
 137 +#define is_ext_irq_cascaded    1
 138 +#define ext_irq_start          (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
 139 +#define ext_irq_end            (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
 140 +#endif
 141  #ifdef CONFIG_BCM63XX_CPU_6368
 142  #define irq_stat_reg           PERF_IRQSTAT_6368_REG
 143  #define irq_mask_reg           PERF_IRQMASK_6368_REG
 144 @@ -170,6 +178,16 @@ static void bcm63xx_init_irq(void)
 145                 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 146                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 147                 break;
 148 +       case BCM6362_CPU_ID:
 149 +               irq_stat_addr += PERF_IRQSTAT_6362_REG;
 150 +               irq_mask_addr += PERF_IRQMASK_6362_REG;
 151 +               irq_bits = 64;
 152 +               ext_irq_count = 4;
 153 +               is_ext_irq_cascaded = 1;
 154 +               ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 155 +               ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 156 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 157 +               break;
 158         case BCM6368_CPU_ID:
 159                 irq_stat_addr += PERF_IRQSTAT_6368_REG;
 160                 irq_mask_addr += PERF_IRQMASK_6368_REG;
 161 @@ -458,6 +476,7 @@ static int bcm63xx_external_irq_set_type
 162         case BCM6338_CPU_ID:
 163         case BCM6345_CPU_ID:
 164         case BCM6358_CPU_ID:
 165 +       case BCM6362_CPU_ID:
 166         case BCM6368_CPU_ID:
 167                 if (levelsense)
 168                         reg |= EXTIRQ_CFG_LEVELSENSE(irq);
 169 --- a/arch/mips/bcm63xx/prom.c
 170 +++ b/arch/mips/bcm63xx/prom.c
 171 @@ -36,6 +36,8 @@ void __init prom_init(void)
 172                 mask = CKCTL_6348_ALL_SAFE_EN;
 173         else if (BCMCPU_IS_6358())
 174                 mask = CKCTL_6358_ALL_SAFE_EN;
 175 +       else if (BCMCPU_IS_6362())
 176 +               mask = CKCTL_6362_ALL_SAFE_EN;
 177         else if (BCMCPU_IS_6368())
 178                 mask = CKCTL_6368_ALL_SAFE_EN;
 179         else
 180 --- a/arch/mips/bcm63xx/reset.c
 181 +++ b/arch/mips/bcm63xx/reset.c
 182 @@ -85,6 +85,20 @@
 183  #define BCM6358_RESET_PCIE     0
 184  #define BCM6358_RESET_PCIE_EXT 0
 185
 186 +#define BCM6362_RESET_SPI      SOFTRESET_6362_SPI_MASK
 187 +#define BCM6362_RESET_ENET     0
 188 +#define BCM6362_RESET_USBH     SOFTRESET_6362_USBH_MASK
 189 +#define BCM6362_RESET_USBD     SOFTRESET_6362_USBS_MASK
 190 +#define BCM6362_RESET_DSL      0
 191 +#define BCM6362_RESET_SAR      SOFTRESET_6362_SAR_MASK
 192 +#define BCM6362_RESET_EPHY     SOFTRESET_6362_EPHY_MASK
 193 +#define BCM6362_RESET_ENETSW   SOFTRESET_6362_ENETSW_MASK
 194 +#define BCM6362_RESET_PCM      SOFTRESET_6362_PCM_MASK
 195 +#define BCM6362_RESET_MPI      0
 196 +#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
 197 +                                SOFTRESET_6362_PCIE_CORE_MASK)
 198 +#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
 199 +
 200  #define BCM6368_RESET_SPI      SOFTRESET_6368_SPI_MASK
 201  #define BCM6368_RESET_ENET     0
 202  #define BCM6368_RESET_USBH     SOFTRESET_6368_USBH_MASK
 203 @@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] =
 204         __GEN_RESET_BITS_TABLE(6358)
 205  };
 206
 207 +static const u32 bcm6362_reset_bits[] = {
 208 +       __GEN_RESET_BITS_TABLE(6362)
 209 +};
 210 +
 211  static const u32 bcm6368_reset_bits[] = {
 212         __GEN_RESET_BITS_TABLE(6368)
 213  };
 214 @@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_ini
 215         } else if (BCMCPU_IS_6358()) {
 216                 reset_reg = PERF_SOFTRESET_6358_REG;
 217                 bcm63xx_reset_bits = bcm6358_reset_bits;
 218 +       } else if (BCMCPU_IS_6362()) {
 219 +               reset_reg = PERF_SOFTRESET_6362_REG;
 220 +               bcm63xx_reset_bits = bcm6362_reset_bits;
 221         } else if (BCMCPU_IS_6368()) {
 222                 reset_reg = PERF_SOFTRESET_6368_REG;
 223                 bcm63xx_reset_bits = bcm6368_reset_bits;
 224 @@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] =
 225  #define reset_reg PERF_SOFTRESET_6358_REG
 226  #endif
 227
 228 +#ifdef CONFIG_BCM63XX_CPU_6362
 229 +static const u32 bcm63xx_reset_bits[] = {
 230 +       __GEN_RESET_BITS_TABLE(6362)
 231 +};
 232 +#define reset_reg PERF_SOFTRESET_6362_REG
 233 +#endif
 234 +
 235  #ifdef CONFIG_BCM63XX_CPU_6368
 236  static const u32 bcm63xx_reset_bits[] = {
 237         __GEN_RESET_BITS_TABLE(6368)
 238 --- a/arch/mips/bcm63xx/setup.c
 239 +++ b/arch/mips/bcm63xx/setup.c
 240 @@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
 241         case BCM6358_CPU_ID:
 242                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
 243                 break;
 244 +       case BCM6362_CPU_ID:
 245 +               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
 246 +               break;
 247         }
 248
 249         for (i = 0; i < 2; i++) {
 250 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 251 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 252 @@ -14,6 +14,7 @@
 253  #define BCM6345_CPU_ID         0x6345
 254  #define BCM6348_CPU_ID         0x6348
 255  #define BCM6358_CPU_ID         0x6358
 256 +#define BCM6362_CPU_ID         0x6362
 257  #define BCM6368_CPU_ID         0x6368
 258
 259  void __init bcm63xx_cpu_init(void);
 260 @@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
 261  # define BCMCPU_IS_6358()      (0)
 262  #endif
 263
 264 +#ifdef CONFIG_BCM63XX_CPU_6362
 265 +# ifdef bcm63xx_get_cpu_id
 266 +#  undef bcm63xx_get_cpu_id
 267 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
 268 +#  define BCMCPU_RUNTIME_DETECT
 269 +# else
 270 +#  define bcm63xx_get_cpu_id() BCM6362_CPU_ID
 271 +# endif
 272 +# define BCMCPU_IS_6362()      (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
 273 +#else
 274 +# define BCMCPU_IS_6362()      (0)
 275 +#endif
 276 +
 277 +
 278  #ifdef CONFIG_BCM63XX_CPU_6368
 279  # ifdef bcm63xx_get_cpu_id
 280  #  undef bcm63xx_get_cpu_id
 281 @@ -413,6 +428,62 @@ enum bcm63xx_regs_set {
 282
 283
 284  /*
 285 + * 6362 register sets base address
 286 + */
 287 +#define BCM_6362_DSL_LMEM_BASE         (0xdeadbeef)
 288 +#define BCM_6362_PERF_BASE             (0xb0000000)
 289 +#define BCM_6362_TIMER_BASE            (0xb0000040)
 290 +#define BCM_6362_WDT_BASE              (0xb000005c)
 291 +#define BCM_6362_UART0_BASE             (0xb0000100)
 292 +#define BCM_6362_UART1_BASE            (0xb0000120)
 293 +#define BCM_6362_GPIO_BASE             (0xb0000080)
 294 +#define BCM_6362_SPI_BASE              (0xb0000800)
 295 +#define BCM_6362_HSSPI_BASE            (0xb0001000)
 296 +#define BCM_6362_UDC0_BASE             (0xdeadbeef)
 297 +#define BCM_6362_USBDMA_BASE           (0xb000c000)
 298 +#define BCM_6362_OHCI0_BASE            (0xb0002600)
 299 +#define BCM_6362_OHCI_PRIV_BASE                (0xdeadbeef)
 300 +#define BCM_6362_USBH_PRIV_BASE                (0xb0002700)
 301 +#define BCM_6362_USBD_BASE             (0xb0002400)
 302 +#define BCM_6362_MPI_BASE              (0xdeadbeef)
 303 +#define BCM_6362_PCMCIA_BASE           (0xdeadbeef)
 304 +#define BCM_6362_PCIE_BASE             (0xb0e40000)
 305 +#define BCM_6362_SDRAM_REGS_BASE       (0xdeadbeef)
 306 +#define BCM_6362_DSL_BASE              (0xdeadbeef)
 307 +#define BCM_6362_UBUS_BASE             (0xdeadbeef)
 308 +#define BCM_6362_ENET0_BASE            (0xdeadbeef)
 309 +#define BCM_6362_ENET1_BASE            (0xdeadbeef)
 310 +#define BCM_6362_ENETDMA_BASE          (0xb000d800)
 311 +#define BCM_6362_ENETDMAC_BASE         (0xb000da00)
 312 +#define BCM_6362_ENETDMAS_BASE         (0xb000dc00)
 313 +#define BCM_6362_ENETSW_BASE           (0xb0e00000)
 314 +#define BCM_6362_EHCI0_BASE            (0xb0002500)
 315 +#define BCM_6362_SDRAM_BASE            (0xdeadbeef)
 316 +#define BCM_6362_MEMC_BASE             (0xdeadbeef)
 317 +#define BCM_6362_DDR_BASE              (0xb0003000)
 318 +#define BCM_6362_M2M_BASE              (0xdeadbeef)
 319 +#define BCM_6362_ATM_BASE              (0xdeadbeef)
 320 +#define BCM_6362_XTM_BASE              (0xb0007800)
 321 +#define BCM_6362_XTMDMA_BASE           (0xb000b800)
 322 +#define BCM_6362_XTMDMAC_BASE          (0xdeadbeef)
 323 +#define BCM_6362_XTMDMAS_BASE          (0xdeadbeef)
 324 +#define BCM_6362_PCM_BASE              (0xb000a800)
 325 +#define BCM_6362_PCMDMA_BASE           (0xdeadbeef)
 326 +#define BCM_6362_PCMDMAC_BASE          (0xdeadbeef)
 327 +#define BCM_6362_PCMDMAS_BASE          (0xdeadbeef)
 328 +#define BCM_6362_RNG_BASE              (0xdeadbeef)
 329 +#define BCM_6362_MISC_BASE             (0xb0001800)
 330 +
 331 +#define BCM_6362_NAND_REG_BASE         (0xb0000200)
 332 +#define BCM_6362_NAND_CACHE_BASE       (0xb0000600)
 333 +#define BCM_6362_LED_BASE              (0xb0001900)
 334 +#define BCM_6362_IPSEC_BASE            (0xb0002800)
 335 +#define BCM_6362_IPSEC_DMA_BASE                (0xb000d000)
 336 +#define BCM_6362_WLAN_CHIPCOMMON_BASE  (0xb0004000)
 337 +#define BCM_6362_WLAN_D11_BASE         (0xb0005000)
 338 +#define BCM_6362_WLAN_SHIM_BASE                (0xb0007000)
 339 +
 340 +/*
 341   * 6368 register sets base address
 342   */
 343  #define BCM_6368_DSL_LMEM_BASE         (0xdeadbeef)
 344 @@ -574,6 +645,9 @@ static inline unsigned long bcm63xx_regs
 345  #ifdef CONFIG_BCM63XX_CPU_6358
 346         __GEN_RSET(6358)
 347  #endif
 348 +#ifdef CONFIG_BCM63XX_CPU_6362
 349 +       __GEN_RSET(6362)
 350 +#endif
 351  #ifdef CONFIG_BCM63XX_CPU_6368
 352         __GEN_RSET(6368)
 353  #endif
 354 @@ -836,6 +910,71 @@ enum bcm63xx_irq {
 355  #define BCM_6358_EXT_IRQ3              (IRQ_INTERNAL_BASE + 28)
 356
 357  /*
 358 + * 6362 irqs
 359 + */
 360 +#define BCM_6362_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 361 +
 362 +#define BCM_6362_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 363 +#define BCM_6362_SPI_IRQ               (IRQ_INTERNAL_BASE + 2)
 364 +#define BCM_6362_UART0_IRQ             (IRQ_INTERNAL_BASE + 3)
 365 +#define BCM_6362_UART1_IRQ             (IRQ_INTERNAL_BASE + 4)
 366 +#define BCM_6362_DSL_IRQ               (IRQ_INTERNAL_BASE + 28)
 367 +#define BCM_6362_UDC0_IRQ              0
 368 +#define BCM_6362_ENET0_IRQ             0
 369 +#define BCM_6362_ENET1_IRQ             0
 370 +#define BCM_6362_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 14)
 371 +#define BCM_6362_HSSPI_IRQ             (IRQ_INTERNAL_BASE + 5)
 372 +#define BCM_6362_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 9)
 373 +#define BCM_6362_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 10)
 374 +#define BCM_6362_USBD_IRQ              (IRQ_INTERNAL_BASE + 11)
 375 +#define BCM_6362_USBD_RXDMA0_IRQ       (IRQ_INTERNAL_BASE + 20)
 376 +#define BCM_6362_USBD_TXDMA0_IRQ       (IRQ_INTERNAL_BASE + 21)
 377 +#define BCM_6362_USBD_RXDMA1_IRQ       (IRQ_INTERNAL_BASE + 22)
 378 +#define BCM_6362_USBD_TXDMA1_IRQ       (IRQ_INTERNAL_BASE + 23)
 379 +#define BCM_6362_USBD_RXDMA2_IRQ       (IRQ_INTERNAL_BASE + 24)
 380 +#define BCM_6362_USBD_TXDMA2_IRQ       (IRQ_INTERNAL_BASE + 25)
 381 +#define BCM_6362_PCMCIA_IRQ            0
 382 +#define BCM_6362_ENET0_RXDMA_IRQ       0
 383 +#define BCM_6362_ENET0_TXDMA_IRQ       0
 384 +#define BCM_6362_ENET1_RXDMA_IRQ       0
 385 +#define BCM_6362_ENET1_TXDMA_IRQ       0
 386 +#define BCM_6362_PCI_IRQ               (IRQ_INTERNAL_BASE + 30)
 387 +#define BCM_6362_ATM_IRQ               0
 388 +#define BCM_6362_ENETSW_RXDMA0_IRQ     (BCM_6362_HIGH_IRQ_BASE + 0)
 389 +#define BCM_6362_ENETSW_RXDMA1_IRQ     (BCM_6362_HIGH_IRQ_BASE + 1)
 390 +#define BCM_6362_ENETSW_RXDMA2_IRQ     (BCM_6362_HIGH_IRQ_BASE + 2)
 391 +#define BCM_6362_ENETSW_RXDMA3_IRQ     (BCM_6362_HIGH_IRQ_BASE + 3)
 392 +#define BCM_6362_ENETSW_TXDMA0_IRQ     0
 393 +#define BCM_6362_ENETSW_TXDMA1_IRQ     0
 394 +#define BCM_6362_ENETSW_TXDMA2_IRQ     0
 395 +#define BCM_6362_ENETSW_TXDMA3_IRQ     0
 396 +#define BCM_6362_XTM_IRQ               0
 397 +#define BCM_6362_XTM_DMA0_IRQ          (BCM_6362_HIGH_IRQ_BASE + 12)
 398 +
 399 +#define BCM_6362_RING_OSC_IRQ          (IRQ_INTERNAL_BASE + 1)
 400 +#define BCM_6362_WLAN_GPIO_IRQ         (IRQ_INTERNAL_BASE + 6)
 401 +#define BCM_6362_WLAN_IRQ              (IRQ_INTERNAL_BASE + 7)
 402 +#define BCM_6362_IPSEC_IRQ             (IRQ_INTERNAL_BASE + 8)
 403 +#define BCM_6362_NAND_IRQ              (IRQ_INTERNAL_BASE + 12)
 404 +#define BCM_6362_PCM_IRQ               (IRQ_INTERNAL_BASE + 13)
 405 +#define BCM_6362_DG_IRQ                        (IRQ_INTERNAL_BASE + 15)
 406 +#define BCM_6362_EPHY_ENERGY0_IRQ      (IRQ_INTERNAL_BASE + 16)
 407 +#define BCM_6362_EPHY_ENERGY1_IRQ      (IRQ_INTERNAL_BASE + 17)
 408 +#define BCM_6362_EPHY_ENERGY2_IRQ      (IRQ_INTERNAL_BASE + 18)
 409 +#define BCM_6362_EPHY_ENERGY3_IRQ      (IRQ_INTERNAL_BASE + 19)
 410 +#define BCM_6362_IPSEC_DMA0_IRQ                (IRQ_INTERNAL_BASE + 26)
 411 +#define BCM_6362_IPSEC_DMA1_IRQ                (IRQ_INTERNAL_BASE + 27)
 412 +#define BCM_6362_FAP0_IRQ              (IRQ_INTERNAL_BASE + 29)
 413 +#define BCM_6362_PCM_DMA0_IRQ          (BCM_6362_HIGH_IRQ_BASE + 4)
 414 +#define BCM_6362_PCM_DMA1_IRQ          (BCM_6362_HIGH_IRQ_BASE + 5)
 415 +#define BCM_6362_DECT0_IRQ             (BCM_6362_HIGH_IRQ_BASE + 6)
 416 +#define BCM_6362_DECT1_IRQ             (BCM_6362_HIGH_IRQ_BASE + 7)
 417 +#define BCM_6362_EXT_IRQ0              (BCM_6362_HIGH_IRQ_BASE + 8)
 418 +#define BCM_6362_EXT_IRQ1              (BCM_6362_HIGH_IRQ_BASE + 9)
 419 +#define BCM_6362_EXT_IRQ2              (BCM_6362_HIGH_IRQ_BASE + 10)
 420 +#define BCM_6362_EXT_IRQ3              (BCM_6362_HIGH_IRQ_BASE + 11)
 421 +
 422 +/*
 423   * 6368 irqs
 424   */
 425  #define BCM_6368_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 426 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 427 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 428 @@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio
 429                 return 8;
 430         case BCM6345_CPU_ID:
 431                 return 16;
 432 +       case BCM6362_CPU_ID:
 433 +               return 48;
 434         case BCM6368_CPU_ID:
 435                 return 38;
 436         case BCM6348_CPU_ID:
 437 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 438 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 439 @@ -107,6 +107,39 @@
 440                                         CKCTL_6358_USBSU_EN |           \
 441                                         CKCTL_6358_EPHY_EN)
 442
 443 +#define CKCTL_6362_ADSL_QPROC_EN       (1 << 1)
 444 +#define CKCTL_6362_ADSL_AFE_EN         (1 << 2)
 445 +#define CKCTL_6362_ADSL_EN             (1 << 3)
 446 +#define CKCTL_6362_MIPS_EN             (1 << 4)
 447 +#define CKCTL_6362_WLAN_OCP_EN         (1 << 5)
 448 +#define CKCTL_6362_SWPKT_USB_EN                (1 << 7)
 449 +#define CKCTL_6362_SWPKT_SAR_EN                (1 << 8)
 450 +#define CKCTL_6362_SAR_EN              (1 << 9)
 451 +#define CKCTL_6362_ROBOSW_EN           (1 << 10)
 452 +#define CKCTL_6362_PCM_EN              (1 << 11)
 453 +#define CKCTL_6362_USBD_EN             (1 << 12)
 454 +#define CKCTL_6362_USBH_EN             (1 << 13)
 455 +#define CKCTL_6362_IPSEC_EN            (1 << 14)
 456 +#define CKCTL_6362_SPI_EN              (1 << 15)
 457 +#define CKCTL_6362_HSSPI_EN            (1 << 16)
 458 +#define CKCTL_6362_PCIE_EN             (1 << 17)
 459 +#define CKCTL_6362_FAP_EN              (1 << 18)
 460 +#define CKCTL_6362_PHYMIPS_EN          (1 << 19)
 461 +#define CKCTL_6362_NAND_EN             (1 << 20)
 462 +
 463 +#define CKCTL_6362_ALL_SAFE_EN         (CKCTL_6362_PHYMIPS_EN |        \
 464 +                                       CKCTL_6362_ADSL_QPROC_EN |      \
 465 +                                       CKCTL_6362_ADSL_AFE_EN |        \
 466 +                                       CKCTL_6362_ADSL_EN |            \
 467 +                                       CKCTL_6362_SAR_EN  |            \
 468 +                                       CKCTL_6362_PCM_EN  |            \
 469 +                                       CKCTL_6362_IPSEC_EN |           \
 470 +                                       CKCTL_6362_USBD_EN |            \
 471 +                                       CKCTL_6362_USBH_EN |            \
 472 +                                       CKCTL_6362_ROBOSW_EN |          \
 473 +                                       CKCTL_6362_PCIE_EN)
 474 +
 475 +
 476  #define CKCTL_6368_VDSL_QPROC_EN       (1 << 2)
 477  #define CKCTL_6368_VDSL_AFE_EN         (1 << 3)
 478  #define CKCTL_6368_VDSL_BONDING_EN     (1 << 4)
 479 @@ -148,6 +181,7 @@
 480  #define PERF_IRQMASK_6345_REG          0xc
 481  #define PERF_IRQMASK_6348_REG          0xc
 482  #define PERF_IRQMASK_6358_REG          0xc
 483 +#define PERF_IRQMASK_6362_REG          0x20
 484  #define PERF_IRQMASK_6368_REG          0x20
 485
 486  /* Interrupt Status register */
 487 @@ -156,6 +190,7 @@
 488  #define PERF_IRQSTAT_6345_REG          0x10
 489  #define PERF_IRQSTAT_6348_REG          0x10
 490  #define PERF_IRQSTAT_6358_REG          0x10
 491 +#define PERF_IRQSTAT_6362_REG          0x28
 492  #define PERF_IRQSTAT_6368_REG          0x28
 493
 494  /* External Interrupt Configuration register */
 495 @@ -164,6 +199,7 @@
 496  #define PERF_EXTIRQ_CFG_REG_6345       0x14
 497  #define PERF_EXTIRQ_CFG_REG_6348       0x14
 498  #define PERF_EXTIRQ_CFG_REG_6358       0x14
 499 +#define PERF_EXTIRQ_CFG_REG_6362       0x18
 500  #define PERF_EXTIRQ_CFG_REG_6368       0x18
 501
 502  #define PERF_EXTIRQ_CFG_REG2_6368      0x1c
 503 @@ -192,6 +228,7 @@
 504  #define PERF_SOFTRESET_REG             0x28
 505  #define PERF_SOFTRESET_6328_REG                0x10
 506  #define PERF_SOFTRESET_6358_REG                0x34
 507 +#define PERF_SOFTRESET_6362_REG                0x10
 508  #define PERF_SOFTRESET_6368_REG                0x10
 509
 510  #define SOFTRESET_6328_SPI_MASK                (1 << 0)
 511 @@ -254,6 +291,22 @@
 512  #define SOFTRESET_6358_PCM_MASK                (1 << 13)
 513  #define SOFTRESET_6358_ADSL_MASK       (1 << 14)
 514
 515 +#define SOFTRESET_6362_SPI_MASK                (1 << 0)
 516 +#define SOFTRESET_6362_IPSEC_MASK      (1 << 1)
 517 +#define SOFTRESET_6362_EPHY_MASK       (1 << 2)
 518 +#define SOFTRESET_6362_SAR_MASK                (1 << 3)
 519 +#define SOFTRESET_6362_ENETSW_MASK     (1 << 4)
 520 +#define SOFTRESET_6362_USBS_MASK       (1 << 5)
 521 +#define SOFTRESET_6362_USBH_MASK       (1 << 6)
 522 +#define SOFTRESET_6362_PCM_MASK                (1 << 7)
 523 +#define SOFTRESET_6362_PCIE_CORE_MASK  (1 << 8)
 524 +#define SOFTRESET_6362_PCIE_MASK       (1 << 9)
 525 +#define SOFTRESET_6362_PCIE_EXT_MASK   (1 << 10)
 526 +#define SOFTRESET_6362_WLAN_SHIM_MASK  (1 << 11)
 527 +#define SOFTRESET_6362_DDR_PHY_MASK    (1 << 12)
 528 +#define SOFTRESET_6362_FAP_MASK                (1 << 13)
 529 +#define SOFTRESET_6362_WLAN_UBUS_MASK  (1 << 14)
 530 +
 531  #define SOFTRESET_6368_SPI_MASK                (1 << 0)
 532  #define SOFTRESET_6368_MPI_MASK                (1 << 3)
 533  #define SOFTRESET_6368_EPHY_MASK       (1 << 6)
 534 @@ -1347,6 +1400,12 @@
 535  #define SERDES_PCIE_EN                 (1 << 0)
 536  #define SERDES_PCIE_EXD_EN             (1 << 15)
 537
 538 +#define MISC_STRAPBUS_6362_REG         0x14
 539 +#define STRAPBUS_6362_FCVO_SHIFT       1
 540 +#define STRAPBUS_6362_FCVO_MASK                (0x1f << STRAPBUS_6362_FCVO_SHIFT)
 541 +#define STRAPBUS_6362_BOOT_SEL_SERIAL  (1 << 15)
 542 +#define STRAPBUS_6362_BOOT_SEL_NAND    (0 << 15)
 543 +
 544  #define MISC_STRAPBUS_6328_REG         0x240
 545  #define STRAPBUS_6328_FCVO_SHIFT       7
 546  #define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 547 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 548 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 549 @@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re
 550                         return 1;
 551                 break;
 552         case BCM6328_CPU_ID:
 553 +       case BCM6362_CPU_ID:
 554         case BCM6368_CPU_ID:
 555                 if (offset >= 0xb0000000 && offset < 0xb1000000)
 556                         return 1;