target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch

   1 From: Florian Fainelli <florian@openwrt.org>
   2 Subject: [PATCH] MIPS: BCM63XX: fix BCM6345 clock bits shifting
   3
   4 BCM6345 has an intermediate 16-bits wide test control register between the
   5 peripheral identifier function, and its clock control register is only 16-bits
   6 wide contrary to other platforms where it is 32-bits wide. By shifting all
   7 clocks bits by 16-bits to the left we ensure they get written to the proper
   8 clock control register, without adding specific BCM6345 handling in the clock
   9 code.
  10
  11 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  12 ---
  13 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  14 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  15 @@ -53,13 +53,13 @@
  16                                         CKCTL_6338_SAR_EN |             \
  17                                         CKCTL_6338_SPI_EN)
  18
  19 -#define CKCTL_6345_CPU_EN              (1 << 0)
  20 -#define CKCTL_6345_BUS_EN              (1 << 1)
  21 -#define CKCTL_6345_EBI_EN              (1 << 2)
  22 -#define CKCTL_6345_UART_EN             (1 << 3)
  23 -#define CKCTL_6345_ADSLPHY_EN          (1 << 4)
  24 -#define CKCTL_6345_ENET_EN             (1 << 7)
  25 -#define CKCTL_6345_USBH_EN             (1 << 8)
  26 +#define CKCTL_6345_CPU_EN              (1 << 16)
  27 +#define CKCTL_6345_BUS_EN              (1 << 17)
  28 +#define CKCTL_6345_EBI_EN              (1 << 18)
  29 +#define CKCTL_6345_UART_EN             (1 << 19)
  30 +#define CKCTL_6345_ADSLPHY_EN          (1 << 20)
  31 +#define CKCTL_6345_ENET_EN             (1 << 23)
  32 +#define CKCTL_6345_USBH_EN             (1 << 24)
  33
  34  #define CKCTL_6345_ALL_SAFE_EN         (CKCTL_6345_ENET_EN |   \
  35                                         CKCTL_6345_USBH_EN |    \