1 From 5b837e6c8499aa9bdf9f76889247feac553870d0 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sun, 28 Oct 2012 13:09:38 +0100
4 Subject: [PATCH 3/3] MIPS: BCM63XX: use the new reset helper
6 Use the new reset helper where appropriate.
8 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
10 arch/mips/bcm63xx/clk.c | 19 +++++--------------
11 arch/mips/pci/pci-bcm63xx.c | 19 ++++++-------------
12 2 files changed, 11 insertions(+), 27 deletions(-)
14 --- a/arch/mips/bcm63xx/clk.c
15 +++ b/arch/mips/bcm63xx/clk.c
17 #include <bcm63xx_cpu.h>
18 #include <bcm63xx_io.h>
19 #include <bcm63xx_regs.h>
20 +#include <bcm63xx_reset.h>
21 #include <bcm63xx_clk.h>
23 static DEFINE_MUTEX(clocks_mutex);
24 @@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk,
25 CKCTL_6368_SWPKT_USB_EN |
26 CKCTL_6368_SWPKT_SAR_EN, enable);
30 /* reset switch core afer clock change */
31 - val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
32 - val &= ~SOFTRESET_6368_ENETSW_MASK;
33 - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
34 + bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
36 - val |= SOFTRESET_6368_ENETSW_MASK;
37 - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
38 + bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
42 @@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int
43 CKCTL_6368_SWPKT_SAR_EN, enable);
48 /* reset sar core afer clock change */
49 - val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
50 - val &= ~SOFTRESET_6368_SAR_MASK;
51 - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
52 + bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
54 - val |= SOFTRESET_6368_SAR_MASK;
55 - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
56 + bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
60 --- a/arch/mips/pci/pci-bcm63xx.c
61 +++ b/arch/mips/pci/pci-bcm63xx.c
63 #include <linux/delay.h>
64 #include <asm/bootinfo.h>
66 +#include <bcm63xx_reset.h>
68 #include "pci-bcm63xx.h"
71 @@ -130,23 +132,14 @@ static void __init bcm63xx_reset_pcie(vo
72 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
74 /* reset the PCIe core */
75 - val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
77 - val &= ~SOFTRESET_6328_PCIE_MASK;
78 - val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
79 - val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
80 - val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
81 - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
82 + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
83 + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
86 - val |= SOFTRESET_6328_PCIE_MASK;
87 - val |= SOFTRESET_6328_PCIE_CORE_MASK;
88 - val |= SOFTRESET_6328_PCIE_HARD_MASK;
89 - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
90 + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
93 - val |= SOFTRESET_6328_PCIE_EXT_MASK;
94 - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
95 + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);