4 #include <linux/types.h>
5 #include <linux/init.h>
7 #include <bcm63xx_regs.h>
10 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
11 * compile time if only one CPU support is enabled (idea stolen from
14 #define BCM6338_CPU_ID 0x6338
15 #define BCM6345_CPU_ID 0x6345
16 #define BCM6348_CPU_ID 0x6348
17 #define BCM6358_CPU_ID 0x6358
19 void __init bcm63xx_cpu_init(void);
20 u16 __bcm63xx_get_cpu_id(void);
21 u16 bcm63xx_get_cpu_rev(void);
22 unsigned int bcm63xx_get_cpu_freq(void);
24 #ifdef CONFIG_BCM63XX_CPU_6338
25 # ifdef bcm63xx_get_cpu_id
26 # undef bcm63xx_get_cpu_id
27 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28 # define BCMCPU_RUNTIME_DETECT
30 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
32 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
34 # define BCMCPU_IS_6338() (0)
37 #ifdef CONFIG_BCM63XX_CPU_6345
38 # ifdef bcm63xx_get_cpu_id
39 # undef bcm63xx_get_cpu_id
40 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
41 # define BCMCPU_RUNTIME_DETECT
43 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
45 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
47 # define BCMCPU_IS_6345() (0)
50 #ifdef CONFIG_BCM63XX_CPU_6348
51 # ifdef bcm63xx_get_cpu_id
52 # undef bcm63xx_get_cpu_id
53 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
54 # define BCMCPU_RUNTIME_DETECT
56 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
58 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
60 # define BCMCPU_IS_6348() (0)
63 #ifdef CONFIG_BCM63XX_CPU_6358
64 # ifdef bcm63xx_get_cpu_id
65 # undef bcm63xx_get_cpu_id
66 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
67 # define BCMCPU_RUNTIME_DETECT
69 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
71 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
73 # define BCMCPU_IS_6358() (0)
76 #ifndef bcm63xx_get_cpu_id
77 #error "No CPU support configured"
81 * While registers sets are (mostly) the same across 63xx CPU, base
82 * address of these sets do change.
84 enum bcm63xx_regs_set {
108 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
109 #define RSET_DSL_SIZE 4096
110 #define RSET_WDT_SIZE 12
111 #define RSET_ENET_SIZE 2048
112 #define RSET_ENETDMA_SIZE 2048
113 #define RSET_UART_SIZE 24
114 #define RSET_SPI_SIZE 256
115 #define RSET_UDC_SIZE 256
116 #define RSET_OHCI_SIZE 256
117 #define RSET_EHCI_SIZE 256
118 #define RSET_PCMCIA_SIZE 12
121 * 6338 register sets base address
124 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
125 #define BCM_6338_PERF_BASE (0xfffe0000)
126 #define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
127 #define BCM_6338_TIMER_BASE (0xfffe0200)
128 #define BCM_6338_WDT_BASE (0xfffe021c)
129 #define BCM_6338_UART0_BASE (0xfffe0300)
130 #define BCM_6338_GPIO_BASE (0xfffe0400)
131 #define BCM_6338_SPI_BASE (0xfffe0c00)
132 #define BCM_6338_DSL_BASE (0xfffe1000)
133 #define BCM_6338_SAR_BASE (0xfffe2000)
134 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
135 #define BCM_6338_USBDMA_BASE (0xfffe2400)
136 #define BCM_6338_ENET0_BASE (0xfffe2800)
137 #define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
138 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
139 #define BCM_6338_SDRAM_BASE (0xfffe3100)
140 #define BCM_6338_MEMC_BASE (0xdeadbeef)
143 * 6345 register sets base address
145 #define BCM_6345_PERF_BASE (0xfffe0000)
146 #define BCM_6345_TIMER_BASE (0xfffe0200)
147 #define BCM_6345_WDT_BASE (0xfffe021c)
148 #define BCM_6345_UART0_BASE (0xfffe0300)
149 #define BCM_6345_GPIO_BASE (0xfffe0400)
152 * 6348 register sets base address
154 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
155 #define BCM_6348_PERF_BASE (0xfffe0000)
156 #define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */
157 #define BCM_6348_TIMER_BASE (0xfffe0200)
158 #define BCM_6348_WDT_BASE (0xfffe021c)
159 #define BCM_6348_UART0_BASE (0xfffe0300)
160 #define BCM_6348_GPIO_BASE (0xfffe0400)
161 #define BCM_6348_SPI_BASE (0xfffe0c00)
162 #define BCM_6348_UDC0_BASE (0xfffe1000)
163 #define BCM_6348_USBDMA_BASE (0xfffe1400)
164 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
165 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
166 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
167 #define BCM_6348_MPI_BASE (0xfffe2000)
168 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
169 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
170 #define BCM_6348_DSL_BASE (0xfffe3000)
171 #define BCM_6348_SAR_BASE (0xfffe4000)
172 #define BCM_6348_UBUS_BASE (0xfffe5000)
173 #define BCM_6348_ENET0_BASE (0xfffe6000)
174 #define BCM_6348_ENET1_BASE (0xfffe6800)
175 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
176 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
177 #define BCM_6348_SDRAM_BASE (0xfffe2300)
178 #define BCM_6348_MEMC_BASE (0xdeadbeef)
179 #define BCM_6348_DDR_BASE (0xdeadbeef)
182 * 6358 register sets base address
184 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
185 #define BCM_6358_PERF_BASE (0xfffe0000)
186 #define BCM_6358_TIMER_BASE (0xfffe0040)
187 #define BCM_6358_WDT_BASE (0xfffe005c)
188 #define BCM_6358_GPIO_BASE (0xfffe0080)
189 #define BCM_6358_UART0_BASE (0xfffe0100)
190 #define BCM_6358_UDC0_BASE (0xfffe0400)
191 #define BCM_6358_SPI_BASE (0xfffe0800)
192 #define BCM_6358_MPI_BASE (0xfffe1000)
193 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
194 #define BCM_6358_OHCI0_BASE (0xfffe1400)
195 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
196 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
197 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
198 #define BCM_6358_DSL_BASE (0xfffe3000)
199 #define BCM_6358_ENET0_BASE (0xfffe4000)
200 #define BCM_6358_ENET1_BASE (0xfffe4800)
201 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
202 #define BCM_6358_EHCI0_BASE (0xfffe1300)
203 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
204 #define BCM_6358_MEMC_BASE (0xfffe1200)
205 #define BCM_6358_DDR_BASE (0xfffe12a0)
208 extern const unsigned long *bcm63xx_regs_base;
210 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
212 #ifdef BCMCPU_RUNTIME_DETECT
213 return bcm63xx_regs_base[set];
215 #ifdef CONFIG_BCM63XX_CPU_6338
218 return BCM_6338_DSL_LMEM_BASE;
220 return BCM_6338_PERF_BASE;
222 return BCM_6338_TIMER_BASE;
224 return BCM_6338_WDT_BASE;
226 return BCM_6338_UART0_BASE;
228 return BCM_6338_GPIO_BASE;
230 return BCM_6338_SPI_BASE;
232 return BCM_6338_MEMC_BASE;
234 return BCM_6338_SDRAM_BASE;
237 #ifdef CONFIG_BCM63XX_CPU_6345
240 return BCM_6345_PERF_BASE;
242 return BCM_6345_TIMER_BASE;
244 return BCM_6345_WDT_BASE;
246 return BCM_6345_UART0_BASE;
248 return BCM_6345_GPIO_BASE;
251 #ifdef CONFIG_BCM63XX_CPU_6348
254 return BCM_6348_DSL_LMEM_BASE;
256 return BCM_6348_PERF_BASE;
258 return BCM_6348_TIMER_BASE;
260 return BCM_6348_WDT_BASE;
262 return BCM_6348_UART0_BASE;
264 return BCM_6348_GPIO_BASE;
266 return BCM_6348_SPI_BASE;
268 return BCM_6348_UDC0_BASE;
270 return BCM_6348_OHCI0_BASE;
272 return BCM_6348_OHCI_PRIV_BASE;
274 return BCM_6348_USBH_PRIV_BASE;
276 return BCM_6348_MPI_BASE;
278 return BCM_6348_PCMCIA_BASE;
280 return BCM_6348_DSL_BASE;
282 return BCM_6348_ENET0_BASE;
284 return BCM_6348_ENET1_BASE;
286 return BCM_6348_ENETDMA_BASE;
288 return BCM_6348_EHCI0_BASE;
290 return BCM_6348_SDRAM_BASE;
292 return BCM_6348_MEMC_BASE;
294 return BCM_6348_DDR_BASE;
297 #ifdef CONFIG_BCM63XX_CPU_6358
300 return BCM_6358_DSL_LMEM_BASE;
302 return BCM_6358_PERF_BASE;
304 return BCM_6358_TIMER_BASE;
306 return BCM_6358_WDT_BASE;
308 return BCM_6358_UART0_BASE;
310 return BCM_6358_GPIO_BASE;
312 return BCM_6358_SPI_BASE;
314 return BCM_6358_UDC0_BASE;
316 return BCM_6358_OHCI0_BASE;
318 return BCM_6358_OHCI_PRIV_BASE;
320 return BCM_6358_USBH_PRIV_BASE;
322 return BCM_6358_MPI_BASE;
324 return BCM_6358_PCMCIA_BASE;
326 return BCM_6358_ENET0_BASE;
328 return BCM_6358_ENET1_BASE;
330 return BCM_6358_ENETDMA_BASE;
332 return BCM_6358_DSL_BASE;
334 return BCM_6358_EHCI0_BASE;
336 return BCM_6358_SDRAM_BASE;
338 return BCM_6358_MEMC_BASE;
340 return BCM_6358_DDR_BASE;
349 * SPI register layout is not compatible
350 * accross CPU versions but it is software
354 enum bcm63xx_regs_spi {
369 extern const unsigned long *bcm63xx_regs_spi;
371 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
373 #ifdef BCMCPU_RUNTIME_DETECT
374 return bcm63xx_regs_spi[reg];
376 #ifdef CONFIG_BCM63XX_CPU_6338
379 return SPI_BCM_6338_SPI_CMD;
381 return SPI_BCM_6338_SPI_INT_STATUS;
382 case SPI_INT_MASK_ST:
383 return SPI_BCM_6338_SPI_MASK_INT_ST;
385 return SPI_BCM_6338_SPI_INT_MASK;
387 return SPI_BCM_6338_SPI_ST;
389 return SPI_BCM_6338_SPI_CLK_CFG;
391 return SPI_BCM_6338_SPI_FILL_BYTE;
393 return SPI_BCM_6338_SPI_MSG_TAIL;
395 return SPI_BCM_6338_SPI_RX_TAIL;
397 return SPI_BCM_6338_SPI_MSG_CTL;
399 return SPI_BCM_6338_SPI_MSG_DATA;
401 return SPI_BCM_6338_SPI_RX_DATA;
404 #ifdef CONFIG_BCM63XX_CPU_6348
407 return SPI_BCM_6348_SPI_CMD;
408 case SPI_INT_MASK_ST:
409 return SPI_BCM_6348_SPI_MASK_INT_ST;
411 return SPI_BCM_6348_SPI_INT_MASK;
413 return SPI_BCM_6348_SPI_INT_STATUS;
415 return SPI_BCM_6348_SPI_ST;
417 return SPI_BCM_6348_SPI_CLK_CFG;
419 return SPI_BCM_6348_SPI_FILL_BYTE;
421 return SPI_BCM_6348_SPI_MSG_TAIL;
423 return SPI_BCM_6348_SPI_RX_TAIL;
425 return SPI_BCM_6348_SPI_MSG_CTL;
427 return SPI_BCM_6348_SPI_MSG_DATA;
429 return SPI_BCM_6348_SPI_RX_DATA;
432 #ifdef CONFIG_BCM63XX_CPU_6358
435 return SPI_BCM_6358_SPI_CMD;
437 return SPI_BCM_6358_SPI_INT_STATUS;
438 case SPI_INT_MASK_ST:
439 return SPI_BCM_6358_SPI_MASK_INT_ST;
441 return SPI_BCM_6358_SPI_INT_MASK;
443 return SPI_BCM_6358_SPI_STATUS;
445 return SPI_BCM_6358_SPI_CLK_CFG;
447 return SPI_BCM_6358_SPI_FILL_BYTE;
449 return SPI_BCM_6358_SPI_MSG_TAIL;
451 return SPI_BCM_6358_SPI_RX_TAIL;
453 return SPI_BCM_6358_MSG_CTL;
455 return SPI_BCM_6358_SPI_MSG_DATA;
457 return SPI_BCM_6358_SPI_RX_DATA;
465 * IRQ number changes across CPU too
490 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
491 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
492 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
493 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
494 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
495 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
496 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
497 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
498 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
499 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
500 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
501 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
502 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
503 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
504 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
505 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
506 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
511 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
512 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
514 #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
515 #define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
516 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
517 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
522 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
523 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
524 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
525 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
526 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
527 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
528 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
529 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
530 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
531 #define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
532 #define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
533 #define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
534 #define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
535 #define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
536 #define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
537 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
538 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
539 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
540 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
541 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
542 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
547 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
548 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
549 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
550 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
551 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
552 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
553 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
554 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
555 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
556 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
557 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
558 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
559 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
560 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
561 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
563 extern const int *bcm63xx_irqs;
565 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
567 return bcm63xx_irqs[irq];
571 * return installed memory size
573 unsigned int bcm63xx_get_memory_size(void);
575 #endif /* !BCM63XX_CPU_H_ */