target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

   1 #ifndef BCM63XX_CPU_H_
   2 #define BCM63XX_CPU_H_
   3
   4 #include <linux/types.h>
   5 #include <linux/init.h>
   6
   7 #include <bcm63xx_regs.h>
   8
   9 /*
  10  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
  11  * compile time if only one CPU support is enabled (idea stolen from
  12  * arm mach-types)
  13  */
  14 #define BCM6338_CPU_ID          0x6338
  15 #define BCM6345_CPU_ID          0x6345
  16 #define BCM6348_CPU_ID          0x6348
  17 #define BCM6358_CPU_ID          0x6358
  18
  19 void __init bcm63xx_cpu_init(void);
  20 u16 __bcm63xx_get_cpu_id(void);
  21 u16 bcm63xx_get_cpu_rev(void);
  22 unsigned int bcm63xx_get_cpu_freq(void);
  23
  24 #ifdef CONFIG_BCM63XX_CPU_6338
  25 # ifdef bcm63xx_get_cpu_id
  26 #  undef bcm63xx_get_cpu_id
  27 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  28 #  define BCMCPU_RUNTIME_DETECT
  29 # else
  30 #  define bcm63xx_get_cpu_id()  BCM6338_CPU_ID
  31 # endif
  32 # define BCMCPU_IS_6338()       (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
  33 #else
  34 # define BCMCPU_IS_6338()       (0)
  35 #endif
  36
  37 #ifdef CONFIG_BCM63XX_CPU_6345
  38 # ifdef bcm63xx_get_cpu_id
  39 #  undef bcm63xx_get_cpu_id
  40 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  41 #  define BCMCPU_RUNTIME_DETECT
  42 # else
  43 #  define bcm63xx_get_cpu_id()  BCM6345_CPU_ID
  44 # endif
  45 # define BCMCPU_IS_6345()       (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
  46 #else
  47 # define BCMCPU_IS_6345()       (0)
  48 #endif
  49
  50 #ifdef CONFIG_BCM63XX_CPU_6348
  51 # ifdef bcm63xx_get_cpu_id
  52 #  undef bcm63xx_get_cpu_id
  53 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  54 #  define BCMCPU_RUNTIME_DETECT
  55 # else
  56 #  define bcm63xx_get_cpu_id()  BCM6348_CPU_ID
  57 # endif
  58 # define BCMCPU_IS_6348()       (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
  59 #else
  60 # define BCMCPU_IS_6348()       (0)
  61 #endif
  62
  63 #ifdef CONFIG_BCM63XX_CPU_6358
  64 # ifdef bcm63xx_get_cpu_id
  65 #  undef bcm63xx_get_cpu_id
  66 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  67 #  define BCMCPU_RUNTIME_DETECT
  68 # else
  69 #  define bcm63xx_get_cpu_id()  BCM6358_CPU_ID
  70 # endif
  71 # define BCMCPU_IS_6358()       (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
  72 #else
  73 # define BCMCPU_IS_6358()       (0)
  74 #endif
  75
  76 #ifndef bcm63xx_get_cpu_id
  77 #error "No CPU support configured"
  78 #endif
  79
  80 /*
  81  * While registers sets are (mostly) the same across 63xx CPU, base
  82  * address of these sets do change.
  83  */
  84 enum bcm63xx_regs_set {
  85         RSET_DSL_LMEM = 0,
  86         RSET_PERF,
  87         RSET_TIMER,
  88         RSET_WDT,
  89         RSET_UART0,
  90         RSET_GPIO,
  91         RSET_SPI,
  92         RSET_UDC0,
  93         RSET_OHCI0,
  94         RSET_OHCI_PRIV,
  95         RSET_USBH_PRIV,
  96         RSET_MPI,
  97         RSET_PCMCIA,
  98         RSET_DSL,
  99         RSET_ENET0,
 100         RSET_ENET1,
 101         RSET_ENETDMA,
 102         RSET_EHCI0,
 103         RSET_SDRAM,
 104         RSET_MEMC,
 105         RSET_DDR,
 106 };
 107
 108 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
 109 #define RSET_DSL_SIZE                   4096
 110 #define RSET_WDT_SIZE                   12
 111 #define RSET_ENET_SIZE                  2048
 112 #define RSET_ENETDMA_SIZE               2048
 113 #define RSET_UART_SIZE                  24
 114 #define RSET_SPI_SIZE                   256
 115 #define RSET_UDC_SIZE                   256
 116 #define RSET_OHCI_SIZE                  256
 117 #define RSET_EHCI_SIZE                  256
 118 #define RSET_PCMCIA_SIZE                12
 119
 120 /*
 121  * 6338 register sets base address
 122  */
 123
 124 #define BCM_6338_PERF_BASE              (0xfffe0000)
 125 #define BCM_6338_BB_BASE                (0xfffe0100) /* bus bridge registers */
 126 #define BCM_6338_TIMER_BASE             (0xfffe0200)
 127 #define BCM_6338_WDT_BASE               (0xfffe021c)
 128 #define BCM_6338_UART0_BASE             (0xfffe0300)
 129 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 130 #define BCM_6338_SPI_BASE               (0xfffe0c00)
 131 #define BCM_6338_DSL_BASE               (0xfffe1000)
 132 #define BCM_6338_SAR_BASE               (0xfffe2000)
 133 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
 134 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 135 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 136 #define BCM_6338_UDC0_BASE              (0xfffe3000) /* USB_CTL_BASE */
 137 #define BCM_6338_MEMC_BASE              (0xfffe3100)
 138
 139 /*
 140  * 6345 register sets base address
 141  */
 142 #define BCM_6345_PERF_BASE              (0xfffe0000)
 143 #define BCM_6345_TIMER_BASE             (0xfffe0200)
 144 #define BCM_6345_WDT_BASE               (0xfffe021c)
 145 #define BCM_6345_UART0_BASE             (0xfffe0300)
 146 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 147
 148 /*
 149  * 6348 register sets base address
 150  */
 151 #define BCM_6348_DSL_LMEM_BASE          (0xfff00000)
 152 #define BCM_6348_PERF_BASE              (0xfffe0000)
 153 #define BCM_6348_BB_BASE                (0xfffe0100) /* bus bridge registers */
 154 #define BCM_6348_TIMER_BASE             (0xfffe0200)
 155 #define BCM_6348_WDT_BASE               (0xfffe021c)
 156 #define BCM_6348_UART0_BASE             (0xfffe0300)
 157 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 158 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 159 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 160 #define BCM_6348_USBDMA_BASE            (0xfffe1400)
 161 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 162 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 163 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
 164 #define BCM_6348_MPI_BASE               (0xfffe2000)
 165 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 166 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
 167 #define BCM_6348_DSL_BASE               (0xfffe3000)
 168 #define BCM_6348_SAR_BASE               (0xfffe4000)
 169 #define BCM_6348_UBUS_BASE              (0xfffe5000)
 170 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 171 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 172 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
 173 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 174 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 175 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 176 #define BCM_6348_DDR_BASE               (0xdeadbeef)
 177
 178 /*
 179  * 6358 register sets base address
 180  */
 181 #define BCM_6358_DSL_LMEM_BASE          (0xfff00000)
 182 #define BCM_6358_PERF_BASE              (0xfffe0000)
 183 #define BCM_6358_TIMER_BASE             (0xfffe0040)
 184 #define BCM_6358_WDT_BASE               (0xfffe005c)
 185 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 186 #define BCM_6358_UART0_BASE             (0xfffe0100)
 187 #define BCM_6358_UDC0_BASE              (0xfffe0400)
 188 #define BCM_6358_SPI_BASE               (0xfffe0800)
 189 #define BCM_6358_MPI_BASE               (0xfffe1000)
 190 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 191 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 192 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 193 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
 194 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
 195 #define BCM_6358_DSL_BASE               (0xfffe3000)
 196 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 197 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 198 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
 199 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 200 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 201 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 202 #define BCM_6358_DDR_BASE               (0xfffe12a0)
 203
 204
 205 extern const unsigned long *bcm63xx_regs_base;
 206
 207 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 208 {
 209 #ifdef BCMCPU_RUNTIME_DETECT
 210         return bcm63xx_regs_base[set];
 211 #else
 212 #ifdef CONFIG_BCM63XX_CPU_6338
 213         switch (set) {
 214         case RSET_PERF:
 215                 return BCM_6338_PERF_BASE;
 216         case RSET_TIMER:
 217                 return BCM_6338_TIMER_BASE;
 218         case RSET_WDT:
 219                 return BCM_6338_WDT_BASE;
 220         case RSET_UART0:
 221                 return BCM_6338_UART0_BASE;
 222         case RSET_GPIO:
 223                 return BCM_6338_GPIO_BASE;
 224         case RSET_SPI:
 225                 return BCM_6338_SPI_BASE;
 226         case RSET_MEMC:
 227                 return BCM_6338_MEMC_BASE;
 228         }
 229 #endif
 230 #ifdef CONFIG_BCM63XX_CPU_6345
 231         switch (set) {
 232         case RSET_PERF:
 233                 return BCM_6345_PERF_BASE;
 234         case RSET_TIMER:
 235                 return BCM_6345_TIMER_BASE;
 236         case RSET_WDT:
 237                 return BCM_6345_WDT_BASE;
 238         case RSET_UART0:
 239                 return BCM_6345_UART0_BASE;
 240         case RSET_GPIO:
 241                 return BCM_6345_GPIO_BASE;
 242         }
 243 #endif
 244 #ifdef CONFIG_BCM63XX_CPU_6348
 245         switch (set) {
 246         case RSET_DSL_LMEM:
 247                 return BCM_6348_DSL_LMEM_BASE;
 248         case RSET_PERF:
 249                 return BCM_6348_PERF_BASE;
 250         case RSET_TIMER:
 251                 return BCM_6348_TIMER_BASE;
 252         case RSET_WDT:
 253                 return BCM_6348_WDT_BASE;
 254         case RSET_UART0:
 255                 return BCM_6348_UART0_BASE;
 256         case RSET_GPIO:
 257                 return BCM_6348_GPIO_BASE;
 258         case RSET_SPI:
 259                 return BCM_6348_SPI_BASE;
 260         case RSET_UDC0:
 261                 return BCM_6348_UDC0_BASE;
 262         case RSET_OHCI0:
 263                 return BCM_6348_OHCI0_BASE;
 264         case RSET_OHCI_PRIV:
 265                 return BCM_6348_OHCI_PRIV_BASE;
 266         case RSET_USBH_PRIV:
 267                 return BCM_6348_USBH_PRIV_BASE;
 268         case RSET_MPI:
 269                 return BCM_6348_MPI_BASE;
 270         case RSET_PCMCIA:
 271                 return BCM_6348_PCMCIA_BASE;
 272         case RSET_DSL:
 273                 return BCM_6348_DSL_BASE;
 274         case RSET_ENET0:
 275                 return BCM_6348_ENET0_BASE;
 276         case RSET_ENET1:
 277                 return BCM_6348_ENET1_BASE;
 278         case RSET_ENETDMA:
 279                 return BCM_6348_ENETDMA_BASE;
 280         case RSET_EHCI0:
 281                 return BCM_6348_EHCI0_BASE;
 282         case RSET_SDRAM:
 283                 return BCM_6348_SDRAM_BASE;
 284         case RSET_MEMC:
 285                 return BCM_6348_MEMC_BASE;
 286         case RSET_DDR:
 287                 return BCM_6348_DDR_BASE;
 288         }
 289 #endif
 290 #ifdef CONFIG_BCM63XX_CPU_6358
 291         switch (set) {
 292         case RSET_DSL_LMEM:
 293                 return BCM_6358_DSL_LMEM_BASE;
 294         case RSET_PERF:
 295                 return BCM_6358_PERF_BASE;
 296         case RSET_TIMER:
 297                 return BCM_6358_TIMER_BASE;
 298         case RSET_WDT:
 299                 return BCM_6358_WDT_BASE;
 300         case RSET_UART0:
 301                 return BCM_6358_UART0_BASE;
 302         case RSET_GPIO:
 303                 return BCM_6358_GPIO_BASE;
 304         case RSET_SPI:
 305                 return BCM_6358_SPI_BASE;
 306         case RSET_UDC0:
 307                 return BCM_6358_UDC0_BASE;
 308         case RSET_OHCI0:
 309                 return BCM_6358_OHCI0_BASE;
 310         case RSET_OHCI_PRIV:
 311                 return BCM_6358_OHCI_PRIV_BASE;
 312         case RSET_USBH_PRIV:
 313                 return BCM_6358_USBH_PRIV_BASE;
 314         case RSET_MPI:
 315                 return BCM_6358_MPI_BASE;
 316         case RSET_PCMCIA:
 317                 return BCM_6358_PCMCIA_BASE;
 318         case RSET_ENET0:
 319                 return BCM_6358_ENET0_BASE;
 320         case RSET_ENET1:
 321                 return BCM_6358_ENET1_BASE;
 322         case RSET_ENETDMA:
 323                 return BCM_6358_ENETDMA_BASE;
 324         case RSET_DSL:
 325                 return BCM_6358_DSL_BASE;
 326         case RSET_EHCI0:
 327                 return BCM_6358_EHCI0_BASE;
 328         case RSET_SDRAM:
 329                 return BCM_6358_SDRAM_BASE;
 330         case RSET_MEMC:
 331                 return BCM_6358_MEMC_BASE;
 332         case RSET_DDR:
 333                 return BCM_6358_DDR_BASE;
 334         }
 335 #endif
 336 #endif
 337         /* unreached */
 338         return 0;
 339 }
 340
 341 /*
 342  * SPI register layout is not compatible
 343  * accross CPU versions but it is software
 344  * compatible
 345  */
 346
 347 enum bcm63xx_regs_spi {
 348         SPI_CMD,
 349         SPI_INT_STATUS,
 350         SPI_INT_MASK_ST,
 351         SPI_INT_MASK,
 352         SPI_ST,
 353         SPI_CLK_CFG,
 354         SPI_FILL_BYTE,
 355         SPI_MSG_TAIL,
 356         SPI_RX_TAIL,
 357         SPI_MSG_CTL,
 358         SPI_MSG_DATA,
 359         SPI_RX_DATA,
 360 };
 361
 362 extern const unsigned long *bcm63xx_regs_spi;
 363
 364 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 365 {
 366 #ifdef BCMCPU_RUNTIME_DETECT
 367         return bcm63xx_regs_spi[reg];
 368 #else
 369 #ifdef CONFIG_BCM63XX_CPU_6338
 370 switch (reg) {
 371         case SPI_CMD:
 372                 return SPI_BCM_6338_SPI_CMD;
 373         case SPI_INT_STATUS:
 374                 return SPI_BCM_6338_SPI_INT_STATUS;
 375         case SPI_INT_MASK_ST:
 376                 return SPI_BCM_6338_SPI_MASK_INT_ST;
 377         case SPI_INT_MASK:
 378                 return SPI_BCM_6338_SPI_INT_MASK;
 379         case SPI_ST:
 380                 return SPI_BCM_6338_SPI_ST;
 381         case SPI_CLK_CFG:
 382                 return SPI_BCM_6338_SPI_CLK_CFG;
 383         case SPI_FILL_BYTE:
 384                 return SPI_BCM_6338_SPI_FILL_BYTE;
 385         case SPI_MSG_TAIL:
 386                 return SPI_BCM_6338_SPI_MSG_TAIL;
 387         case SPI_RX_TAIL:
 388                 return SPI_BCM_6338_SPI_RX_TAIL;
 389         case SPI_MSG_CTL:
 390                 return SPI_BCM_6338_SPI_MSG_CTL;
 391         case SPI_MSG_DATA:
 392                 return SPI_BCM_6338_SPI_MSG_DATA;
 393         case SPI_RX_DATA:
 394                 return SPI_BCM_6338_SPI_RX_DATA;
 395 }
 396 #endif
 397 #ifdef CONFIG_BCM63XX_CPU_6348
 398 switch (reg) {
 399         case SPI_CMD:
 400                 return SPI_BCM_6348_SPI_CMD;
 401         case SPI_INT_MASK_ST:
 402                 return SPI_BCM_6348_SPI_MASK_INT_ST;
 403         case SPI_INT_MASK:
 404                 return SPI_BCM_6348_SPI_INT_MASK;
 405         case SPI_INT_STATUS:
 406                 return SPI_BCM_6348_SPI_INT_STATUS;
 407         case SPI_ST:
 408                 return SPI_BCM_6348_SPI_ST;
 409         case SPI_CLK_CFG:
 410                 return SPI_BCM_6348_SPI_CLK_CFG;
 411         case SPI_FILL_BYTE:
 412                 return SPI_BCM_6348_SPI_FILL_BYTE;
 413         case SPI_MSG_TAIL:
 414                 return SPI_BCM_6348_SPI_MSG_TAIL;
 415         case SPI_RX_TAIL:
 416                 return SPI_BCM_6348_SPI_RX_TAIL;
 417         case SPI_MSG_CTL:
 418                 return SPI_BCM_6348_SPI_MSG_CTL;
 419         case SPI_MSG_DATA:
 420                 return SPI_BCM_6348_SPI_MSG_DATA;
 421         case SPI_RX_DATA:
 422                 return SPI_BCM_6348_SPI_RX_DATA;
 423 }
 424 #endif
 425 #ifdef CONFIG_BCM63XX_CPU_6358
 426 switch (reg) {
 427         case SPI_CMD:
 428                 return SPI_BCM_6358_SPI_CMD;
 429         case SPI_INT_STATUS:
 430                 return SPI_BCM_6358_SPI_INT_STATUS;
 431         case SPI_INT_MASK_ST:
 432                 return SPI_BCM_6358_SPI_MASK_INT_ST;
 433         case SPI_INT_MASK:
 434                 return SPI_BCM_6358_SPI_INT_MASK;
 435         case SPI_ST:
 436                 return SPI_BCM_6358_SPI_STATUS;
 437         case SPI_CLK_CFG:
 438                 return SPI_BCM_6358_SPI_CLK_CFG;
 439         case SPI_FILL_BYTE:
 440                 return SPI_BCM_6358_SPI_FILL_BYTE;
 441         case SPI_MSG_TAIL:
 442                 return SPI_BCM_6358_SPI_MSG_TAIL;
 443         case SPI_RX_TAIL:
 444                 return SPI_BCM_6358_SPI_RX_TAIL;
 445         case SPI_MSG_CTL:
 446                 return SPI_BCM_6358_MSG_CTL;
 447         case SPI_MSG_DATA:
 448                 return SPI_BCM_6358_SPI_MSG_DATA;
 449         case SPI_RX_DATA:
 450                 return SPI_BCM_6358_SPI_RX_DATA;
 451 }
 452 #endif
 453 #endif
 454         return 0;
 455 }
 456
 457 /*
 458  * IRQ number changes across CPU too
 459  */
 460 enum bcm63xx_irq {
 461         IRQ_TIMER = 0,
 462         IRQ_UART0,
 463         IRQ_SPI,
 464         IRQ_DSL,
 465         IRQ_UDC0,
 466         IRQ_ENET0,
 467         IRQ_ENET1,
 468         IRQ_ENET_PHY,
 469         IRQ_OHCI0,
 470         IRQ_EHCI0,
 471         IRQ_PCMCIA0,
 472         IRQ_ENET0_RXDMA,
 473         IRQ_ENET0_TXDMA,
 474         IRQ_ENET1_RXDMA,
 475         IRQ_ENET1_TXDMA,
 476         IRQ_PCI,
 477         IRQ_PCMCIA,
 478 };
 479
 480 /*
 481  * 6338 irqs
 482  */
 483 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 484 #define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 485 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 486 #define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
 487 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
 488 #define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
 489 #define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 490 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 491 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 492 #define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
 493 #define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
 494 #define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
 495 #define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
 496 #define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
 497 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 498 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 499 #define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
 500
 501 /*
 502  * 6345 irqs
 503  */
 504 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 505 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 506 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
 507 #define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
 508 #define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 509 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 510 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
 511
 512 /*
 513  * 6348 irqs
 514  */
 515 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 516 #define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 517 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 518 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
 519 #define BCM_6348_UDC0_IRQ               (IRQ_INTERNAL_BASE + 6)
 520 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 521 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 522 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 523 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 524 #define BCM_6348_USB_CNTL_RX_DMA        (IRQ_INTERNAL_BASE + 14)
 525 #define BCM_6348_USB_CNTL_TX_DMA        (IRQ_INTERNAL_BASE + 15)
 526 #define BCM_6348_USB_BULK_RX_DMA        (IRQ_INTERNAL_BASE + 16)
 527 #define BCM_6348_USB_BULK_TX_DMA        (IRQ_INTERNAL_BASE + 17)
 528 #define BCM_6348_USB_ISO_RX_DMA         (IRQ_INTERNAL_BASE + 18)
 529 #define BCM_6348_USB_ISO_TX_DMA         (IRQ_INTERNAL_BASE + 19)
 530 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 531 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 532 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 533 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
 534 #define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 535 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 536
 537 /*
 538  * 6358 irqs
 539  */
 540 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 541 #define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 542 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 543 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 544 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 545 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 546 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 547 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 548 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 549 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 550 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 551 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 552 #define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 553 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 554 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 555
 556 extern const int *bcm63xx_irqs;
 557
 558 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 559 {
 560         return bcm63xx_irqs[irq];
 561 }
 562
 563 /*
 564  * return installed memory size
 565  */
 566 unsigned int bcm63xx_get_memory_size(void);
 567
 568 #endif /* !BCM63XX_CPU_H_ */