4 #include <linux/types.h>
5 #include <linux/init.h>
7 #include <bcm63xx_regs.h>
10 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
11 * compile time if only one CPU support is enabled (idea stolen from
14 #define BCM6338_CPU_ID 0x6338
15 #define BCM6348_CPU_ID 0x6348
16 #define BCM6358_CPU_ID 0x6358
18 void __init bcm63xx_cpu_init(void);
19 u16 __bcm63xx_get_cpu_id(void);
20 u16 bcm63xx_get_cpu_rev(void);
21 unsigned int bcm63xx_get_cpu_freq(void);
23 #ifdef CONFIG_BCM63XX_CPU_6338
24 # ifdef bcm63xx_get_cpu_id
25 # undef bcm63xx_get_cpu_id
26 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
27 # define BCMCPU_RUNTIME_DETECT
29 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
31 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
33 # define BCMCPU_IS_6338() (0)
36 #ifdef CONFIG_BCM63XX_CPU_6348
37 # ifdef bcm63xx_get_cpu_id
38 # undef bcm63xx_get_cpu_id
39 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
40 # define BCMCPU_RUNTIME_DETECT
42 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
44 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
46 # define BCMCPU_IS_6348() (0)
49 #ifdef CONFIG_BCM63XX_CPU_6358
50 # ifdef bcm63xx_get_cpu_id
51 # undef bcm63xx_get_cpu_id
52 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
53 # define BCMCPU_RUNTIME_DETECT
55 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
57 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
59 # define BCMCPU_IS_6358() (0)
62 #ifndef bcm63xx_get_cpu_id
63 #error "No CPU support configured"
67 * While registers sets are (mostly) the same across 63xx CPU, base
68 * address of these sets do change.
70 enum bcm63xx_regs_set {
94 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
95 #define RSET_DSL_SIZE 4096
96 #define RSET_WDT_SIZE 12
97 #define RSET_ENET_SIZE 2048
98 #define RSET_ENETDMA_SIZE 2048
99 #define RSET_UART_SIZE 24
100 #define RSET_SPI_SIZE 256
101 #define RSET_UDC_SIZE 256
102 #define RSET_OHCI_SIZE 256
103 #define RSET_EHCI_SIZE 256
104 #define RSET_PCMCIA_SIZE 12
107 * 6338 register sets base address
110 #define BCM_6338_PERF_BASE (0xfffe0000)
111 #define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
112 #define BCM_6338_TIMER_BASE (0xfffe0200)
113 #define BCM_6338_WDT_BASE (0xfffe021c)
114 #define BCM_6338_UART0_BASE (0xfffe0300)
115 #define BCM_6338_GPIO_BASE (0xfffe0400)
116 #define BCM_6338_SPI_BASE (0xfffe0c00)
117 #define BCM_6338_DSL_BASE (0xfffe1000)
118 #define BCM_6338_SAR_BASE (0xfffe2000)
119 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
120 #define BCM_6338_USBDMA_BASE (0xfffe2400)
121 #define BCM_6338_ENET0_BASE (0xfffe2800)
122 #define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
123 #define BCM_6338_MEMC_BASE (0xfffe3100)
126 * 6348 register sets base address
128 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
129 #define BCM_6348_PERF_BASE (0xfffe0000)
130 #define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */
131 #define BCM_6348_TIMER_BASE (0xfffe0200)
132 #define BCM_6348_WDT_BASE (0xfffe021c)
133 #define BCM_6348_UART0_BASE (0xfffe0300)
134 #define BCM_6348_GPIO_BASE (0xfffe0400)
135 #define BCM_6348_SPI_BASE (0xfffe0c00)
136 #define BCM_6348_UDC0_BASE (0xfffe1000)
137 #define BCM_6348_USBDMA_BASE (0xfffe1400)
138 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
139 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
140 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
141 #define BCM_6348_MPI_BASE (0xfffe2000)
142 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
143 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
144 #define BCM_6348_DSL_BASE (0xfffe3000)
145 #define BCM_6348_SAR_BASE (0xfffe4000)
146 #define BCM_6348_UBUS_BASE (0xfffe5000)
147 #define BCM_6348_ENET0_BASE (0xfffe6000)
148 #define BCM_6348_ENET1_BASE (0xfffe6800)
149 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
150 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
151 #define BCM_6348_SDRAM_BASE (0xfffe2300)
152 #define BCM_6348_MEMC_BASE (0xdeadbeef)
153 #define BCM_6348_DDR_BASE (0xdeadbeef)
156 * 6358 register sets base address
158 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
159 #define BCM_6358_PERF_BASE (0xfffe0000)
160 #define BCM_6358_TIMER_BASE (0xfffe0040)
161 #define BCM_6358_WDT_BASE (0xfffe005c)
162 #define BCM_6358_GPIO_BASE (0xfffe0080)
163 #define BCM_6358_UART0_BASE (0xfffe0100)
164 #define BCM_6358_UDC0_BASE (0xfffe0400)
165 #define BCM_6358_SPI_BASE (0xfffe0800)
166 #define BCM_6358_MPI_BASE (0xfffe1000)
167 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
168 #define BCM_6358_OHCI0_BASE (0xfffe1400)
169 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
170 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
171 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
172 #define BCM_6358_DSL_BASE (0xfffe3000)
173 #define BCM_6358_ENET0_BASE (0xfffe4000)
174 #define BCM_6358_ENET1_BASE (0xfffe4800)
175 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
176 #define BCM_6358_EHCI0_BASE (0xfffe1300)
177 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
178 #define BCM_6358_MEMC_BASE (0xfffe1200)
179 #define BCM_6358_DDR_BASE (0xfffe12a0)
182 extern const unsigned long *bcm63xx_regs_base;
184 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
186 #ifdef BCMCPU_RUNTIME_DETECT
187 return bcm63xx_regs_base[set];
189 #ifdef CONFIG_BCM63XX_CPU_6338
192 return BCM_6338_PERF_BASE;
194 return BCM_6338_TIMER_BASE;
196 return BCM_6338_WDT_BASE;
198 return BCM_6338_UART0_BASE;
200 return BCM_6338_GPIO_BASE;
202 return BCM_6338_SPI_BASE;
204 return BCM_6338_MEMC_BASE;
207 #ifdef CONFIG_BCM63XX_CPU_6348
210 return BCM_6348_DSL_LMEM_BASE;
212 return BCM_6348_PERF_BASE;
214 return BCM_6348_TIMER_BASE;
216 return BCM_6348_WDT_BASE;
218 return BCM_6348_UART0_BASE;
220 return BCM_6348_GPIO_BASE;
222 return BCM_6348_SPI_BASE;
224 return BCM_6348_UDC0_BASE;
226 return BCM_6348_OHCI0_BASE;
228 return BCM_6348_OHCI_PRIV_BASE;
230 return BCM_6348_USBH_PRIV_BASE;
232 return BCM_6348_MPI_BASE;
234 return BCM_6348_PCMCIA_BASE;
236 return BCM_6348_DSL_BASE;
238 return BCM_6348_ENET0_BASE;
240 return BCM_6348_ENET1_BASE;
242 return BCM_6348_ENETDMA_BASE;
244 return BCM_6348_EHCI0_BASE;
246 return BCM_6348_SDRAM_BASE;
248 return BCM_6348_MEMC_BASE;
250 return BCM_6348_DDR_BASE;
253 #ifdef CONFIG_BCM63XX_CPU_6358
256 return BCM_6358_DSL_LMEM_BASE;
258 return BCM_6358_PERF_BASE;
260 return BCM_6358_TIMER_BASE;
262 return BCM_6358_WDT_BASE;
264 return BCM_6358_UART0_BASE;
266 return BCM_6358_GPIO_BASE;
268 return BCM_6358_SPI_BASE;
270 return BCM_6358_UDC0_BASE;
272 return BCM_6358_OHCI0_BASE;
274 return BCM_6358_OHCI_PRIV_BASE;
276 return BCM_6358_USBH_PRIV_BASE;
278 return BCM_6358_MPI_BASE;
280 return BCM_6358_PCMCIA_BASE;
282 return BCM_6358_ENET0_BASE;
284 return BCM_6358_ENET1_BASE;
286 return BCM_6358_ENETDMA_BASE;
288 return BCM_6358_DSL_BASE;
290 return BCM_6358_EHCI0_BASE;
292 return BCM_6358_SDRAM_BASE;
294 return BCM_6358_MEMC_BASE;
296 return BCM_6358_DDR_BASE;
305 * SPI register layout is not compatible
306 * accross CPU versions but it is software
310 enum bcm63xx_regs_spi {
325 extern const unsigned long *bcm63xx_regs_spi;
327 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
329 #ifdef BCMCPU_RUNTIME_DETECT
330 return bcm63xx_regs_spi[reg];
332 #ifdef CONFIG_BCM63XX_CPU_6338
335 return SPI_BCM_6338_SPI_CMD;
337 return SPI_BCM_6338_SPI_INT_STATUS;
338 case SPI_INT_MASK_ST:
339 return SPI_BCM_6338_SPI_MASK_INT_ST;
341 return SPI_BCM_6338_SPI_INT_MASK;
343 return SPI_BCM_6338_SPI_ST;
345 return SPI_BCM_6338_SPI_CLK_CFG;
347 return SPI_BCM_6338_SPI_FILL_BYTE;
349 return SPI_BCM_6338_SPI_MSG_TAIL;
351 return SPI_BCM_6338_SPI_RX_TAIL;
353 return SPI_BCM_6338_SPI_MSG_CTL;
355 return SPI_BCM_6338_SPI_MSG_DATA;
357 return SPI_BCM_6338_SPI_RX_DATA;
360 #ifdef CONFIG_BCM63XX_CPU_6348
363 return SPI_BCM_6348_SPI_CMD;
364 case SPI_INT_MASK_ST:
365 return SPI_BCM_6348_SPI_MASK_INT_ST;
367 return SPI_BCM_6348_SPI_INT_MASK;
369 return SPI_BCM_6348_SPI_INT_STATUS;
371 return SPI_BCM_6348_SPI_ST;
373 return SPI_BCM_6348_SPI_CLK_CFG;
375 return SPI_BCM_6348_SPI_FILL_BYTE;
377 return SPI_BCM_6348_SPI_MSG_TAIL;
379 return SPI_BCM_6348_SPI_RX_TAIL;
381 return SPI_BCM_6348_SPI_MSG_CTL;
383 return SPI_BCM_6348_SPI_MSG_DATA;
385 return SPI_BCM_6348_SPI_RX_DATA;
388 #ifdef CONFIG_BCM63XX_CPU_6358
391 return SPI_BCM_6358_SPI_CMD;
393 return SPI_BCM_6358_SPI_INT_STATUS;
394 case SPI_INT_MASK_ST:
395 return SPI_BCM_6358_SPI_MASK_INT_ST;
397 return SPI_BCM_6358_SPI_INT_MASK;
399 return SPI_BCM_6358_SPI_STATUS;
401 return SPI_BCM_6358_SPI_CLK_CFG;
403 return SPI_BCM_6358_SPI_FILL_BYTE;
405 return SPI_BCM_6358_SPI_MSG_TAIL;
407 return SPI_BCM_6358_SPI_RX_TAIL;
409 return SPI_BCM_6358_MSG_CTL;
411 return SPI_BCM_6358_SPI_MSG_DATA;
413 return SPI_BCM_6358_SPI_RX_DATA;
421 * IRQ number changes across CPU too
446 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
447 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
448 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
449 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
450 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
451 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
452 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
453 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
454 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
455 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
456 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
457 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
458 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
459 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
460 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
461 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
462 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
467 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
468 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
469 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
470 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
471 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
472 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
473 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
474 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
475 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
476 #define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
477 #define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
478 #define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
479 #define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
480 #define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
481 #define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
482 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
483 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
484 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
485 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
486 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
487 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
492 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
493 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
494 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
495 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
496 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
497 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
498 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
499 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
500 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
501 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
502 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
503 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
504 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
505 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
506 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
508 extern const int *bcm63xx_irqs;
510 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
512 return bcm63xx_irqs[irq];
516 * return installed memory size
518 unsigned int bcm63xx_get_memory_size(void);
520 #endif /* !BCM63XX_CPU_H_ */