target/linux/brcm63xx/files/drivers/spi/bcm63xx_spi.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the
  18  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/clk.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/spi_bitbang.h>
  30 #include <linux/gpio.h>
  31 #include <linux/completion.h>
  32 #include <linux/err.h>
  33
  34 #include <bcm63xx_io.h>
  35 #include <bcm63xx_regs.h>
  36 #include <bcm63xx_dev_spi.h>
  37
  38 #define PFX             KBUILD_MODNAME
  39 #define DRV_VER         "0.1.0"
  40
  41 struct bcm63xx_spi {
  42         /* bitbang has to be first */
  43         struct spi_bitbang      bitbang;
  44         struct completion       done;
  45
  46         void __iomem            *regs;
  47         int                     irq;
  48
  49         /* Platform data */
  50         u32                     speed_hz;
  51         unsigned                msg_fifo_size;
  52         unsigned                rx_fifo_size;
  53
  54         /* Data buffers */
  55         const unsigned char     *tx_ptr;
  56         unsigned char           *rx_ptr;
  57         int                     remaining_bytes;
  58
  59         struct clk              *clk;
  60         struct resource         *ioarea;
  61         struct platform_device  *pdev;
  62 };
  63
  64 static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
  65 {
  66         u16 val;
  67
  68         val = bcm_spi_readw(SPI_CMD);
  69         if (is_on == BITBANG_CS_INACTIVE)
  70                 val |= SPI_CMD_NOOP;
  71         else if (is_on == BITBANG_CS_ACTIVE)
  72                 val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
  73         bcm_spi_writew(val, SPI_CMD);
  74 }
  75
  76 static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
  77                                         struct spi_transfer *t)
  78 {
  79         u8 bits_per_word;
  80         u8 clk_cfg;
  81         u32 hz;
  82         unsigned int div;
  83
  84         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  85
  86         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
  87         hz = (t) ? t->speed_hz : spi->max_speed_hz;
  88         if (bits_per_word != 8) {
  89                 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
  90                         __func__, bits_per_word);
  91                 return -EINVAL;
  92         }
  93
  94         if (spi->chip_select > spi->master->num_chipselect) {
  95                 dev_err(&spi->dev, "%s, unsupported slave %d\n",
  96                         __func__, spi->chip_select);
  97                 return -EINVAL;
  98         }
  99
 100         /* Check clock setting */
 101         div = (bs->speed_hz / hz);
 102         switch (div) {
 103         case 2:
 104                 clk_cfg = SPI_CLK_25MHZ;
 105                 break;
 106         case 4:
 107                 clk_cfg = SPI_CLK_12_50MHZ;
 108                 break;
 109         case 8:
 110                 clk_cfg = SPI_CLK_6_250MHZ;
 111                 break;
 112         case 16:
 113                 clk_cfg = SPI_CLK_3_125MHZ;
 114                 break;
 115         case 32:
 116                 clk_cfg = SPI_CLK_1_563MHZ;
 117                 break;
 118         case 128:
 119                 clk_cfg = SPI_CLK_0_781MHZ;
 120                 break;
 121         case 64:
 122         default:
 123                 /* Set to slowest mode for compatibility */
 124                 clk_cfg = SPI_CLK_0_781MHZ;
 125                 break;
 126         }
 127
 128         bcm_spi_writeb(clk_cfg, SPI_CLK_CFG);
 129         dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 130                                                                 div, hz, clk_cfg);
 131
 132         return 0;
 133 }
 134
 135 /* the spi->mode bits understood by this driver: */
 136 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 137
 138 static int bcm63xx_spi_setup(struct spi_device *spi)
 139 {
 140         struct spi_bitbang *bitbang;
 141         struct bcm63xx_spi *bs;
 142         int retval;
 143
 144         bs = spi_master_get_devdata(spi->master);
 145         bitbang = &bs->bitbang;
 146
 147         if (!spi->bits_per_word)
 148                 spi->bits_per_word = 8;
 149
 150         if (spi->mode & ~MODEBITS) {
 151                 dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 152                         __func__, spi->mode & ~MODEBITS);
 153                 return -EINVAL;
 154         }
 155
 156         retval = bcm63xx_spi_setup_transfer(spi, NULL);
 157         if (retval < 0) {
 158                 dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 159                         spi->mode & ~MODEBITS);
 160                 return retval;
 161         }
 162
 163         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 164                 __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 165
 166         return 0;
 167 }
 168
 169 /* Fill the TX FIFO with as many bytes as possible */
 170 static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 171 {
 172         u8 tail;
 173
 174         /* Fill the Tx FIFO with as many bytes as possible */
 175         tail = bcm_spi_readb(SPI_MSG_TAIL);
 176         while ((tail < bs->msg_fifo_size) && (bs->remaining_bytes > 0)) {
 177                 if (bs->tx_ptr)
 178                         bcm_spi_writeb(*bs->tx_ptr++, SPI_MSG_DATA);
 179                 else
 180                         bcm_spi_writeb(0, SPI_MSG_DATA);
 181                 bs->remaining_bytes--;
 182                 tail = bcm_spi_readb(SPI_MSG_TAIL);
 183         }
 184 }
 185
 186 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 187 {
 188         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 189         u8 msg_ctl;
 190         u16 cmd;
 191
 192         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 193                                 t->tx_buf, t->rx_buf, t->len);
 194
 195         /* Transmitter is inhibited */
 196         bs->tx_ptr = t->tx_buf;
 197         bs->rx_ptr = t->rx_buf;
 198         bs->remaining_bytes = t->len;
 199         init_completion(&bs->done);
 200
 201         bcm63xx_spi_fill_tx_fifo(bs);
 202
 203         /* Enable the command done interrupt which
 204          * we use to determine completion of a command */
 205         bcm_writeb(SPI_INTR_CMD_DONE, SPI_INT_MASK);
 206
 207         /* Fill in the Message control register */
 208         msg_ctl = bcm_spi_readb(SPI_MSG_CTL);
 209         msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
 210         msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
 211         bcm_spi_writeb(msg_ctl, SPI_MSG_CTL);
 212
 213         /* Issue the transfer */
 214         cmd = bcm_spi_readb(SPI_CMD);
 215         cmd |= SPI_CMD_START_IMMEDIATE;
 216         cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 217         bcm_spi_writeb(cmd, SPI_CMD);
 218
 219         wait_for_completion(&bs->done);
 220
 221         /* Disable the CMD_DONE interrupt */
 222         bcm_spi_writeb(~(SPI_INTR_CMD_DONE), SPI_INT_MASK);
 223
 224         return t->len - bs->remaining_bytes;
 225 }
 226
 227 /* This driver supports single master mode only. Hence
 228  * CMD_DONE is the only interrupt we care about
 229  */
 230 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 231 {
 232         struct spi_master *master = (struct spi_master *)dev_id;
 233         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 234         u8 intr;
 235         u16 cmd;
 236
 237         /* Read interupts and clear them immediately */
 238         intr = bcm_spi_readb(SPI_INT_STATUS);
 239         bcm_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 240
 241         /* A tansfer completed */
 242         if (intr & SPI_INTR_CMD_DONE) {
 243                 u8 rx_empty;
 244
 245                 rx_empty = bcm_spi_readb(SPI_ST);
 246                 /* Read out all the data */
 247                 while ((rx_empty & SPI_RX_EMPTY) == 0) {
 248                         u8 data;
 249
 250                         data = bcm_spi_readb(SPI_RX_DATA);
 251                         if (bs->rx_ptr)
 252                                 *bs->rx_ptr++ = data;
 253
 254                         rx_empty = bcm_spi_readb(SPI_RX_EMPTY);
 255                 }
 256
 257                 /* See if there is more data to send */
 258                 if (bs->remaining_bytes > 0) {
 259                         bcm63xx_spi_fill_tx_fifo(bs);
 260
 261                         /* Start the transfer */
 262                         cmd = bcm_spi_readb(SPI_CMD);
 263                         cmd |= SPI_CMD_START_IMMEDIATE;
 264                         cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 265                         bcm_spi_writeb(cmd, SPI_CMD);
 266                 } else
 267                         complete(&bs->done);
 268         }
 269
 270         return IRQ_HANDLED;
 271 }
 272
 273
 274 static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 275 {
 276         struct resource *r;
 277         struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 278         int irq;
 279         struct spi_master *master;
 280         struct clk *clk;
 281         struct bcm63xx_spi *bs;
 282         int ret;
 283
 284         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 285         if (!r) {
 286                 ret = -ENXIO;
 287                 goto out;
 288         }
 289
 290         irq = platform_get_irq(pdev, 0);
 291         if (irq < 0) {
 292                 ret = -ENXIO;
 293                 goto out;
 294         }
 295
 296         clk = clk_get(&pdev->dev, "spi");
 297         if (IS_ERR(clk)) {
 298                 dev_err(&pdev->dev, "No clock for device\n");
 299                 ret = -ENODEV;
 300                 goto out;
 301         }
 302
 303         master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
 304         if (!master) {
 305                 ret = -ENOMEM;
 306                 goto out_free;
 307         }
 308
 309         bs = spi_master_get_devdata(master);
 310         bs->bitbang.master = spi_master_get(master);
 311         bs->bitbang.chipselect = bcm63xx_spi_chipselect;
 312         bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
 313         bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
 314         bs->bitbang.master->setup = bcm63xx_spi_setup;
 315         init_completion(&bs->done);
 316
 317         platform_set_drvdata(pdev, master);
 318         bs->pdev = pdev;
 319
 320         bs->regs = ioremap_nocache(r->start, r->end - r->start);
 321         if (!bs->regs) {
 322                 printk(KERN_ERR PFX " unable to ioremap regs\n");
 323                 ret = -ENOMEM;
 324                 goto out_free;
 325         }
 326         bs->irq = irq;
 327         bs->clk = clk;
 328         bs->msg_fifo_size = pdata->msg_fifo_size;
 329         bs->rx_fifo_size = pdata->rx_fifo_size;
 330
 331         ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
 332                                 pdev->dev.bus_id, master);
 333         if (ret) {
 334                 printk(KERN_ERR PFX " unable to request irq\n");
 335                 goto out_unmap;
 336         }
 337
 338         master->bus_num = pdata->bus_num;
 339         master->num_chipselect = pdata->num_chipselect;
 340         bs->speed_hz = pdata->speed_hz;
 341
 342         /* Initialize hardware */
 343         clk_enable(bs->clk);
 344         bcm_spi_writew(SPI_CMD_HARD_RESET, SPI_CMD);
 345         bcm_spi_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_MASK);
 346
 347         dev_info(&pdev->dev, PFX " at 0x%08x (irq %d) %s\n",
 348                                 r->start, irq, DRV_VER);
 349
 350         ret = spi_bitbang_start(&bs->bitbang);
 351         if (ret) {
 352                 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
 353                 goto out_reset_hw;
 354         }
 355
 356         return ret;
 357
 358 out_reset_hw:
 359         clk_disable(clk);
 360         free_irq(irq, master);
 361 out_unmap:
 362         iounmap(bs->regs);
 363 out_free:
 364         clk_put(clk);
 365         spi_master_put(master);
 366 out:
 367         return ret;
 368 }
 369
 370 static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 371 {
 372         struct spi_master       *master = platform_get_drvdata(pdev);
 373         struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 374
 375         spi_bitbang_stop(&bs->bitbang);
 376         clk_disable(bs->clk);
 377         clk_put(bs->clk);
 378         free_irq(bs->irq, master);
 379         iounmap(bs->regs);
 380         platform_set_drvdata(pdev, 0);
 381         spi_master_put(bs->bitbang.master);
 382
 383         return 0;
 384 }
 385
 386 #ifdef CONFIG_PM
 387 static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 388 {
 389         struct spi_master       *master = platform_get_drvdata(pdev);
 390         struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 391
 392         clk_disable(bs->clk);
 393
 394         return 0;
 395 }
 396
 397 static int bcm63xx_spi_resume(struct platform_device *pdev)
 398 {
 399         struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 400         struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 401
 402         clk_enable(bs->clk);
 403
 404         return 0;
 405 }
 406 #else
 407 #define bcm63xx_spi_suspend     NULL
 408 #define bcm63xx_spi_resume      NULL
 409 #endif
 410
 411 static struct platform_driver bcm63xx_spi_driver = {
 412         .driver = {
 413                 .name   = "bcm63xx-spi",
 414                 .owner  = THIS_MODULE,
 415         },
 416         .probe          = bcm63xx_spi_probe,
 417         .remove         = bcm63xx_spi_remove,
 418         .suspend        = bcm63xx_spi_suspend,
 419         .resume         = bcm63xx_spi_resume,
 420 };
 421
 422
 423 static int __init bcm63xx_spi_init(void)
 424 {
 425         return platform_driver_register(&bcm63xx_spi_driver);
 426 }
 427
 428 static void __exit bcm63xx_spi_exit(void)
 429 {
 430         platform_driver_unregister(&bcm63xx_spi_driver);
 431 }
 432
 433 module_init(bcm63xx_spi_init);
 434 module_exit(bcm63xx_spi_exit);
 435
 436 MODULE_ALIAS("platform:bcm63xx_spi");
 437 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 438 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 439 MODULE_LICENSE("GPL");