target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *               2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/cpu.h>
  13 #include <bcm63xx_cpu.h>
  14 #include <bcm63xx_regs.h>
  15 #include <bcm63xx_io.h>
  16 #include <bcm63xx_irq.h>
  17
  18 const unsigned long *bcm63xx_regs_base;
  19 EXPORT_SYMBOL(bcm63xx_regs_base);
  20
  21 const int *bcm63xx_irqs;
  22 EXPORT_SYMBOL(bcm63xx_irqs);
  23
  24 const unsigned long *bcm63xx_regs_spi;
  25 EXPORT_SYMBOL(bcm63xx_regs_spi);
  26
  27 static u16 bcm63xx_cpu_id;
  28 static u16 bcm63xx_cpu_rev;
  29 static unsigned int bcm63xx_cpu_freq;
  30 static unsigned int bcm63xx_memory_size;
  31
  32 /*
  33  * 6338 register sets and irqs
  34  */
  35
  36 static const unsigned long bcm96338_regs_base[] = {
  37         [RSET_PERF]             = BCM_6338_PERF_BASE,
  38         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
  39         [RSET_WDT]              = BCM_6338_WDT_BASE,
  40         [RSET_UART0]            = BCM_6338_UART0_BASE,
  41         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
  42         [RSET_SPI]              = BCM_6338_SPI_BASE,
  43         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
  44 };
  45
  46 static const int bcm96338_irqs[] = {
  47         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
  48         [IRQ_SPI]               = BCM_6338_SPI_IRQ,
  49         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
  50         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  51         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  52         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
  53         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
  54         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
  55 };
  56
  57 static const unsigned long bcm96338_regs_spi[] = {
  58         [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
  59         [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
  60         [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
  61         [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
  62         [SPI_ST]                = SPI_BCM_6338_SPI_ST,
  63         [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
  64         [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
  65         [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
  66         [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
  67         [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
  68         [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
  69         [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
  70 };
  71
  72 /*
  73  * 6348 register sets and irqs
  74  */
  75 static const unsigned long bcm96348_regs_base[] = {
  76         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
  77         [RSET_PERF]             = BCM_6348_PERF_BASE,
  78         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
  79         [RSET_WDT]              = BCM_6348_WDT_BASE,
  80         [RSET_UART0]            = BCM_6348_UART0_BASE,
  81         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
  82         [RSET_SPI]              = BCM_6348_SPI_BASE,
  83         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
  84         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
  85         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
  86         [RSET_MPI]              = BCM_6348_MPI_BASE,
  87         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
  88         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
  89         [RSET_DSL]              = BCM_6348_DSL_BASE,
  90         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
  91         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
  92         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
  93         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
  94         [RSET_DDR]              = BCM_6348_DDR_BASE,
  95 };
  96
  97 static const int bcm96348_irqs[] = {
  98         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  99         [IRQ_SPI]               = BCM_6348_SPI_IRQ,
 100         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
 101         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
 102         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
 103         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
 104         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
 105         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
 106         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
 107         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
 108         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
 109         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
 110         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
 111         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
 112 };
 113
 114 static const unsigned long bcm96348_regs_spi[] = {
 115         [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 116         [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 117         [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 118         [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 119         [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 120         [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 121         [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 122         [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 123         [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 124         [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 125         [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 126         [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 127 };
 128
 129 /*
 130  * 6358 register sets and irqs
 131  */
 132 static const unsigned long bcm96358_regs_base[] = {
 133         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
 134         [RSET_PERF]             = BCM_6358_PERF_BASE,
 135         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 136         [RSET_WDT]              = BCM_6358_WDT_BASE,
 137         [RSET_UART0]            = BCM_6358_UART0_BASE,
 138         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 139         [RSET_SPI]              = BCM_6358_SPI_BASE,
 140         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 141         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 142         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 143         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 144         [RSET_MPI]              = BCM_6358_MPI_BASE,
 145         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 146         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 147         [RSET_DSL]              = BCM_6358_DSL_BASE,
 148         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 149         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 150         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 151         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 152         [RSET_DDR]              = BCM_6358_DDR_BASE,
 153 };
 154
 155 static const int bcm96358_irqs[] = {
 156         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 157         [IRQ_SPI]               = BCM_6358_SPI_IRQ,
 158         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 159         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 160         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 161         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 162         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 163         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 164         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 165         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 166         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 167         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 168         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 169         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 170         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 171 };
 172
 173 static const unsigned long bcm96358_regs_spi[] = {
 174         [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 175         [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 176         [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 177         [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 178         [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 179         [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 180         [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 181         [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 182         [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 183         [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 184         [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 185         [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 186 };
 187
 188 u16 __bcm63xx_get_cpu_id(void)
 189 {
 190         return bcm63xx_cpu_id;
 191 }
 192
 193 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 194
 195 u16 bcm63xx_get_cpu_rev(void)
 196 {
 197         return bcm63xx_cpu_rev;
 198 }
 199
 200 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 201
 202 unsigned int bcm63xx_get_cpu_freq(void)
 203 {
 204         return bcm63xx_cpu_freq;
 205 }
 206
 207 unsigned int bcm63xx_get_memory_size(void)
 208 {
 209         return bcm63xx_memory_size;
 210 }
 211
 212 static unsigned int detect_cpu_clock(void)
 213 {
 214         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 215
 216         if (BCMCPU_IS_6338()) {
 217                 return 240000000;
 218         }
 219
 220         /*
 221          * frequency depends on PLL configuration:
 222          */
 223         if (BCMCPU_IS_6348()) {
 224                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 225                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 226                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 227                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 228                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 229                 n1 += 1;
 230                 n2 += 2;
 231                 m1 += 1;
 232         }
 233
 234         if (BCMCPU_IS_6358()) {
 235                 /* 16MHz * N1 * N2 / M1_CPU */
 236                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 237                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 238                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 239                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 240         }
 241
 242         return (16 * 1000000 * n1 * n2) / m1;
 243 }
 244
 245 /*
 246  * attempt to detect the amount of memory installed
 247  */
 248 static unsigned int detect_memory_size(void)
 249 {
 250         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 251         u32 val;
 252
 253         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 254                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 255                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 256                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 257                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 258                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 259         }
 260
 261         if (BCMCPU_IS_6358()) {
 262                 val = bcm_memc_readl(MEMC_CFG_REG);
 263                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 264                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 265                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 266                 banks = 2;
 267         }
 268
 269         /* 0 => 11 address bits ... 2 => 13 address bits */
 270         rows += 11;
 271
 272         /* 0 => 8 address bits ... 2 => 10 address bits */
 273         cols += 8;
 274
 275         return 1 << (cols + rows + (is_32bits + 1) + banks);
 276 }
 277
 278 void __init bcm63xx_cpu_init(void)
 279 {
 280         unsigned int tmp, expected_cpu_id;
 281         struct cpuinfo_mips *c = &current_cpu_data;
 282
 283         /* soc registers location depends on cpu type */
 284         expected_cpu_id = 0;
 285
 286         switch (c->cputype) {
 287         case CPU_BCM6338:
 288                 expected_cpu_id = BCM6338_CPU_ID;
 289                 bcm63xx_regs_base = bcm96338_regs_base;
 290                 bcm63xx_irqs = bcm96338_irqs;
 291                 bcm63xx_regs_spi = bcm96338_regs_spi;
 292                 break;
 293         case CPU_BCM6348:
 294                 expected_cpu_id = BCM6348_CPU_ID;
 295                 bcm63xx_regs_base = bcm96348_regs_base;
 296                 bcm63xx_irqs = bcm96348_irqs;
 297                 bcm63xx_regs_spi = bcm96348_regs_spi;
 298                 break;
 299         case CPU_BCM6358:
 300                 expected_cpu_id = BCM6358_CPU_ID;
 301                 bcm63xx_regs_base = bcm96358_regs_base;
 302                 bcm63xx_irqs = bcm96358_irqs;
 303                 bcm63xx_regs_spi = bcm96358_regs_spi;
 304                 break;
 305         }
 306
 307         /* really early to panic, but delaying panic would not help
 308          * since we will never get any working console */
 309         if (!expected_cpu_id)
 310                 panic("unsupported Broadcom CPU");
 311
 312         /*
 313          * bcm63xx_regs_base is set, we can access soc registers
 314          */
 315
 316         /* double check CPU type */
 317         tmp = bcm_perf_readl(PERF_REV_REG);
 318         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 319         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 320
 321         if (bcm63xx_cpu_id != expected_cpu_id)
 322                 panic("bcm63xx CPU id mismatch");
 323
 324         bcm63xx_cpu_freq = detect_cpu_clock();
 325         bcm63xx_memory_size = detect_memory_size();
 326
 327         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 328                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 329         printk(KERN_INFO "CPU frequency is %u Hz\n",
 330                bcm63xx_cpu_freq);
 331         printk(KERN_INFO "%uMB of RAM installed\n",
 332                bcm63xx_memory_size >> 20);
 333 }