add support for bcm6345 SoC, needs testing
[oweals/openwrt.git] / target / linux / brcm63xx / files / arch / mips / bcm63xx / cpu.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7  *               2009 Florian Fainelli <florian@openwrt.org>
8  */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/cpu.h>
13 #include <bcm63xx_cpu.h>
14 #include <bcm63xx_regs.h>
15 #include <bcm63xx_io.h>
16 #include <bcm63xx_irq.h>
17
18 const unsigned long *bcm63xx_regs_base;
19 EXPORT_SYMBOL(bcm63xx_regs_base);
20
21 const int *bcm63xx_irqs;
22 EXPORT_SYMBOL(bcm63xx_irqs);
23
24 const unsigned long *bcm63xx_regs_spi;
25 EXPORT_SYMBOL(bcm63xx_regs_spi);
26
27 static u16 bcm63xx_cpu_id;
28 static u16 bcm63xx_cpu_rev;
29 static unsigned int bcm63xx_cpu_freq;
30 static unsigned int bcm63xx_memory_size;
31
32 /*
33  * 6338 register sets and irqs
34  */
35
36 static const unsigned long bcm96338_regs_base[] = {
37         [RSET_PERF]             = BCM_6338_PERF_BASE,
38         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
39         [RSET_WDT]              = BCM_6338_WDT_BASE,
40         [RSET_UDC0]             = BCM_6338_UDC0_BASE,
41         [RSET_UART0]            = BCM_6338_UART0_BASE,
42         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
43         [RSET_SPI]              = BCM_6338_SPI_BASE,
44         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
45 };
46
47 static const int bcm96338_irqs[] = {
48         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
49         [IRQ_SPI]               = BCM_6338_SPI_IRQ,
50         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
51         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
52         [IRQ_UDC0]              = BCM_6338_UDC0_IRQ,
53         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
54         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
55         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
56         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
57 };
58
59 static const unsigned long bcm96338_regs_spi[] = {
60         [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
61         [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
62         [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
63         [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
64         [SPI_ST]                = SPI_BCM_6338_SPI_ST,
65         [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
66         [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
67         [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
68         [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
69         [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
70         [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
71         [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
72 };
73
74 /*
75  * 6345 register sets and irqs
76  */
77
78 static const unsigned long bcm96345_regs_base[] = {
79         [RSET_PERF]             = BCM_6345_PERF_BASE,
80         [RSET_TIMER]            = BCM_6345_TIMER_BASE,
81         [RSET_WDT]              = BCM_6345_WDT_BASE,
82         [RSET_UART0]            = BCM_6345_UART0_BASE,
83         [RSET_GPIO]             = BCM_6345_GPIO_BASE,
84 };
85
86 static const int bcm96345_irqs[] = {
87         [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
88         [IRQ_UART0]             = BCM_6345_UART0_IRQ,
89         [IRQ_DSL]               = BCM_6345_DSL_IRQ,
90         [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
91         [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
92 };
93
94 /*
95  * 6348 register sets and irqs
96  */
97 static const unsigned long bcm96348_regs_base[] = {
98         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
99         [RSET_PERF]             = BCM_6348_PERF_BASE,
100         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
101         [RSET_WDT]              = BCM_6348_WDT_BASE,
102         [RSET_UART0]            = BCM_6348_UART0_BASE,
103         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
104         [RSET_SPI]              = BCM_6348_SPI_BASE,
105         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
106         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
107         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
108         [RSET_UDC0]             = BCM_6348_UDC0_BASE,
109         [RSET_MPI]              = BCM_6348_MPI_BASE,
110         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
111         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
112         [RSET_DSL]              = BCM_6348_DSL_BASE,
113         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
114         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
115         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
116         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
117         [RSET_DDR]              = BCM_6348_DDR_BASE,
118 };
119
120 static const int bcm96348_irqs[] = {
121         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
122         [IRQ_SPI]               = BCM_6348_SPI_IRQ,
123         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
124         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
125         [IRQ_UDC0]              = BCM_6348_UDC0_IRQ,
126         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
127         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
128         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
129         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
130         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
131         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
132         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
133         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
134         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
135         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
136 };
137
138 static const unsigned long bcm96348_regs_spi[] = {
139         [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
140         [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
141         [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
142         [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
143         [SPI_ST]                = SPI_BCM_6348_SPI_ST,
144         [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
145         [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
146         [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
147         [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
148         [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
149         [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
150         [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
151 };
152
153 /*
154  * 6358 register sets and irqs
155  */
156 static const unsigned long bcm96358_regs_base[] = {
157         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
158         [RSET_PERF]             = BCM_6358_PERF_BASE,
159         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
160         [RSET_WDT]              = BCM_6358_WDT_BASE,
161         [RSET_UART0]            = BCM_6358_UART0_BASE,
162         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
163         [RSET_SPI]              = BCM_6358_SPI_BASE,
164         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
165         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
166         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
167         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
168         [RSET_MPI]              = BCM_6358_MPI_BASE,
169         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
170         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
171         [RSET_DSL]              = BCM_6358_DSL_BASE,
172         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
173         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
174         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
175         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
176         [RSET_DDR]              = BCM_6358_DDR_BASE,
177 };
178
179 static const int bcm96358_irqs[] = {
180         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
181         [IRQ_SPI]               = BCM_6358_SPI_IRQ,
182         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
183         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
184         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
185         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
186         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
187         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
188         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
189         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
190         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
191         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
192         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
193         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
194         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
195 };
196
197 static const unsigned long bcm96358_regs_spi[] = {
198         [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
199         [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
200         [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
201         [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
202         [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
203         [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
204         [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
205         [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
206         [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
207         [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
208         [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
209         [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
210 };
211
212 u16 __bcm63xx_get_cpu_id(void)
213 {
214         return bcm63xx_cpu_id;
215 }
216
217 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
218
219 u16 bcm63xx_get_cpu_rev(void)
220 {
221         return bcm63xx_cpu_rev;
222 }
223
224 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
225
226 unsigned int bcm63xx_get_cpu_freq(void)
227 {
228         return bcm63xx_cpu_freq;
229 }
230
231 unsigned int bcm63xx_get_memory_size(void)
232 {
233         return bcm63xx_memory_size;
234 }
235
236 static unsigned int detect_cpu_clock(void)
237 {
238         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
239
240         if (BCMCPU_IS_6338())
241                 return 240000000;
242
243         if (BCMCPU_IS_6345())
244                 return 140000000;
245
246         /*
247          * frequency depends on PLL configuration:
248          */
249         if (BCMCPU_IS_6348()) {
250                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
251                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
252                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
253                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
254                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
255                 n1 += 1;
256                 n2 += 2;
257                 m1 += 1;
258         }
259
260         if (BCMCPU_IS_6358()) {
261                 /* 16MHz * N1 * N2 / M1_CPU */
262                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
263                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
264                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
265                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
266         }
267
268         return (16 * 1000000 * n1 * n2) / m1;
269 }
270
271 /*
272  * attempt to detect the amount of memory installed
273  */
274 static unsigned int detect_memory_size(void)
275 {
276         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
277         u32 val;
278
279         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
280                 val = bcm_sdram_readl(SDRAM_CFG_REG);
281                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
282                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
283                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
284                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
285         }
286
287         if (BCMCPU_IS_6358()) {
288                 val = bcm_memc_readl(MEMC_CFG_REG);
289                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
290                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
291                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
292                 banks = 2;
293         }
294
295         /* 0 => 11 address bits ... 2 => 13 address bits */
296         rows += 11;
297
298         /* 0 => 8 address bits ... 2 => 10 address bits */
299         cols += 8;
300
301         return 1 << (cols + rows + (is_32bits + 1) + banks);
302 }
303
304 void __init bcm63xx_cpu_init(void)
305 {
306         unsigned int tmp, expected_cpu_id;
307         struct cpuinfo_mips *c = &current_cpu_data;
308
309         /* soc registers location depends on cpu type */
310         expected_cpu_id = 0;
311
312         switch (c->cputype) {
313         case CPU_BCM6338:
314                 expected_cpu_id = BCM6338_CPU_ID;
315                 bcm63xx_regs_base = bcm96338_regs_base;
316                 bcm63xx_irqs = bcm96338_irqs;
317                 bcm63xx_regs_spi = bcm96338_regs_spi;
318                 break;
319         case CPU_BCM6345:
320                 expected_cpu_id = BCM6345_CPU_ID;
321                 bcm63xx_regs_base = bcm96345_regs_base;
322                 bcm63xx_irqs = bcm96345_irqs;
323                 break;
324         case CPU_BCM6348:
325                 expected_cpu_id = BCM6348_CPU_ID;
326                 bcm63xx_regs_base = bcm96348_regs_base;
327                 bcm63xx_irqs = bcm96348_irqs;
328                 bcm63xx_regs_spi = bcm96348_regs_spi;
329                 break;
330         case CPU_BCM6358:
331                 expected_cpu_id = BCM6358_CPU_ID;
332                 bcm63xx_regs_base = bcm96358_regs_base;
333                 bcm63xx_irqs = bcm96358_irqs;
334                 bcm63xx_regs_spi = bcm96358_regs_spi;
335                 break;
336         }
337
338         /* really early to panic, but delaying panic would not help
339          * since we will never get any working console */
340         if (!expected_cpu_id)
341                 panic("unsupported Broadcom CPU");
342
343         /*
344          * bcm63xx_regs_base is set, we can access soc registers
345          */
346
347         /* double check CPU type */
348         tmp = bcm_perf_readl(PERF_REV_REG);
349         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
350         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
351
352         if (bcm63xx_cpu_id != expected_cpu_id)
353                 panic("bcm63xx CPU id mismatch");
354
355         bcm63xx_cpu_freq = detect_cpu_clock();
356         bcm63xx_memory_size = detect_memory_size();
357
358         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
359                bcm63xx_cpu_id, bcm63xx_cpu_rev);
360         printk(KERN_INFO "CPU frequency is %u Hz\n",
361                bcm63xx_cpu_freq);
362         printk(KERN_INFO "%uMB of RAM installed\n",
363                bcm63xx_memory_size >> 20);
364 }