target/linux/brcm47xx-2.6/patches/150-cpu_fixes.patch

   1 Index: linux-2.6.22-rc4/arch/mips/kernel/genex.S
   2 ===================================================================
   3 --- linux-2.6.22-rc4.orig/arch/mips/kernel/genex.S      2007-06-10 21:32:12.000000000 +0100
   4 +++ linux-2.6.22-rc4/arch/mips/kernel/genex.S   2007-06-10 21:33:19.000000000 +0100
   5 @@ -51,6 +51,10 @@
   6  NESTED(except_vec3_generic, 0, sp)
   7         .set    push
   8         .set    noat
   9 +#ifdef CONFIG_BCM947XX
  10 +       nop
  11 +       nop
  12 +#endif
  13  #if R5432_CP0_INTERRUPT_WAR
  14         mfc0    k0, CP0_INDEX
  15  #endif
  16 Index: linux-2.6.22-rc4/arch/mips/mm/c-r4k.c
  17 ===================================================================
  18 --- linux-2.6.22-rc4.orig/arch/mips/mm/c-r4k.c  2007-06-10 21:33:17.000000000 +0100
  19 +++ linux-2.6.22-rc4/arch/mips/mm/c-r4k.c       2007-06-10 21:33:19.000000000 +0100
  20 @@ -29,6 +29,9 @@
  21  #include <asm/cacheflush.h> /* for run_uncached() */
  22
  23
  24 +/* For enabling BCM4710 cache workarounds */
  25 +int bcm4710 = 0;
  26 +
  27  /*
  28   * Special Variant of smp_call_function for use by cache functions:
  29   *
  30 @@ -93,6 +96,9 @@
  31  {
  32         unsigned long  dc_lsize = cpu_dcache_line_size();
  33
  34 +       if (bcm4710)
  35 +               r4k_blast_dcache_page = blast_dcache_page;
  36 +       else
  37         if (dc_lsize == 0)
  38                 r4k_blast_dcache_page = (void *)cache_noop;
  39         else if (dc_lsize == 16)
  40 @@ -107,6 +113,9 @@
  41  {
  42         unsigned long dc_lsize = cpu_dcache_line_size();
  43
  44 +       if (bcm4710)
  45 +               r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
  46 +       else
  47         if (dc_lsize == 0)
  48                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
  49         else if (dc_lsize == 16)
  50 @@ -121,6 +130,9 @@
  51  {
  52         unsigned long dc_lsize = cpu_dcache_line_size();
  53
  54 +       if (bcm4710)
  55 +               r4k_blast_dcache = blast_dcache;
  56 +       else
  57         if (dc_lsize == 0)
  58                 r4k_blast_dcache = (void *)cache_noop;
  59         else if (dc_lsize == 16)
  60 @@ -538,6 +550,9 @@
  61                 r4k_blast_icache();
  62         else
  63                 protected_blast_icache_range(start, end);
  64 +
  65 +       if (bcm4710)
  66 +               r4k_flush_cache_all();
  67  }
  68
  69  static void r4k_flush_icache_range(unsigned long start, unsigned long end)
  70 @@ -618,6 +633,8 @@
  71         unsigned long addr = (unsigned long) arg;
  72
  73         R4600_HIT_CACHEOP_WAR_IMPL;
  74 +       BCM4710_PROTECTED_FILL_TLB(addr);
  75 +       BCM4710_PROTECTED_FILL_TLB(addr + 4);
  76         if (dc_lsize)
  77                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  78         if (!cpu_icache_snoops_remote_store && scache_size)
  79 @@ -1173,6 +1190,15 @@
  80
  81         /* Default cache error handler for R4000 and R5000 family */
  82         set_uncached_handler (0x100, &except_vec2_generic, 0x80);
  83 +
  84 +       /* Check if special workarounds are required */
  85 +#ifdef CONFIG_BCM947XX
  86 +       if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
  87 +               printk("Enabling BCM4710A0 cache workarounds.\n");
  88 +               bcm4710 = 1;
  89 +       } else
  90 +#endif
  91 +               bcm4710 = 0;
  92
  93         probe_pcache();
  94         setup_scache();
  95 Index: linux-2.6.22-rc4/arch/mips/mm/tlbex.c
  96 ===================================================================
  97 --- linux-2.6.22-rc4.orig/arch/mips/mm/tlbex.c  2007-06-10 21:33:12.000000000 +0100
  98 +++ linux-2.6.22-rc4/arch/mips/mm/tlbex.c       2007-06-10 21:33:19.000000000 +0100
  99 @@ -1229,6 +1229,10 @@
 100  #endif
 101  }
 102
 103 +#ifdef CONFIG_BCM947XX
 104 +extern int bcm4710;
 105 +#endif
 106 +
 107  static void __init build_r4000_tlb_refill_handler(void)
 108  {
 109         u32 *p = tlb_handler;
 110 @@ -1243,6 +1247,12 @@
 111         memset(relocs, 0, sizeof(relocs));
 112         memset(final_handler, 0, sizeof(final_handler));
 113
 114 +#ifdef CONFIG_BCM947XX
 115 +       if (bcm4710) {
 116 +               i_nop(&p);
 117 +       }
 118 +#endif
 119 +
 120         /*
 121          * create the plain linear handler
 122          */
 123 Index: linux-2.6.22-rc4/include/asm-mips/r4kcache.h
 124 ===================================================================
 125 --- linux-2.6.22-rc4.orig/include/asm-mips/r4kcache.h   2007-06-10 21:32:12.000000000 +0100
 126 +++ linux-2.6.22-rc4/include/asm-mips/r4kcache.h        2007-06-10 21:33:19.000000000 +0100
 127 @@ -17,6 +17,20 @@
 128  #include <asm/cpu-features.h>
 129  #include <asm/mipsmtregs.h>
 130
 131 +#ifdef CONFIG_BCM947XX
 132 +#include <asm/paccess.h>
 133 +#include <linux/ssb/ssb.h>
 134 +#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
 135 +
 136 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
 137 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
 138 +#else
 139 +#define BCM4710_DUMMY_RREG()
 140 +
 141 +#define BCM4710_FILL_TLB(addr)
 142 +#define BCM4710_PROTECTED_FILL_TLB(addr)
 143 +#endif
 144 +
 145  /*
 146   * This macro return a properly sign-extended address suitable as base address
 147   * for indexed cache operations.  Two issues here:
 148 @@ -150,6 +164,7 @@
 149  static inline void flush_dcache_line_indexed(unsigned long addr)
 150  {
 151         __dflush_prologue
 152 +       BCM4710_DUMMY_RREG();
 153         cache_op(Index_Writeback_Inv_D, addr);
 154         __dflush_epilogue
 155  }
 156 @@ -169,6 +184,7 @@
 157  static inline void flush_dcache_line(unsigned long addr)
 158  {
 159         __dflush_prologue
 160 +       BCM4710_DUMMY_RREG();
 161         cache_op(Hit_Writeback_Inv_D, addr);
 162         __dflush_epilogue
 163  }
 164 @@ -176,6 +192,7 @@
 165  static inline void invalidate_dcache_line(unsigned long addr)
 166  {
 167         __dflush_prologue
 168 +       BCM4710_DUMMY_RREG();
 169         cache_op(Hit_Invalidate_D, addr);
 170         __dflush_epilogue
 171  }
 172 @@ -208,6 +225,7 @@
 173   */
 174  static inline void protected_flush_icache_line(unsigned long addr)
 175  {
 176 +       BCM4710_DUMMY_RREG();
 177         protected_cache_op(Hit_Invalidate_I, addr);
 178  }
 179
 180 @@ -219,6 +237,7 @@
 181   */
 182  static inline void protected_writeback_dcache_line(unsigned long addr)
 183  {
 184 +       BCM4710_DUMMY_RREG();
 185         protected_cache_op(Hit_Writeback_Inv_D, addr);
 186  }
 187
 188 @@ -339,8 +358,52 @@
 189                 : "r" (base),                                           \
 190                   "i" (op));
 191
 192 +static inline void blast_dcache(void)
 193 +{
 194 +       unsigned long start = KSEG0;
 195 +       unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
 196 +       unsigned long end = (start + dcache_size);
 197 +
 198 +       do {
 199 +               BCM4710_DUMMY_RREG();
 200 +               cache_op(Index_Writeback_Inv_D, start);
 201 +               start += current_cpu_data.dcache.linesz;
 202 +       } while(start < end);
 203 +}
 204 +
 205 +static inline void blast_dcache_page(unsigned long page)
 206 +{
 207 +       unsigned long start = page;
 208 +       unsigned long end = start + PAGE_SIZE;
 209 +
 210 +       BCM4710_FILL_TLB(start);
 211 +       do {
 212 +               BCM4710_DUMMY_RREG();
 213 +               cache_op(Hit_Writeback_Inv_D, start);
 214 +               start += current_cpu_data.dcache.linesz;
 215 +       } while(start < end);
 216 +}
 217 +
 218 +static inline void blast_dcache_page_indexed(unsigned long page)
 219 +{
 220 +       unsigned long start = page;
 221 +       unsigned long end = start + PAGE_SIZE;
 222 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 223 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 224 +                              current_cpu_data.dcache.waybit;
 225 +       unsigned long ws, addr;
 226 +       for (ws = 0; ws < ws_end; ws += ws_inc) {
 227 +               start = page + ws;
 228 +               for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
 229 +                       BCM4710_DUMMY_RREG();
 230 +                       cache_op(Index_Writeback_Inv_D, addr);
 231 +               }
 232 +       }
 233 +}
 234 +
 235 +
 236  /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 237 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
 238 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
 239  static inline void blast_##pfx##cache##lsize(void)                     \
 240  {                                                                      \
 241         unsigned long start = INDEX_BASE;                               \
 242 @@ -352,6 +415,7 @@
 243                                                                         \
 244         __##pfx##flush_prologue                                         \
 245                                                                         \
 246 +       war                                                             \
 247         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 248                 for (addr = start; addr < end; addr += lsize * 32)      \
 249                         cache##lsize##_unroll32(addr|ws,indexop);       \
 250 @@ -366,6 +430,7 @@
 251                                                                         \
 252         __##pfx##flush_prologue                                         \
 253                                                                         \
 254 +       war                                                             \
 255         do {                                                            \
 256                 cache##lsize##_unroll32(start,hitop);                   \
 257                 start += lsize * 32;                                    \
 258 @@ -384,6 +449,8 @@
 259                                current_cpu_data.desc.waybit;            \
 260         unsigned long ws, addr;                                         \
 261                                                                         \
 262 +       war                                                             \
 263 +                                                                       \
 264         __##pfx##flush_prologue                                         \
 265                                                                         \
 266         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 267 @@ -393,28 +460,30 @@
 268         __##pfx##flush_epilogue                                         \
 269  }
 270
 271 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
 272 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
 273 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
 274 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
 275 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 276 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
 277 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 278 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
 279 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
 280 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
 281 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
 282 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
 283 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
 284 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
 285 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
 286 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
 287 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
 288 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
 289
 290  /* build blast_xxx_range, protected_blast_xxx_range */
 291 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
 292 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
 293  static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
 294                                                     unsigned long end)  \
 295  {                                                                      \
 296         unsigned long lsize = cpu_##desc##_line_size();                 \
 297         unsigned long addr = start & ~(lsize - 1);                      \
 298         unsigned long aend = (end - 1) & ~(lsize - 1);                  \
 299 +       war                                                             \
 300                                                                         \
 301         __##pfx##flush_prologue                                         \
 302                                                                         \
 303         while (1) {                                                     \
 304 +               war2                                            \
 305                 prot##cache_op(hitop, addr);                            \
 306                 if (addr == aend)                                       \
 307                         break;                                          \
 308 @@ -424,13 +493,13 @@
 309         __##pfx##flush_epilogue                                         \
 310  }
 311
 312 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
 313 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
 314 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
 315 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
 316 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
 317 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 318 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
 319 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
 320 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 321 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
 322  /* blast_inv_dcache_range */
 323 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
 324 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
 325 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
 326 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
 327
 328  #endif /* _ASM_R4KCACHE_H */
 329 Index: linux-2.6.22-rc4/include/asm-mips/stackframe.h
 330 ===================================================================
 331 --- linux-2.6.22-rc4.orig/include/asm-mips/stackframe.h 2007-06-10 21:32:12.000000000 +0100
 332 +++ linux-2.6.22-rc4/include/asm-mips/stackframe.h      2007-06-10 21:33:19.000000000 +0100
 333 @@ -352,6 +352,10 @@
 334                 .macro  RESTORE_SP_AND_RET
 335                 LONG_L  sp, PT_R29(sp)
 336                 .set    mips3
 337 +#ifdef CONFIG_BCM947XX
 338 +               nop
 339 +               nop
 340 +#endif
 341                 eret
 342                 .set    mips0
 343                 .endm