target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mipscore.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom MIPS core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12
  13 #include <linux/serial.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/serial_reg.h>
  16 #include <asm/time.h>
  17
  18 #include "ssb_private.h"
  19
  20
  21 static inline u32 mips_read32(struct ssb_mipscore *mcore,
  22                               u16 offset)
  23 {
  24         return ssb_read32(mcore->dev, offset);
  25 }
  26
  27 static inline void mips_write32(struct ssb_mipscore *mcore,
  28                                 u16 offset,
  29                                 u32 value)
  30 {
  31         ssb_write32(mcore->dev, offset, value);
  32 }
  33
  34 static const u32 ipsflag_irq_mask[] = {
  35         0,
  36         SSB_IPSFLAG_IRQ1,
  37         SSB_IPSFLAG_IRQ2,
  38         SSB_IPSFLAG_IRQ3,
  39         SSB_IPSFLAG_IRQ4,
  40 };
  41
  42 static const u32 ipsflag_irq_shift[] = {
  43         0,
  44         SSB_IPSFLAG_IRQ1_SHIFT,
  45         SSB_IPSFLAG_IRQ2_SHIFT,
  46         SSB_IPSFLAG_IRQ3_SHIFT,
  47         SSB_IPSFLAG_IRQ4_SHIFT,
  48 };
  49
  50 static inline u32 ssb_irqflag(struct ssb_device *dev)
  51 {
  52         return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
  53 }
  54
  55 /* Get the MIPS IRQ assignment for a specified device.
  56  * If unassigned, 0 is returned.
  57  */
  58 unsigned int ssb_mips_irq(struct ssb_device *dev)
  59 {
  60         struct ssb_bus *bus = dev->bus;
  61         u32 irqflag;
  62         u32 ipsflag;
  63         u32 tmp;
  64         unsigned int irq;
  65
  66         irqflag = ssb_irqflag(dev);
  67         ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
  68         for (irq = 1; irq <= 4; irq++) {
  69                 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
  70                 if (tmp == irqflag)
  71                         break;
  72         }
  73         if (irq == 5)
  74                 irq = 0;
  75
  76         return irq;
  77 }
  78
  79 static void clear_irq(struct ssb_bus *bus, unsigned int irq)
  80 {
  81         struct ssb_device *dev = bus->mipscore.dev;
  82
  83         /* Clear the IRQ in the MIPScore backplane registers */
  84         if (irq == 0) {
  85                 ssb_write32(dev, SSB_INTVEC, 0);
  86         } else {
  87                 ssb_write32(dev, SSB_IPSFLAG,
  88                             ssb_read32(dev, SSB_IPSFLAG) |
  89                             ipsflag_irq_mask[irq]);
  90         }
  91 }
  92
  93 static void set_irq(struct ssb_device *dev, unsigned int irq)
  94 {
  95         unsigned int oldirq = ssb_mips_irq(dev);
  96         struct ssb_bus *bus = dev->bus;
  97         struct ssb_device *mdev = bus->mipscore.dev;
  98         u32 irqflag = ssb_irqflag(dev);
  99
 100         dev->irq = irq + 2;
 101
 102         ssb_dprintk(KERN_INFO PFX
 103                     "set_irq: core 0x%04x, irq %d => %d\n",
 104                     dev->id.coreid, oldirq, irq);
 105         /* clear the old irq */
 106         if (oldirq == 0)
 107                 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
 108         else
 109                 clear_irq(bus, oldirq);
 110
 111         /* assign the new one */
 112         if (irq == 0)
 113                 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
 114
 115         irqflag <<= ipsflag_irq_shift[irq];
 116         irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
 117         ssb_write32(mdev, SSB_IPSFLAG, irqflag);
 118 }
 119
 120 /* XXX: leave here or move into separate extif driver? */
 121 static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
 122 {
 123
 124 }
 125
 126
 127 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
 128 {
 129         struct ssb_bus *bus = mcore->dev->bus;
 130
 131         //TODO if (EXTIF available
 132 #if 0
 133                 extifregs_t *eir = (extifregs_t *) regs;
 134                 sbconfig_t *sb;
 135
 136                 /* Determine external UART register base */
 137                 sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
 138                 base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
 139
 140                 /* Determine IRQ */
 141                 irq = sb_irq(sbh);
 142
 143                 /* Disable GPIO interrupt initially */
 144                 W_REG(&eir->gpiointpolarity, 0);
 145                 W_REG(&eir->gpiointmask, 0);
 146
 147                 /* Search for external UARTs */
 148                 n = 2;
 149                 for (i = 0; i < 2; i++) {
 150                         regs = (void *) REG_MAP(base + (i * 8), 8);
 151                         if (BCMINIT(serial_exists)(regs)) {
 152                                 /* Set GPIO 1 to be the external UART IRQ */
 153                                 W_REG(&eir->gpiointmask, 2);
 154                                 if (add)
 155                                         add(regs, irq, 13500000, 0);
 156                         }
 157                 }
 158
 159                 /* Add internal UART if enabled */
 160                 if (R_REG(&eir->corecontrol) & CC_UE)
 161                         if (add)
 162                                 add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
 163
 164 #endif
 165         if (bus->extif.dev)
 166                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
 167         else if (bus->chipco.dev)
 168                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
 169         else
 170                 mcore->nr_serial_ports = 0;
 171 }
 172
 173 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
 174 {
 175         struct ssb_bus *bus = mcore->dev->bus;
 176
 177         if (bus->chipco.dev) {
 178                 mcore->flash_window = 0x1c000000;
 179                 mcore->flash_window_size = 0x800000;
 180         } else {
 181                 mcore->flash_window = 0x1fc00000;
 182                 mcore->flash_window_size = 0x400000;
 183         }
 184 }
 185
 186
 187 static void ssb_cpu_clock(struct ssb_mipscore *mcore)
 188 {
 189 }
 190
 191 void ssb_mipscore_init(struct ssb_mipscore *mcore)
 192 {
 193         struct ssb_bus *bus = mcore->dev->bus;
 194         struct ssb_device *dev;
 195         unsigned long hz, ns;
 196         unsigned int irq, i;
 197
 198         if (!mcore->dev)
 199                 return; /* We don't have a MIPS core */
 200
 201         ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
 202
 203         hz = ssb_clockspeed(bus);
 204         if (!hz)
 205                 hz = 100000000;
 206         ns = 1000000000 / hz;
 207
 208 //TODO
 209 #if 0
 210         if (have EXTIF) {
 211                 /* Initialize extif so we can get to the LEDs and external UART */
 212                 W_REG(&eir->prog_config, CF_EN);
 213
 214                 /* Set timing for the flash */
 215                 tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
 216                 tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
 217                 tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
 218                 W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
 219
 220                 /* Set programmable interface timing for external uart */
 221                 tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
 222                 tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
 223                 tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
 224                 tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
 225                 W_REG(&eir->prog_waitcount, tmp);
 226         }
 227         else... chipcommon
 228 #endif
 229         if (bus->chipco.dev)
 230                 ssb_chipco_timing_init(&bus->chipco, ns);
 231
 232         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
 233         for (irq = 2, i = 0; i < bus->nr_devices; i++) {
 234                 dev = &(bus->devices[i]);
 235                 dev->irq = ssb_mips_irq(dev) + 2;
 236                 switch(dev->id.coreid) {
 237                         case SSB_DEV_USB11_HOST:
 238                                 /* shouldn't need a separate irq line for non-4710, most of them have a proper
 239                                  * external usb controller on the pci */
 240                                 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
 241                                         set_irq(dev, irq++);
 242                                         break;
 243                                 }
 244                         case SSB_DEV_PCI:
 245                         case SSB_DEV_ETHERNET:
 246                         case SSB_DEV_80211:
 247                         case SSB_DEV_USB20_HOST:
 248                                 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
 249                                 if (irq <= 4) {
 250                                         set_irq(dev, irq++);
 251                                         break;
 252                                 }
 253                 }
 254         }
 255
 256         ssb_mips_serial_init(mcore);
 257         ssb_mips_flash_detect(mcore);
 258 }