target/linux/brcm47xx/patches-4.4/159-cpu_fixes.patch

   1 --- a/arch/mips/include/asm/r4kcache.h
   2 +++ b/arch/mips/include/asm/r4kcache.h
   3 @@ -25,6 +25,38 @@
   4  extern void (*r4k_blast_dcache)(void);
   5  extern void (*r4k_blast_icache)(void);
   6
   7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
   8 +#include <asm/paccess.h>
   9 +#include <linux/ssb/ssb.h>
  10 +#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
  11 +
  12 +static inline unsigned long bcm4710_dummy_rreg(void)
  13 +{
  14 +      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
  15 +}
  16 +
  17 +#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
  18 +
  19 +static inline unsigned long bcm4710_fill_tlb(void *addr)
  20 +{
  21 +      return *(unsigned long *)addr;
  22 +}
  23 +
  24 +#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
  25 +
  26 +static inline void bcm4710_protected_fill_tlb(void *addr)
  27 +{
  28 +      unsigned long x;
  29 +      get_dbe(x, (unsigned long *)addr);;
  30 +}
  31 +
  32 +#else
  33 +#define BCM4710_DUMMY_RREG()
  34 +
  35 +#define BCM4710_FILL_TLB(addr)
  36 +#define BCM4710_PROTECTED_FILL_TLB(addr)
  37 +#endif
  38 +
  39  /*
  40   * This macro return a properly sign-extended address suitable as base address
  41   * for indexed cache operations.  Two issues here:
  42 @@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
  43  static inline void flush_dcache_line_indexed(unsigned long addr)
  44  {
  45         __dflush_prologue
  46 +       BCM4710_DUMMY_RREG();
  47         cache_op(Index_Writeback_Inv_D, addr);
  48         __dflush_epilogue
  49  }
  50 @@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
  51  static inline void flush_dcache_line(unsigned long addr)
  52  {
  53         __dflush_prologue
  54 +       BCM4710_DUMMY_RREG();
  55         cache_op(Hit_Writeback_Inv_D, addr);
  56         __dflush_epilogue
  57  }
  58 @@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
  59  static inline void invalidate_dcache_line(unsigned long addr)
  60  {
  61         __dflush_prologue
  62 +       BCM4710_DUMMY_RREG();
  63         cache_op(Hit_Invalidate_D, addr);
  64         __dflush_epilogue
  65  }
  66 @@ -187,6 +222,7 @@ static inline void protected_flush_icach
  67  #ifdef CONFIG_EVA
  68                 protected_cachee_op(Hit_Invalidate_I, addr);
  69  #else
  70 +               BCM4710_DUMMY_RREG();
  71                 protected_cache_op(Hit_Invalidate_I, addr);
  72  #endif
  73                 break;
  74 @@ -201,6 +237,7 @@ static inline void protected_flush_icach
  75   */
  76  static inline void protected_writeback_dcache_line(unsigned long addr)
  77  {
  78 +       BCM4710_DUMMY_RREG();
  79  #ifdef CONFIG_EVA
  80         protected_cachee_op(Hit_Writeback_Inv_D, addr);
  81  #else
  82 @@ -554,8 +591,51 @@ static inline void invalidate_tcache_pag
  83                 : "r" (base),                                           \
  84                   "i" (op));
  85
  86 +static inline void blast_dcache(void)
  87 +{
  88 +       unsigned long start = KSEG0;
  89 +       unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
  90 +       unsigned long end = (start + dcache_size);
  91 +
  92 +       do {
  93 +               BCM4710_DUMMY_RREG();
  94 +               cache_op(Index_Writeback_Inv_D, start);
  95 +               start += current_cpu_data.dcache.linesz;
  96 +       } while(start < end);
  97 +}
  98 +
  99 +static inline void blast_dcache_page(unsigned long page)
 100 +{
 101 +       unsigned long start = page;
 102 +       unsigned long end = start + PAGE_SIZE;
 103 +
 104 +       BCM4710_FILL_TLB(start);
 105 +       do {
 106 +               BCM4710_DUMMY_RREG();
 107 +               cache_op(Hit_Writeback_Inv_D, start);
 108 +               start += current_cpu_data.dcache.linesz;
 109 +       } while(start < end);
 110 +}
 111 +
 112 +static inline void blast_dcache_page_indexed(unsigned long page)
 113 +{
 114 +       unsigned long start = page;
 115 +       unsigned long end = start + PAGE_SIZE;
 116 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 117 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 118 +                              current_cpu_data.dcache.waybit;
 119 +       unsigned long ws, addr;
 120 +       for (ws = 0; ws < ws_end; ws += ws_inc) {
 121 +               start = page + ws;
 122 +               for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
 123 +                       BCM4710_DUMMY_RREG();
 124 +                       cache_op(Index_Writeback_Inv_D, addr);
 125 +               }
 126 +       }
 127 +}
 128 +
 129  /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 130 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)   \
 131 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
 132  static inline void extra##blast_##pfx##cache##lsize(void)              \
 133  {                                                                      \
 134         unsigned long start = INDEX_BASE;                               \
 135 @@ -567,6 +647,7 @@ static inline void extra##blast_##pfx##c
 136                                                                         \
 137         __##pfx##flush_prologue                                         \
 138                                                                         \
 139 +       war                                                             \
 140         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 141                 for (addr = start; addr < end; addr += lsize * 32)      \
 142                         cache##lsize##_unroll32(addr|ws, indexop);      \
 143 @@ -581,6 +662,7 @@ static inline void extra##blast_##pfx##c
 144                                                                         \
 145         __##pfx##flush_prologue                                         \
 146                                                                         \
 147 +       war                                                             \
 148         do {                                                            \
 149                 cache##lsize##_unroll32(start, hitop);                  \
 150                 start += lsize * 32;                                    \
 151 @@ -599,6 +681,8 @@ static inline void extra##blast_##pfx##c
 152                                current_cpu_data.desc.waybit;            \
 153         unsigned long ws, addr;                                         \
 154                                                                         \
 155 +       war                                                             \
 156 +                                                                       \
 157         __##pfx##flush_prologue                                         \
 158                                                                         \
 159         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 160 @@ -608,26 +692,26 @@ static inline void extra##blast_##pfx##c
 161         __##pfx##flush_epilogue                                         \
 162  }
 163
 164 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
 165 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
 166 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
 167 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
 168 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
 169 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
 170 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
 171 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
 172 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
 173 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
 174 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
 175 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
 176 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
 177 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
 178 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
 179 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
 180 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
 181 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
 182 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
 183 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
 184 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
 185 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
 186 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
 187 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
 188 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
 189 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
 190
 191 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
 192 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
 193 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
 194 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
 195 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
 196 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
 197 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
 198 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
 199 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
 200 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
 201 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
 202 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
 203
 204  #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
 205  static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
 206 @@ -656,17 +740,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
 207  __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 208
 209  /* build blast_xxx_range, protected_blast_xxx_range */
 210 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)       \
 211 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)    \
 212  static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
 213                                                     unsigned long end)  \
 214  {                                                                      \
 215         unsigned long lsize = cpu_##desc##_line_size();                 \
 216         unsigned long addr = start & ~(lsize - 1);                      \
 217         unsigned long aend = (end - 1) & ~(lsize - 1);                  \
 218 +       war                                                             \
 219                                                                         \
 220         __##pfx##flush_prologue                                         \
 221                                                                         \
 222         while (1) {                                                     \
 223 +               war2                                                    \
 224                 prot##cache_op(hitop, addr);                            \
 225                 if (addr == aend)                                       \
 226                         break;                                          \
 227 @@ -678,8 +764,8 @@ static inline void prot##extra##blast_##
 228
 229  #ifndef CONFIG_EVA
 230
 231 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 232 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
 233 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 234 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
 235
 236  #else
 237
 238 @@ -716,14 +802,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
 239  __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
 240
 241  #endif
 242 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 243 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
 244  __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
 245 -       protected_, loongson2_)
 246 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 247 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
 248 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 249 +       protected_, loongson2_, , )
 250 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 251 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
 252 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
 253  /* blast_inv_dcache_range */
 254 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
 255 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
 256 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
 257 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
 258
 259  #endif /* _ASM_R4KCACHE_H */
 260 --- a/arch/mips/include/asm/stackframe.h
 261 +++ b/arch/mips/include/asm/stackframe.h
 262 @@ -358,6 +358,10 @@
 263                 .macro  RESTORE_SP_AND_RET
 264                 LONG_L  sp, PT_R29(sp)
 265                 .set    arch=r4000
 266 +#ifdef CONFIG_BCM47XX
 267 +               nop
 268 +               nop
 269 +#endif
 270                 eret
 271                 .set    mips0
 272                 .endm
 273 --- a/arch/mips/kernel/genex.S
 274 +++ b/arch/mips/kernel/genex.S
 275 @@ -21,6 +21,19 @@
 276  #include <asm/war.h>
 277  #include <asm/thread_info.h>
 278
 279 +#ifdef CONFIG_BCM47XX
 280 +# ifdef eret
 281 +#  undef eret
 282 +# endif
 283 +# define eret                                  \
 284 +       .set push;                              \
 285 +       .set noreorder;                         \
 286 +        nop;                                   \
 287 +        nop;                                   \
 288 +        eret;                                  \
 289 +       .set pop;
 290 +#endif
 291 +
 292         __INIT
 293
 294  /*
 295 @@ -32,6 +45,9 @@
 296  NESTED(except_vec3_generic, 0, sp)
 297         .set    push
 298         .set    noat
 299 +#ifdef CONFIG_BCM47XX
 300 +       nop
 301 +#endif
 302  #if R5432_CP0_INTERRUPT_WAR
 303         mfc0    k0, CP0_INDEX
 304  #endif
 305 @@ -55,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
 306         .set    push
 307         .set    arch=r4000
 308         .set    noat
 309 +#ifdef CONFIG_BCM47XX
 310 +       nop
 311 +#endif
 312         mfc0    k1, CP0_CAUSE
 313         li      k0, 31<<2
 314         andi    k1, k1, 0x7c
 315 --- a/arch/mips/mm/c-r4k.c
 316 +++ b/arch/mips/mm/c-r4k.c
 317 @@ -39,6 +39,9 @@
 318  #include <asm/dma-coherence.h>
 319  #include <asm/mips-cm.h>
 320
 321 +/* For enabling BCM4710 cache workarounds */
 322 +static int bcm4710 = 0;
 323 +
 324  /*
 325   * Bits describing what cache ops an IPI callback function may perform.
 326   *
 327 @@ -202,6 +205,9 @@ static void r4k_blast_dcache_user_page_s
 328  {
 329         unsigned long  dc_lsize = cpu_dcache_line_size();
 330
 331 +       if (bcm4710)
 332 +               r4k_blast_dcache_page = blast_dcache_page;
 333 +       else
 334         if (dc_lsize == 0)
 335                 r4k_blast_dcache_user_page = (void *)cache_noop;
 336         else if (dc_lsize == 16)
 337 @@ -220,6 +226,9 @@ static void r4k_blast_dcache_page_indexe
 338  {
 339         unsigned long dc_lsize = cpu_dcache_line_size();
 340
 341 +       if (bcm4710)
 342 +               r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
 343 +       else
 344         if (dc_lsize == 0)
 345                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 346         else if (dc_lsize == 16)
 347 @@ -239,6 +248,9 @@ static void r4k_blast_dcache_setup(void)
 348  {
 349         unsigned long dc_lsize = cpu_dcache_line_size();
 350
 351 +       if (bcm4710)
 352 +               r4k_blast_dcache = blast_dcache;
 353 +       else
 354         if (dc_lsize == 0)
 355                 r4k_blast_dcache = (void *)cache_noop;
 356         else if (dc_lsize == 16)
 357 @@ -880,6 +892,8 @@ static void local_r4k_flush_cache_sigtra
 358         unsigned long addr = (unsigned long) arg;
 359
 360         R4600_HIT_CACHEOP_WAR_IMPL;
 361 +       BCM4710_PROTECTED_FILL_TLB(addr);
 362 +       BCM4710_PROTECTED_FILL_TLB(addr + 4);
 363         if (dc_lsize)
 364                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 365         if (!cpu_icache_snoops_remote_store && scache_size)
 366 @@ -1704,6 +1718,17 @@ static void coherency_setup(void)
 367          * silly idea of putting something else there ...
 368          */
 369         switch (current_cpu_type()) {
 370 +       case CPU_BMIPS3300:
 371 +               {
 372 +                       u32 cm;
 373 +                       cm = read_c0_diag();
 374 +                       /* Enable icache */
 375 +                       cm |= (1 << 31);
 376 +                       /* Enable dcache */
 377 +                       cm |= (1 << 30);
 378 +                       write_c0_diag(cm);
 379 +               }
 380 +               break;
 381         case CPU_R4000PC:
 382         case CPU_R4000SC:
 383         case CPU_R4000MC:
 384 @@ -1750,6 +1775,15 @@ void r4k_cache_init(void)
 385         extern void build_copy_page(void);
 386         struct cpuinfo_mips *c = &current_cpu_data;
 387
 388 +       /* Check if special workarounds are required */
 389 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
 390 +       if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
 391 +               printk("Enabling BCM4710A0 cache workarounds.\n");
 392 +               bcm4710 = 1;
 393 +       } else
 394 +#endif
 395 +               bcm4710 = 0;
 396 +
 397         probe_pcache();
 398         setup_scache();
 399
 400 @@ -1819,7 +1853,15 @@ void r4k_cache_init(void)
 401          */
 402         local_r4k___flush_cache_all(NULL);
 403
 404 +#ifdef CONFIG_BCM47XX
 405 +       {
 406 +               static void (*_coherency_setup)(void);
 407 +               _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
 408 +               _coherency_setup();
 409 +       }
 410 +#else
 411         coherency_setup();
 412 +#endif
 413         board_cache_error_setup = r4k_cache_error_setup;
 414
 415         /*
 416 --- a/arch/mips/mm/tlbex.c
 417 +++ b/arch/mips/mm/tlbex.c
 418 @@ -943,6 +943,9 @@ build_get_pgde32(u32 **p, unsigned int t
 419                 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
 420                 uasm_i_addu(p, ptr, tmp, ptr);
 421  #else
 422 +#ifdef CONFIG_BCM47XX
 423 +               uasm_i_nop(p);
 424 +#endif
 425                 UASM_i_LA_mostly(p, ptr, pgdc);
 426  #endif
 427                 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
 428 @@ -1284,6 +1287,9 @@ static void build_r4000_tlb_refill_handl
 429  #ifdef CONFIG_64BIT
 430                 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
 431  #else
 432 +# ifdef CONFIG_BCM47XX
 433 +               uasm_i_nop(&p);
 434 +# endif
 435                 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
 436  #endif
 437
 438 @@ -1295,6 +1301,9 @@ static void build_r4000_tlb_refill_handl
 439                 build_update_entries(&p, K0, K1);
 440                 build_tlb_write_entry(&p, &l, &r, tlb_random);
 441                 uasm_l_leave(&l, p);
 442 +#ifdef CONFIG_BCM47XX
 443 +               uasm_i_nop(&p);
 444 +#endif
 445                 uasm_i_eret(&p); /* return from trap */
 446         }
 447  #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 448 @@ -1871,6 +1880,9 @@ build_r4000_tlbchange_handler_head(u32 *
 449  #ifdef CONFIG_64BIT
 450         build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
 451  #else
 452 +# ifdef CONFIG_BCM47XX
 453 +       uasm_i_nop(p);
 454 +# endif
 455         build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
 456  #endif
 457
 458 @@ -1917,6 +1929,9 @@ build_r4000_tlbchange_handler_tail(u32 *
 459         build_tlb_write_entry(p, l, r, tlb_indexed);
 460         uasm_l_leave(l, *p);
 461         build_restore_work_registers(p);
 462 +#ifdef CONFIG_BCM47XX
 463 +       uasm_i_nop(p);
 464 +#endif
 465         uasm_i_eret(p); /* return from trap */
 466
 467  #ifdef CONFIG_64BIT