1 --- a/drivers/net/ethernet/broadcom/tg3.c
2 +++ b/drivers/net/ethernet/broadcom/tg3.c
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
11 @@ -251,6 +252,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
12 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
13 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
14 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
15 + {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
16 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
17 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
18 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
19 @@ -533,7 +535,9 @@ static void _tw32_flush(struct tg3 *tp,
20 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
22 tp->write32_mbox(tp, off, val);
23 - if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
24 + if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
25 + (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
26 + !tg3_flag(tp, ICH_WORKAROUND)))
27 tp->read32_mbox(tp, off);
30 @@ -543,7 +547,8 @@ static void tg3_write32_tx_mbox(struct t
32 if (tg3_flag(tp, TXD_MBOX_HWBUG))
34 - if (tg3_flag(tp, MBOX_WRITE_REORDER))
35 + if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
36 + tg3_flag(tp, FLUSH_POSTED_WRITES))
40 @@ -1050,7 +1055,8 @@ static void tg3_switch_clocks(struct tg3
42 #define PHY_BUSY_LOOPS 5000
44 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
45 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
50 @@ -1066,7 +1072,7 @@ static int tg3_readphy(struct tg3 *tp, i
54 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
55 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
56 MI_COM_PHY_ADDR_MASK);
57 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
58 MI_COM_REG_ADDR_MASK);
59 @@ -1103,7 +1109,13 @@ static int tg3_readphy(struct tg3 *tp, i
63 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
64 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
66 + return __tg3_readphy(tp, tp->phy_addr, reg, val);
69 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
74 @@ -1121,7 +1133,7 @@ static int tg3_writephy(struct tg3 *tp,
76 tg3_ape_lock(tp, tp->phy_ape_lock);
78 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
79 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
80 MI_COM_PHY_ADDR_MASK);
81 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
82 MI_COM_REG_ADDR_MASK);
83 @@ -1156,6 +1168,11 @@ static int tg3_writephy(struct tg3 *tp,
87 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
89 + return __tg3_writephy(tp, tp->phy_addr, reg, val);
92 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
95 @@ -1728,6 +1745,11 @@ static int tg3_poll_fw(struct tg3 *tp)
99 + if (tg3_flag(tp, IS_SSB_CORE)) {
100 + /* We don't use firmware. */
104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
105 /* Wait up to 20ms for init done. */
106 for (i = 0; i < 200; i++) {
107 @@ -3310,6 +3332,8 @@ static int tg3_nvram_write_block(struct
111 + if (tg3_flag(tp, IS_SSB_CORE))
113 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
114 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
115 ~GRC_LCLCTRL_GPIO_OUTPUT1);
116 @@ -3385,6 +3409,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
117 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
120 + /* There is only an Rx CPU for the 5750 derivative in the
122 + if (tg3_flag(tp, IS_SSB_CORE))
125 for (i = 0; i < 10000; i++) {
126 tw32(offset + CPU_STATE, 0xffffffff);
127 tw32(offset + CPU_MODE, CPU_MODE_HALT);
128 @@ -3399,9 +3428,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
132 - /* Clear firmware's nvram arbitration. */
133 - if (tg3_flag(tp, NVRAM))
134 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
135 + if (!tg3_flag(tp, IS_SSB_CORE)) {
136 + /* Clear firmware's nvram arbitration. */
137 + if (tg3_flag(tp, NVRAM))
138 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
144 @@ -3464,6 +3496,11 @@ static int tg3_load_5701_a0_firmware_fix
145 const __be32 *fw_data;
148 + if (tg3_flag(tp, IS_SSB_CORE)) {
149 + /* We don't use firmware. */
153 fw_data = (void *)tp->fw->data;
155 /* Firmware blob starts with version numbers, followed by
156 @@ -3520,6 +3557,11 @@ static int tg3_load_tso_firmware(struct
157 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
160 + if (tg3_flag(tp, IS_SSB_CORE)) {
161 + /* We don't use firmware. */
165 if (tg3_flag(tp, HW_TSO_1) ||
166 tg3_flag(tp, HW_TSO_2) ||
167 tg3_flag(tp, HW_TSO_3))
168 @@ -3860,8 +3902,9 @@ static int tg3_power_down_prepare(struct
169 tg3_frob_aux_power(tp, true);
171 /* Workaround for unstable PLL clock */
172 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
173 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
174 + if ((!tg3_flag(tp, IS_SSB_CORE)) &&
175 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
176 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
177 u32 val = tr32(0x7d00);
179 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
180 @@ -4363,6 +4406,14 @@ relink:
181 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
182 tg3_phy_copper_begin(tp);
184 + if (tg3_flag(tp, ROBOSWITCH)) {
185 + current_link_up = 1;
186 + current_speed = SPEED_1000; /* FIXME */
187 + current_duplex = DUPLEX_FULL;
188 + tp->link_config.active_speed = current_speed;
189 + tp->link_config.active_duplex = current_duplex;
192 tg3_readphy(tp, MII_BMSR, &bmsr);
193 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
194 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
195 @@ -4381,6 +4432,26 @@ relink:
197 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
199 + /* In order for the 5750 core in BCM4785 chip to work properly
200 + * in RGMII mode, the Led Control Register must be set up.
202 + if (tg3_flag(tp, RGMII_MODE)) {
203 + u32 led_ctrl = tr32(MAC_LED_CTRL);
204 + led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
206 + if (tp->link_config.active_speed == SPEED_10)
207 + led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
208 + else if (tp->link_config.active_speed == SPEED_100)
209 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
210 + LED_CTRL_100MBPS_ON);
211 + else if (tp->link_config.active_speed == SPEED_1000)
212 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
213 + LED_CTRL_1000MBPS_ON);
215 + tw32(MAC_LED_CTRL, led_ctrl);
219 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
220 if (tp->link_config.active_duplex == DUPLEX_HALF)
221 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
222 @@ -8108,6 +8179,14 @@ static int tg3_chip_reset(struct tg3 *tp
226 + if (tg3_flag(tp, IS_SSB_CORE)) {
227 + /* BCM4785: In order to avoid repercussions from using
228 + * potentially defective internal ROM, stop the Rx RISC CPU,
229 + * which is not required. */
231 + tg3_halt_cpu(tp, RX_CPU_BASE);
234 tw32(GRC_MODE, tp->grc_mode);
236 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
237 @@ -9720,6 +9799,11 @@ static void tg3_timer(unsigned long __op
238 tg3_flag(tp, 57765_CLASS))
239 tg3_chk_missed_msi(tp);
241 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
242 + /* BCM4785: Flush posted writes from GbE to host memory. */
246 if (!tg3_flag(tp, TAGGED_STATUS)) {
247 /* All of this garbage is because when using non-tagged
248 * IRQ status the mailbox/status_block protocol the chip
249 @@ -11415,6 +11499,11 @@ static int tg3_test_nvram(struct tg3 *tp
250 if (tg3_flag(tp, NO_NVRAM))
253 + if (tg3_flag(tp, IS_SSB_CORE)) {
254 + /* We don't have NVRAM. */
258 if (tg3_nvram_read(tp, 0, &magic) != 0)
261 @@ -12383,11 +12472,12 @@ static int tg3_ioctl(struct net_device *
262 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
263 break; /* We have no PHY */
265 - if (!netif_running(dev))
266 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
269 spin_lock_bh(&tp->lock);
270 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
271 + err = __tg3_readphy(tp, data->phy_id & 0x1f,
272 + data->reg_num & 0x1f, &mii_regval);
273 spin_unlock_bh(&tp->lock);
275 data->val_out = mii_regval;
276 @@ -12399,11 +12489,12 @@ static int tg3_ioctl(struct net_device *
277 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
278 break; /* We have no PHY */
280 - if (!netif_running(dev))
281 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
284 spin_lock_bh(&tp->lock);
285 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
286 + err = __tg3_writephy(tp, data->phy_id & 0x1f,
287 + data->reg_num & 0x1f, data->val_in);
288 spin_unlock_bh(&tp->lock);
291 @@ -13251,6 +13342,13 @@ static void __devinit tg3_get_5720_nvram
292 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
293 static void __devinit tg3_nvram_init(struct tg3 *tp)
295 + if (tg3_flag(tp, IS_SSB_CORE)) {
296 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
297 + tg3_flag_clear(tp, NVRAM);
298 + tg3_flag_clear(tp, NVRAM_BUFFERED);
302 tw32_f(GRC_EEPROM_ADDR,
303 (EEPROM_ADDR_FSM_RESET |
304 (EEPROM_DEFAULT_CLOCK_PERIOD <<
305 @@ -13743,10 +13841,19 @@ static int __devinit tg3_phy_probe(struc
306 * subsys device table.
308 p = tg3_lookup_by_subsys(tp);
311 + tp->phy_id = p->phy_id;
312 + } else if (!tg3_flag(tp, IS_SSB_CORE)) {
313 + /* For now we saw the IDs 0xbc050cd0,
314 + * 0xbc050f80 and 0xbc050c30 on devices
315 + * connected to an BCM4785 and there are
316 + * probably more. Just assume that the phy is
317 + * supported when it is connected to a SSB core
323 - tp->phy_id = p->phy_id;
325 tp->phy_id == TG3_PHY_ID_BCM8002)
326 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
327 @@ -14756,6 +14863,11 @@ static int __devinit tg3_get_invariants(
331 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
332 + tp->write32_tx_mbox = tg3_write_flush_reg32;
333 + tp->write32_rx_mbox = tg3_write_flush_reg32;
336 /* Get eeprom hw config before calling tg3_set_power_state().
337 * In particular, the TG3_FLAG_IS_NIC flag must be
338 * determined before calling tg3_set_power_state() so that
339 @@ -15165,6 +15277,10 @@ static int __devinit tg3_get_device_addr
342 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
343 + if (tg3_flag(tp, IS_SSB_CORE))
344 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
346 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
348 if (!tg3_get_default_macaddr_sparc(tp))
350 @@ -15449,7 +15565,8 @@ static int __devinit tg3_test_dma(struct
351 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
353 tp->dma_rwctrl |= 0x8000;
354 - else if (ccval == 0x6 || ccval == 0x7)
355 + else if ((ccval == 0x6 || ccval == 0x7) ||
356 + tg3_flag(tp, ONE_DMA_AT_ONCE))
357 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
359 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
360 @@ -15811,6 +15928,17 @@ static int __devinit tg3_init_one(struct
361 tp->msg_enable = tg3_debug;
363 tp->msg_enable = TG3_DEF_MSG_ENABLE;
364 + if (pdev_is_ssb_gige_core(pdev)) {
365 + tg3_flag_set(tp, IS_SSB_CORE);
366 + if (ssb_gige_must_flush_posted_writes(pdev))
367 + tg3_flag_set(tp, FLUSH_POSTED_WRITES);
368 + if (ssb_gige_one_dma_at_once(pdev))
369 + tg3_flag_set(tp, ONE_DMA_AT_ONCE);
370 + if (ssb_gige_have_roboswitch(pdev))
371 + tg3_flag_set(tp, ROBOSWITCH);
372 + if (ssb_gige_is_rgmii(pdev))
373 + tg3_flag_set(tp, RGMII_MODE);
376 /* The word/byte swap controls here control register access byte
377 * swapping. DMA data byte swapping is controlled in the GRC_MODE
378 --- a/drivers/net/ethernet/broadcom/tg3.h
379 +++ b/drivers/net/ethernet/broadcom/tg3.h
380 @@ -2973,6 +2973,11 @@ enum TG3_FLAGS {
382 TG3_FLAG_57765_CLASS,
384 + TG3_FLAG_IS_SSB_CORE,
385 + TG3_FLAG_FLUSH_POSTED_WRITES,
386 + TG3_FLAG_ROBOSWITCH,
387 + TG3_FLAG_ONE_DMA_AT_ONCE,
388 + TG3_FLAG_RGMII_MODE,
390 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
391 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
392 --- a/include/linux/pci_ids.h
393 +++ b/include/linux/pci_ids.h
394 @@ -2121,6 +2121,7 @@
395 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
396 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
397 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
398 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676
399 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
400 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
401 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
402 --- a/include/linux/ssb/ssb_driver_gige.h
403 +++ b/include/linux/ssb/ssb_driver_gige.h
404 @@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
408 -#ifdef CONFIG_BCM47XX
409 -#include <asm/mach-bcm47xx/nvram.h>
410 -/* Get the device MAC address */
411 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
414 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
416 - nvram_parse_macaddr(buf, macaddr);
419 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
421 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
423 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
427 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
428 struct pci_dev *pdev);
429 @@ -175,6 +166,9 @@ static inline bool ssb_gige_must_flush_p
433 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
437 #endif /* CONFIG_SSB_DRIVER_GIGE */
438 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */