target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch

   1 Index: linux-2.6.23.16/drivers/ssb/Kconfig
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/drivers/ssb/Kconfig    2008-02-22 19:40:57.000000000 +0100
   4 +++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-22 19:42:52.000000000 +0100
   5 @@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF
   6
   7           If unsure, say N
   8
   9 +config SSB_DRIVER_GIGE
  10 +       bool "SSB Broadcom Gigabit Ethernet driver (EXPERIMENTAL)"
  11 +       depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS && EXPERIMENTAL
  12 +       help
  13 +         Driver the the Sonics Silicon Backplane attached
  14 +         Broadcom Gigabit Ethernet.
  15 +
  16 +         If unsure, say N
  17 +
  18  endmenu
  19 Index: linux-2.6.23.16/drivers/ssb/Makefile
  20 ===================================================================
  21 --- linux-2.6.23.16.orig/drivers/ssb/Makefile   2008-02-22 19:40:57.000000000 +0100
  22 +++ linux-2.6.23.16/drivers/ssb/Makefile        2008-02-22 19:42:52.000000000 +0100
  23 @@ -11,6 +11,7 @@ ssb-y                                 += driver_chipcommon.o
  24  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  25  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  26  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  27 +ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  28
  29  # b43 pci-ssb-bridge driver
  30  # Not strictly a part of SSB, but kept here for convenience
  31 Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
  32 ===================================================================
  33 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  34 +++ linux-2.6.23.16/drivers/ssb/driver_gige.c   2008-02-28 12:26:18.000000000 +0100
  35 @@ -0,0 +1,286 @@
  36 +/*
  37 + * Sonics Silicon Backplane
  38 + * Broadcom Gigabit Ethernet core driver
  39 + *
  40 + * Copyright 2008, Broadcom Corporation
  41 + * Copyright 2008, Michael Buesch <mb@bu3sch.de>
  42 + *
  43 + * Licensed under the GNU/GPL. See COPYING for details.
  44 + */
  45 +
  46 +#include <linux/ssb/ssb.h>
  47 +#include <linux/pci.h>
  48 +#include <linux/pci_regs.h>
  49 +#include <linux/ssb/ssb_driver_gige.h>
  50 +
  51 +
  52 +/*
  53 +MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
  54 +MODULE_AUTHOR("Michael Buesch");
  55 +MODULE_LICENSE("GPL");
  56 +*/
  57 +
  58 +static const struct ssb_device_id ssb_gige_tbl[] = {
  59 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
  60 +       SSB_DEVTABLE_END
  61 +};
  62 +/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
  63 +
  64 +
  65 +static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
  66 +{
  67 +       return ssb_read8(dev->dev, offset);
  68 +}
  69 +
  70 +static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
  71 +{
  72 +       return ssb_read16(dev->dev, offset);
  73 +}
  74 +
  75 +static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
  76 +{
  77 +       return ssb_read32(dev->dev, offset);
  78 +}
  79 +
  80 +static inline void gige_write8(struct ssb_gige *dev,
  81 +                              u16 offset, u8 value)
  82 +{
  83 +       ssb_write8(dev->dev, offset, value);
  84 +}
  85 +
  86 +static inline void gige_write16(struct ssb_gige *dev,
  87 +                               u16 offset, u16 value)
  88 +{
  89 +       ssb_write16(dev->dev, offset, value);
  90 +}
  91 +
  92 +static inline void gige_write32(struct ssb_gige *dev,
  93 +                               u16 offset, u32 value)
  94 +{
  95 +       ssb_write32(dev->dev, offset, value);
  96 +}
  97 +
  98 +static inline
  99 +u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
 100 +{
 101 +       BUG_ON(offset >= 256);
 102 +       return gige_read8(dev, SSB_GIGE_PCICFG + offset);
 103 +}
 104 +
 105 +static inline
 106 +u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
 107 +{
 108 +       BUG_ON(offset >= 256);
 109 +       return gige_read16(dev, SSB_GIGE_PCICFG + offset);
 110 +}
 111 +
 112 +static inline
 113 +u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
 114 +{
 115 +       BUG_ON(offset >= 256);
 116 +       return gige_read32(dev, SSB_GIGE_PCICFG + offset);
 117 +}
 118 +
 119 +static inline
 120 +void gige_pcicfg_write8(struct ssb_gige *dev,
 121 +                       unsigned int offset, u8 value)
 122 +{
 123 +       BUG_ON(offset >= 256);
 124 +       gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
 125 +}
 126 +
 127 +static inline
 128 +void gige_pcicfg_write16(struct ssb_gige *dev,
 129 +                        unsigned int offset, u16 value)
 130 +{
 131 +       BUG_ON(offset >= 256);
 132 +       gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
 133 +}
 134 +
 135 +static inline
 136 +void gige_pcicfg_write32(struct ssb_gige *dev,
 137 +                        unsigned int offset, u32 value)
 138 +{
 139 +       BUG_ON(offset >= 256);
 140 +       gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
 141 +}
 142 +
 143 +static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 144 +                                   int reg, int size, u32 *val)
 145 +{
 146 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 147 +       unsigned long flags;
 148 +
 149 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 150 +               return PCIBIOS_DEVICE_NOT_FOUND;
 151 +       if (reg >= 256)
 152 +               return PCIBIOS_DEVICE_NOT_FOUND;
 153 +
 154 +       spin_lock_irqsave(&dev->lock, flags);
 155 +       switch (size) {
 156 +       case 1:
 157 +               *val = gige_pcicfg_read8(dev, reg);
 158 +               break;
 159 +       case 2:
 160 +               *val = gige_pcicfg_read16(dev, reg);
 161 +               break;
 162 +       case 4:
 163 +               *val = gige_pcicfg_read32(dev, reg);
 164 +               break;
 165 +       default:
 166 +               WARN_ON(1);
 167 +       }
 168 +       spin_unlock_irqrestore(&dev->lock, flags);
 169 +
 170 +       return PCIBIOS_SUCCESSFUL;
 171 +}
 172 +
 173 +static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 174 +                                    int reg, int size, u32 val)
 175 +{
 176 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 177 +       unsigned long flags;
 178 +
 179 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 180 +               return PCIBIOS_DEVICE_NOT_FOUND;
 181 +       if (reg >= 256)
 182 +               return PCIBIOS_DEVICE_NOT_FOUND;
 183 +
 184 +       spin_lock_irqsave(&dev->lock, flags);
 185 +       switch (size) {
 186 +       case 1:
 187 +               gige_pcicfg_write8(dev, reg, val);
 188 +               break;
 189 +       case 2:
 190 +               gige_pcicfg_write16(dev, reg, val);
 191 +               break;
 192 +       case 4:
 193 +               gige_pcicfg_write32(dev, reg, val);
 194 +               break;
 195 +       default:
 196 +               WARN_ON(1);
 197 +       }
 198 +       spin_unlock_irqrestore(&dev->lock, flags);
 199 +
 200 +       return PCIBIOS_SUCCESSFUL;
 201 +}
 202 +
 203 +static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
 204 +{
 205 +       struct ssb_gige *dev;
 206 +       u32 base, tmslow, tmshigh;
 207 +
 208 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 209 +       if (!dev)
 210 +               return -ENOMEM;
 211 +       dev->dev = sdev;
 212 +
 213 +       spin_lock_init(&dev->lock);
 214 +       dev->pci_controller.pci_ops = &dev->pci_ops;
 215 +       dev->pci_controller.io_resource = &dev->io_resource;
 216 +       dev->pci_controller.mem_resource = &dev->mem_resource;
 217 +       dev->pci_controller.io_map_base = 0x800;
 218 +       dev->pci_ops.read = ssb_gige_pci_read_config;
 219 +       dev->pci_ops.write = ssb_gige_pci_write_config;
 220 +
 221 +       dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
 222 +       dev->io_resource.start = 0x800;
 223 +       dev->io_resource.end = 0x8FF;
 224 +       dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
 225 +
 226 +       if (!ssb_device_is_enabled(sdev))
 227 +               ssb_device_enable(sdev, 0);
 228 +
 229 +       /* Setup BAR0. This is a 64k MMIO region. */
 230 +       base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
 231 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
 232 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
 233 +
 234 +       dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
 235 +       dev->mem_resource.start = base;
 236 +       dev->mem_resource.end = base + 0x10000 - 1;
 237 +       dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 238 +
 239 +       /* Enable the memory region. */
 240 +       gige_pcicfg_write16(dev, PCI_COMMAND,
 241 +                           gige_pcicfg_read16(dev, PCI_COMMAND)
 242 +                           | PCI_COMMAND_MEMORY);
 243 +
 244 +       /* Write flushing is controlled by the Flush Status Control register.
 245 +        * We want to flush every register write with a timeout and we want
 246 +        * to disable the IRQ mask while flushing to avoid concurrency.
 247 +        * Note that automatic write flushing does _not_ work from
 248 +        * an IRQ handler. The driver must flush manually by reading a register.
 249 +        */
 250 +       gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
 251 +
 252 +       /* Check if we have an RGMII or GMII PHY-bus.
 253 +        * On RGMII do not bypass the DLLs */
 254 +       tmslow = ssb_read32(sdev, SSB_TMSLOW);
 255 +       tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
 256 +       if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
 257 +               tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
 258 +               tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
 259 +               dev->has_rgmii = 1;
 260 +       } else {
 261 +               tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
 262 +               tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
 263 +               dev->has_rgmii = 0;
 264 +       }
 265 +       tmslow |= SSB_GIGE_TMSLOW_DLLEN;
 266 +       ssb_write32(sdev, SSB_TMSLOW, tmslow);
 267 +
 268 +       ssb_set_drvdata(sdev, dev);
 269 +       register_pci_controller(&dev->pci_controller);
 270 +
 271 +       return 0;
 272 +}
 273 +
 274 +int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 275 +                                  struct pci_dev *pdev)
 276 +{
 277 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 278 +       struct resource *res;
 279 +
 280 +       if (pdev->bus->ops != &dev->pci_ops) {
 281 +               /* The PCI device is not on this SSB GigE bridge device. */
 282 +               return -ENODEV;
 283 +       }
 284 +
 285 +       /* Fixup the PCI resources. */
 286 +       res = &(pdev->resource[0]);
 287 +       res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 288 +       res->name = dev->mem_resource.name;
 289 +       res->start = dev->mem_resource.start;
 290 +       res->end = dev->mem_resource.end;
 291 +
 292 +       /* Fixup interrupt lines. */
 293 +       pdev->irq = ssb_mips_irq(sdev) + 2;
 294 +       pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
 295 +
 296 +       return 0;
 297 +}
 298 +
 299 +int ssb_gige_map_irq(struct ssb_device *sdev,
 300 +                    const struct pci_dev *pdev)
 301 +{
 302 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 303 +
 304 +       if (pdev->bus->ops != &dev->pci_ops) {
 305 +               /* The PCI device is not on this SSB GigE bridge device. */
 306 +               return -ENODEV;
 307 +       }
 308 +
 309 +       return ssb_mips_irq(sdev) + 2;
 310 +}
 311 +
 312 +static struct ssb_driver ssb_gige_driver = {
 313 +       .name           = "BCM-GigE",
 314 +       .id_table       = ssb_gige_tbl,
 315 +       .probe          = ssb_gige_probe,
 316 +};
 317 +
 318 +int ssb_gige_init(void)
 319 +{
 320 +       return ssb_driver_register(&ssb_gige_driver);
 321 +}
 322 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
 323 ===================================================================
 324 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 325 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-22 20:47:58.000000000 +0100
 326 @@ -0,0 +1,178 @@
 327 +#ifndef LINUX_SSB_DRIVER_GIGE_H_
 328 +#define LINUX_SSB_DRIVER_GIGE_H_
 329 +
 330 +#include <linux/ssb/ssb.h>
 331 +#include <linux/pci.h>
 332 +#include <linux/spinlock.h>
 333 +
 334 +
 335 +#ifdef CONFIG_SSB_DRIVER_GIGE
 336 +
 337 +
 338 +#define SSB_GIGE_PCIIO                 0x0000 /* PCI I/O Registers (1024 bytes) */
 339 +#define SSB_GIGE_RESERVED              0x0400 /* Reserved (1024 bytes) */
 340 +#define SSB_GIGE_PCICFG                        0x0800 /* PCI config space (256 bytes) */
 341 +#define SSB_GIGE_SHIM_FLUSHSTAT                0x0C00 /* PCI to OCP: Flush status control (32bit) */
 342 +#define SSB_GIGE_SHIM_FLUSHRDA         0x0C04 /* PCI to OCP: Flush read address (32bit) */
 343 +#define SSB_GIGE_SHIM_FLUSHTO          0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
 344 +#define SSB_GIGE_SHIM_BARRIER          0x0C0C /* PCI to OCP: Barrier register (32bit) */
 345 +#define SSB_GIGE_SHIM_MAOCPSI          0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
 346 +#define SSB_GIGE_SHIM_SIOCPMA          0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
 347 +
 348 +/* TM Status High flags */
 349 +#define SSB_GIGE_TMSHIGH_RGMII         0x00010000 /* Have an RGMII PHY-bus */
 350 +/* TM Status Low flags */
 351 +#define SSB_GIGE_TMSLOW_TXBYPASS       0x00080000 /* TX bypass (no delay) */
 352 +#define SSB_GIGE_TMSLOW_RXBYPASS       0x00100000 /* RX bypass (no delay) */
 353 +#define SSB_GIGE_TMSLOW_DLLEN          0x01000000 /* Enable DLL controls */
 354 +
 355 +/* Boardflags (low) */
 356 +#define SSB_GIGE_BFL_ROBOSWITCH                0x0010
 357 +
 358 +
 359 +#define SSB_GIGE_MEM_RES_NAME          "SSB Broadcom 47xx GigE memory"
 360 +#define SSB_GIGE_IO_RES_NAME           "SSB Broadcom 47xx GigE I/O"
 361 +
 362 +struct ssb_gige {
 363 +       struct ssb_device *dev;
 364 +
 365 +       spinlock_t lock;
 366 +
 367 +       /* True, if the device has an RGMII bus.
 368 +        * False, if the device has a GMII bus. */
 369 +       bool has_rgmii;
 370 +
 371 +       /* The PCI controller device. */
 372 +       struct pci_controller pci_controller;
 373 +       struct pci_ops pci_ops;
 374 +       struct resource mem_resource;
 375 +       struct resource io_resource;
 376 +};
 377 +
 378 +/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
 379 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 380 +{
 381 +       return (pdev->resource[0].name &&
 382 +               strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
 383 +}
 384 +
 385 +/* Convert a pci_dev pointer to a ssb_gige pointer. */
 386 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 387 +{
 388 +       if (!pdev_is_ssb_gige_core(pdev))
 389 +               return NULL;
 390 +       return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
 391 +}
 392 +
 393 +/* Returns whether the PHY is connected by an RGMII bus. */
 394 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 395 +{
 396 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 397 +       return (dev ? dev->has_rgmii : 0);
 398 +}
 399 +
 400 +/* Returns whether we have a Roboswitch. */
 401 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 402 +{
 403 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 404 +       if (dev)
 405 +               return !!(dev->dev->bus->sprom.boardflags_lo &
 406 +                         SSB_GIGE_BFL_ROBOSWITCH);
 407 +       return 0;
 408 +}
 409 +
 410 +/* Returns whether we can only do one DMA at once. */
 411 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 412 +{
 413 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 414 +       if (dev)
 415 +               return ((dev->dev->bus->chip_id == 0x4785) &&
 416 +                       (dev->dev->bus->chip_rev < 2));
 417 +       return 0;
 418 +}
 419 +
 420 +/* Returns whether we must flush posted writes. */
 421 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 422 +{
 423 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 424 +       if (dev)
 425 +               return (dev->dev->bus->chip_id == 0x4785);
 426 +       return 0;
 427 +}
 428 +
 429 +extern char * nvram_get(const char *name); //FIXME
 430 +/* Get the device MAC address */
 431 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 432 +{
 433 +#ifdef CONFIG_BCM947XX
 434 +       char *res = nvram_get("et0macaddr"); //FIXME
 435 +       if (res)
 436 +               memcpy(macaddr, res, 6);
 437 +#endif
 438 +}
 439 +
 440 +extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 441 +                                         struct pci_dev *pdev);
 442 +extern int ssb_gige_map_irq(struct ssb_device *sdev,
 443 +                           const struct pci_dev *pdev);
 444 +
 445 +/* The GigE driver is not a standalone module, because we don't have support
 446 + * for unregistering the driver. So we could not unload the module anyway. */
 447 +extern int ssb_gige_init(void);
 448 +static inline void ssb_gige_exit(void)
 449 +{
 450 +       /* Currently we can not unregister the GigE driver,
 451 +        * because we can not unregister the PCI bridge. */
 452 +       BUG();
 453 +}
 454 +
 455 +
 456 +#else /* CONFIG_SSB_DRIVER_GIGE */
 457 +/* Gigabit Ethernet driver disabled */
 458 +
 459 +
 460 +static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 461 +                                                struct pci_dev *pdev)
 462 +{
 463 +       return -ENOSYS;
 464 +}
 465 +static inline int ssb_gige_map_irq(struct ssb_device *sdev,
 466 +                                  const struct pci_dev *pdev)
 467 +{
 468 +       return -ENOSYS;
 469 +}
 470 +static inline int ssb_gige_init(void)
 471 +{
 472 +       return 0;
 473 +}
 474 +static inline void ssb_gige_exit(void)
 475 +{
 476 +}
 477 +
 478 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 479 +{
 480 +       return 0;
 481 +}
 482 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 483 +{
 484 +       return NULL;
 485 +}
 486 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 487 +{
 488 +       return 0;
 489 +}
 490 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 491 +{
 492 +       return 0;
 493 +}
 494 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 495 +{
 496 +       return 0;
 497 +}
 498 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 499 +{
 500 +       return 0;
 501 +}
 502 +
 503 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 504 +#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
 505 Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
 506 ===================================================================
 507 --- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c   2008-02-22 19:40:57.000000000 +0100
 508 +++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c        2008-02-22 19:42:52.000000000 +0100
 509 @@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
 510  /* Core to access the external PCI config space. Can only have one. */
 511  static struct ssb_pcicore *extpci_core;
 512
 513 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
 514 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 515 -
 516 -int pcibios_plat_dev_init(struct pci_dev *d)
 517 -{
 518 -       struct resource *res;
 519 -       int pos, size;
 520 -       u32 *base;
 521 -
 522 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 523 -                  pci_name(d));
 524 -
 525 -       /* Fix up resource bases */
 526 -       for (pos = 0; pos < 6; pos++) {
 527 -               res = &d->resource[pos];
 528 -               if (res->flags & IORESOURCE_IO)
 529 -                       base = &ssb_pcicore_pcibus_iobase;
 530 -               else
 531 -                       base = &ssb_pcicore_pcibus_membase;
 532 -               res->flags |= IORESOURCE_PCI_FIXED;
 533 -               if (res->end) {
 534 -                       size = res->end - res->start + 1;
 535 -                       if (*base & (size - 1))
 536 -                               *base = (*base + size) & ~(size - 1);
 537 -                       res->start = *base;
 538 -                       res->end = res->start + size - 1;
 539 -                       *base += size;
 540 -                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 541 -               }
 542 -               /* Fix up PCI bridge BAR0 only */
 543 -               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 544 -                       break;
 545 -       }
 546 -       /* Fix up interrupt lines */
 547 -       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 548 -       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 549 -
 550 -       return 0;
 551 -}
 552 -
 553 -static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
 554 -{
 555 -       u8 lat;
 556 -
 557 -       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 558 -               return;
 559 -
 560 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 561 -
 562 -       /* Enable PCI bridge bus mastering and memory space */
 563 -       pci_set_master(dev);
 564 -       pcibios_enable_device(dev, ~0);
 565 -
 566 -       /* Enable PCI bridge BAR1 prefetch and burst */
 567 -       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 568 -
 569 -       /* Make sure our latency is high enough to handle the devices behind us */
 570 -       lat = 168;
 571 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 572 -                  pci_name(dev), lat);
 573 -       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 574 -}
 575 -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 576 -
 577 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 578 -{
 579 -       return ssb_mips_irq(extpci_core->dev) + 2;
 580 -}
 581
 582  static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
 583                              unsigned int bus, unsigned int dev,
 584 @@ -317,6 +249,92 @@ static struct pci_controller ssb_pcicore
 585         .mem_offset     = 0x24000000,
 586  };
 587
 588 +static u32 ssb_pcicore_pcibus_iobase = 0x100;
 589 +static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 590 +
 591 +/* This function is called when doing a pci_enable_device().
 592 + * We must first check if the device is a device on the PCI-core bridge. */
 593 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 594 +{
 595 +       struct resource *res;
 596 +       int pos, size;
 597 +       u32 *base;
 598 +
 599 +       if (d->bus->ops != &ssb_pcicore_pciops) {
 600 +               /* This is not a device on the PCI-core bridge. */
 601 +               return -ENODEV;
 602 +       }
 603 +
 604 +       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 605 +                  pci_name(d));
 606 +
 607 +       /* Fix up resource bases */
 608 +       for (pos = 0; pos < 6; pos++) {
 609 +               res = &d->resource[pos];
 610 +               if (res->flags & IORESOURCE_IO)
 611 +                       base = &ssb_pcicore_pcibus_iobase;
 612 +               else
 613 +                       base = &ssb_pcicore_pcibus_membase;
 614 +               res->flags |= IORESOURCE_PCI_FIXED;
 615 +               if (res->end) {
 616 +                       size = res->end - res->start + 1;
 617 +                       if (*base & (size - 1))
 618 +                               *base = (*base + size) & ~(size - 1);
 619 +                       res->start = *base;
 620 +                       res->end = res->start + size - 1;
 621 +                       *base += size;
 622 +                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 623 +               }
 624 +               /* Fix up PCI bridge BAR0 only */
 625 +               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 626 +                       break;
 627 +       }
 628 +       /* Fix up interrupt lines */
 629 +       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 630 +       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 631 +
 632 +       return 0;
 633 +}
 634 +
 635 +/* Early PCI fixup for a device on the PCI-core bridge. */
 636 +static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 637 +{
 638 +       u8 lat;
 639 +
 640 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 641 +               /* This is not a device on the PCI-core bridge. */
 642 +               return;
 643 +       }
 644 +       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 645 +               return;
 646 +
 647 +       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 648 +
 649 +       /* Enable PCI bridge bus mastering and memory space */
 650 +       pci_set_master(dev);
 651 +       pcibios_enable_device(dev, ~0);
 652 +
 653 +       /* Enable PCI bridge BAR1 prefetch and burst */
 654 +       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 655 +
 656 +       /* Make sure our latency is high enough to handle the devices behind us */
 657 +       lat = 168;
 658 +       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 659 +                  pci_name(dev), lat);
 660 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 661 +}
 662 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 663 +
 664 +/* PCI device IRQ mapping. */
 665 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 666 +{
 667 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 668 +               /* This is not a device on the PCI-core bridge. */
 669 +               return -ENODEV;
 670 +       }
 671 +       return ssb_mips_irq(extpci_core->dev) + 2;
 672 +}
 673 +
 674  static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 675  {
 676         u32 val;
 677 Index: linux-2.6.23.16/drivers/ssb/embedded.c
 678 ===================================================================
 679 --- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-22 19:40:57.000000000 +0100
 680 +++ linux-2.6.23.16/drivers/ssb/embedded.c      2008-02-22 19:42:52.000000000 +0100
 681 @@ -10,6 +10,9 @@
 682
 683  #include <linux/ssb/ssb.h>
 684  #include <linux/ssb/ssb_embedded.h>
 685 +#include <linux/ssb/ssb_driver_pci.h>
 686 +#include <linux/ssb/ssb_driver_gige.h>
 687 +#include <linux/pci.h>
 688
 689  #include "ssb_private.h"
 690
 691 @@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
 692         return res;
 693  }
 694  EXPORT_SYMBOL(ssb_gpio_polarity);
 695 +
 696 +#ifdef CONFIG_SSB_DRIVER_GIGE
 697 +static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
 698 +{
 699 +       struct pci_dev *pdev = (struct pci_dev *)data;
 700 +       struct ssb_device *dev;
 701 +       unsigned int i;
 702 +       int res;
 703 +
 704 +       for (i = 0; i < bus->nr_devices; i++) {
 705 +               dev = &(bus->devices[i]);
 706 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 707 +                       continue;
 708 +               if (!dev->dev ||
 709 +                   !dev->dev->driver ||
 710 +                   !device_is_registered(dev->dev))
 711 +                       continue;
 712 +               res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
 713 +               if (res >= 0)
 714 +                       return res;
 715 +       }
 716 +
 717 +       return -ENODEV;
 718 +}
 719 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 720 +
 721 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
 722 +{
 723 +       int err;
 724 +
 725 +       err = ssb_pcicore_plat_dev_init(dev);
 726 +       if (!err)
 727 +               return 0;
 728 +#ifdef CONFIG_SSB_DRIVER_GIGE
 729 +       err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
 730 +       if (err >= 0)
 731 +               return err;
 732 +#endif
 733 +       /* This is not a PCI device on any SSB device. */
 734 +
 735 +       return -ENODEV;
 736 +}
 737 +
 738 +#ifdef CONFIG_SSB_DRIVER_GIGE
 739 +static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
 740 +{
 741 +       const struct pci_dev *pdev = (const struct pci_dev *)data;
 742 +       struct ssb_device *dev;
 743 +       unsigned int i;
 744 +       int res;
 745 +
 746 +       for (i = 0; i < bus->nr_devices; i++) {
 747 +               dev = &(bus->devices[i]);
 748 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 749 +                       continue;
 750 +               if (!dev->dev ||
 751 +                   !dev->dev->driver ||
 752 +                   !device_is_registered(dev->dev))
 753 +                       continue;
 754 +               res = ssb_gige_map_irq(dev, pdev);
 755 +               if (res >= 0)
 756 +                       return res;
 757 +       }
 758 +
 759 +       return -ENODEV;
 760 +}
 761 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 762 +
 763 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 764 +{
 765 +       int res;
 766 +
 767 +       /* Check if this PCI device is a device on a SSB bus or device
 768 +        * and return the IRQ number for it. */
 769 +
 770 +       res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
 771 +       if (res >= 0)
 772 +               return res;
 773 +#ifdef CONFIG_SSB_DRIVER_GIGE
 774 +       res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
 775 +       if (res >= 0)
 776 +               return res;
 777 +#endif
 778 +       /* This is not a PCI device on any SSB device. */
 779 +
 780 +       return -ENODEV;
 781 +}
 782 Index: linux-2.6.23.16/include/linux/ssb/ssb.h
 783 ===================================================================
 784 --- linux-2.6.23.16.orig/include/linux/ssb/ssb.h        2008-02-22 19:40:57.000000000 +0100
 785 +++ linux-2.6.23.16/include/linux/ssb/ssb.h     2008-02-22 19:42:52.000000000 +0100
 786 @@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu
 787  extern u32 ssb_admatch_base(u32 adm);
 788  extern u32 ssb_admatch_size(u32 adm);
 789
 790 +/* PCI device mapping and fixup routines.
 791 + * Called from the architecture pcibios init code.
 792 + * These are only available on SSB_EMBEDDED configurations. */
 793 +#ifdef CONFIG_SSB_EMBEDDED
 794 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
 795 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 796 +#endif /* CONFIG_SSB_EMBEDDED */
 797
 798  #endif /* LINUX_SSB_H_ */
 799 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
 800 ===================================================================
 801 --- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h     2008-02-22 19:40:57.000000000 +0100
 802 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h  2008-02-22 19:42:52.000000000 +0100
 803 @@ -1,6 +1,11 @@
 804  #ifndef LINUX_SSB_PCICORE_H_
 805  #define LINUX_SSB_PCICORE_H_
 806
 807 +#include <linux/types.h>
 808 +
 809 +struct pci_dev;
 810 +
 811 +
 812  #ifdef CONFIG_SSB_DRIVER_PCICORE
 813
 814  /* PCI core registers. */
 815 @@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
 816  extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 817                                           struct ssb_device *dev);
 818
 819 +int ssb_pcicore_plat_dev_init(struct pci_dev *d);
 820 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 821 +
 822
 823  #else /* CONFIG_SSB_DRIVER_PCICORE */
 824
 825 @@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
 826         return 0;
 827  }
 828
 829 +static inline
 830 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 831 +{
 832 +       return -ENODEV;
 833 +}
 834 +static inline
 835 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 836 +{
 837 +       return -ENODEV;
 838 +}
 839 +
 840  #endif /* CONFIG_SSB_DRIVER_PCICORE */
 841  #endif /* LINUX_SSB_PCICORE_H_ */
 842 Index: linux-2.6.23.16/drivers/ssb/main.c
 843 ===================================================================
 844 --- linux-2.6.23.16.orig/drivers/ssb/main.c     2008-02-22 19:40:57.000000000 +0100
 845 +++ linux-2.6.23.16/drivers/ssb/main.c  2008-02-22 19:42:52.000000000 +0100
 846 @@ -14,6 +14,7 @@
 847  #include <linux/io.h>
 848  #include <linux/ssb/ssb.h>
 849  #include <linux/ssb/ssb_regs.h>
 850 +#include <linux/ssb/ssb_driver_gige.h>
 851  #include <linux/dma-mapping.h>
 852  #include <linux/pci.h>
 853
 854 @@ -68,6 +69,25 @@ found:
 855  }
 856  #endif /* CONFIG_SSB_PCIHOST */
 857
 858 +int ssb_for_each_bus_call(unsigned long data,
 859 +                         int (*func)(struct ssb_bus *bus, unsigned long data))
 860 +{
 861 +       struct ssb_bus *bus;
 862 +       int res;
 863 +
 864 +       ssb_buses_lock();
 865 +       list_for_each_entry(bus, &buses, list) {
 866 +               res = func(bus, data);
 867 +               if (res >= 0) {
 868 +                       ssb_buses_unlock();
 869 +                       return res;
 870 +               }
 871 +       }
 872 +       ssb_buses_unlock();
 873 +
 874 +       return -ENODEV;
 875 +}
 876 +
 877  static struct ssb_device *ssb_device_get(struct ssb_device *dev)
 878  {
 879         if (dev)
 880 @@ -1175,7 +1195,14 @@ static int __init ssb_modinit(void)
 881         err = b43_pci_ssb_bridge_init();
 882         if (err) {
 883                 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
 884 -                          "initialization failed");
 885 +                          "initialization failed\n");
 886 +               /* don't fail SSB init because of this */
 887 +               err = 0;
 888 +       }
 889 +       err = ssb_gige_init();
 890 +       if (err) {
 891 +               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
 892 +                          "driver initialization failed\n");
 893                 /* don't fail SSB init because of this */
 894                 err = 0;
 895         }
 896 @@ -1189,6 +1216,7 @@ fs_initcall(ssb_modinit);
 897
 898  static void __exit ssb_modexit(void)
 899  {
 900 +       ssb_gige_exit();
 901         b43_pci_ssb_bridge_exit();
 902         bus_unregister(&ssb_bustype);
 903  }
 904 Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
 905 ===================================================================
 906 --- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h      2008-02-22 19:40:57.000000000 +0100
 907 +++ linux-2.6.23.16/drivers/ssb/ssb_private.h   2008-02-22 19:42:52.000000000 +0100
 908 @@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
 909  extern int ssb_devices_freeze(struct ssb_bus *bus);
 910  extern int ssb_devices_thaw(struct ssb_bus *bus);
 911  extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
 912 +int ssb_for_each_bus_call(unsigned long data,
 913 +                         int (*func)(struct ssb_bus *bus, unsigned long data));
 914
 915  /* b43_pci_bridge.c */
 916  #ifdef CONFIG_SSB_PCIHOST
 917 Index: linux-2.6.23.16/drivers/net/tg3.c
 918 ===================================================================
 919 --- linux-2.6.23.16.orig/drivers/net/tg3.c      2008-02-22 19:40:57.000000000 +0100
 920 +++ linux-2.6.23.16/drivers/net/tg3.c   2008-02-28 12:28:17.000000000 +0100
 921 @@ -38,6 +38,7 @@
 922  #include <linux/workqueue.h>
 923  #include <linux/prefetch.h>
 924  #include <linux/dma-mapping.h>
 925 +#include <linux/ssb/ssb_driver_gige.h>
 926
 927  #include <net/checksum.h>
 928  #include <net/ip.h>
 929 @@ -410,8 +411,9 @@ static void _tw32_flush(struct tg3 *tp,
 930  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 931  {
 932         tp->write32_mbox(tp, off, val);
 933 -       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 934 -           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 935 +       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
 936 +           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 937 +            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
 938                 tp->read32_mbox(tp, off);
 939  }
 940
 941 @@ -623,7 +625,7 @@ static void tg3_switch_clocks(struct tg3
 942
 943  #define PHY_BUSY_LOOPS 5000
 944
 945 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 946 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
 947  {
 948         u32 frame_val;
 949         unsigned int loops;
 950 @@ -637,7 +639,7 @@ static int tg3_readphy(struct tg3 *tp, i
 951
 952         *val = 0x0;
 953
 954 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 955 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 956                       MI_COM_PHY_ADDR_MASK);
 957         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 958                       MI_COM_REG_ADDR_MASK);
 959 @@ -672,7 +674,12 @@ static int tg3_readphy(struct tg3 *tp, i
 960         return ret;
 961  }
 962
 963 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 964 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 965 +{
 966 +       return __tg3_readphy(tp, PHY_ADDR, reg, val);
 967 +}
 968 +
 969 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
 970  {
 971         u32 frame_val;
 972         unsigned int loops;
 973 @@ -688,7 +695,7 @@ static int tg3_writephy(struct tg3 *tp,
 974                 udelay(80);
 975         }
 976
 977 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 978 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 979                       MI_COM_PHY_ADDR_MASK);
 980         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 981                       MI_COM_REG_ADDR_MASK);
 982 @@ -721,6 +728,11 @@ static int tg3_writephy(struct tg3 *tp,
 983         return ret;
 984  }
 985
 986 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 987 +{
 988 +       return __tg3_writephy(tp, PHY_ADDR, reg, val);
 989 +}
 990 +
 991  static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 992  {
 993         u32 phy;
 994 @@ -1988,6 +2000,14 @@ static int tg3_setup_copper_phy(struct t
 995                 tp->link_config.active_duplex = current_duplex;
 996         }
 997
 998 +       if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
 999 +               current_link_up = 1;
1000 +               current_speed = SPEED_1000; //FIXME
1001 +               current_duplex = DUPLEX_FULL;
1002 +               tp->link_config.active_speed = current_speed;
1003 +               tp->link_config.active_duplex = current_duplex;
1004 +       }
1005 +
1006         if (current_link_up == 1 &&
1007             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1008             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1009 @@ -4813,6 +4833,11 @@ static int tg3_poll_fw(struct tg3 *tp)
1010         int i;
1011         u32 val;
1012
1013 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1014 +               /* We don't use firmware. */
1015 +               return 0;
1016 +       }
1017 +
1018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1019                 /* Wait up to 20ms for init done. */
1020                 for (i = 0; i < 200; i++) {
1021 @@ -5040,6 +5065,14 @@ static int tg3_chip_reset(struct tg3 *tp
1022                 tw32(0x5000, 0x400);
1023         }
1024
1025 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1026 +               /* BCM4785: In order to avoid repercussions from using potentially
1027 +                * defective internal ROM, stop the Rx RISC CPU, which is not
1028 +                * required. */
1029 +               tg3_stop_fw(tp);
1030 +               tg3_halt_cpu(tp, RX_CPU_BASE);
1031 +       }
1032 +
1033         tw32(GRC_MODE, tp->grc_mode);
1034
1035         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
1036 @@ -5308,9 +5341,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
1037                 return -ENODEV;
1038         }
1039
1040 -       /* Clear firmware's nvram arbitration. */
1041 -       if (tp->tg3_flags & TG3_FLAG_NVRAM)
1042 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1043 +       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
1044 +               /* Clear firmware's nvram arbitration. */
1045 +               if (tp->tg3_flags & TG3_FLAG_NVRAM)
1046 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1047 +       }
1048 +
1049         return 0;
1050  }
1051
1052 @@ -5391,6 +5427,11 @@ static int tg3_load_5701_a0_firmware_fix
1053         struct fw_info info;
1054         int err, i;
1055
1056 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1057 +               /* We don't use firmware. */
1058 +               return 0;
1059 +       }
1060 +
1061         info.text_base = TG3_FW_TEXT_ADDR;
1062         info.text_len = TG3_FW_TEXT_LEN;
1063         info.text_data = &tg3FwText[0];
1064 @@ -5949,6 +5990,11 @@ static int tg3_load_tso_firmware(struct
1065         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
1066         int err, i;
1067
1068 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1069 +               /* We don't use firmware. */
1070 +               return 0;
1071 +       }
1072 +
1073         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
1074                 return 0;
1075
1076 @@ -6850,6 +6896,11 @@ static void tg3_timer(unsigned long __op
1077
1078         spin_lock(&tp->lock);
1079
1080 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1081 +               /* BCM4785: Flush posted writes from GbE to host memory. */
1082 +               tr32(HOSTCC_MODE);
1083 +       }
1084 +
1085         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
1086                 /* All of this garbage is because when using non-tagged
1087                  * IRQ status the mailbox/status_block protocol the chip
1088 @@ -8432,6 +8483,11 @@ static int tg3_test_nvram(struct tg3 *tp
1089         u32 *buf, csum, magic;
1090         int i, j, err = 0, size;
1091
1092 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1093 +               /* We don't have NVRAM. */
1094 +               return 0;
1095 +       }
1096 +
1097         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1098                 return -EIO;
1099
1100 @@ -9154,7 +9210,7 @@ static int tg3_ioctl(struct net_device *
1101                         return -EAGAIN;
1102
1103                 spin_lock_bh(&tp->lock);
1104 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
1105 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1106                 spin_unlock_bh(&tp->lock);
1107
1108                 data->val_out = mii_regval;
1109 @@ -9173,7 +9229,7 @@ static int tg3_ioctl(struct net_device *
1110                         return -EAGAIN;
1111
1112                 spin_lock_bh(&tp->lock);
1113 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
1114 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1115                 spin_unlock_bh(&tp->lock);
1116
1117                 return err;
1118 @@ -9571,6 +9627,12 @@ static void __devinit tg3_get_5906_nvram
1119  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
1120  static void __devinit tg3_nvram_init(struct tg3 *tp)
1121  {
1122 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1123 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
1124 +               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
1125 +               return;
1126 +       }
1127 +
1128         tw32_f(GRC_EEPROM_ADDR,
1129              (EEPROM_ADDR_FSM_RESET |
1130               (EEPROM_DEFAULT_CLOCK_PERIOD <<
1131 @@ -9706,6 +9768,9 @@ static int tg3_nvram_read(struct tg3 *tp
1132  {
1133         int ret;
1134
1135 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1136 +               return -ENODEV;
1137 +
1138         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1139                 return tg3_nvram_read_using_eeprom(tp, offset, val);
1140
1141 @@ -9938,6 +10003,9 @@ static int tg3_nvram_write_block(struct
1142  {
1143         int ret;
1144
1145 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1146 +               return -ENODEV;
1147 +
1148         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
1149                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
1150                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
1151 @@ -10804,7 +10872,6 @@ static int __devinit tg3_get_invariants(
1152                 tp->write32 = tg3_write_flush_reg32;
1153         }
1154
1155 -
1156         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
1157             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
1158                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
1159 @@ -10840,6 +10907,11 @@ static int __devinit tg3_get_invariants(
1160               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
1161                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
1162
1163 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1164 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
1165 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
1166 +       }
1167 +
1168         /* Get eeprom hw config before calling tg3_set_power_state().
1169          * In particular, the TG3_FLG2_IS_NIC flag must be
1170          * determined before calling tg3_set_power_state() so that
1171 @@ -11184,6 +11256,10 @@ static int __devinit tg3_get_device_addr
1172         }
1173
1174         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1175 +               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1176 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
1177 +       }
1178 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1179  #ifdef CONFIG_SPARC64
1180                 if (!tg3_get_default_macaddr_sparc(tp))
1181                         return 0;
1182 @@ -11675,6 +11751,7 @@ static char * __devinit tg3_phy_string(s
1183         case PHY_ID_BCM5704:    return "5704";
1184         case PHY_ID_BCM5705:    return "5705";
1185         case PHY_ID_BCM5750:    return "5750";
1186 +       case PHY_ID_BCM5750_2:  return "5750-2";
1187         case PHY_ID_BCM5752:    return "5752";
1188         case PHY_ID_BCM5714:    return "5714";
1189         case PHY_ID_BCM5780:    return "5780";
1190 @@ -11859,6 +11936,13 @@ static int __devinit tg3_init_one(struct
1191                 tp->msg_enable = tg3_debug;
1192         else
1193                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
1194 +       if (pdev_is_ssb_gige_core(pdev)) {
1195 +               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
1196 +               if (ssb_gige_must_flush_posted_writes(pdev))
1197 +                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
1198 +               if (ssb_gige_have_roboswitch(pdev))
1199 +                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
1200 +       }
1201
1202         /* The word/byte swap controls here control register access byte
1203          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
1204 Index: linux-2.6.23.16/drivers/net/tg3.h
1205 ===================================================================
1206 --- linux-2.6.23.16.orig/drivers/net/tg3.h      2008-02-22 19:40:57.000000000 +0100
1207 +++ linux-2.6.23.16/drivers/net/tg3.h   2008-02-23 20:56:08.000000000 +0100
1208 @@ -2279,6 +2279,10 @@ struct tg3 {
1209  #define TG3_FLG2_PHY_JITTER_BUG                0x20000000
1210  #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
1211  #define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
1212 +       u32                             tg3_flags3;
1213 +#define TG3_FLG3_IS_SSB_CORE           0x00000001
1214 +#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00000002
1215 +#define TG3_FLG3_ROBOSWITCH            0x00000004
1216
1217         struct timer_list               timer;
1218         u16                             timer_counter;
1219 @@ -2333,6 +2337,7 @@ struct tg3 {
1220  #define PHY_ID_BCM5714                 0x60008340
1221  #define PHY_ID_BCM5780                 0x60008350
1222  #define PHY_ID_BCM5755                 0xbc050cc0
1223 +#define PHY_ID_BCM5750_2               0xbc050cd0
1224  #define PHY_ID_BCM5787                 0xbc050ce0
1225  #define PHY_ID_BCM5756                 0xbc050ed0
1226  #define PHY_ID_BCM5906                 0xdc00ac40
1227 @@ -2364,7 +2369,8 @@ struct tg3 {
1228          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
1229          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
1230          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
1231 -        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
1232 +        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002 || \
1233 +        (X) == PHY_ID_BCM5750_2)
1234
1235         struct tg3_hw_stats             *hw_stats;
1236         dma_addr_t                      stats_mapping;
1237 Index: linux-2.6.23.16/drivers/ssb/driver_mipscore.c
1238 ===================================================================
1239 --- linux-2.6.23.16.orig/drivers/ssb/driver_mipscore.c  2008-02-20 20:02:43.000000000 +0100
1240 +++ linux-2.6.23.16/drivers/ssb/driver_mipscore.c       2008-02-28 12:16:12.000000000 +0100
1241 @@ -211,6 +211,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1242                         /* fallthrough */
1243                 case SSB_DEV_PCI:
1244                 case SSB_DEV_ETHERNET:
1245 +               case SSB_DEV_ETHERNET_GBIT:
1246                 case SSB_DEV_80211:
1247                 case SSB_DEV_USB20_HOST:
1248                         /* These devices get their own IRQ line if available, the rest goes on IRQ0 */