target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch

   1 Index: linux-2.6.23.16/drivers/ssb/Kconfig
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/drivers/ssb/Kconfig    2008-02-22 19:40:57.000000000 +0100
   4 +++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-22 19:42:52.000000000 +0100
   5 @@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF
   6
   7           If unsure, say N
   8
   9 +config SSB_DRIVER_GIGE
  10 +       bool "SSB Broadcom Gigabit Ethernet driver (EXPERIMENTAL)"
  11 +       depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS && EXPERIMENTAL
  12 +       help
  13 +         Driver the the Sonics Silicon Backplane attached
  14 +         Broadcom Gigabit Ethernet.
  15 +
  16 +         If unsure, say N
  17 +
  18  endmenu
  19 Index: linux-2.6.23.16/drivers/ssb/Makefile
  20 ===================================================================
  21 --- linux-2.6.23.16.orig/drivers/ssb/Makefile   2008-02-22 19:40:57.000000000 +0100
  22 +++ linux-2.6.23.16/drivers/ssb/Makefile        2008-02-22 19:42:52.000000000 +0100
  23 @@ -11,6 +11,7 @@ ssb-y                                 += driver_chipcommon.o
  24  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  25  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  26  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  27 +ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  28
  29  # b43 pci-ssb-bridge driver
  30  # Not strictly a part of SSB, but kept here for convenience
  31 Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
  32 ===================================================================
  33 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  34 +++ linux-2.6.23.16/drivers/ssb/driver_gige.c   2008-02-22 20:59:46.000000000 +0100
  35 @@ -0,0 +1,281 @@
  36 +/*
  37 + * Sonics Silicon Backplane
  38 + * Broadcom Gigabit Ethernet core driver
  39 + *
  40 + * Copyright 2008, Broadcom Corporation
  41 + * Copyright 2008, Michael Buesch <mb@bu3sch.de>
  42 + *
  43 + * Licensed under the GNU/GPL. See COPYING for details.
  44 + */
  45 +
  46 +#include <linux/ssb/ssb.h>
  47 +#include <linux/pci.h>
  48 +#include <linux/pci_regs.h>
  49 +#include <linux/ssb/ssb_driver_gige.h>
  50 +
  51 +
  52 +MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
  53 +MODULE_AUTHOR("Michael Buesch");
  54 +MODULE_LICENSE("GPL");
  55 +
  56 +
  57 +static const struct ssb_device_id ssb_gige_tbl[] = {
  58 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
  59 +       SSB_DEVTABLE_END
  60 +};
  61 +MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl);
  62 +
  63 +
  64 +static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
  65 +{
  66 +       return ssb_read8(dev->dev, offset);
  67 +}
  68 +
  69 +static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
  70 +{
  71 +       return ssb_read16(dev->dev, offset);
  72 +}
  73 +
  74 +static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
  75 +{
  76 +       return ssb_read32(dev->dev, offset);
  77 +}
  78 +
  79 +static inline void gige_write8(struct ssb_gige *dev,
  80 +                              u16 offset, u8 value)
  81 +{
  82 +       ssb_write8(dev->dev, offset, value);
  83 +}
  84 +
  85 +static inline void gige_write16(struct ssb_gige *dev,
  86 +                               u16 offset, u16 value)
  87 +{
  88 +       ssb_write16(dev->dev, offset, value);
  89 +}
  90 +
  91 +static inline void gige_write32(struct ssb_gige *dev,
  92 +                               u16 offset, u32 value)
  93 +{
  94 +       ssb_write32(dev->dev, offset, value);
  95 +}
  96 +
  97 +static inline
  98 +u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
  99 +{
 100 +       BUG_ON(offset >= 256);
 101 +       return gige_read8(dev, SSB_GIGE_PCICFG + offset);
 102 +}
 103 +
 104 +static inline
 105 +u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
 106 +{
 107 +       BUG_ON(offset >= 256);
 108 +       return gige_read16(dev, SSB_GIGE_PCICFG + offset);
 109 +}
 110 +
 111 +static inline
 112 +u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
 113 +{
 114 +       BUG_ON(offset >= 256);
 115 +       return gige_read32(dev, SSB_GIGE_PCICFG + offset);
 116 +}
 117 +
 118 +static inline
 119 +void gige_pcicfg_write8(struct ssb_gige *dev,
 120 +                       unsigned int offset, u8 value)
 121 +{
 122 +       BUG_ON(offset >= 256);
 123 +       gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
 124 +}
 125 +
 126 +static inline
 127 +void gige_pcicfg_write16(struct ssb_gige *dev,
 128 +                        unsigned int offset, u16 value)
 129 +{
 130 +       BUG_ON(offset >= 256);
 131 +       gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
 132 +}
 133 +
 134 +static inline
 135 +void gige_pcicfg_write32(struct ssb_gige *dev,
 136 +                        unsigned int offset, u32 value)
 137 +{
 138 +       BUG_ON(offset >= 256);
 139 +       gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
 140 +}
 141 +
 142 +static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 143 +                                   int reg, int size, u32 *val)
 144 +{
 145 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 146 +       unsigned long flags;
 147 +
 148 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 149 +               return PCIBIOS_DEVICE_NOT_FOUND;
 150 +       if (reg >= 256)
 151 +               return PCIBIOS_DEVICE_NOT_FOUND;
 152 +
 153 +       spin_lock_irqsave(&dev->lock, flags);
 154 +       switch (size) {
 155 +       case 1:
 156 +               *val = gige_pcicfg_read8(dev, reg);
 157 +               break;
 158 +       case 2:
 159 +               *val = gige_pcicfg_read16(dev, reg);
 160 +               break;
 161 +       case 4:
 162 +               *val = gige_pcicfg_read32(dev, reg);
 163 +               break;
 164 +       default:
 165 +               WARN_ON(1);
 166 +       }
 167 +       spin_unlock_irqrestore(&dev->lock, flags);
 168 +
 169 +       return PCIBIOS_SUCCESSFUL;
 170 +}
 171 +
 172 +static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 173 +                                    int reg, int size, u32 val)
 174 +{
 175 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 176 +       unsigned long flags;
 177 +
 178 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 179 +               return PCIBIOS_DEVICE_NOT_FOUND;
 180 +       if (reg >= 256)
 181 +               return PCIBIOS_DEVICE_NOT_FOUND;
 182 +
 183 +       spin_lock_irqsave(&dev->lock, flags);
 184 +       switch (size) {
 185 +       case 1:
 186 +               gige_pcicfg_write8(dev, reg, val);
 187 +               break;
 188 +       case 2:
 189 +               gige_pcicfg_write16(dev, reg, val);
 190 +               break;
 191 +       case 4:
 192 +               gige_pcicfg_write32(dev, reg, val);
 193 +               break;
 194 +       default:
 195 +               WARN_ON(1);
 196 +       }
 197 +       spin_unlock_irqrestore(&dev->lock, flags);
 198 +
 199 +       return PCIBIOS_SUCCESSFUL;
 200 +}
 201 +
 202 +static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
 203 +{
 204 +       struct ssb_gige *dev;
 205 +       u32 base, tmslow, tmshigh;
 206 +
 207 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 208 +       if (!dev)
 209 +               return -ENOMEM;
 210 +       dev->dev = sdev;
 211 +
 212 +       spin_lock_init(&dev->lock);
 213 +       dev->pci_controller.pci_ops = &dev->pci_ops;
 214 +       dev->pci_controller.io_resource = &dev->io_resource;
 215 +       dev->pci_controller.mem_resource = &dev->mem_resource;
 216 +       dev->pci_controller.io_map_base = 0x800;
 217 +       dev->pci_ops.read = ssb_gige_pci_read_config;
 218 +       dev->pci_ops.write = ssb_gige_pci_write_config;
 219 +
 220 +       dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
 221 +       dev->io_resource.start = 0x800;
 222 +       dev->io_resource.end = 0x8FF;
 223 +       dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
 224 +
 225 +       if (!ssb_device_is_enabled(sdev))
 226 +               ssb_device_enable(sdev, 0);
 227 +
 228 +       /* Setup BAR0. This is a 64k MMIO region. */
 229 +       base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
 230 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
 231 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
 232 +
 233 +       dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
 234 +       dev->mem_resource.start = base;
 235 +       dev->mem_resource.end = base + 0x10000 - 1;
 236 +       dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 237 +
 238 +       /* Enable the memory region. */
 239 +       gige_pcicfg_write16(dev, PCI_COMMAND,
 240 +                           gige_pcicfg_read16(dev, PCI_COMMAND)
 241 +                           | PCI_COMMAND_MEMORY);
 242 +
 243 +       /* Write flushing is controlled by the Flush Status Control register.
 244 +        * We want to flush every register write with a timeout and we want
 245 +        * to disable the IRQ mask while flushing to avoid concurrency.
 246 +        * Note that automatic write flushing does _not_ work from
 247 +        * an IRQ handler. The driver must flush manually by reading a register.
 248 +        */
 249 +       gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
 250 +
 251 +       /* Check if we have an RGMII or GMII PHY-bus.
 252 +        * On RGMII do not bypass the DLLs */
 253 +       tmslow = ssb_read32(sdev, SSB_TMSLOW);
 254 +       tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
 255 +       if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
 256 +               tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
 257 +               tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
 258 +               dev->has_rgmii = 1;
 259 +       } else {
 260 +               tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
 261 +               tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
 262 +               dev->has_rgmii = 0;
 263 +       }
 264 +       tmslow |= SSB_GIGE_TMSLOW_DLLEN;
 265 +       ssb_write32(sdev, SSB_TMSLOW, tmslow);
 266 +
 267 +       ssb_set_drvdata(sdev, dev);
 268 +       register_pci_controller(&dev->pci_controller);
 269 +
 270 +       return 0;
 271 +}
 272 +
 273 +int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 274 +                                  struct pci_dev *pdev)
 275 +{
 276 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 277 +       struct resource *res;
 278 +
 279 +       if (pdev->bus->ops != &dev->pci_ops) {
 280 +               /* The PCI device is not on this SSB GigE bridge device. */
 281 +               return -ENODEV;
 282 +       }
 283 +
 284 +       /* Fixup the PCI resources. */
 285 +       res = &(pdev->resource[0]);
 286 +       res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 287 +       res->name = dev->mem_resource.name;
 288 +       res->start = dev->mem_resource.start;
 289 +       res->end = dev->mem_resource.end;
 290 +
 291 +       return 0;
 292 +}
 293 +
 294 +int ssb_gige_map_irq(struct ssb_device *sdev,
 295 +                    const struct pci_dev *pdev)
 296 +{
 297 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 298 +
 299 +       if (pdev->bus->ops != &dev->pci_ops) {
 300 +               /* The PCI device is not on this SSB GigE bridge device. */
 301 +               return -ENODEV;
 302 +       }
 303 +
 304 +       return ssb_mips_irq(sdev) + 2;
 305 +}
 306 +
 307 +static struct ssb_driver ssb_gige_driver = {
 308 +       .name           = "BCM-GigE",
 309 +       .id_table       = ssb_gige_tbl,
 310 +       .probe          = ssb_gige_probe,
 311 +};
 312 +
 313 +int ssb_gige_init(void)
 314 +{
 315 +       return ssb_driver_register(&ssb_gige_driver);
 316 +}
 317 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
 318 ===================================================================
 319 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 320 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-22 20:47:58.000000000 +0100
 321 @@ -0,0 +1,178 @@
 322 +#ifndef LINUX_SSB_DRIVER_GIGE_H_
 323 +#define LINUX_SSB_DRIVER_GIGE_H_
 324 +
 325 +#include <linux/ssb/ssb.h>
 326 +#include <linux/pci.h>
 327 +#include <linux/spinlock.h>
 328 +
 329 +
 330 +#ifdef CONFIG_SSB_DRIVER_GIGE
 331 +
 332 +
 333 +#define SSB_GIGE_PCIIO                 0x0000 /* PCI I/O Registers (1024 bytes) */
 334 +#define SSB_GIGE_RESERVED              0x0400 /* Reserved (1024 bytes) */
 335 +#define SSB_GIGE_PCICFG                        0x0800 /* PCI config space (256 bytes) */
 336 +#define SSB_GIGE_SHIM_FLUSHSTAT                0x0C00 /* PCI to OCP: Flush status control (32bit) */
 337 +#define SSB_GIGE_SHIM_FLUSHRDA         0x0C04 /* PCI to OCP: Flush read address (32bit) */
 338 +#define SSB_GIGE_SHIM_FLUSHTO          0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
 339 +#define SSB_GIGE_SHIM_BARRIER          0x0C0C /* PCI to OCP: Barrier register (32bit) */
 340 +#define SSB_GIGE_SHIM_MAOCPSI          0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
 341 +#define SSB_GIGE_SHIM_SIOCPMA          0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
 342 +
 343 +/* TM Status High flags */
 344 +#define SSB_GIGE_TMSHIGH_RGMII         0x00010000 /* Have an RGMII PHY-bus */
 345 +/* TM Status Low flags */
 346 +#define SSB_GIGE_TMSLOW_TXBYPASS       0x00080000 /* TX bypass (no delay) */
 347 +#define SSB_GIGE_TMSLOW_RXBYPASS       0x00100000 /* RX bypass (no delay) */
 348 +#define SSB_GIGE_TMSLOW_DLLEN          0x01000000 /* Enable DLL controls */
 349 +
 350 +/* Boardflags (low) */
 351 +#define SSB_GIGE_BFL_ROBOSWITCH                0x0010
 352 +
 353 +
 354 +#define SSB_GIGE_MEM_RES_NAME          "SSB Broadcom 47xx GigE memory"
 355 +#define SSB_GIGE_IO_RES_NAME           "SSB Broadcom 47xx GigE I/O"
 356 +
 357 +struct ssb_gige {
 358 +       struct ssb_device *dev;
 359 +
 360 +       spinlock_t lock;
 361 +
 362 +       /* True, if the device has an RGMII bus.
 363 +        * False, if the device has a GMII bus. */
 364 +       bool has_rgmii;
 365 +
 366 +       /* The PCI controller device. */
 367 +       struct pci_controller pci_controller;
 368 +       struct pci_ops pci_ops;
 369 +       struct resource mem_resource;
 370 +       struct resource io_resource;
 371 +};
 372 +
 373 +/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
 374 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 375 +{
 376 +       return (pdev->resource[0].name &&
 377 +               strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
 378 +}
 379 +
 380 +/* Convert a pci_dev pointer to a ssb_gige pointer. */
 381 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 382 +{
 383 +       if (!pdev_is_ssb_gige_core(pdev))
 384 +               return NULL;
 385 +       return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
 386 +}
 387 +
 388 +/* Returns whether the PHY is connected by an RGMII bus. */
 389 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 390 +{
 391 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 392 +       return (dev ? dev->has_rgmii : 0);
 393 +}
 394 +
 395 +/* Returns whether we have a Roboswitch. */
 396 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 397 +{
 398 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 399 +       if (dev)
 400 +               return !!(dev->dev->bus->sprom.boardflags_lo &
 401 +                         SSB_GIGE_BFL_ROBOSWITCH);
 402 +       return 0;
 403 +}
 404 +
 405 +/* Returns whether we can only do one DMA at once. */
 406 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 407 +{
 408 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 409 +       if (dev)
 410 +               return ((dev->dev->bus->chip_id == 0x4785) &&
 411 +                       (dev->dev->bus->chip_rev < 2));
 412 +       return 0;
 413 +}
 414 +
 415 +/* Returns whether we must flush posted writes. */
 416 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 417 +{
 418 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 419 +       if (dev)
 420 +               return (dev->dev->bus->chip_id == 0x4785);
 421 +       return 0;
 422 +}
 423 +
 424 +extern char * nvram_get(const char *name); //FIXME
 425 +/* Get the device MAC address */
 426 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 427 +{
 428 +#ifdef CONFIG_BCM947XX
 429 +       char *res = nvram_get("et0macaddr"); //FIXME
 430 +       if (res)
 431 +               memcpy(macaddr, res, 6);
 432 +#endif
 433 +}
 434 +
 435 +extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 436 +                                         struct pci_dev *pdev);
 437 +extern int ssb_gige_map_irq(struct ssb_device *sdev,
 438 +                           const struct pci_dev *pdev);
 439 +
 440 +/* The GigE driver is not a standalone module, because we don't have support
 441 + * for unregistering the driver. So we could not unload the module anyway. */
 442 +extern int ssb_gige_init(void);
 443 +static inline void ssb_gige_exit(void)
 444 +{
 445 +       /* Currently we can not unregister the GigE driver,
 446 +        * because we can not unregister the PCI bridge. */
 447 +       BUG();
 448 +}
 449 +
 450 +
 451 +#else /* CONFIG_SSB_DRIVER_GIGE */
 452 +/* Gigabit Ethernet driver disabled */
 453 +
 454 +
 455 +static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 456 +                                                struct pci_dev *pdev)
 457 +{
 458 +       return -ENOSYS;
 459 +}
 460 +static inline int ssb_gige_map_irq(struct ssb_device *sdev,
 461 +                                  const struct pci_dev *pdev)
 462 +{
 463 +       return -ENOSYS;
 464 +}
 465 +static inline int ssb_gige_init(void)
 466 +{
 467 +       return 0;
 468 +}
 469 +static inline void ssb_gige_exit(void)
 470 +{
 471 +}
 472 +
 473 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 474 +{
 475 +       return 0;
 476 +}
 477 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 478 +{
 479 +       return NULL;
 480 +}
 481 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 482 +{
 483 +       return 0;
 484 +}
 485 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 486 +{
 487 +       return 0;
 488 +}
 489 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 490 +{
 491 +       return 0;
 492 +}
 493 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 494 +{
 495 +       return 0;
 496 +}
 497 +
 498 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 499 +#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
 500 Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
 501 ===================================================================
 502 --- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c   2008-02-22 19:40:57.000000000 +0100
 503 +++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c        2008-02-22 19:42:52.000000000 +0100
 504 @@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
 505  /* Core to access the external PCI config space. Can only have one. */
 506  static struct ssb_pcicore *extpci_core;
 507
 508 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
 509 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 510 -
 511 -int pcibios_plat_dev_init(struct pci_dev *d)
 512 -{
 513 -       struct resource *res;
 514 -       int pos, size;
 515 -       u32 *base;
 516 -
 517 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 518 -                  pci_name(d));
 519 -
 520 -       /* Fix up resource bases */
 521 -       for (pos = 0; pos < 6; pos++) {
 522 -               res = &d->resource[pos];
 523 -               if (res->flags & IORESOURCE_IO)
 524 -                       base = &ssb_pcicore_pcibus_iobase;
 525 -               else
 526 -                       base = &ssb_pcicore_pcibus_membase;
 527 -               res->flags |= IORESOURCE_PCI_FIXED;
 528 -               if (res->end) {
 529 -                       size = res->end - res->start + 1;
 530 -                       if (*base & (size - 1))
 531 -                               *base = (*base + size) & ~(size - 1);
 532 -                       res->start = *base;
 533 -                       res->end = res->start + size - 1;
 534 -                       *base += size;
 535 -                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 536 -               }
 537 -               /* Fix up PCI bridge BAR0 only */
 538 -               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 539 -                       break;
 540 -       }
 541 -       /* Fix up interrupt lines */
 542 -       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 543 -       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 544 -
 545 -       return 0;
 546 -}
 547 -
 548 -static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
 549 -{
 550 -       u8 lat;
 551 -
 552 -       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 553 -               return;
 554 -
 555 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 556 -
 557 -       /* Enable PCI bridge bus mastering and memory space */
 558 -       pci_set_master(dev);
 559 -       pcibios_enable_device(dev, ~0);
 560 -
 561 -       /* Enable PCI bridge BAR1 prefetch and burst */
 562 -       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 563 -
 564 -       /* Make sure our latency is high enough to handle the devices behind us */
 565 -       lat = 168;
 566 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 567 -                  pci_name(dev), lat);
 568 -       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 569 -}
 570 -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 571 -
 572 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 573 -{
 574 -       return ssb_mips_irq(extpci_core->dev) + 2;
 575 -}
 576
 577  static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
 578                              unsigned int bus, unsigned int dev,
 579 @@ -317,6 +249,92 @@ static struct pci_controller ssb_pcicore
 580         .mem_offset     = 0x24000000,
 581  };
 582
 583 +static u32 ssb_pcicore_pcibus_iobase = 0x100;
 584 +static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 585 +
 586 +/* This function is called when doing a pci_enable_device().
 587 + * We must first check if the device is a device on the PCI-core bridge. */
 588 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 589 +{
 590 +       struct resource *res;
 591 +       int pos, size;
 592 +       u32 *base;
 593 +
 594 +       if (d->bus->ops != &ssb_pcicore_pciops) {
 595 +               /* This is not a device on the PCI-core bridge. */
 596 +               return -ENODEV;
 597 +       }
 598 +
 599 +       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 600 +                  pci_name(d));
 601 +
 602 +       /* Fix up resource bases */
 603 +       for (pos = 0; pos < 6; pos++) {
 604 +               res = &d->resource[pos];
 605 +               if (res->flags & IORESOURCE_IO)
 606 +                       base = &ssb_pcicore_pcibus_iobase;
 607 +               else
 608 +                       base = &ssb_pcicore_pcibus_membase;
 609 +               res->flags |= IORESOURCE_PCI_FIXED;
 610 +               if (res->end) {
 611 +                       size = res->end - res->start + 1;
 612 +                       if (*base & (size - 1))
 613 +                               *base = (*base + size) & ~(size - 1);
 614 +                       res->start = *base;
 615 +                       res->end = res->start + size - 1;
 616 +                       *base += size;
 617 +                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 618 +               }
 619 +               /* Fix up PCI bridge BAR0 only */
 620 +               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 621 +                       break;
 622 +       }
 623 +       /* Fix up interrupt lines */
 624 +       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 625 +       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 626 +
 627 +       return 0;
 628 +}
 629 +
 630 +/* Early PCI fixup for a device on the PCI-core bridge. */
 631 +static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 632 +{
 633 +       u8 lat;
 634 +
 635 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 636 +               /* This is not a device on the PCI-core bridge. */
 637 +               return;
 638 +       }
 639 +       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 640 +               return;
 641 +
 642 +       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 643 +
 644 +       /* Enable PCI bridge bus mastering and memory space */
 645 +       pci_set_master(dev);
 646 +       pcibios_enable_device(dev, ~0);
 647 +
 648 +       /* Enable PCI bridge BAR1 prefetch and burst */
 649 +       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 650 +
 651 +       /* Make sure our latency is high enough to handle the devices behind us */
 652 +       lat = 168;
 653 +       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 654 +                  pci_name(dev), lat);
 655 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 656 +}
 657 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 658 +
 659 +/* PCI device IRQ mapping. */
 660 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 661 +{
 662 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 663 +               /* This is not a device on the PCI-core bridge. */
 664 +               return -ENODEV;
 665 +       }
 666 +       return ssb_mips_irq(extpci_core->dev) + 2;
 667 +}
 668 +
 669  static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 670  {
 671         u32 val;
 672 Index: linux-2.6.23.16/drivers/ssb/embedded.c
 673 ===================================================================
 674 --- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-22 19:40:57.000000000 +0100
 675 +++ linux-2.6.23.16/drivers/ssb/embedded.c      2008-02-22 19:42:52.000000000 +0100
 676 @@ -10,6 +10,9 @@
 677
 678  #include <linux/ssb/ssb.h>
 679  #include <linux/ssb/ssb_embedded.h>
 680 +#include <linux/ssb/ssb_driver_pci.h>
 681 +#include <linux/ssb/ssb_driver_gige.h>
 682 +#include <linux/pci.h>
 683
 684  #include "ssb_private.h"
 685
 686 @@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
 687         return res;
 688  }
 689  EXPORT_SYMBOL(ssb_gpio_polarity);
 690 +
 691 +#ifdef CONFIG_SSB_DRIVER_GIGE
 692 +static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
 693 +{
 694 +       struct pci_dev *pdev = (struct pci_dev *)data;
 695 +       struct ssb_device *dev;
 696 +       unsigned int i;
 697 +       int res;
 698 +
 699 +       for (i = 0; i < bus->nr_devices; i++) {
 700 +               dev = &(bus->devices[i]);
 701 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 702 +                       continue;
 703 +               if (!dev->dev ||
 704 +                   !dev->dev->driver ||
 705 +                   !device_is_registered(dev->dev))
 706 +                       continue;
 707 +               res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
 708 +               if (res >= 0)
 709 +                       return res;
 710 +       }
 711 +
 712 +       return -ENODEV;
 713 +}
 714 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 715 +
 716 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
 717 +{
 718 +       int err;
 719 +
 720 +       err = ssb_pcicore_plat_dev_init(dev);
 721 +       if (!err)
 722 +               return 0;
 723 +#ifdef CONFIG_SSB_DRIVER_GIGE
 724 +       err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
 725 +       if (err >= 0)
 726 +               return err;
 727 +#endif
 728 +       /* This is not a PCI device on any SSB device. */
 729 +
 730 +       return -ENODEV;
 731 +}
 732 +
 733 +#ifdef CONFIG_SSB_DRIVER_GIGE
 734 +static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
 735 +{
 736 +       const struct pci_dev *pdev = (const struct pci_dev *)data;
 737 +       struct ssb_device *dev;
 738 +       unsigned int i;
 739 +       int res;
 740 +
 741 +       for (i = 0; i < bus->nr_devices; i++) {
 742 +               dev = &(bus->devices[i]);
 743 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 744 +                       continue;
 745 +               if (!dev->dev ||
 746 +                   !dev->dev->driver ||
 747 +                   !device_is_registered(dev->dev))
 748 +                       continue;
 749 +               res = ssb_gige_map_irq(dev, pdev);
 750 +               if (res >= 0)
 751 +                       return res;
 752 +       }
 753 +
 754 +       return -ENODEV;
 755 +}
 756 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 757 +
 758 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 759 +{
 760 +       int res;
 761 +
 762 +       /* Check if this PCI device is a device on a SSB bus or device
 763 +        * and return the IRQ number for it. */
 764 +
 765 +       res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
 766 +       if (res >= 0)
 767 +               return res;
 768 +#ifdef CONFIG_SSB_DRIVER_GIGE
 769 +       res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
 770 +       if (res >= 0)
 771 +               return res;
 772 +#endif
 773 +       /* This is not a PCI device on any SSB device. */
 774 +
 775 +       return -ENODEV;
 776 +}
 777 Index: linux-2.6.23.16/include/linux/ssb/ssb.h
 778 ===================================================================
 779 --- linux-2.6.23.16.orig/include/linux/ssb/ssb.h        2008-02-22 19:40:57.000000000 +0100
 780 +++ linux-2.6.23.16/include/linux/ssb/ssb.h     2008-02-22 19:42:52.000000000 +0100
 781 @@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu
 782  extern u32 ssb_admatch_base(u32 adm);
 783  extern u32 ssb_admatch_size(u32 adm);
 784
 785 +/* PCI device mapping and fixup routines.
 786 + * Called from the architecture pcibios init code.
 787 + * These are only available on SSB_EMBEDDED configurations. */
 788 +#ifdef CONFIG_SSB_EMBEDDED
 789 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
 790 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 791 +#endif /* CONFIG_SSB_EMBEDDED */
 792
 793  #endif /* LINUX_SSB_H_ */
 794 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
 795 ===================================================================
 796 --- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h     2008-02-22 19:40:57.000000000 +0100
 797 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h  2008-02-22 19:42:52.000000000 +0100
 798 @@ -1,6 +1,11 @@
 799  #ifndef LINUX_SSB_PCICORE_H_
 800  #define LINUX_SSB_PCICORE_H_
 801
 802 +#include <linux/types.h>
 803 +
 804 +struct pci_dev;
 805 +
 806 +
 807  #ifdef CONFIG_SSB_DRIVER_PCICORE
 808
 809  /* PCI core registers. */
 810 @@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
 811  extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 812                                           struct ssb_device *dev);
 813
 814 +int ssb_pcicore_plat_dev_init(struct pci_dev *d);
 815 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 816 +
 817
 818  #else /* CONFIG_SSB_DRIVER_PCICORE */
 819
 820 @@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
 821         return 0;
 822  }
 823
 824 +static inline
 825 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 826 +{
 827 +       return -ENODEV;
 828 +}
 829 +static inline
 830 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 831 +{
 832 +       return -ENODEV;
 833 +}
 834 +
 835  #endif /* CONFIG_SSB_DRIVER_PCICORE */
 836  #endif /* LINUX_SSB_PCICORE_H_ */
 837 Index: linux-2.6.23.16/drivers/ssb/main.c
 838 ===================================================================
 839 --- linux-2.6.23.16.orig/drivers/ssb/main.c     2008-02-22 19:40:57.000000000 +0100
 840 +++ linux-2.6.23.16/drivers/ssb/main.c  2008-02-22 19:42:52.000000000 +0100
 841 @@ -14,6 +14,7 @@
 842  #include <linux/io.h>
 843  #include <linux/ssb/ssb.h>
 844  #include <linux/ssb/ssb_regs.h>
 845 +#include <linux/ssb/ssb_driver_gige.h>
 846  #include <linux/dma-mapping.h>
 847  #include <linux/pci.h>
 848
 849 @@ -68,6 +69,25 @@ found:
 850  }
 851  #endif /* CONFIG_SSB_PCIHOST */
 852
 853 +int ssb_for_each_bus_call(unsigned long data,
 854 +                         int (*func)(struct ssb_bus *bus, unsigned long data))
 855 +{
 856 +       struct ssb_bus *bus;
 857 +       int res;
 858 +
 859 +       ssb_buses_lock();
 860 +       list_for_each_entry(bus, &buses, list) {
 861 +               res = func(bus, data);
 862 +               if (res >= 0) {
 863 +                       ssb_buses_unlock();
 864 +                       return res;
 865 +               }
 866 +       }
 867 +       ssb_buses_unlock();
 868 +
 869 +       return -ENODEV;
 870 +}
 871 +
 872  static struct ssb_device *ssb_device_get(struct ssb_device *dev)
 873  {
 874         if (dev)
 875 @@ -1175,7 +1195,14 @@ static int __init ssb_modinit(void)
 876         err = b43_pci_ssb_bridge_init();
 877         if (err) {
 878                 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
 879 -                          "initialization failed");
 880 +                          "initialization failed\n");
 881 +               /* don't fail SSB init because of this */
 882 +               err = 0;
 883 +       }
 884 +       err = ssb_gige_init();
 885 +       if (err) {
 886 +               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
 887 +                          "driver initialization failed\n");
 888                 /* don't fail SSB init because of this */
 889                 err = 0;
 890         }
 891 @@ -1189,6 +1216,7 @@ fs_initcall(ssb_modinit);
 892
 893  static void __exit ssb_modexit(void)
 894  {
 895 +       ssb_gige_exit();
 896         b43_pci_ssb_bridge_exit();
 897         bus_unregister(&ssb_bustype);
 898  }
 899 Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
 900 ===================================================================
 901 --- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h      2008-02-22 19:40:57.000000000 +0100
 902 +++ linux-2.6.23.16/drivers/ssb/ssb_private.h   2008-02-22 19:42:52.000000000 +0100
 903 @@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
 904  extern int ssb_devices_freeze(struct ssb_bus *bus);
 905  extern int ssb_devices_thaw(struct ssb_bus *bus);
 906  extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
 907 +int ssb_for_each_bus_call(unsigned long data,
 908 +                         int (*func)(struct ssb_bus *bus, unsigned long data));
 909
 910  /* b43_pci_bridge.c */
 911  #ifdef CONFIG_SSB_PCIHOST
 912 Index: linux-2.6.23.16/drivers/net/tg3.c
 913 ===================================================================
 914 --- linux-2.6.23.16.orig/drivers/net/tg3.c      2008-02-22 19:40:57.000000000 +0100
 915 +++ linux-2.6.23.16/drivers/net/tg3.c   2008-02-23 20:02:58.000000000 +0100
 916 @@ -38,6 +38,7 @@
 917  #include <linux/workqueue.h>
 918  #include <linux/prefetch.h>
 919  #include <linux/dma-mapping.h>
 920 +#include <linux/ssb/ssb_driver_gige.h>
 921
 922  #include <net/checksum.h>
 923  #include <net/ip.h>
 924 @@ -410,8 +411,9 @@ static void _tw32_flush(struct tg3 *tp,
 925  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 926  {
 927         tp->write32_mbox(tp, off, val);
 928 -       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 929 -           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 930 +       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
 931 +           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 932 +            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
 933                 tp->read32_mbox(tp, off);
 934  }
 935
 936 @@ -1988,6 +1990,14 @@ static int tg3_setup_copper_phy(struct t
 937                 tp->link_config.active_duplex = current_duplex;
 938         }
 939
 940 +       if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
 941 +               current_link_up = 1;
 942 +               current_speed = SPEED_1000; //FIXME
 943 +               current_duplex = DUPLEX_FULL;
 944 +               tp->link_config.active_speed = current_speed;
 945 +               tp->link_config.active_duplex = current_duplex;
 946 +       }
 947 +
 948         if (current_link_up == 1 &&
 949             (tp->link_config.active_duplex == DUPLEX_FULL) &&
 950             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
 951 @@ -4813,6 +4823,11 @@ static int tg3_poll_fw(struct tg3 *tp)
 952         int i;
 953         u32 val;
 954
 955 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 956 +               /* We don't use firmware. */
 957 +               return 0;
 958 +       }
 959 +
 960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 961                 /* Wait up to 20ms for init done. */
 962                 for (i = 0; i < 200; i++) {
 963 @@ -5040,6 +5055,14 @@ static int tg3_chip_reset(struct tg3 *tp
 964                 tw32(0x5000, 0x400);
 965         }
 966
 967 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 968 +               /* BCM4785: In order to avoid repercussions from using potentially
 969 +                * defective internal ROM, stop the Rx RISC CPU, which is not
 970 +                * required. */
 971 +               tg3_stop_fw(tp);
 972 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 973 +       }
 974 +
 975         tw32(GRC_MODE, tp->grc_mode);
 976
 977         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 978 @@ -5308,9 +5331,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
 979                 return -ENODEV;
 980         }
 981
 982 -       /* Clear firmware's nvram arbitration. */
 983 -       if (tp->tg3_flags & TG3_FLAG_NVRAM)
 984 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 985 +       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
 986 +               /* Clear firmware's nvram arbitration. */
 987 +               if (tp->tg3_flags & TG3_FLAG_NVRAM)
 988 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 989 +       }
 990 +
 991         return 0;
 992  }
 993
 994 @@ -5391,6 +5417,11 @@ static int tg3_load_5701_a0_firmware_fix
 995         struct fw_info info;
 996         int err, i;
 997
 998 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 999 +               /* We don't use firmware. */
1000 +               return 0;
1001 +       }
1002 +
1003         info.text_base = TG3_FW_TEXT_ADDR;
1004         info.text_len = TG3_FW_TEXT_LEN;
1005         info.text_data = &tg3FwText[0];
1006 @@ -5949,6 +5980,11 @@ static int tg3_load_tso_firmware(struct
1007         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
1008         int err, i;
1009
1010 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1011 +               /* We don't use firmware. */
1012 +               return 0;
1013 +       }
1014 +
1015         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
1016                 return 0;
1017
1018 @@ -6850,6 +6886,11 @@ static void tg3_timer(unsigned long __op
1019
1020         spin_lock(&tp->lock);
1021
1022 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1023 +               /* BCM4785: Flush posted writes from GbE to host memory. */
1024 +               tr32(HOSTCC_MODE);
1025 +       }
1026 +
1027         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
1028                 /* All of this garbage is because when using non-tagged
1029                  * IRQ status the mailbox/status_block protocol the chip
1030 @@ -8432,6 +8473,11 @@ static int tg3_test_nvram(struct tg3 *tp
1031         u32 *buf, csum, magic;
1032         int i, j, err = 0, size;
1033
1034 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1035 +               /* We don't have NVRAM. */
1036 +               return 0;
1037 +       }
1038 +
1039         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1040                 return -EIO;
1041
1042 @@ -9571,6 +9617,12 @@ static void __devinit tg3_get_5906_nvram
1043  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
1044  static void __devinit tg3_nvram_init(struct tg3 *tp)
1045  {
1046 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1047 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
1048 +               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
1049 +               return;
1050 +       }
1051 +
1052         tw32_f(GRC_EEPROM_ADDR,
1053              (EEPROM_ADDR_FSM_RESET |
1054               (EEPROM_DEFAULT_CLOCK_PERIOD <<
1055 @@ -9706,6 +9758,9 @@ static int tg3_nvram_read(struct tg3 *tp
1056  {
1057         int ret;
1058
1059 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1060 +               return -ENODEV;
1061 +
1062         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1063                 return tg3_nvram_read_using_eeprom(tp, offset, val);
1064
1065 @@ -9938,6 +9993,9 @@ static int tg3_nvram_write_block(struct
1066  {
1067         int ret;
1068
1069 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1070 +               return -ENODEV;
1071 +
1072         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
1073                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
1074                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
1075 @@ -10804,7 +10862,6 @@ static int __devinit tg3_get_invariants(
1076                 tp->write32 = tg3_write_flush_reg32;
1077         }
1078
1079 -
1080         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
1081             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
1082                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
1083 @@ -10840,6 +10897,11 @@ static int __devinit tg3_get_invariants(
1084               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
1085                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
1086
1087 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1088 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
1089 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
1090 +       }
1091 +
1092         /* Get eeprom hw config before calling tg3_set_power_state().
1093          * In particular, the TG3_FLG2_IS_NIC flag must be
1094          * determined before calling tg3_set_power_state() so that
1095 @@ -11184,6 +11246,10 @@ static int __devinit tg3_get_device_addr
1096         }
1097
1098         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1099 +               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1100 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
1101 +       }
1102 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1103  #ifdef CONFIG_SPARC64
1104                 if (!tg3_get_default_macaddr_sparc(tp))
1105                         return 0;
1106 @@ -11675,6 +11741,7 @@ static char * __devinit tg3_phy_string(s
1107         case PHY_ID_BCM5704:    return "5704";
1108         case PHY_ID_BCM5705:    return "5705";
1109         case PHY_ID_BCM5750:    return "5750";
1110 +       case PHY_ID_BCM5750_2:  return "5750-2";
1111         case PHY_ID_BCM5752:    return "5752";
1112         case PHY_ID_BCM5714:    return "5714";
1113         case PHY_ID_BCM5780:    return "5780";
1114 @@ -11859,6 +11926,13 @@ static int __devinit tg3_init_one(struct
1115                 tp->msg_enable = tg3_debug;
1116         else
1117                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
1118 +       if (pdev_is_ssb_gige_core(pdev)) {
1119 +               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
1120 +               if (ssb_gige_must_flush_posted_writes(pdev))
1121 +                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
1122 +               if (ssb_gige_have_roboswitch(pdev))
1123 +                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
1124 +       }
1125
1126         /* The word/byte swap controls here control register access byte
1127          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
1128 Index: linux-2.6.23.16/drivers/net/tg3.h
1129 ===================================================================
1130 --- linux-2.6.23.16.orig/drivers/net/tg3.h      2008-02-22 19:40:57.000000000 +0100
1131 +++ linux-2.6.23.16/drivers/net/tg3.h   2008-02-23 19:35:15.000000000 +0100
1132 @@ -2279,6 +2279,10 @@ struct tg3 {
1133  #define TG3_FLG2_PHY_JITTER_BUG                0x20000000
1134  #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
1135  #define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
1136 +       u32                             tg3_flags3;
1137 +#define TG3_FLG3_IS_SSB_CORE           0x00000001
1138 +#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00000002
1139 +#define TG3_FLG3_ROBOSWITCH            0x00000004
1140
1141         struct timer_list               timer;
1142         u16                             timer_counter;
1143 @@ -2333,6 +2337,7 @@ struct tg3 {
1144  #define PHY_ID_BCM5714                 0x60008340
1145  #define PHY_ID_BCM5780                 0x60008350
1146  #define PHY_ID_BCM5755                 0xbc050cc0
1147 +#define PHY_ID_BCM5750_2               0xbc050cd0
1148  #define PHY_ID_BCM5787                 0xbc050ce0
1149  #define PHY_ID_BCM5756                 0xbc050ed0
1150  #define PHY_ID_BCM5906                 0xdc00ac40
1151 @@ -2364,7 +2369,8 @@ struct tg3 {
1152          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
1153          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
1154          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
1155 -        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
1156 +        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002 || \
1157 +        (X) == PHY_ID_BCM5750_2)
1158
1159         struct tg3_hw_stats             *hw_stats;
1160         dma_addr_t                      stats_mapping;