target/linux/brcm47xx/patches-2.6.23/602-ssb-fix-serial-on-new-devices.patch

   1 --- a/drivers/ssb/driver_chipcommon.c
   2 +++ b/drivers/ssb/driver_chipcommon.c
   3 @@ -403,6 +403,7 @@
   4         unsigned int irq;
   5         u32 baud_base, div;
   6         u32 i, n;
   7 +       unsigned int ccrev = cc->dev->id.revision;
   8
   9         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  10         irq = ssb_mips_irq(cc->dev);
  11 @@ -414,14 +415,39 @@
  12                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
  13                 div = 1;
  14         } else {
  15 -               if (cc->dev->id.revision >= 11) {
  16 +               if (ccrev == 20) {
  17 +                       /* BCM5354 uses constant 25MHz clock */
  18 +                       baud_base = 25000000;
  19 +                       div = 48;
  20 +                       /* Set the override bit so we don't divide it */
  21 +                       chipco_write32(cc, SSB_CHIPCO_CORECTL,
  22 +                                      chipco_read32(cc, SSB_CHIPCO_CORECTL)
  23 +                                      | SSB_CHIPCO_CORECTL_UARTCLK0);
  24 +               } else if ((ccrev >= 11) && (ccrev != 15)) {
  25                         /* Fixed ALP clock */
  26                         baud_base = 20000000;
  27 +                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  28 +                               /* FIXME: baud_base is different for devices with a PMU */
  29 +                               SSB_WARN_ON(1);
  30 +                       }
  31                         div = 1;
  32 +                       if (ccrev >= 21) {
  33 +                               /* Turn off UART clock before switching clocksource. */
  34 +                               chipco_write32(cc, SSB_CHIPCO_CORECTL,
  35 +                                              chipco_read32(cc, SSB_CHIPCO_CORECTL)
  36 +                                              & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
  37 +                       }
  38                         /* Set the override bit so we don't divide it */
  39                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
  40 -                                      SSB_CHIPCO_CORECTL_UARTCLK0);
  41 -               } else if (cc->dev->id.revision >= 3) {
  42 +                                      chipco_read32(cc, SSB_CHIPCO_CORECTL)
  43 +                                      | SSB_CHIPCO_CORECTL_UARTCLK0);
  44 +                       if (ccrev >= 21) {
  45 +                               /* Re-enable the UART clock. */
  46 +                               chipco_write32(cc, SSB_CHIPCO_CORECTL,
  47 +                                              chipco_read32(cc, SSB_CHIPCO_CORECTL)
  48 +                                              | SSB_CHIPCO_CORECTL_UARTCLKEN);
  49 +                       }
  50 +               } else if (ccrev >= 3) {
  51                         /* Internal backplane clock */
  52                         baud_base = ssb_clockspeed(bus);
  53                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
  54 @@ -433,7 +459,7 @@
  55                 }
  56
  57                 /* Clock source depends on strapping if UartClkOverride is unset */
  58 -               if ((cc->dev->id.revision > 0) &&
  59 +               if ((ccrev > 0) &&
  60                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
  61                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
  62                             SSB_CHIPCO_CAP_UARTCLK_INT) {
  63 @@ -455,7 +481,7 @@
  64                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
  65                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
  66                 /* Offset changed at after rev 0 */
  67 -               if (cc->dev->id.revision == 0)
  68 +               if (ccrev == 0)
  69                         uart_regs += (i * 8);
  70                 else
  71                         uart_regs += (i * 256);
  72 --- a/include/linux/ssb/ssb_driver_chipcommon.h
  73 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
  74 @@ -51,9 +51,12 @@
  75  #define  SSB_CHIPCO_CAP_JTAGM          0x00400000      /* JTAG master present */
  76  #define  SSB_CHIPCO_CAP_BROM           0x00800000      /* Internal boot ROM active */
  77  #define  SSB_CHIPCO_CAP_64BIT          0x08000000      /* 64-bit Backplane */
  78 +#define  SSB_CHIPCO_CAP_PMU            0x10000000      /* PMU available (rev >= 20) */
  79 +#define  SSB_CHIPCO_CAP_ECI            0x20000000      /* ECI available (rev >= 20) */
  80  #define SSB_CHIPCO_CORECTL             0x0008
  81  #define  SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001      /* Drive UART with internal clock */
  82  #define         SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
  83 +#define  SSB_CHIPCO_CORECTL_UARTCLKEN  0x00000008      /* UART clock enable (rev >= 21) */
  84  #define SSB_CHIPCO_BIST                        0x000C
  85  #define SSB_CHIPCO_OTPS                        0x0010          /* OTP status */
  86  #define         SSB_CHIPCO_OTPS_PROGFAIL       0x80000000